patches/gcc-13.2.0-psp.diff

   1 diff --git a/config.sub b/config.sub
   2 index 38f3d037a78..41942ba061a 100755
   3 --- a/config.sub
   4 +++ b/config.sub
   5 @@ -491,10 +491,6 @@ case $1 in
   6                                 basic_machine=hppa-unknown
   7                                 basic_os=linux
   8                                 ;;
   9 -                       psp)
  10 -                               basic_machine=mipsallegrexel-sony
  11 -                               basic_os=psp
  12 -                               ;;
  13                         pw32)
  14                                 basic_machine=i586-unknown
  15                                 basic_os=pw32
  16 @@ -647,6 +643,10 @@ case $1 in
  17                                 basic_machine=ymp-cray
  18                                 basic_os=unicos
  19                                 ;;
  20 +                       psp)
  21 +                               basic_machine=mipsallegrexel-psp
  22 +                               os=elf
  23 +                               ;;
  24                         *)
  25                                 basic_machine=$1
  26                                 basic_os=
  27 @@ -659,6 +659,10 @@ esac
  28  case $basic_machine in
  29         # Here we handle the default manufacturer of certain CPU types.  It is in
  30         # some cases the only manufacturer, in others, it is the most popular.
  31 +       mipsallegrexel-*)
  32 +               cpu=mipsallegrexel
  33 +               vendor=psp
  34 +               ;;
  35         w89k)
  36                 cpu=hppa1.1
  37                 vendor=winbond
  38 @@ -1161,10 +1165,6 @@ case $cpu-$vendor in
  39                 cpu=nsx
  40                 vendor=tandem
  41                 ;;
  42 -       mipsallegrexel-sony)
  43 -               cpu=mipsallegrexel
  44 -               vendor=sony
  45 -               ;;
  46         tile*-*)
  47                 basic_os=${basic_os:-linux-gnu}
  48                 ;;
  49 @@ -1233,6 +1233,7 @@ case $cpu-$vendor in
  50                         | mipsisa64sr71k | mipsisa64sr71kel \
  51                         | mipsr5900 | mipsr5900el \
  52                         | mipstx39 | mipstx39el \
  53 +                       | mipsallegrex | mipsallegrexel \
  54                         | mmix \
  55                         | mn10200 | mn10300 \
  56                         | moxie \
  57 diff --git a/config/mt-allegrex-psp b/config/mt-allegrex-psp
  58 new file mode 100644
  59 index 00000000000..34d52a18b50
  60 --- /dev/null
  61 +++ b/config/mt-allegrex-psp
  62 @@ -0,0 +1,3 @@
  63 +# Disable use of GP-relative addressing
  64 +CFLAGS_FOR_TARGET += -mno-gpopt
  65 +CXXFLAGS_FOR_TARGET += -mno-gpopt
  66 diff --git a/configure b/configure
  67 index 117a7ef23f2..b05c21b9430 100755
  68 --- a/configure
  69 +++ b/configure
  70 @@ -9578,6 +9578,9 @@ case "${target}" in
  71      extra_arflags_for_target=" -X32_64"
  72      extra_nmflags_for_target=" -B -X32_64"
  73      ;;
  74 +  mipsallegrex*-psp-elf*)
  75 +    target_makefile_frag="config/mt-allegrex-psp"
  76 +    ;;
  77  esac
  78
  79  alphaieee_frag=/dev/null
  80 diff --git a/configure.ac b/configure.ac
  81 index b3e9bbd2aa5..180a3a222e4 100644
  82 --- a/configure.ac
  83 +++ b/configure.ac
  84 @@ -2739,6 +2739,9 @@ case "${target}" in
  85      extra_arflags_for_target=" -X32_64"
  86      extra_nmflags_for_target=" -B -X32_64"
  87      ;;
  88 +  mipsallegrex*-psp-elf*)
  89 +    target_makefile_frag="config/mt-allegrex-psp"
  90 +    ;;
  91  esac
  92
  93  alphaieee_frag=/dev/null
  94 diff --git a/gcc/config.gcc b/gcc/config.gcc
  95 index 648b3dc2110..44ad1211a18 100644
  96 --- a/gcc/config.gcc
  97 +++ b/gcc/config.gcc
  98 @@ -2717,6 +2717,17 @@ mipstx39-*-elf* | mipstx39el-*-elf*)
  99         tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
 100         tmake_file="mips/t-r3900"
 101         ;;
 102 +mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
 103 +       tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h"
 104 +       tmake_file="${tmake_file} mips/t-elf"
 105 +       target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
 106 +       tm_defines="${tm_defines} MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
 107 +       case ${target} in
 108 +       mipsallegrex*-psp-elf*)
 109 +               tm_file="${tm_file} mips/psp.h"
 110 +               ;;
 111 +       esac
 112 +       ;;
 113  mmix-knuth-mmixware)
 114         tm_file="${tm_file} newlib-stdint.h"
 115         use_gcc_stdint=wrap
 116 @@ -4048,8 +4059,9 @@ fi
 117  # Infer a default setting for --with-fpu.
 118  if test x$with_fpu = x; then
 119    case ${target} in
 120 -    mips64r5900-*-* | mips64r5900el-*-* | mipsr5900-*-* | mipsr5900el-*-*)
 121 -      # The R5900 FPU only supports single precision.
 122 +    mips64r5900-*-* | mips64r5900el-*-* | mipsr5900-*-* | mipsr5900el-*-* | \
 123 +    mipsallegrex-*-* | mipsallegrexel-*-*)
 124 +      # The R5900 and Allegrex FPU only supports single precision.
 125        with_fpu=single
 126        ;;
 127    esac
 128 diff --git a/gcc/config/mips/allegrex.md b/gcc/config/mips/allegrex.md
 129 new file mode 100644
 130 index 00000000000..e9ae897bb18
 131 --- /dev/null
 132 +++ b/gcc/config/mips/allegrex.md
 133 @@ -0,0 +1,145 @@
 134 +;; Sony ALLEGREX instructions.
 135 +;; Copyright (C) 2005 Free Software Foundation, Inc.
 136 +;;
 137 +;; This file is part of GCC.
 138 +;;
 139 +;; GCC is free software; you can redistribute it and/or modify
 140 +;; it under the terms of the GNU General Public License as published by
 141 +;; the Free Software Foundation; either version 2, or (at your option)
 142 +;; any later version.
 143 +;;
 144 +;; GCC is distributed in the hope that it will be useful,
 145 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
 146 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 147 +;; GNU General Public License for more details.
 148 +;;
 149 +;; You should have received a copy of the GNU General Public License
 150 +;; along with GCC; see the file COPYING.  If not, write to
 151 +;; the Free Software Foundation, 59 Temple Place - Suite 330,
 152 +;; Boston, MA 02111-1307, USA.
 153 +
 154 +(define_c_enum "unspec" [
 155 +  UNSPEC_CLO
 156 +  UNSPEC_CTO
 157 +  UNSPEC_CACHE
 158 +  UNSPEC_CEIL_W_S
 159 +  UNSPEC_FLOOR_W_S
 160 +  UNSPEC_ROUND_W_S
 161 +])
 162 +
 163 +;; Min and max.
 164 +
 165 +(define_insn "sminsi3"
 166 +  [(set (match_operand:SI 0 "register_operand" "=d")
 167 +        (smin:SI (match_operand:SI 1 "register_operand" "d")
 168 +                 (match_operand:SI 2 "register_operand" "d")))]
 169 +  "TARGET_ALLEGREX"
 170 +  "min\t%0,%1,%2"
 171 +  [(set_attr "type"    "arith")
 172 +   (set_attr "mode"    "SI")])
 173 +
 174 +(define_insn "smaxsi3"
 175 +  [(set (match_operand:SI 0 "register_operand" "=d")
 176 +        (smax:SI (match_operand:SI 1 "register_operand" "d")
 177 +                 (match_operand:SI 2 "register_operand" "d")))]
 178 +  "TARGET_ALLEGREX"
 179 +  "max\t%0,%1,%2"
 180 +  [(set_attr "type"    "arith")
 181 +   (set_attr "mode"    "SI")])
 182 +
 183 +
 184 +;; Extended shift instructions.
 185 +
 186 +(define_insn "allegrex_bitrevsi2"
 187 +  [(set (match_operand:SI 0 "register_operand" "=d")
 188 +   (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
 189 +          UNSPEC_BITREV))]
 190 +  "TARGET_ALLEGREX"
 191 +  "bitrev\t%0,%1"
 192 +  [(set_attr "type"    "arith")
 193 +   (set_attr "mode"    "SI")])
 194 +
 195 +
 196 +;; Count leading ones, count trailing zeros, and count trailing ones (clz is
 197 +;; already defined).
 198 +
 199 +(define_insn "allegrex_closi2"
 200 +  [(set (match_operand:SI 0 "register_operand" "=d")
 201 +       (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
 202 +          UNSPEC_CLO))]
 203 +  "TARGET_ALLEGREX"
 204 +  "clo\t%0,%1"
 205 +  [(set_attr "type"    "clz")
 206 +   (set_attr "mode"    "SI")])
 207 +
 208 +
 209 +(define_expand "allegrex_ctzsi2"
 210 +  [(set (match_operand:SI 0 "register_operand")
 211 +       (ctz:SI (match_operand:SI 1 "register_operand")))]
 212 +  "TARGET_ALLEGREX"
 213 +{
 214 +  emit_insn (gen_allegrex_bitrevsi2 (operands[0], operands[1]));
 215 +  emit_insn (gen_clzsi2 (operands[0], operands[0]));
 216 +  DONE;
 217 +})
 218 +
 219 +(define_expand "allegrex_ctosi2"
 220 +  [(set (match_operand:SI 0 "register_operand")
 221 +       (unspec:SI [(match_operand:SI 1 "register_operand")]
 222 +          UNSPEC_CTO))]
 223 +  "TARGET_ALLEGREX"
 224 +{
 225 +  emit_insn (gen_allegrex_bitrevsi2 (operands[0], operands[1]));
 226 +  emit_insn (gen_allegrex_closi2 (operands[0], operands[0]));
 227 +  DONE;
 228 +})
 229 +
 230 +
 231 +;; Misc.
 232 +
 233 +(define_insn "allegrex_sync"
 234 +  [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
 235 +  "TARGET_ALLEGREX"
 236 +  "sync"
 237 +  [(set_attr "type"    "unknown")
 238 +   (set_attr "mode"    "none")])
 239 +
 240 +(define_insn "allegrex_cache"
 241 +  [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
 242 +            (match_operand:SI 1 "register_operand" "d")]
 243 +           UNSPEC_CACHE)]
 244 +  "TARGET_ALLEGREX"
 245 +  "cache\t%0,0(%1)"
 246 +  [(set_attr "type"    "unknown")
 247 +   (set_attr "mode"    "none")])
 248 +
 249 +
 250 +;; Floating-point builtins.
 251 +
 252 +(define_insn "allegrex_ceilsfsi2"
 253 +  [(set (match_operand:SI 0 "register_operand" "=f")
 254 +       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
 255 +          UNSPEC_CEIL_W_S))]
 256 +  "TARGET_ALLEGREX"
 257 +  "ceil.w.s\t%0,%1"
 258 +  [(set_attr "type"    "fcvt")
 259 +   (set_attr "mode"    "SF")])
 260 +
 261 +(define_insn "allegrex_floorsfsi2"
 262 +  [(set (match_operand:SI 0 "register_operand" "=f")
 263 +       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
 264 +          UNSPEC_FLOOR_W_S))]
 265 +  "TARGET_ALLEGREX"
 266 +  "floor.w.s\t%0,%1"
 267 +  [(set_attr "type"    "fcvt")
 268 +   (set_attr "mode"    "SF")])
 269 +
 270 +(define_insn "allegrex_roundsfsi2"
 271 +  [(set (match_operand:SI 0 "register_operand" "=f")
 272 +       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
 273 +          UNSPEC_ROUND_W_S))]
 274 +  "TARGET_ALLEGREX"
 275 +  "round.w.s\t%0,%1"
 276 +  [(set_attr "type"    "fcvt")
 277 +   (set_attr "mode"    "SF")])
 278 +
 279 diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
 280 index e2fcb8527ae..4deb7d32d15 100644
 281 --- a/gcc/config/mips/mips-cpus.def
 282 +++ b/gcc/config/mips/mips-cpus.def
 283 @@ -62,6 +62,7 @@ MIPS_CPU ("r3900", PROCESSOR_R3900, MIPS_ISA_MIPS1, 0)
 284
 285  /* MIPS II processors.  */
 286  MIPS_CPU ("r6000", PROCESSOR_R6000, MIPS_ISA_MIPS2, 0)
 287 +MIPS_CPU ("allegrex", PROCESSOR_ALLEGREX, MIPS_ISA_MIPS2, 0)
 288
 289  /* MIPS III processors.  */
 290  MIPS_CPU ("r4000", PROCESSOR_R4000, MIPS_ISA_MIPS3, 0)
 291 diff --git a/gcc/config/mips/mips-ftypes.def b/gcc/config/mips/mips-ftypes.def
 292 index b94788df5de..b9d8d131a08 100644
 293 --- a/gcc/config/mips/mips-ftypes.def
 294 +++ b/gcc/config/mips/mips-ftypes.def
 295 @@ -48,6 +48,8 @@ DEF_MIPS_FTYPE (2, (DI, SI, SI))
 296  DEF_MIPS_FTYPE (2, (DI, USI, USI))
 297  DEF_MIPS_FTYPE (2, (DI, V2DI, UQI))
 298
 299 +DEF_MIPS_FTYPE (1, (HI, HI))
 300 +
 301  DEF_MIPS_FTYPE (2, (INT, DF, DF))
 302  DEF_MIPS_FTYPE (2, (INT, SF, SF))
 303  DEF_MIPS_FTYPE (2, (INT, V2SF, V2SF))
 304 @@ -59,7 +61,10 @@ DEF_MIPS_FTYPE (1, (SF, V2SF))
 305  DEF_MIPS_FTYPE (1, (SF, V4SF))
 306
 307  DEF_MIPS_FTYPE (2, (SI, DI, SI))
 308 +DEF_MIPS_FTYPE (1, (SI, HI))
 309  DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
 310 +DEF_MIPS_FTYPE (1, (SI, QI))
 311 +DEF_MIPS_FTYPE (1, (SI, SF))
 312  DEF_MIPS_FTYPE (1, (SI, SI))
 313  DEF_MIPS_FTYPE (2, (SI, SI, SI))
 314  DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
 315 @@ -284,3 +289,4 @@ DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
 316  DEF_MIPS_FTYPE (3, (VOID, V4SF, POINTER, SI))
 317  DEF_MIPS_FTYPE (3, (VOID, V4SI, CVPOINTER, SI))
 318  DEF_MIPS_FTYPE (3, (VOID, V8HI, CVPOINTER, SI))
 319 +DEF_MIPS_FTYPE (1, (VOID, VOID))
 320 diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt
 321 index f3be044d975..69eefbb2a06 100644
 322 --- a/gcc/config/mips/mips-tables.opt
 323 +++ b/gcc/config/mips/mips-tables.opt
 324 @@ -160,554 +160,557 @@ EnumValue
 325  Enum(mips_arch_opt_value) String(6k) Value(17)
 326
 327  EnumValue
 328 -Enum(mips_arch_opt_value) String(r4000) Value(18) Canonical
 329 +Enum(mips_arch_opt_value) String(allegrex) Value(18) Canonical
 330
 331  EnumValue
 332 -Enum(mips_arch_opt_value) String(r4k) Value(18)
 333 +Enum(mips_arch_opt_value) String(r4000) Value(19) Canonical
 334
 335  EnumValue
 336 -Enum(mips_arch_opt_value) String(4000) Value(18)
 337 +Enum(mips_arch_opt_value) String(r4k) Value(19)
 338
 339  EnumValue
 340 -Enum(mips_arch_opt_value) String(4k) Value(18)
 341 +Enum(mips_arch_opt_value) String(4000) Value(19)
 342
 343  EnumValue
 344 -Enum(mips_arch_opt_value) String(vr4100) Value(19) Canonical
 345 +Enum(mips_arch_opt_value) String(4k) Value(19)
 346
 347  EnumValue
 348 -Enum(mips_arch_opt_value) String(4100) Value(19)
 349 +Enum(mips_arch_opt_value) String(vr4100) Value(20) Canonical
 350
 351  EnumValue
 352 -Enum(mips_arch_opt_value) String(r4100) Value(19)
 353 +Enum(mips_arch_opt_value) String(4100) Value(20)
 354
 355  EnumValue
 356 -Enum(mips_arch_opt_value) String(vr4111) Value(20) Canonical
 357 +Enum(mips_arch_opt_value) String(r4100) Value(20)
 358
 359  EnumValue
 360 -Enum(mips_arch_opt_value) String(4111) Value(20)
 361 +Enum(mips_arch_opt_value) String(vr4111) Value(21) Canonical
 362
 363  EnumValue
 364 -Enum(mips_arch_opt_value) String(r4111) Value(20)
 365 +Enum(mips_arch_opt_value) String(4111) Value(21)
 366
 367  EnumValue
 368 -Enum(mips_arch_opt_value) String(vr4120) Value(21) Canonical
 369 +Enum(mips_arch_opt_value) String(r4111) Value(21)
 370
 371  EnumValue
 372 -Enum(mips_arch_opt_value) String(4120) Value(21)
 373 +Enum(mips_arch_opt_value) String(vr4120) Value(22) Canonical
 374
 375  EnumValue
 376 -Enum(mips_arch_opt_value) String(r4120) Value(21)
 377 +Enum(mips_arch_opt_value) String(4120) Value(22)
 378
 379  EnumValue
 380 -Enum(mips_arch_opt_value) String(vr4130) Value(22) Canonical
 381 +Enum(mips_arch_opt_value) String(r4120) Value(22)
 382
 383  EnumValue
 384 -Enum(mips_arch_opt_value) String(4130) Value(22)
 385 +Enum(mips_arch_opt_value) String(vr4130) Value(23) Canonical
 386
 387  EnumValue
 388 -Enum(mips_arch_opt_value) String(r4130) Value(22)
 389 +Enum(mips_arch_opt_value) String(4130) Value(23)
 390
 391  EnumValue
 392 -Enum(mips_arch_opt_value) String(vr4300) Value(23) Canonical
 393 +Enum(mips_arch_opt_value) String(r4130) Value(23)
 394
 395  EnumValue
 396 -Enum(mips_arch_opt_value) String(4300) Value(23)
 397 +Enum(mips_arch_opt_value) String(vr4300) Value(24) Canonical
 398
 399  EnumValue
 400 -Enum(mips_arch_opt_value) String(r4300) Value(23)
 401 +Enum(mips_arch_opt_value) String(4300) Value(24)
 402
 403  EnumValue
 404 -Enum(mips_arch_opt_value) String(r4400) Value(24) Canonical
 405 +Enum(mips_arch_opt_value) String(r4300) Value(24)
 406
 407  EnumValue
 408 -Enum(mips_arch_opt_value) String(4400) Value(24)
 409 +Enum(mips_arch_opt_value) String(r4400) Value(25) Canonical
 410
 411  EnumValue
 412 -Enum(mips_arch_opt_value) String(r4600) Value(25) Canonical
 413 +Enum(mips_arch_opt_value) String(4400) Value(25)
 414
 415  EnumValue
 416 -Enum(mips_arch_opt_value) String(4600) Value(25)
 417 +Enum(mips_arch_opt_value) String(r4600) Value(26) Canonical
 418
 419  EnumValue
 420 -Enum(mips_arch_opt_value) String(orion) Value(26) Canonical
 421 +Enum(mips_arch_opt_value) String(4600) Value(26)
 422
 423  EnumValue
 424 -Enum(mips_arch_opt_value) String(r4650) Value(27) Canonical
 425 +Enum(mips_arch_opt_value) String(orion) Value(27) Canonical
 426
 427  EnumValue
 428 -Enum(mips_arch_opt_value) String(4650) Value(27)
 429 +Enum(mips_arch_opt_value) String(r4650) Value(28) Canonical
 430
 431  EnumValue
 432 -Enum(mips_arch_opt_value) String(r4700) Value(28) Canonical
 433 +Enum(mips_arch_opt_value) String(4650) Value(28)
 434
 435  EnumValue
 436 -Enum(mips_arch_opt_value) String(4700) Value(28)
 437 +Enum(mips_arch_opt_value) String(r4700) Value(29) Canonical
 438
 439  EnumValue
 440 -Enum(mips_arch_opt_value) String(r5900) Value(29) Canonical
 441 +Enum(mips_arch_opt_value) String(4700) Value(29)
 442
 443  EnumValue
 444 -Enum(mips_arch_opt_value) String(5900) Value(29)
 445 +Enum(mips_arch_opt_value) String(r5900) Value(30) Canonical
 446
 447  EnumValue
 448 -Enum(mips_arch_opt_value) String(loongson2e) Value(30) Canonical
 449 +Enum(mips_arch_opt_value) String(5900) Value(30)
 450
 451  EnumValue
 452 -Enum(mips_arch_opt_value) String(loongson2f) Value(31) Canonical
 453 +Enum(mips_arch_opt_value) String(loongson2e) Value(31) Canonical
 454
 455  EnumValue
 456 -Enum(mips_arch_opt_value) String(r8000) Value(32) Canonical
 457 +Enum(mips_arch_opt_value) String(loongson2f) Value(32) Canonical
 458
 459  EnumValue
 460 -Enum(mips_arch_opt_value) String(r8k) Value(32)
 461 +Enum(mips_arch_opt_value) String(r8000) Value(33) Canonical
 462
 463  EnumValue
 464 -Enum(mips_arch_opt_value) String(8000) Value(32)
 465 +Enum(mips_arch_opt_value) String(r8k) Value(33)
 466
 467  EnumValue
 468 -Enum(mips_arch_opt_value) String(8k) Value(32)
 469 +Enum(mips_arch_opt_value) String(8000) Value(33)
 470
 471  EnumValue
 472 -Enum(mips_arch_opt_value) String(r10000) Value(33) Canonical
 473 +Enum(mips_arch_opt_value) String(8k) Value(33)
 474
 475  EnumValue
 476 -Enum(mips_arch_opt_value) String(r10k) Value(33)
 477 +Enum(mips_arch_opt_value) String(r10000) Value(34) Canonical
 478
 479  EnumValue
 480 -Enum(mips_arch_opt_value) String(10000) Value(33)
 481 +Enum(mips_arch_opt_value) String(r10k) Value(34)
 482
 483  EnumValue
 484 -Enum(mips_arch_opt_value) String(10k) Value(33)
 485 +Enum(mips_arch_opt_value) String(10000) Value(34)
 486
 487  EnumValue
 488 -Enum(mips_arch_opt_value) String(r12000) Value(34) Canonical
 489 +Enum(mips_arch_opt_value) String(10k) Value(34)
 490
 491  EnumValue
 492 -Enum(mips_arch_opt_value) String(r12k) Value(34)
 493 +Enum(mips_arch_opt_value) String(r12000) Value(35) Canonical
 494
 495  EnumValue
 496 -Enum(mips_arch_opt_value) String(12000) Value(34)
 497 +Enum(mips_arch_opt_value) String(r12k) Value(35)
 498
 499  EnumValue
 500 -Enum(mips_arch_opt_value) String(12k) Value(34)
 501 +Enum(mips_arch_opt_value) String(12000) Value(35)
 502
 503  EnumValue
 504 -Enum(mips_arch_opt_value) String(r14000) Value(35) Canonical
 505 +Enum(mips_arch_opt_value) String(12k) Value(35)
 506
 507  EnumValue
 508 -Enum(mips_arch_opt_value) String(r14k) Value(35)
 509 +Enum(mips_arch_opt_value) String(r14000) Value(36) Canonical
 510
 511  EnumValue
 512 -Enum(mips_arch_opt_value) String(14000) Value(35)
 513 +Enum(mips_arch_opt_value) String(r14k) Value(36)
 514
 515  EnumValue
 516 -Enum(mips_arch_opt_value) String(14k) Value(35)
 517 +Enum(mips_arch_opt_value) String(14000) Value(36)
 518
 519  EnumValue
 520 -Enum(mips_arch_opt_value) String(r16000) Value(36) Canonical
 521 +Enum(mips_arch_opt_value) String(14k) Value(36)
 522
 523  EnumValue
 524 -Enum(mips_arch_opt_value) String(r16k) Value(36)
 525 +Enum(mips_arch_opt_value) String(r16000) Value(37) Canonical
 526
 527  EnumValue
 528 -Enum(mips_arch_opt_value) String(16000) Value(36)
 529 +Enum(mips_arch_opt_value) String(r16k) Value(37)
 530
 531  EnumValue
 532 -Enum(mips_arch_opt_value) String(16k) Value(36)
 533 +Enum(mips_arch_opt_value) String(16000) Value(37)
 534
 535  EnumValue
 536 -Enum(mips_arch_opt_value) String(vr5000) Value(37) Canonical
 537 +Enum(mips_arch_opt_value) String(16k) Value(37)
 538
 539  EnumValue
 540 -Enum(mips_arch_opt_value) String(vr5k) Value(37)
 541 +Enum(mips_arch_opt_value) String(vr5000) Value(38) Canonical
 542
 543  EnumValue
 544 -Enum(mips_arch_opt_value) String(5000) Value(37)
 545 +Enum(mips_arch_opt_value) String(vr5k) Value(38)
 546
 547  EnumValue
 548 -Enum(mips_arch_opt_value) String(5k) Value(37)
 549 +Enum(mips_arch_opt_value) String(5000) Value(38)
 550
 551  EnumValue
 552 -Enum(mips_arch_opt_value) String(r5000) Value(37)
 553 +Enum(mips_arch_opt_value) String(5k) Value(38)
 554
 555  EnumValue
 556 -Enum(mips_arch_opt_value) String(r5k) Value(37)
 557 +Enum(mips_arch_opt_value) String(r5000) Value(38)
 558
 559  EnumValue
 560 -Enum(mips_arch_opt_value) String(vr5400) Value(38) Canonical
 561 +Enum(mips_arch_opt_value) String(r5k) Value(38)
 562
 563  EnumValue
 564 -Enum(mips_arch_opt_value) String(5400) Value(38)
 565 +Enum(mips_arch_opt_value) String(vr5400) Value(39) Canonical
 566
 567  EnumValue
 568 -Enum(mips_arch_opt_value) String(r5400) Value(38)
 569 +Enum(mips_arch_opt_value) String(5400) Value(39)
 570
 571  EnumValue
 572 -Enum(mips_arch_opt_value) String(vr5500) Value(39) Canonical
 573 +Enum(mips_arch_opt_value) String(r5400) Value(39)
 574
 575  EnumValue
 576 -Enum(mips_arch_opt_value) String(5500) Value(39)
 577 +Enum(mips_arch_opt_value) String(vr5500) Value(40) Canonical
 578
 579  EnumValue
 580 -Enum(mips_arch_opt_value) String(r5500) Value(39)
 581 +Enum(mips_arch_opt_value) String(5500) Value(40)
 582
 583  EnumValue
 584 -Enum(mips_arch_opt_value) String(rm7000) Value(40) Canonical
 585 +Enum(mips_arch_opt_value) String(r5500) Value(40)
 586
 587  EnumValue
 588 -Enum(mips_arch_opt_value) String(rm7k) Value(40)
 589 +Enum(mips_arch_opt_value) String(rm7000) Value(41) Canonical
 590
 591  EnumValue
 592 -Enum(mips_arch_opt_value) String(7000) Value(40)
 593 +Enum(mips_arch_opt_value) String(rm7k) Value(41)
 594
 595  EnumValue
 596 -Enum(mips_arch_opt_value) String(7k) Value(40)
 597 +Enum(mips_arch_opt_value) String(7000) Value(41)
 598
 599  EnumValue
 600 -Enum(mips_arch_opt_value) String(r7000) Value(40)
 601 +Enum(mips_arch_opt_value) String(7k) Value(41)
 602
 603  EnumValue
 604 -Enum(mips_arch_opt_value) String(r7k) Value(40)
 605 +Enum(mips_arch_opt_value) String(r7000) Value(41)
 606
 607  EnumValue
 608 -Enum(mips_arch_opt_value) String(rm9000) Value(41) Canonical
 609 +Enum(mips_arch_opt_value) String(r7k) Value(41)
 610
 611  EnumValue
 612 -Enum(mips_arch_opt_value) String(rm9k) Value(41)
 613 +Enum(mips_arch_opt_value) String(rm9000) Value(42) Canonical
 614
 615  EnumValue
 616 -Enum(mips_arch_opt_value) String(9000) Value(41)
 617 +Enum(mips_arch_opt_value) String(rm9k) Value(42)
 618
 619  EnumValue
 620 -Enum(mips_arch_opt_value) String(9k) Value(41)
 621 +Enum(mips_arch_opt_value) String(9000) Value(42)
 622
 623  EnumValue
 624 -Enum(mips_arch_opt_value) String(r9000) Value(41)
 625 +Enum(mips_arch_opt_value) String(9k) Value(42)
 626
 627  EnumValue
 628 -Enum(mips_arch_opt_value) String(r9k) Value(41)
 629 +Enum(mips_arch_opt_value) String(r9000) Value(42)
 630
 631  EnumValue
 632 -Enum(mips_arch_opt_value) String(4kc) Value(42) Canonical
 633 +Enum(mips_arch_opt_value) String(r9k) Value(42)
 634
 635  EnumValue
 636 -Enum(mips_arch_opt_value) String(r4kc) Value(42)
 637 +Enum(mips_arch_opt_value) String(4kc) Value(43) Canonical
 638
 639  EnumValue
 640 -Enum(mips_arch_opt_value) String(4km) Value(43) Canonical
 641 +Enum(mips_arch_opt_value) String(r4kc) Value(43)
 642
 643  EnumValue
 644 -Enum(mips_arch_opt_value) String(r4km) Value(43)
 645 +Enum(mips_arch_opt_value) String(4km) Value(44) Canonical
 646
 647  EnumValue
 648 -Enum(mips_arch_opt_value) String(4kp) Value(44) Canonical
 649 +Enum(mips_arch_opt_value) String(r4km) Value(44)
 650
 651  EnumValue
 652 -Enum(mips_arch_opt_value) String(r4kp) Value(44)
 653 +Enum(mips_arch_opt_value) String(4kp) Value(45) Canonical
 654
 655  EnumValue
 656 -Enum(mips_arch_opt_value) String(4ksc) Value(45) Canonical
 657 +Enum(mips_arch_opt_value) String(r4kp) Value(45)
 658
 659  EnumValue
 660 -Enum(mips_arch_opt_value) String(r4ksc) Value(45)
 661 +Enum(mips_arch_opt_value) String(4ksc) Value(46) Canonical
 662
 663  EnumValue
 664 -Enum(mips_arch_opt_value) String(m4k) Value(46) Canonical
 665 +Enum(mips_arch_opt_value) String(r4ksc) Value(46)
 666
 667  EnumValue
 668 -Enum(mips_arch_opt_value) String(m14kc) Value(47) Canonical
 669 +Enum(mips_arch_opt_value) String(m4k) Value(47) Canonical
 670
 671  EnumValue
 672 -Enum(mips_arch_opt_value) String(m14k) Value(48) Canonical
 673 +Enum(mips_arch_opt_value) String(m14kc) Value(48) Canonical
 674
 675  EnumValue
 676 -Enum(mips_arch_opt_value) String(m14ke) Value(49) Canonical
 677 +Enum(mips_arch_opt_value) String(m14k) Value(49) Canonical
 678
 679  EnumValue
 680 -Enum(mips_arch_opt_value) String(m14kec) Value(50) Canonical
 681 +Enum(mips_arch_opt_value) String(m14ke) Value(50) Canonical
 682
 683  EnumValue
 684 -Enum(mips_arch_opt_value) String(4kec) Value(51) Canonical
 685 +Enum(mips_arch_opt_value) String(m14kec) Value(51) Canonical
 686
 687  EnumValue
 688 -Enum(mips_arch_opt_value) String(r4kec) Value(51)
 689 +Enum(mips_arch_opt_value) String(4kec) Value(52) Canonical
 690
 691  EnumValue
 692 -Enum(mips_arch_opt_value) String(4kem) Value(52) Canonical
 693 +Enum(mips_arch_opt_value) String(r4kec) Value(52)
 694
 695  EnumValue
 696 -Enum(mips_arch_opt_value) String(r4kem) Value(52)
 697 +Enum(mips_arch_opt_value) String(4kem) Value(53) Canonical
 698
 699  EnumValue
 700 -Enum(mips_arch_opt_value) String(4kep) Value(53) Canonical
 701 +Enum(mips_arch_opt_value) String(r4kem) Value(53)
 702
 703  EnumValue
 704 -Enum(mips_arch_opt_value) String(r4kep) Value(53)
 705 +Enum(mips_arch_opt_value) String(4kep) Value(54) Canonical
 706
 707  EnumValue
 708 -Enum(mips_arch_opt_value) String(4ksd) Value(54) Canonical
 709 +Enum(mips_arch_opt_value) String(r4kep) Value(54)
 710
 711  EnumValue
 712 -Enum(mips_arch_opt_value) String(r4ksd) Value(54)
 713 +Enum(mips_arch_opt_value) String(4ksd) Value(55) Canonical
 714
 715  EnumValue
 716 -Enum(mips_arch_opt_value) String(24kc) Value(55) Canonical
 717 +Enum(mips_arch_opt_value) String(r4ksd) Value(55)
 718
 719  EnumValue
 720 -Enum(mips_arch_opt_value) String(r24kc) Value(55)
 721 +Enum(mips_arch_opt_value) String(24kc) Value(56) Canonical
 722
 723  EnumValue
 724 -Enum(mips_arch_opt_value) String(24kf2_1) Value(56) Canonical
 725 +Enum(mips_arch_opt_value) String(r24kc) Value(56)
 726
 727  EnumValue
 728 -Enum(mips_arch_opt_value) String(r24kf2_1) Value(56)
 729 +Enum(mips_arch_opt_value) String(24kf2_1) Value(57) Canonical
 730
 731  EnumValue
 732 -Enum(mips_arch_opt_value) String(24kf) Value(57) Canonical
 733 +Enum(mips_arch_opt_value) String(r24kf2_1) Value(57)
 734
 735  EnumValue
 736 -Enum(mips_arch_opt_value) String(r24kf) Value(57)
 737 +Enum(mips_arch_opt_value) String(24kf) Value(58) Canonical
 738
 739  EnumValue
 740 -Enum(mips_arch_opt_value) String(24kf1_1) Value(58) Canonical
 741 +Enum(mips_arch_opt_value) String(r24kf) Value(58)
 742
 743  EnumValue
 744 -Enum(mips_arch_opt_value) String(r24kf1_1) Value(58)
 745 +Enum(mips_arch_opt_value) String(24kf1_1) Value(59) Canonical
 746
 747  EnumValue
 748 -Enum(mips_arch_opt_value) String(24kfx) Value(59) Canonical
 749 +Enum(mips_arch_opt_value) String(r24kf1_1) Value(59)
 750
 751  EnumValue
 752 -Enum(mips_arch_opt_value) String(r24kfx) Value(59)
 753 +Enum(mips_arch_opt_value) String(24kfx) Value(60) Canonical
 754
 755  EnumValue
 756 -Enum(mips_arch_opt_value) String(24kx) Value(60) Canonical
 757 +Enum(mips_arch_opt_value) String(r24kfx) Value(60)
 758
 759  EnumValue
 760 -Enum(mips_arch_opt_value) String(r24kx) Value(60)
 761 +Enum(mips_arch_opt_value) String(24kx) Value(61) Canonical
 762
 763  EnumValue
 764 -Enum(mips_arch_opt_value) String(24kec) Value(61) Canonical
 765 +Enum(mips_arch_opt_value) String(r24kx) Value(61)
 766
 767  EnumValue
 768 -Enum(mips_arch_opt_value) String(r24kec) Value(61)
 769 +Enum(mips_arch_opt_value) String(24kec) Value(62) Canonical
 770
 771  EnumValue
 772 -Enum(mips_arch_opt_value) String(24kef2_1) Value(62) Canonical
 773 +Enum(mips_arch_opt_value) String(r24kec) Value(62)
 774
 775  EnumValue
 776 -Enum(mips_arch_opt_value) String(r24kef2_1) Value(62)
 777 +Enum(mips_arch_opt_value) String(24kef2_1) Value(63) Canonical
 778
 779  EnumValue
 780 -Enum(mips_arch_opt_value) String(24kef) Value(63) Canonical
 781 +Enum(mips_arch_opt_value) String(r24kef2_1) Value(63)
 782
 783  EnumValue
 784 -Enum(mips_arch_opt_value) String(r24kef) Value(63)
 785 +Enum(mips_arch_opt_value) String(24kef) Value(64) Canonical
 786
 787  EnumValue
 788 -Enum(mips_arch_opt_value) String(24kef1_1) Value(64) Canonical
 789 +Enum(mips_arch_opt_value) String(r24kef) Value(64)
 790
 791  EnumValue
 792 -Enum(mips_arch_opt_value) String(r24kef1_1) Value(64)
 793 +Enum(mips_arch_opt_value) String(24kef1_1) Value(65) Canonical
 794
 795  EnumValue
 796 -Enum(mips_arch_opt_value) String(24kefx) Value(65) Canonical
 797 +Enum(mips_arch_opt_value) String(r24kef1_1) Value(65)
 798
 799  EnumValue
 800 -Enum(mips_arch_opt_value) String(r24kefx) Value(65)
 801 +Enum(mips_arch_opt_value) String(24kefx) Value(66) Canonical
 802
 803  EnumValue
 804 -Enum(mips_arch_opt_value) String(24kex) Value(66) Canonical
 805 +Enum(mips_arch_opt_value) String(r24kefx) Value(66)
 806
 807  EnumValue
 808 -Enum(mips_arch_opt_value) String(r24kex) Value(66)
 809 +Enum(mips_arch_opt_value) String(24kex) Value(67) Canonical
 810
 811  EnumValue
 812 -Enum(mips_arch_opt_value) String(34kc) Value(67) Canonical
 813 +Enum(mips_arch_opt_value) String(r24kex) Value(67)
 814
 815  EnumValue
 816 -Enum(mips_arch_opt_value) String(r34kc) Value(67)
 817 +Enum(mips_arch_opt_value) String(34kc) Value(68) Canonical
 818
 819  EnumValue
 820 -Enum(mips_arch_opt_value) String(34kf2_1) Value(68) Canonical
 821 +Enum(mips_arch_opt_value) String(r34kc) Value(68)
 822
 823  EnumValue
 824 -Enum(mips_arch_opt_value) String(r34kf2_1) Value(68)
 825 +Enum(mips_arch_opt_value) String(34kf2_1) Value(69) Canonical
 826
 827  EnumValue
 828 -Enum(mips_arch_opt_value) String(34kf) Value(69) Canonical
 829 +Enum(mips_arch_opt_value) String(r34kf2_1) Value(69)
 830
 831  EnumValue
 832 -Enum(mips_arch_opt_value) String(r34kf) Value(69)
 833 +Enum(mips_arch_opt_value) String(34kf) Value(70) Canonical
 834
 835  EnumValue
 836 -Enum(mips_arch_opt_value) String(34kf1_1) Value(70) Canonical
 837 +Enum(mips_arch_opt_value) String(r34kf) Value(70)
 838
 839  EnumValue
 840 -Enum(mips_arch_opt_value) String(r34kf1_1) Value(70)
 841 +Enum(mips_arch_opt_value) String(34kf1_1) Value(71) Canonical
 842
 843  EnumValue
 844 -Enum(mips_arch_opt_value) String(34kfx) Value(71) Canonical
 845 +Enum(mips_arch_opt_value) String(r34kf1_1) Value(71)
 846
 847  EnumValue
 848 -Enum(mips_arch_opt_value) String(r34kfx) Value(71)
 849 +Enum(mips_arch_opt_value) String(34kfx) Value(72) Canonical
 850
 851  EnumValue
 852 -Enum(mips_arch_opt_value) String(34kx) Value(72) Canonical
 853 +Enum(mips_arch_opt_value) String(r34kfx) Value(72)
 854
 855  EnumValue
 856 -Enum(mips_arch_opt_value) String(r34kx) Value(72)
 857 +Enum(mips_arch_opt_value) String(34kx) Value(73) Canonical
 858
 859  EnumValue
 860 -Enum(mips_arch_opt_value) String(34kn) Value(73) Canonical
 861 +Enum(mips_arch_opt_value) String(r34kx) Value(73)
 862
 863  EnumValue
 864 -Enum(mips_arch_opt_value) String(r34kn) Value(73)
 865 +Enum(mips_arch_opt_value) String(34kn) Value(74) Canonical
 866
 867  EnumValue
 868 -Enum(mips_arch_opt_value) String(74kc) Value(74) Canonical
 869 +Enum(mips_arch_opt_value) String(r34kn) Value(74)
 870
 871  EnumValue
 872 -Enum(mips_arch_opt_value) String(r74kc) Value(74)
 873 +Enum(mips_arch_opt_value) String(74kc) Value(75) Canonical
 874
 875  EnumValue
 876 -Enum(mips_arch_opt_value) String(74kf2_1) Value(75) Canonical
 877 +Enum(mips_arch_opt_value) String(r74kc) Value(75)
 878
 879  EnumValue
 880 -Enum(mips_arch_opt_value) String(r74kf2_1) Value(75)
 881 +Enum(mips_arch_opt_value) String(74kf2_1) Value(76) Canonical
 882
 883  EnumValue
 884 -Enum(mips_arch_opt_value) String(74kf) Value(76) Canonical
 885 +Enum(mips_arch_opt_value) String(r74kf2_1) Value(76)
 886
 887  EnumValue
 888 -Enum(mips_arch_opt_value) String(r74kf) Value(76)
 889 +Enum(mips_arch_opt_value) String(74kf) Value(77) Canonical
 890
 891  EnumValue
 892 -Enum(mips_arch_opt_value) String(74kf1_1) Value(77) Canonical
 893 +Enum(mips_arch_opt_value) String(r74kf) Value(77)
 894
 895  EnumValue
 896 -Enum(mips_arch_opt_value) String(r74kf1_1) Value(77)
 897 +Enum(mips_arch_opt_value) String(74kf1_1) Value(78) Canonical
 898
 899  EnumValue
 900 -Enum(mips_arch_opt_value) String(74kfx) Value(78) Canonical
 901 +Enum(mips_arch_opt_value) String(r74kf1_1) Value(78)
 902
 903  EnumValue
 904 -Enum(mips_arch_opt_value) String(r74kfx) Value(78)
 905 +Enum(mips_arch_opt_value) String(74kfx) Value(79) Canonical
 906
 907  EnumValue
 908 -Enum(mips_arch_opt_value) String(74kx) Value(79) Canonical
 909 +Enum(mips_arch_opt_value) String(r74kfx) Value(79)
 910
 911  EnumValue
 912 -Enum(mips_arch_opt_value) String(r74kx) Value(79)
 913 +Enum(mips_arch_opt_value) String(74kx) Value(80) Canonical
 914
 915  EnumValue
 916 -Enum(mips_arch_opt_value) String(74kf3_2) Value(80) Canonical
 917 +Enum(mips_arch_opt_value) String(r74kx) Value(80)
 918
 919  EnumValue
 920 -Enum(mips_arch_opt_value) String(r74kf3_2) Value(80)
 921 +Enum(mips_arch_opt_value) String(74kf3_2) Value(81) Canonical
 922
 923  EnumValue
 924 -Enum(mips_arch_opt_value) String(1004kc) Value(81) Canonical
 925 +Enum(mips_arch_opt_value) String(r74kf3_2) Value(81)
 926
 927  EnumValue
 928 -Enum(mips_arch_opt_value) String(r1004kc) Value(81)
 929 +Enum(mips_arch_opt_value) String(1004kc) Value(82) Canonical
 930
 931  EnumValue
 932 -Enum(mips_arch_opt_value) String(1004kf2_1) Value(82) Canonical
 933 +Enum(mips_arch_opt_value) String(r1004kc) Value(82)
 934
 935  EnumValue
 936 -Enum(mips_arch_opt_value) String(r1004kf2_1) Value(82)
 937 +Enum(mips_arch_opt_value) String(1004kf2_1) Value(83) Canonical
 938
 939  EnumValue
 940 -Enum(mips_arch_opt_value) String(1004kf) Value(83) Canonical
 941 +Enum(mips_arch_opt_value) String(r1004kf2_1) Value(83)
 942
 943  EnumValue
 944 -Enum(mips_arch_opt_value) String(r1004kf) Value(83)
 945 +Enum(mips_arch_opt_value) String(1004kf) Value(84) Canonical
 946
 947  EnumValue
 948 -Enum(mips_arch_opt_value) String(1004kf1_1) Value(84) Canonical
 949 +Enum(mips_arch_opt_value) String(r1004kf) Value(84)
 950
 951  EnumValue
 952 -Enum(mips_arch_opt_value) String(r1004kf1_1) Value(84)
 953 +Enum(mips_arch_opt_value) String(1004kf1_1) Value(85) Canonical
 954
 955  EnumValue
 956 -Enum(mips_arch_opt_value) String(interaptiv) Value(85) Canonical
 957 +Enum(mips_arch_opt_value) String(r1004kf1_1) Value(85)
 958
 959  EnumValue
 960 -Enum(mips_arch_opt_value) String(p5600) Value(86) Canonical
 961 +Enum(mips_arch_opt_value) String(interaptiv) Value(86) Canonical
 962
 963  EnumValue
 964 -Enum(mips_arch_opt_value) String(m5100) Value(87) Canonical
 965 +Enum(mips_arch_opt_value) String(p5600) Value(87) Canonical
 966
 967  EnumValue
 968 -Enum(mips_arch_opt_value) String(m5101) Value(88) Canonical
 969 +Enum(mips_arch_opt_value) String(m5100) Value(88) Canonical
 970
 971  EnumValue
 972 -Enum(mips_arch_opt_value) String(5kc) Value(89) Canonical
 973 +Enum(mips_arch_opt_value) String(m5101) Value(89) Canonical
 974
 975  EnumValue
 976 -Enum(mips_arch_opt_value) String(r5kc) Value(89)
 977 +Enum(mips_arch_opt_value) String(5kc) Value(90) Canonical
 978
 979  EnumValue
 980 -Enum(mips_arch_opt_value) String(5kf) Value(90) Canonical
 981 +Enum(mips_arch_opt_value) String(r5kc) Value(90)
 982
 983  EnumValue
 984 -Enum(mips_arch_opt_value) String(r5kf) Value(90)
 985 +Enum(mips_arch_opt_value) String(5kf) Value(91) Canonical
 986
 987  EnumValue
 988 -Enum(mips_arch_opt_value) String(20kc) Value(91) Canonical
 989 +Enum(mips_arch_opt_value) String(r5kf) Value(91)
 990
 991  EnumValue
 992 -Enum(mips_arch_opt_value) String(r20kc) Value(91)
 993 +Enum(mips_arch_opt_value) String(20kc) Value(92) Canonical
 994
 995  EnumValue
 996 -Enum(mips_arch_opt_value) String(sb1) Value(92) Canonical
 997 +Enum(mips_arch_opt_value) String(r20kc) Value(92)
 998
 999  EnumValue
1000 -Enum(mips_arch_opt_value) String(sb1a) Value(93) Canonical
1001 +Enum(mips_arch_opt_value) String(sb1) Value(93) Canonical
1002
1003  EnumValue
1004 -Enum(mips_arch_opt_value) String(sr71000) Value(94) Canonical
1005 +Enum(mips_arch_opt_value) String(sb1a) Value(94) Canonical
1006
1007  EnumValue
1008 -Enum(mips_arch_opt_value) String(sr71k) Value(94)
1009 +Enum(mips_arch_opt_value) String(sr71000) Value(95) Canonical
1010
1011  EnumValue
1012 -Enum(mips_arch_opt_value) String(xlr) Value(95) Canonical
1013 +Enum(mips_arch_opt_value) String(sr71k) Value(95)
1014
1015  EnumValue
1016 -Enum(mips_arch_opt_value) String(loongson3a) Value(96) Canonical
1017 +Enum(mips_arch_opt_value) String(xlr) Value(96) Canonical
1018
1019  EnumValue
1020 -Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical
1021 +Enum(mips_arch_opt_value) String(loongson3a) Value(97) Canonical
1022
1023  EnumValue
1024 -Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical
1025 +Enum(mips_arch_opt_value) String(gs464) Value(98) Canonical
1026
1027  EnumValue
1028 -Enum(mips_arch_opt_value) String(gs264e) Value(99) Canonical
1029 +Enum(mips_arch_opt_value) String(gs464e) Value(99) Canonical
1030
1031  EnumValue
1032 -Enum(mips_arch_opt_value) String(octeon) Value(100) Canonical
1033 +Enum(mips_arch_opt_value) String(gs264e) Value(100) Canonical
1034
1035  EnumValue
1036 -Enum(mips_arch_opt_value) String(octeon+) Value(101) Canonical
1037 +Enum(mips_arch_opt_value) String(octeon) Value(101) Canonical
1038
1039  EnumValue
1040 -Enum(mips_arch_opt_value) String(octeon2) Value(102) Canonical
1041 +Enum(mips_arch_opt_value) String(octeon+) Value(102) Canonical
1042
1043  EnumValue
1044 -Enum(mips_arch_opt_value) String(octeon3) Value(103) Canonical
1045 +Enum(mips_arch_opt_value) String(octeon2) Value(103) Canonical
1046
1047  EnumValue
1048 -Enum(mips_arch_opt_value) String(xlp) Value(104) Canonical
1049 +Enum(mips_arch_opt_value) String(octeon3) Value(104) Canonical
1050
1051  EnumValue
1052 -Enum(mips_arch_opt_value) String(i6400) Value(105) Canonical
1053 +Enum(mips_arch_opt_value) String(xlp) Value(105) Canonical
1054
1055  EnumValue
1056 -Enum(mips_arch_opt_value) String(i6500) Value(106) Canonical
1057 +Enum(mips_arch_opt_value) String(i6400) Value(106) Canonical
1058
1059  EnumValue
1060 -Enum(mips_arch_opt_value) String(p6600) Value(107) Canonical
1061 +Enum(mips_arch_opt_value) String(i6500) Value(107) Canonical
1062 +
1063 +EnumValue
1064 +Enum(mips_arch_opt_value) String(p6600) Value(108) Canonical
1065
1066 diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
1067 index ca822758b41..a1d83c5a759 100644
1068 --- a/gcc/config/mips/mips.cc
1069 +++ b/gcc/config/mips/mips.cc
1070 @@ -265,7 +265,12 @@ enum mips_builtin_type {
1071    MIPS_BUILTIN_MSA_TEST_BRANCH,
1072
1073    /* For generating bposge32 branch instructions in MIPS32 DSP ASE.  */
1074 -  MIPS_BUILTIN_BPOSGE32
1075 +  MIPS_BUILTIN_BPOSGE32,
1076 +
1077 +  /* The builtin corresponds to the ALLEGREX cache instruction.  Operand 0
1078 +     is the function code (must be less than 32) and operand 1 is the base
1079 +     address.  */
1080 +  MIPS_BUILTIN_CACHE
1081  };
1082
1083  /* Invoke MACRO (COND) for each C.cond.fmt condition.  */
1084 @@ -471,6 +476,10 @@ struct mips_asm_switch mips_noat = { "at", 0 };
1085     normal branch.  */
1086  static bool mips_branch_likely;
1087
1088 +/* Preferred stack boundary for proper stack vars alignment */
1089 +unsigned int mips_preferred_stack_boundary;
1090 +unsigned int mips_preferred_stack_align;
1091 +
1092  /* The current instruction-set architecture.  */
1093  enum processor mips_arch;
1094  const struct mips_cpu_info *mips_arch_info;
1095 @@ -832,6 +841,9 @@ static const struct mips_rtx_cost_data
1096                      1,           /* branch_cost */
1097                      4            /* memory_latency */
1098    },
1099 +  { /* Allegrex */
1100 +    DEFAULT_COSTS
1101 +  },
1102    { /* Loongson-2E */
1103      DEFAULT_COSTS
1104    },
1105 @@ -15428,6 +15440,7 @@ AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
1106  AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
1107  AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI)
1108  AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
1109 +AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
1110  AVAIL_NON_MIPS16 (msa, TARGET_MSA)
1111
1112  /* Construct a mips_builtin_description from the given arguments.
1113 @@ -15534,6 +15547,24 @@ AVAIL_NON_MIPS16 (msa, TARGET_MSA)
1114    MIPS_BUILTIN (bposge, f, "bposge" #VALUE,                            \
1115                 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL, false)
1116
1117 +/* Same as the above, but mapped to an instruction that doesn't share the
1118 +   NAME.  NAME is the name of the builtin without the builtin prefix.  */
1119 +#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
1120 +  { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME,             \
1121 +    MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
1122 +
1123 +/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
1124 +   CODE_FOR_allegrex_<INSN>.  FUNCTION_TYPE and TARGET_FLAGS are
1125 +   builtin_description fields.  */
1126 +#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS)   \
1127 +  { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN,            \
1128 +    MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex, false }
1129 +
1130 +/* Define a builtin with a specific function TYPE.  */
1131 +#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS)  \
1132 +  { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN,            \
1133 +    MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
1134 +
1135  /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
1136     for instruction CODE_FOR_loongson_<INSN>.  FUNCTION_TYPE is a
1137     builtin_description field.  */
1138 @@ -16017,6 +16048,37 @@ static const struct mips_builtin_description mips_builtins[] = {
1139    DIRECT_BUILTIN_PURE (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
1140    DIRECT_BUILTIN_PURE (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
1141
1142 +  /* Builtin functions for the Sony ALLEGREX processor.
1143 +   These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
1144 +   to maintain compatibility with Sony's ALLEGREX GCC port.
1145 +   Some of the builtins may seem redundant, but they are the same as the
1146 +   builtins defined in the Sony compiler.  I chose to map redundant and
1147 +   trivial builtins to the original instruction instead of creating
1148 +   duplicate patterns specifically for the ALLEGREX (as Sony does).  */
1149 +
1150 +  DIRECT_ALLEGREX_NAMED_BUILTIN(bitrev, allegrex_bitrevsi2, MIPS_SI_FTYPE_SI, 0),
1151 +  DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
1152 +  DIRECT_ALLEGREX_NAMED_BUILTIN(clo, allegrex_closi2, MIPS_SI_FTYPE_SI, 0),
1153 +  DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, allegrex_ctzsi2, MIPS_SI_FTYPE_SI, 0),
1154 +  DIRECT_ALLEGREX_NAMED_BUILTIN(cto, allegrex_ctosi2, MIPS_SI_FTYPE_SI, 0),
1155 +  DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
1156 +
1157 +  DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
1158 +  DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
1159 +  DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
1160 +  DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
1161 +  DIRECT_ALLEGREX_NAMED_BUILTIN(wsbw, bswapsi2, MIPS_SI_FTYPE_SI, 0),
1162 +  DIRECT_ALLEGREX_NAMED_BUILTIN(wsbh, bswaphi2, MIPS_HI_FTYPE_HI, 0),
1163 +
1164 +  DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
1165 +  SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
1166 +
1167 +  DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
1168 +  DIRECT_ALLEGREX_NAMED_BUILTIN(ceil_w_s, allegrex_ceilsfsi2, MIPS_SI_FTYPE_SF, 0),
1169 +  DIRECT_ALLEGREX_NAMED_BUILTIN(floor_w_s, allegrex_floorsfsi2, MIPS_SI_FTYPE_SF, 0),
1170 +  DIRECT_ALLEGREX_NAMED_BUILTIN(round_w_s, allegrex_roundsfsi2, MIPS_SI_FTYPE_SF, 0),
1171 +  DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
1172 +
1173    /* Builtin functions for ST Microelectronics Loongson-2E/2F cores.  */
1174    LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
1175    LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
1176 @@ -17411,6 +17473,26 @@ mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
1177                                        const1_rtx, const0_rtx);
1178  }
1179
1180 +/* Expand a __builtin_allegrex_cache() function.  Make sure the passed
1181 +   cache function code is less than 32.  */
1182 +
1183 +static rtx
1184 +mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
1185 +{
1186 +  int argno;
1187 +  struct expand_operand ops[2];
1188 +
1189 +  for (argno = 0; argno < 2; argno++)
1190 +    mips_prepare_builtin_arg (&ops[argno], exp, argno);
1191 +
1192 +  if (GET_CODE(ops[0].value) != CONST_INT ||
1193 +      INTVAL(ops[0].value) < 0 || INTVAL(ops[0].value) > 0x1f)
1194 +    error("Invalid first argument for cache builtin (0 <= arg <= 31)");
1195 +
1196 +  emit_insn(mips_expand_builtin_insn (icode, 2, ops, false));
1197 +  return target;
1198 +}
1199 +
1200  /* Implement TARGET_EXPAND_BUILTIN.  */
1201
1202  static rtx
1203 @@ -17459,6 +17541,9 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
1204
1205      case MIPS_BUILTIN_BPOSGE32:
1206        return mips_expand_builtin_bposge (d->builtin_type, target);
1207 +
1208 +    case MIPS_BUILTIN_CACHE:
1209 +      return mips_expand_builtin_cache (d->icode, target, exp);
1210      }
1211    gcc_unreachable ();
1212  }
1213 @@ -20598,6 +20683,22 @@ mips_option_override (void)
1214    if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
1215      REAL_MODE_FORMAT (SFmode) = &spu_single_format;
1216
1217 +  /* Validate -mpreferred-stack-boundary= value, or provide default.
1218 +     The default of 128-bit is for newABI else 64-bit.  */
1219 +  mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
1220 +  mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
1221 +  if (mips_preferred_stack_boundary_string)
1222 +    {
1223 +      i = atoi (mips_preferred_stack_boundary_string);
1224 +      if (i < 2 || i > 12)
1225 +       error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
1226 +      else
1227 +        {
1228 +          mips_preferred_stack_align = (1 << i);
1229 +          mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
1230 +        }
1231 +    }
1232 +
1233    mips_register_frame_header_opt ();
1234  }
1235
1236 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
1237 index 6daf6d37165..ac1eb96b0d0 100644
1238 --- a/gcc/config/mips/mips.h
1239 +++ b/gcc/config/mips/mips.h
1240 @@ -308,6 +308,7 @@ struct mips_cpu_info {
1241                                      || mips_arch == PROCESSOR_SB1A)
1242  #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
1243  #define TARGET_XLP                  (mips_arch == PROCESSOR_XLP)
1244 +#define TARGET_ALLEGREX             (mips_arch == PROCESSOR_ALLEGREX)
1245
1246  /* Scheduling target defines.  */
1247  #define TUNE_20KC                  (mips_tune == PROCESSOR_20KC)
1248 @@ -342,6 +343,7 @@ struct mips_cpu_info {
1249  #define TUNE_P5600                  (mips_tune == PROCESSOR_P5600)
1250  #define TUNE_I6400                  (mips_tune == PROCESSOR_I6400)
1251  #define TUNE_P6600                  (mips_tune == PROCESSOR_P6600)
1252 +#define TUNE_ALLEGREX               (mips_tune == PROCESSOR_ALLEGREX)
1253
1254  /* True if the pre-reload scheduler should try to create chains of
1255     multiply-add or multiply-subtract instructions.  For example,
1256 @@ -1078,6 +1080,7 @@ struct mips_cpu_info {
1257     ST Loongson 2E/2F.  */
1258  #define ISA_HAS_CONDMOVE        (ISA_HAS_FP_CONDMOVE                   \
1259                                  || TARGET_MIPS5900                     \
1260 +                                || TARGET_ALLEGREX                     \
1261                                  || TARGET_LOONGSON_2EF)
1262
1263  /* ISA has LDC1 and SDC1.  */
1264 @@ -1120,11 +1123,13 @@ struct mips_cpu_info {
1265
1266  /* ISA has conditional trap instructions.  */
1267  #define ISA_HAS_COND_TRAP      (!ISA_MIPS1                             \
1268 +                                && !TARGET_ALLEGREX                    \
1269                                  && !TARGET_MIPS16)
1270
1271  /* ISA has conditional trap with immediate instructions.  */
1272  #define ISA_HAS_COND_TRAPI     (!ISA_MIPS1                             \
1273                                  && mips_isa_rev <= 5                   \
1274 +                                && !TARGET_ALLEGREX                    \
1275                                  && !TARGET_MIPS16)
1276
1277  /* ISA has integer multiply-accumulate instructions, madd and msub.  */
1278 @@ -1183,7 +1188,8 @@ struct mips_cpu_info {
1279  #define ISA_HAS_IEEE_754_2008  (mips_isa_rev >= 2)
1280
1281  /* ISA has count leading zeroes/ones instruction (not implemented).  */
1282 -#define ISA_HAS_CLZ_CLO                (mips_isa_rev >= 1 && !TARGET_MIPS16)
1283 +#define ISA_HAS_CLZ_CLO                ((mips_isa_rev >= 1 && !TARGET_MIPS16)   \
1284 +                                 || TARGET_ALLEGREX)
1285
1286  /* ISA has count trailing zeroes/ones instruction.  */
1287  #define ISA_HAS_CTZ_CTO                (TARGET_LOONGSON_EXT2)
1288 @@ -1225,6 +1231,7 @@ struct mips_cpu_info {
1289
1290  /* ISA has the "ror" (rotate right) instructions.  */
1291  #define ISA_HAS_ROR            ((mips_isa_rev >= 2                     \
1292 +                                 || TARGET_ALLEGREX                    \
1293                                   || TARGET_MIPS5400                    \
1294                                   || TARGET_MIPS5500                    \
1295                                   || TARGET_SR71K                       \
1296 @@ -1233,7 +1240,11 @@ struct mips_cpu_info {
1297
1298  /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1299     64-bit targets also provide DSBH and DSHD.  */
1300 -#define ISA_HAS_WSBH           (mips_isa_rev >= 2 && !TARGET_MIPS16)
1301 +#define ISA_HAS_WSBH           ((mips_isa_rev >= 2 && !TARGET_MIPS16)  \
1302 +                                 || TARGET_ALLEGREX)
1303 +
1304 +/* Similar to WSBH but for 32 bit words. */
1305 +#define ISA_HAS_WSBW           (TARGET_ALLEGREX)
1306
1307  /* ISA has data prefetch instructions.  This controls use of 'pref'.  */
1308  #define ISA_HAS_PREFETCH       ((ISA_MIPS4                             \
1309 @@ -1259,10 +1270,12 @@ struct mips_cpu_info {
1310  #define ISA_HAS_TRUNC_W                (!ISA_MIPS1)
1311
1312  /* ISA includes the MIPS32r2 seb and seh instructions.  */
1313 -#define ISA_HAS_SEB_SEH                (mips_isa_rev >= 2 && !TARGET_MIPS16)
1314 +#define ISA_HAS_SEB_SEH                ((mips_isa_rev >= 2 && !TARGET_MIPS16)  \
1315 +                                 || TARGET_ALLEGREX)
1316
1317  /* ISA includes the MIPS32/64 rev 2 ext and ins instructions.  */
1318 -#define ISA_HAS_EXT_INS                (mips_isa_rev >= 2 && !TARGET_MIPS16)
1319 +#define ISA_HAS_EXT_INS                ((mips_isa_rev >= 2 && !TARGET_MIPS16)  \
1320 +                                 || TARGET_ALLEGREX)
1321
1322  /* ISA has instructions for accessing top part of 64-bit fp regs.  */
1323  #define ISA_HAS_MXHC1          (!TARGET_FLOAT32        \
1324 @@ -1323,6 +1336,7 @@ struct mips_cpu_info {
1325     earlier-ISA CPUs for which CPU documentation declares that the
1326     instructions are really interlocked.  */
1327  #define ISA_HAS_HILO_INTERLOCKS        (mips_isa_rev >= 1                      \
1328 +                                || TARGET_ALLEGREX                     \
1329                                  || TARGET_MIPS5500                     \
1330                                  || TARGET_MIPS5900                     \
1331                                  || TARGET_LOONGSON_2EF)
1332 @@ -2411,7 +2425,7 @@ enum reg_class
1333     `crtl->outgoing_args_size'.  */
1334  #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1335
1336 -#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1337 +#define STACK_BOUNDARY (mips_preferred_stack_boundary)
1338  \f
1339  /* Symbolic macros for the registers used to return integer and floating
1340     point values.  */
1341 @@ -2538,7 +2552,7 @@ typedef struct mips_args {
1342  /* Treat LOC as a byte offset from the stack pointer and round it up
1343     to the next fully-aligned offset.  */
1344  #define MIPS_STACK_ALIGN(LOC) \
1345 -  (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
1346 +  (ROUND_UP ((LOC), mips_preferred_stack_align))
1347
1348  \f
1349  /* Output assembler code to FILE to increment profiler label # LABELNO
1350 @@ -3187,6 +3201,9 @@ while (0)
1351         " TEXT_SECTION_ASM_OP);
1352  #endif
1353
1354 +extern unsigned int mips_preferred_stack_boundary;
1355 +extern unsigned int mips_preferred_stack_align;
1356 +
1357  #ifndef HAVE_AS_TLS
1358  #define HAVE_AS_TLS 0
1359  #endif
1360 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
1361 index ac1d77afc7d..4ce2ba66db0 100644
1362 --- a/gcc/config/mips/mips.md
1363 +++ b/gcc/config/mips/mips.md
1364 @@ -35,6 +35,7 @@
1365    74kf2_1
1366    74kf1_1
1367    74kf3_2
1368 +  allegrex
1369    loongson_2e
1370    loongson_2f
1371    gs464
1372 @@ -820,7 +821,8 @@
1373  (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
1374                                (CC "TARGET_HARD_FLOAT
1375                                    && !TARGET_LOONGSON_2EF
1376 -                                  && !TARGET_MIPS5900")])
1377 +                                  && !TARGET_MIPS5900
1378 +                                  && !TARGET_ALLEGREX")])
1379
1380  ;; This mode iterator allows :FPCC to be used anywhere that an FP condition
1381  ;; is needed.
1382 @@ -2261,11 +2263,11 @@
1383            (mult:DI
1384               (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1385               (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1386 -  "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
1387 +  "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)"
1388  {
1389    if (ISA_HAS_DSP_MULT)
1390      return "msub<u>\t%q0,%1,%2";
1391 -  else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1392 +  else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX)
1393      return "msub<u>\t%1,%2";
1394    else
1395      return "msac<u>\t$0,%1,%2";
1396 @@ -2544,14 +2546,14 @@
1397          (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1398                   (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1399          (match_operand:DI 3 "muldiv_target_operand" "0")))]
1400 -  "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
1401 +  "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)
1402     && !TARGET_64BIT"
1403  {
1404    if (TARGET_MAD)
1405      return "mad<u>\t%1,%2";
1406    else if (ISA_HAS_DSP_MULT)
1407      return "madd<u>\t%q0,%1,%2";
1408 -  else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
1409 +  else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX)
1410      return "madd<u>\t%1,%2";
1411    else
1412      /* See comment in *macc.  */
1413 @@ -5886,12 +5888,19 @@
1414    "wsbh\t%0,%1"
1415    [(set_attr "type" "shift")])
1416
1417 -(define_insn_and_split "bswapsi2"
1418 +(define_insn "bswapsi2"
1419 +  [(set (match_operand:SI 0 "register_operand" "=d")
1420 +       (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
1421 +  "ISA_HAS_WSBW"
1422 +  "wsbw\t%0,%1"
1423 +  [(set_attr "type" "shift")])
1424 +
1425 +(define_insn_and_split "bswapsi2_split"
1426    [(set (match_operand:SI 0 "register_operand" "=d")
1427         (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
1428    "ISA_HAS_WSBH && ISA_HAS_ROR"
1429    "#"
1430 -  "&& 1"
1431 +  "&& !ISA_HAS_WSBW"
1432    [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH))
1433     (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
1434    ""
1435 @@ -7839,6 +7848,9 @@
1436  ; The MIPS MSA Instructions.
1437  (include "mips-msa.md")
1438
1439 +; Sony ALLEGREX instructions.
1440 +(include "allegrex.md")
1441 +
1442  (define_c_enum "unspec" [
1443    UNSPEC_ADDRESS_FIRST
1444  ])
1445 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
1446 index 195f5be01cc..931a72870cb 100644
1447 --- a/gcc/config/mips/mips.opt
1448 +++ b/gcc/config/mips/mips.opt
1449 @@ -479,3 +479,7 @@ Use Loongson EXTension (EXT) instructions.
1450  mloongson-ext2
1451  Target Var(TARGET_LOONGSON_EXT2)
1452  Use Loongson EXTension R2 (EXT2) instructions.
1453 +
1454 +mpreferred-stack-boundary=
1455 +Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
1456 +Attempt to keep stack aligned to this power of 2
1457 diff --git a/gcc/config/mips/psp.h b/gcc/config/mips/psp.h
1458 new file mode 100644
1459 index 00000000000..ebe54af60ed
1460 --- /dev/null
1461 +++ b/gcc/config/mips/psp.h
1462 @@ -0,0 +1,42 @@
1463 +/* Support for Sony's Playstation Portable (PSP).
1464 +   Copyright (C) 2005 Free Software Foundation, Inc.
1465 +   Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
1466 +
1467 +This file is part of GCC.
1468 +
1469 +GCC is free software; you can redistribute it and/or modify
1470 +it under the terms of the GNU General Public License as published by
1471 +the Free Software Foundation; either version 2, or (at your option)
1472 +any later version.
1473 +
1474 +GCC is distributed in the hope that it will be useful,
1475 +but WITHOUT ANY WARRANTY; without even the implied warranty of
1476 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1477 +GNU General Public License for more details.
1478 +
1479 +You should have received a copy of the GNU General Public License
1480 +along with GCC; see the file COPYING.  If not, write to
1481 +the Free Software Foundation, 59 Temple Place - Suite 330,
1482 +Boston, MA 02111-1307, USA.  */
1483 +
1484 +#undef  LIB_SPEC
1485 +#define LIB_SPEC " \
1486 +    -lm \
1487 +    --start-group \
1488 +    -lpthreadglue \
1489 +    -lpthread \
1490 +    -lcglue \
1491 +    %{g:-lg} %{!g:-lc} \
1492 +    --end-group \
1493 +    -lpsputility -lpsprtc -lpspnet_inet -lpspnet_resolver \
1494 +    -lpspsdk -lpspmodinfo -lpspuser -lpspkernel"
1495 +
1496 +/* Override the startfile spec to include crt0.o. */
1497 +#undef STARTFILE_SPEC
1498 +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
1499 +
1500 +#undef SUBTARGET_CPP_SPEC
1501 +#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__PSP__=1 -D_PSP=1 -D__psp__=1"
1502 +
1503 +#undef ENDFILE_SPEC
1504 +#define ENDFILE_SPEC "crtend%O%s crtn%O%s"
1505 diff --git a/libatomic/configure b/libatomic/configure
1506 index e47d2d7fb35..6cfe99ce8b6 100755
1507 --- a/libatomic/configure
1508 +++ b/libatomic/configure
1509 @@ -1265,6 +1265,13 @@ build=$build_alias
1510  host=$host_alias
1511  target=$target_alias
1512
1513 +# PSP SPECIFIC CODE
1514 +# Skipping some Tests for PSP platform because pspsdk libraries aren't ready yet.
1515 +skipTests=0
1516 +if [ "$target" == "psp" ]; then
1517 +   skipTests=1
1518 +fi
1519 +
1520  # FIXME: To remove some day.
1521  if test "x$host_alias" != x; then
1522    if test "x$build_alias" = x; then
1523 @@ -3818,7 +3825,7 @@ test "$ac_cv_exeext" = no && ac_cv_exeext=
1524  else
1525    ac_file=''
1526  fi
1527 -if test -z "$ac_file"; then :
1528 +if [test -z "$ac_file"] && [ "$skipTests" -eq "0" ]; then :
1529    { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
1530  $as_echo "no" >&6; }
1531  $as_echo "$as_me: failed program was:" >&5
1532 @@ -3866,7 +3873,7 @@ for ac_file in conftest.exe conftest conftest.*; do
1533      * ) break;;
1534    esac
1535  done
1536 -else
1537 +elif "$skipTests" -eq "0"; then :
1538    { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
1539  $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
1540  as_fn_error $? "cannot compute suffix of executables: cannot compile and link
1541 @@ -14921,7 +14928,7 @@ pthread_t t; pthread_create(&t,NULL,g,NULL);
1542  _ACEOF
1543  if ac_fn_c_try_link "$LINENO"; then :
1544
1545 -else
1546 +elif "$skipTests" -eq "0"; then :
1547    as_fn_error $? "Pthreads are required to build libatomic" "$LINENO" 5
1548  fi
1549  rm -f core conftest.err conftest.$ac_objext \
1550 diff --git a/libatomic/configure.tgt b/libatomic/configure.tgt
1551 index a92ae9e8309..912228a253e 100644
1552 --- a/libatomic/configure.tgt
1553 +++ b/libatomic/configure.tgt
1554 @@ -149,7 +149,7 @@ case "${target}" in
1555         tmake_file="t-aix"
1556         ;;
1557
1558 -  *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu \
1559 +  *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu | *-psp-elf* \
1560    | *-*-netbsd* | *-*-freebsd* | *-*-openbsd* | *-*-dragonfly* \
1561    | *-*-solaris2* | *-*-sysv4* | *-*-irix6* | *-*-osf* | *-*-hpux11* \
1562    | *-*-darwin* | *-*-aix* | *-*-cygwin*)
1563 diff --git a/libgcc/config.host b/libgcc/config.host
1564 index 9d7212028d0..49be3a50b84 100644
1565 --- a/libgcc/config.host
1566 +++ b/libgcc/config.host
1567 @@ -162,10 +162,16 @@ microblaze*-*-*)
1568         ;;
1569  mips*-*-*)
1570         # All MIPS targets provide a full set of FP routines.
1571 +       # (except for allegrex and R5900)
1572         cpu_type=mips
1573         tmake_file="mips/t-mips"
1574         if test "${libgcc_cv_mips_hard_float}" = yes; then
1575 -               tmake_file="${tmake_file} t-hardfp-sfdf t-hardfp"
1576 +               if test "${libgcc_cv_mips_single_float}" = yes; then
1577 +                       tmake_file="${tmake_file} t-hardfp-sf"
1578 +               else
1579 +                       tmake_file="${tmake_file} t-hardfp-sfdf"
1580 +               fi
1581 +               tmake_file="${tmake_file} t-hardfp"
1582         else
1583                 tmake_file="${tmake_file} t-softfp-sfdf"
1584         fi
1585 @@ -1081,6 +1087,10 @@ mips-wrs-vxworks)
1586  mipstx39-*-elf* | mipstx39el-*-elf*)
1587         tmake_file="$tmake_file mips/t-crtstuff mips/t-mips16"
1588         ;;
1589 +mipsallegrex*-psp*)
1590 +       tmake_file="$tmake_file mips/t-allegrex-psp"
1591 +       extra_parts="$extra_parts crti.o crtn.o"
1592 +       ;;
1593  mmix-knuth-mmixware)
1594         extra_parts="crti.o crtn.o crtbegin.o crtend.o"
1595         tmake_file="${tmake_file} ${cpu_type}/t-${cpu_type}"
1596 diff --git a/libgcc/config/mips/t-allegrex-psp b/libgcc/config/mips/t-allegrex-psp
1597 new file mode 100644
1598 index 00000000000..e4dfb5276ca
1599 --- /dev/null
1600 +++ b/libgcc/config/mips/t-allegrex-psp
1601 @@ -0,0 +1,2 @@
1602 +# Disable use of GP-relative addressing in startup code.
1603 +CRTSTUFF_T_CFLAGS += -mno-gpopt
1604 diff --git a/libgcc/config/t-hardfp-sf b/libgcc/config/t-hardfp-sf
1605 new file mode 100644
1606 index 00000000000..da50f354db3
1607 --- /dev/null
1608 +++ b/libgcc/config/t-hardfp-sf
1609 @@ -0,0 +1,32 @@
1610 +# Copyright (C) 2014-2021 Free Software Foundation, Inc.
1611 +
1612 +# This file is part of GCC.
1613 +
1614 +# GCC is free software; you can redistribute it and/or modify
1615 +# it under the terms of the GNU General Public License as published by
1616 +# the Free Software Foundation; either version 3, or (at your option)
1617 +# any later version.
1618 +
1619 +# GCC is distributed in the hope that it will be useful,
1620 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
1621 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1622 +# GNU General Public License for more details.
1623 +
1624 +# You should have received a copy of the GNU General Public License
1625 +# along with GCC; see the file COPYING3.  If not see
1626 +# <http://www.gnu.org/licenses/>.
1627 +
1628 +hardfp_float_modes := sf
1629 +# di and ti are provided by libgcc2.c where needed.
1630 +hardfp_int_modes := si
1631 +hardfp_extensions :=
1632 +hardfp_truncations :=
1633 +
1634 +# Emulate 64 bit float:
1635 +FPBIT = true
1636 +DPBIT = true
1637 +# Don't build functions handled by 32 bit hardware:
1638 +LIB2FUNCS_EXCLUDE = _addsub_sf _mul_sf _div_sf \
1639 +    _fpcmp_parts_sf _compare_sf _eq_sf _ne_sf _gt_sf _ge_sf \
1640 +    _lt_sf _le_sf _unord_sf _si_to_sf _sf_to_si _negate_sf \
1641 +    _thenan_sf _sf_to_usi _usi_to_sf
1642 diff --git a/libgcc/configure b/libgcc/configure
1643 index be5d45f1755..b22d6a8ce0f 100755
1644 --- a/libgcc/configure
1645 +++ b/libgcc/configure
1646 @@ -675,6 +675,7 @@ infodir
1647  docdir
1648  oldincludedir
1649  includedir
1650 +runstatedir
1651  localstatedir
1652  sharedstatedir
1653  sysconfdir
1654 @@ -766,6 +767,7 @@ datadir='${datarootdir}'
1655  sysconfdir='${prefix}/etc'
1656  sharedstatedir='${prefix}/com'
1657  localstatedir='${prefix}/var'
1658 +runstatedir='${localstatedir}/run'
1659  includedir='${prefix}/include'
1660  oldincludedir='/usr/include'
1661  docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
1662 @@ -1018,6 +1020,15 @@ do
1663    | -silent | --silent | --silen | --sile | --sil)
1664      silent=yes ;;
1665
1666 +  -runstatedir | --runstatedir | --runstatedi | --runstated \
1667 +  | --runstate | --runstat | --runsta | --runst | --runs \
1668 +  | --run | --ru | --r)
1669 +    ac_prev=runstatedir ;;
1670 +  -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
1671 +  | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
1672 +  | --run=* | --ru=* | --r=*)
1673 +    runstatedir=$ac_optarg ;;
1674 +
1675    -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
1676      ac_prev=sbindir ;;
1677    -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
1678 @@ -1155,7 +1166,7 @@ fi
1679  for ac_var in  exec_prefix prefix bindir sbindir libexecdir datarootdir \
1680                 datadir sysconfdir sharedstatedir localstatedir includedir \
1681                 oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
1682 -               libdir localedir mandir
1683 +               libdir localedir mandir runstatedir
1684  do
1685    eval ac_val=\$$ac_var
1686    # Remove trailing slashes.
1687 @@ -1308,6 +1319,7 @@ Fine tuning of the installation directories:
1688    --sysconfdir=DIR        read-only single-machine data [PREFIX/etc]
1689    --sharedstatedir=DIR    modifiable architecture-independent data [PREFIX/com]
1690    --localstatedir=DIR     modifiable single-machine data [PREFIX/var]
1691 +  --runstatedir=DIR       modifiable per-process data [LOCALSTATEDIR/run]
1692    --libdir=DIR            object code libraries [EPREFIX/lib]
1693    --includedir=DIR        C header files [PREFIX/include]
1694    --oldincludedir=DIR     C header files for non-gcc [/usr/include]
1695 @@ -5109,6 +5121,28 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
1696  fi
1697  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_hard_float" >&5
1698  $as_echo "$libgcc_cv_mips_hard_float" >&6; }
1699 +
1700 +  { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the target is single-float" >&5
1701 +$as_echo_n "checking whether the target is single-float... " >&6; }
1702 +if ${libgcc_cv_mips_single_float+:} false; then :
1703 +  $as_echo_n "(cached) " >&6
1704 +else
1705 +  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
1706 +/* end confdefs.h.  */
1707 +#ifndef __mips_single_float
1708 +     #error FOO
1709 +     #endif
1710 +
1711 +_ACEOF
1712 +if ac_fn_c_try_compile "$LINENO"; then :
1713 +  libgcc_cv_mips_single_float=yes
1714 +else
1715 +  libgcc_cv_mips_single_float=no
1716 +fi
1717 +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
1718 +fi
1719 +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_single_float" >&5
1720 +$as_echo "$libgcc_cv_mips_single_float" >&6; }
1721  esac
1722
1723  case ${host} in
1724 diff --git a/libgcc/configure.ac b/libgcc/configure.ac
1725 index 2fc9d5d7c93..3f750dbe076 100644
1726 --- a/libgcc/configure.ac
1727 +++ b/libgcc/configure.ac
1728 @@ -344,6 +344,16 @@ mips*-*-*)
1729      ])],
1730      [libgcc_cv_mips_hard_float=yes],
1731      [libgcc_cv_mips_hard_float=no])])
1732 +
1733 +  AC_CACHE_CHECK([whether the target is single-float],
1734 +                [libgcc_cv_mips_single_float],
1735 +                [AC_COMPILE_IFELSE(
1736 +    [AC_LANG_SOURCE([#ifndef __mips_single_float
1737 +     #error FOO
1738 +     #endif
1739 +    ])],
1740 +    [libgcc_cv_mips_single_float=yes],
1741 +    [libgcc_cv_mips_single_float=no])])
1742  esac
1743
1744  case ${host} in
1745 diff --git a/libgcc/gthr.h b/libgcc/gthr.h
1746 index 1989c0c86ed..8710f1c2938 100644
1747 --- a/libgcc/gthr.h
1748 +++ b/libgcc/gthr.h
1749 @@ -144,6 +144,17 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
1750  #ifndef GTHREAD_USE_WEAK
1751  #define GTHREAD_USE_WEAK 1
1752  #endif
1753 +
1754 +/* *** PSP Specific change for std::thread ***
1755 +   This file is modified by running sed commands on the
1756 +   libstdc++-v3/include/Makefile.am
1757 +   These sed commands add prefix to the existing macros
1758 +   this is why we CAN'T add here an #if __PSP__
1759 +   As solution we force here GTHREAD_USE_WEAK to be 0
1760 +*/
1761 +#undef GTHREAD_USE_WEAK
1762 +#define GTHREAD_USE_WEAK 0
1763 +
1764  #endif
1765  #include "gthr-default.h"
1766
1767 diff --git a/libobjc/Makefile.in b/libobjc/Makefile.in
1768 index 8375f6f9951..027cb469943 100644
1769 --- a/libobjc/Makefile.in
1770 +++ b/libobjc/Makefile.in
1771 @@ -71,7 +71,7 @@ AR_FLAGS = rc
1772  RANLIB = @RANLIB@
1773
1774  CC = @CC@
1775 -CFLAGS = @CFLAGS@
1776 +CFLAGS = -G0 @CFLAGS@
1777  XCFLAGS = @XCFLAGS@
1778  WARN_CFLAGS = -W -Wall -Wwrite-strings -Wstrict-prototypes
1779  ALL_CFLAGS = -I. -I$(srcdir) $(CPPFLAGS) $(DEFS) \
1780 From 954cc8bda44496b5927a6b72e54a1a3765c04d61 Mon Sep 17 00:00:00 2001
1781 From: root <root@loser.party>
1782 Date: Mon, 8 Apr 2024 15:38:55 +0000
1783 Subject: [PATCH] Revert "Add pthread as standard libary"
1784
1785 This reverts commit c2c9dff649f7e8576f6be32b1c15c46f1c4c0d42.
1786 ---
1787  gcc/config/mips/psp.h | 4 +---
1788  1 file changed, 1 insertion(+), 3 deletions(-)
1789
1790 diff --git a/gcc/config/mips/psp.h b/gcc/config/mips/psp.h
1791 index ebe54af60ed..49849fb6bd4 100644
1792 --- a/gcc/config/mips/psp.h
1793 +++ b/gcc/config/mips/psp.h
1794 @@ -23,13 +23,11 @@ Boston, MA 02111-1307, USA.  */
1795  #define LIB_SPEC " \
1796      -lm \
1797      --start-group \
1798 -    -lpthreadglue \
1799 -    -lpthread \
1800      -lcglue \
1801      %{g:-lg} %{!g:-lc} \
1802      --end-group \
1803      -lpsputility -lpsprtc -lpspnet_inet -lpspnet_resolver \
1804 -    -lpspsdk -lpspmodinfo -lpspuser -lpspkernel"
1805 +    -lpspmodinfo -lpspuser -lpspkernel"
1806
1807  /* Override the startfile spec to include crt0.o. */
1808  #undef STARTFILE_SPEC
1809 --
1810 2.31.1
1811
1812 From e7c3cd9daf24c83c5d356f392a2a5ce97eec3855 Mon Sep 17 00:00:00 2001
1813 From: root <root@loser.party>
1814 Date: Mon, 8 Apr 2024 15:49:36 +0000
1815 Subject: [PATCH] Revert "add atomic library"
1816
1817 This reverts commit b82cfa69dbb2d375f9c21d2c70b9a248c830e8ba.
1818 ---
1819  libatomic/configure.tgt | 2 +-
1820  1 file changed, 1 insertion(+), 1 deletion(-)
1821
1822 diff --git a/libatomic/configure.tgt b/libatomic/configure.tgt
1823 index 912228a253e..a92ae9e8309 100644
1824 --- a/libatomic/configure.tgt
1825 +++ b/libatomic/configure.tgt
1826 @@ -149,7 +149,7 @@ case "${target}" in
1827         tmake_file="t-aix"
1828         ;;
1829
1830 -  *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu | *-psp-elf* \
1831 +  *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu \
1832    | *-*-netbsd* | *-*-freebsd* | *-*-openbsd* | *-*-dragonfly* \
1833    | *-*-solaris2* | *-*-sysv4* | *-*-irix6* | *-*-osf* | *-*-hpux11* \
1834    | *-*-darwin* | *-*-aix* | *-*-cygwin*)
1835 --
1836 2.31.1
1837