| blob | e8fcafa44a2a9a8234f8ef66cac4b944bad81f4a |
1 diff --git a/config.sub b/config.sub
2 index 75bb6a3135b..c47e1a7bc10 100755
3 --- a/config.sub
4 +++ b/config.sub
5 @@ -632,6 +632,10 @@ case $1 in
6 basic_machine=ymp-cray
7 os=unicos
8 ;;
9 + psp)
10 + basic_machine=mipsallegrexel-psp
11 + os=elf
12 + ;;
13 *)
14 basic_machine=$1
15 os=
16 @@ -644,6 +648,10 @@ esac
17 case $basic_machine in
18 # Here we handle the default manufacturer of certain CPU types. It is in
19 # some cases the only manufacturer, in others, it is the most popular.
20 + mipsallegrexel-*)
21 + cpu=mipsallegrexel
22 + vendor=psp
23 + ;;
24 w89k)
25 cpu=hppa1.1
26 vendor=winbond
27 @@ -1210,6 +1218,7 @@ case $cpu-$vendor in
28 | mipsisa64sr71k | mipsisa64sr71kel \
29 | mipsr5900 | mipsr5900el \
30 | mipstx39 | mipstx39el \
31 + | mipsallegrex | mipsallegrexel \
32 | mmix \
33 | mn10200 | mn10300 \
34 | moxie \
35 diff --git a/gcc/config.gcc b/gcc/config.gcc
36 index b2282ecdf0b..9bc76e6c3b4 100644
37 --- a/gcc/config.gcc
38 +++ b/gcc/config.gcc
39 @@ -2457,6 +2457,18 @@ mipstx39-*-elf* | mipstx39el-*-elf*)
40 tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
41 tmake_file="mips/t-r3900"
42 ;;
43 +mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
44 + tm_file="elfos.h ${tm_file} mips/elf.h"
45 + tmake_file=mips/t-allegrex;
46 + target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
47 + tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
48 + case ${target} in
49 + mipsallegrex*-psp-elf*)
50 + tm_file="${tm_file} mips/psp.h";
51 + ;;
52 + esac
53 + use_fixproto=yes
54 + ;;
55 mmix-knuth-mmixware)
56 tm_file="${tm_file} newlib-stdint.h"
57 use_gcc_stdint=wrap
58 diff --git a/gcc/config/mips/allegrex.md b/gcc/config/mips/allegrex.md
59 new file mode 100644
60 index 00000000000..97ed72f8821
61 --- /dev/null
62 +++ b/gcc/config/mips/allegrex.md
63 @@ -0,0 +1,172 @@
64 +;; Sony ALLEGREX instructions.
65 +;; Copyright (C) 2005 Free Software Foundation, Inc.
66 +;;
67 +;; This file is part of GCC.
68 +;;
69 +;; GCC is free software; you can redistribute it and/or modify
70 +;; it under the terms of the GNU General Public License as published by
71 +;; the Free Software Foundation; either version 2, or (at your option)
72 +;; any later version.
73 +;;
74 +;; GCC is distributed in the hope that it will be useful,
75 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
76 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
77 +;; GNU General Public License for more details.
78 +;;
79 +;; You should have received a copy of the GNU General Public License
80 +;; along with GCC; see the file COPYING. If not, write to
81 +;; the Free Software Foundation, 59 Temple Place - Suite 330,
82 +;; Boston, MA 02111-1307, USA.
83 +
84 +(define_c_enum "unspec" [
85 + UNSPEC_CLO
86 + UNSPEC_CTO
87 + UNSPEC_CACHE
88 + UNSPEC_CEIL_W_S
89 + UNSPEC_FLOOR_W_S
90 + UNSPEC_ROUND_W_S
91 +])
92 +
93 +;; Multiply Add and Subtract.
94 +;; Note: removed clobbering for madd and msub (testing needed)
95 +
96 +(define_insn "allegrex_madd"
97 + [(set (match_operand:SI 0 "register_operand" "+l")
98 + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
99 + (match_operand:SI 2 "register_operand" "d"))
100 + (match_dup 0)))]
101 + "TARGET_ALLEGREX"
102 + "madd\t%1,%2"
103 + [(set_attr "type" "imadd")
104 + (set_attr "mode" "SI")])
105 +
106 +(define_insn "allegrex_msub"
107 + [(set (match_operand:SI 0 "register_operand" "+l")
108 + (minus:SI (match_dup 0)
109 + (mult:SI (match_operand:SI 1 "register_operand" "d")
110 + (match_operand:SI 2 "register_operand" "d"))))]
111 + "TARGET_ALLEGREX"
112 + "msub\t%1,%2"
113 + [(set_attr "type" "imadd")
114 + (set_attr "mode" "SI")])
115 +
116 +
117 +;; Min and max.
118 +
119 +(define_insn "sminsi3"
120 + [(set (match_operand:SI 0 "register_operand" "=d")
121 + (smin:SI (match_operand:SI 1 "register_operand" "d")
122 + (match_operand:SI 2 "register_operand" "d")))]
123 + "TARGET_ALLEGREX"
124 + "min\t%0,%1,%2"
125 + [(set_attr "type" "arith")
126 + (set_attr "mode" "SI")])
127 +
128 +(define_insn "smaxsi3"
129 + [(set (match_operand:SI 0 "register_operand" "=d")
130 + (smax:SI (match_operand:SI 1 "register_operand" "d")
131 + (match_operand:SI 2 "register_operand" "d")))]
132 + "TARGET_ALLEGREX"
133 + "max\t%0,%1,%2"
134 + [(set_attr "type" "arith")
135 + (set_attr "mode" "SI")])
136 +
137 +
138 +;; Extended shift instructions.
139 +
140 +(define_insn "allegrex_bitrev"
141 + [(set (match_operand:SI 0 "register_operand" "=d")
142 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
143 + UNSPEC_BITREV))]
144 + "TARGET_ALLEGREX"
145 + "bitrev\t%0,%1"
146 + [(set_attr "type" "arith")
147 + (set_attr "mode" "SI")])
148 +
149 +;; Count leading ones, count trailing zeros, and count trailing ones (clz is
150 +;; already defined).
151 +
152 +(define_insn "allegrex_clo"
153 + [(set (match_operand:SI 0 "register_operand" "=d")
154 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
155 + UNSPEC_CLO))]
156 + "TARGET_ALLEGREX"
157 + "clo\t%0,%1"
158 + [(set_attr "type" "clz")
159 + (set_attr "mode" "SI")])
160 +
161 +;;(define_expand "ctzsi2"
162 +;; [(set (match_operand:SI 0 "register_operand")
163 +;; (ctz:SI (match_operand:SI 1 "register_operand")))]
164 +;; "TARGET_ALLEGREX"
165 +;;{
166 +;; rtx r1;
167 +;;
168 +;; r1 = gen_reg_rtx (SImode);
169 +;; emit_insn (gen_allegrex_bitrev (r1, operands[1]));
170 +;; emit_insn (gen_clzsi2 (operands[0], r1));
171 +;; DONE;
172 +;;})
173 +
174 +(define_expand "allegrex_cto"
175 + [(set (match_operand:SI 0 "register_operand")
176 + (unspec:SI [(match_operand:SI 1 "register_operand")]
177 + UNSPEC_CTO))]
178 + "TARGET_ALLEGREX"
179 +{
180 + rtx r1;
181 +
182 + r1 = gen_reg_rtx (SImode);
183 + emit_insn (gen_allegrex_bitrev (r1, operands[1]));
184 + emit_insn (gen_allegrex_clo (operands[0], r1));
185 + DONE;
186 +})
187 +
188 +
189 +;; Misc.
190 +
191 +(define_insn "allegrex_sync"
192 + [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
193 + "TARGET_ALLEGREX"
194 + "sync"
195 + [(set_attr "type" "unknown")
196 + (set_attr "mode" "none")])
197 +
198 +(define_insn "allegrex_cache"
199 + [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
200 + (match_operand:SI 1 "register_operand" "d")]
201 + UNSPEC_CACHE)]
202 + "TARGET_ALLEGREX"
203 + "cache\t%0,0(%1)"
204 + [(set_attr "type" "unknown")
205 + (set_attr "mode" "none")])
206 +
207 +
208 +;; Floating-point builtins.
209 +
210 +(define_insn "allegrex_ceil_w_s"
211 + [(set (match_operand:SI 0 "register_operand" "=f")
212 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
213 + UNSPEC_CEIL_W_S))]
214 + "TARGET_ALLEGREX"
215 + "ceil.w.s\t%0,%1"
216 + [(set_attr "type" "fcvt")
217 + (set_attr "mode" "SF")])
218 +
219 +(define_insn "allegrex_floor_w_s"
220 + [(set (match_operand:SI 0 "register_operand" "=f")
221 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
222 + UNSPEC_FLOOR_W_S))]
223 + "TARGET_ALLEGREX"
224 + "floor.w.s\t%0,%1"
225 + [(set_attr "type" "fcvt")
226 + (set_attr "mode" "SF")])
227 +
228 +(define_insn "allegrex_round_w_s"
229 + [(set (match_operand:SI 0 "register_operand" "=f")
230 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
231 + UNSPEC_ROUND_W_S))]
232 + "TARGET_ALLEGREX"
233 + "round.w.s\t%0,%1"
234 + [(set_attr "type" "fcvt")
235 + (set_attr "mode" "SF")])
236 diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
237 index 5075f550a68..90a57d57cff 100644
238 --- a/gcc/config/mips/mips-cpus.def
239 +++ b/gcc/config/mips/mips-cpus.def
240 @@ -62,6 +62,7 @@ MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
242 /* MIPS II processors. */
243 MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
244 +MIPS_CPU ("allegrex", PROCESSOR_ALLEGREX, 2, 0)
246 /* MIPS III processors. */
247 MIPS_CPU ("r4000", PROCESSOR_R4000, 3, 0)
248 diff --git a/gcc/config/mips/mips-ftypes.def b/gcc/config/mips/mips-ftypes.def
249 index 5b5dc6b609f..d3fe6e17745 100644
250 --- a/gcc/config/mips/mips-ftypes.def
251 +++ b/gcc/config/mips/mips-ftypes.def
252 @@ -44,6 +44,8 @@ DEF_MIPS_FTYPE (3, (DI, DI, USI, USI))
253 DEF_MIPS_FTYPE (3, (DI, DI, V2HI, V2HI))
254 DEF_MIPS_FTYPE (3, (DI, DI, V4QI, V4QI))
255 DEF_MIPS_FTYPE (2, (DI, POINTER, SI))
256 +DEF_MIPS_FTYPE (1, (SI, HI))
257 +DEF_MIPS_FTYPE (1, (SI, SF))
258 DEF_MIPS_FTYPE (2, (DI, SI, SI))
259 DEF_MIPS_FTYPE (2, (DI, USI, USI))
260 DEF_MIPS_FTYPE (2, (DI, V2DI, UQI))
261 @@ -63,6 +65,7 @@ DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
262 DEF_MIPS_FTYPE (1, (SI, SI))
263 DEF_MIPS_FTYPE (2, (SI, SI, SI))
264 DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
265 +DEF_MIPS_FTYPE (1, (SI, QI))
266 DEF_MIPS_FTYPE (1, (SI, UQI))
267 DEF_MIPS_FTYPE (1, (SI, UV16QI))
268 DEF_MIPS_FTYPE (1, (SI, UV2DI))
269 @@ -281,6 +284,7 @@ DEF_MIPS_FTYPE (3, (VOID, V2DF, POINTER, SI))
270 DEF_MIPS_FTYPE (3, (VOID, V2DI, CVPOINTER, SI))
271 DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
272 DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
273 +DEF_MIPS_FTYPE (1, (VOID, VOID))
274 DEF_MIPS_FTYPE (3, (VOID, V4SF, POINTER, SI))
275 DEF_MIPS_FTYPE (3, (VOID, V4SI, CVPOINTER, SI))
276 DEF_MIPS_FTYPE (3, (VOID, V8HI, CVPOINTER, SI))
277 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
278 index d758fbf1be6..423b213d9d3 100644
279 --- a/gcc/config/mips/mips.c
280 +++ b/gcc/config/mips/mips.c
281 @@ -263,7 +263,12 @@ enum mips_builtin_type {
282 MIPS_BUILTIN_MSA_TEST_BRANCH,
284 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
285 - MIPS_BUILTIN_BPOSGE32
286 + MIPS_BUILTIN_BPOSGE32,
287 +
288 + /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0
289 + is the function code (must be less than 32) and operand 1 is the base
290 + address. */
291 + MIPS_BUILTIN_CACHE
292 };
294 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
295 @@ -470,6 +475,10 @@ struct mips_asm_switch mips_noat = { "at", 0 };
296 normal branch. */
297 static bool mips_branch_likely;
299 +/* Preferred stack boundary for proper stack vars alignment */
300 +unsigned int mips_preferred_stack_boundary;
301 +unsigned int mips_preferred_stack_align;
302 +
303 /* The current instruction-set architecture. */
304 enum processor mips_arch;
305 const struct mips_cpu_info *mips_arch_info;
306 @@ -830,6 +839,9 @@ static const struct mips_rtx_cost_data
307 1, /* branch_cost */
308 4 /* memory_latency */
309 },
310 + { /* Allegrex */
311 + DEFAULT_COSTS
312 + },
313 { /* Loongson-2E */
314 DEFAULT_COSTS
315 },
316 @@ -15260,6 +15272,7 @@ AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
317 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
318 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI)
319 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
320 +AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
321 AVAIL_NON_MIPS16 (msa, TARGET_MSA)
323 /* Construct a mips_builtin_description from the given arguments.
324 @@ -15357,6 +15370,30 @@ AVAIL_NON_MIPS16 (msa, TARGET_MSA)
325 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
326 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
328 +/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
329 + FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
330 +#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
331 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
332 + MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
333 +
334 +/* Same as the above, but mapped to an instruction that doesn't share the
335 + NAME. NAME is the name of the builtin without the builtin prefix. */
336 +#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
337 + { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME, \
338 + MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
339 +
340 +/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
341 + CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
342 + builtin_description fields. */
343 +#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
344 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
345 + MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex }
346 +
347 +/* Define a builtin with a specific function TYPE. */
348 +#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
349 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
350 + MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
351 +
352 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
353 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
354 builtin_description field. */
355 @@ -15832,6 +15869,38 @@ static const struct mips_builtin_description mips_builtins[] = {
356 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
357 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
359 +/* Builtin functions for the Sony ALLEGREX processor.
360 +
361 + These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
362 + to maintain compatibility with Sony's ALLEGREX GCC port.
363 +
364 + Some of the builtins may seem redundant, but they are the same as the
365 + builtins defined in the Sony compiler. I chose to map redundant and
366 + trivial builtins to the original instruction instead of creating
367 + duplicate patterns specifically for the ALLEGREX (as Sony does). */
368 +
369 + DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
370 + DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
371 + DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
372 + //DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
373 + DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
374 + DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
375 + DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
376 +
377 + DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
378 + DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
379 + DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
380 + DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
381 +
382 + DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
383 + SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
384 +
385 + DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
386 + DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
387 + DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
388 + DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
389 + DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
390 +
391 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
392 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
393 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
394 @@ -16520,6 +16589,7 @@ mips_build_cvpointer_type (void)
395 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
396 #define MIPS_ATYPE_HI intHI_type_node
397 #define MIPS_ATYPE_SI intSI_type_node
398 +#define MIPS_ATYPE_QI intQI_type_node
399 #define MIPS_ATYPE_USI unsigned_intSI_type_node
400 #define MIPS_ATYPE_DI intDI_type_node
401 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
402 @@ -17204,6 +17274,26 @@ mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
403 const1_rtx, const0_rtx);
404 }
406 +/* Expand a __builtin_allegrex_cache() function. Make sure the passed
407 + cache function code is less than 32. */
408 +
409 +static rtx
410 +mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
411 +{
412 + int argno;
413 + struct expand_operand ops[2];
414 +
415 + for (argno = 0; argno < 2; argno++)
416 + mips_prepare_builtin_arg (&ops[argno], exp, argno);
417 +
418 + if (GET_CODE(ops[0].value) != CONST_INT ||
419 + INTVAL(ops[0].value) < 0 || INTVAL(ops[0].value) > 0x1f)
420 + error("Invalid first argument for cache builtin (0 <= arg <= 31)");
421 +
422 + emit_insn(mips_expand_builtin_insn (icode, 2, ops, false));
423 + return target;
424 +}
425 +
426 /* Implement TARGET_EXPAND_BUILTIN. */
428 static rtx
429 @@ -17252,6 +17342,9 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
431 case MIPS_BUILTIN_BPOSGE32:
432 return mips_expand_builtin_bposge (d->builtin_type, target);
433 +
434 + case MIPS_BUILTIN_CACHE:
435 + return mips_expand_builtin_cache (d->icode, target, exp);
436 }
437 gcc_unreachable ();
438 }
439 @@ -20396,6 +20489,22 @@ mips_option_override (void)
440 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
441 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
443 + /* Validate -mpreferred-stack-boundary= value, or provide default.
444 + The default of 128-bit is for newABI else 64-bit. */
445 + mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
446 + mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
447 + if (mips_preferred_stack_boundary_string)
448 + {
449 + i = atoi (mips_preferred_stack_boundary_string);
450 + if (i < 2 || i > 12)
451 + error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
452 + else
453 + {
454 + mips_preferred_stack_align = (1 << i);
455 + mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
456 + }
457 + }
458 +
459 mips_register_frame_header_opt ();
460 }
462 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
463 index 953d82e85c2..feac072413e 100644
464 --- a/gcc/config/mips/mips.h
465 +++ b/gcc/config/mips/mips.h
466 @@ -287,6 +287,7 @@ struct mips_cpu_info {
467 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
468 || mips_arch == PROCESSOR_SB1A)
469 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
470 +#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX)
471 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
473 /* Scheduling target defines. */
474 @@ -319,6 +320,7 @@ struct mips_cpu_info {
475 || mips_tune == PROCESSOR_OCTEON3)
476 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
477 || mips_tune == PROCESSOR_SB1A)
478 +#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX)
479 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
480 #define TUNE_I6400 (mips_tune == PROCESSOR_I6400)
481 #define TUNE_P6600 (mips_tune == PROCESSOR_P6600)
482 @@ -1058,6 +1060,9 @@ struct mips_cpu_info {
483 && !TARGET_MIPS5900 \
484 && !TARGET_MIPS16)
486 +/* ISA has just the integer condition move instructions (movn,movz) */
487 +#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX)
488 +
489 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
490 branch on CC, and move (both FP and non-FP) on CC. */
491 #define ISA_HAS_8CC (ISA_MIPS4 \
492 @@ -1093,6 +1098,7 @@ struct mips_cpu_info {
494 /* ISA has conditional trap instructions. */
495 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
496 + && !TARGET_ALLEGREX \
497 && !TARGET_MIPS16)
499 /* ISA has conditional trap with immediate instructions. */
500 @@ -1156,7 +1162,8 @@ struct mips_cpu_info {
501 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
503 /* ISA has count leading zeroes/ones instruction (not implemented). */
504 -#define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
505 +#define ISA_HAS_CLZ_CLO ((mips_isa_rev >= 1 && !TARGET_MIPS16) \
506 + || TARGET_ALLEGREX)
508 /* ISA has count trailing zeroes/ones instruction. */
509 #define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2)
510 @@ -1201,6 +1208,7 @@ struct mips_cpu_info {
511 || TARGET_MIPS5400 \
512 || TARGET_MIPS5500 \
513 || TARGET_SR71K \
514 + || TARGET_ALLEGREX \
515 || TARGET_SMARTMIPS) \
516 && !TARGET_MIPS16)
518 @@ -1232,10 +1240,12 @@ struct mips_cpu_info {
519 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
521 /* ISA includes the MIPS32r2 seb and seh instructions. */
522 -#define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
523 +#define ISA_HAS_SEB_SEH ((mips_isa_rev >= 2 && !TARGET_MIPS16) \
524 + || TARGET_ALLEGREX)
526 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
527 -#define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
528 +#define ISA_HAS_EXT_INS ((mips_isa_rev >= 2 && !TARGET_MIPS16) \
529 + || TARGET_ALLEGREX)
531 /* ISA has instructions for accessing top part of 64-bit fp regs. */
532 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
533 @@ -1298,7 +1308,8 @@ struct mips_cpu_info {
534 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
535 || TARGET_MIPS5500 \
536 || TARGET_MIPS5900 \
537 - || TARGET_LOONGSON_2EF)
538 + || TARGET_LOONGSON_2EF \
539 + || TARGET_ALLEGREX)
541 /* ISA includes synci, jr.hb and jalr.hb. */
542 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
543 @@ -2421,7 +2432,7 @@ enum reg_class
544 `crtl->outgoing_args_size'. */
545 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
547 -#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
548 +#define STACK_BOUNDARY (mips_preferred_stack_boundary)
549 \f
550 /* Symbolic macros for the registers used to return integer and floating
551 point values. */
552 @@ -2548,7 +2559,7 @@ typedef struct mips_args {
553 /* Treat LOC as a byte offset from the stack pointer and round it up
554 to the next fully-aligned offset. */
555 #define MIPS_STACK_ALIGN(LOC) \
556 - (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
557 + (ROUND_UP ((LOC), mips_preferred_stack_align))
559 \f
560 /* Output assembler code to FILE to increment profiler label # LABELNO
561 @@ -3197,6 +3208,9 @@ while (0)
562 " TEXT_SECTION_ASM_OP);
563 #endif
565 +extern unsigned int mips_preferred_stack_boundary;
566 +extern unsigned int mips_preferred_stack_align;
567 +
568 #ifndef HAVE_AS_TLS
569 #define HAVE_AS_TLS 0
570 #endif
571 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
572 index 3cfb1a751e9..9e1e72ee2de 100644
573 --- a/gcc/config/mips/mips.md
574 +++ b/gcc/config/mips/mips.md
575 @@ -35,6 +35,7 @@
576 74kf2_1
577 74kf1_1
578 74kf3_2
579 + allegrex
580 loongson_2e
581 loongson_2f
582 gs464
583 @@ -813,6 +814,7 @@
584 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
585 (CC "TARGET_HARD_FLOAT
586 && !TARGET_LOONGSON_2EF
587 + && !TARGET_ALLEGREX
588 && !TARGET_MIPS5900")])
590 ;; This mode iterator allows :FPCC to be used anywhere that an FP condition
591 @@ -2254,11 +2256,11 @@
592 (mult:DI
593 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
594 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
595 - "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
596 + "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)"
597 {
598 if (ISA_HAS_DSP_MULT)
599 return "msub<u>\t%q0,%1,%2";
600 - else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
601 + else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX)
602 return "msub<u>\t%1,%2";
603 else
604 return "msac<u>\t$0,%1,%2";
605 @@ -2528,14 +2530,14 @@
606 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
607 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
608 (match_operand:DI 3 "muldiv_target_operand" "0")))]
609 - "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
610 + "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)
611 && !TARGET_64BIT"
612 {
613 if (TARGET_MAD)
614 return "mad<u>\t%1,%2";
615 else if (ISA_HAS_DSP_MULT)
616 return "madd<u>\t%q0,%1,%2";
617 - else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
618 + else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX)
619 return "madd<u>\t%1,%2";
620 else
621 /* See comment in *macc. */
622 @@ -3193,6 +3195,33 @@
623 [(set_attr "type" "pop")
624 (set_attr "mode" "SI")])
625 \f
626 +;;
627 +;; ....................
628 +;;
629 +;; FIND FIRST BIT INSTRUCTION
630 +;;
631 +;; ....................
632 +;;
633 +
634 +(define_expand "ffs<mode>2"
635 + [(set (match_operand:GPR 0 "register_operand" "")
636 + (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
637 + "ISA_HAS_CLZ_CLO"
638 +{
639 + rtx r1, r2, r3, r4;
640 +
641 + r1 = gen_reg_rtx (<MODE>mode);
642 + r2 = gen_reg_rtx (<MODE>mode);
643 + r3 = gen_reg_rtx (<MODE>mode);
644 + r4 = gen_reg_rtx (<MODE>mode);
645 + emit_insn (gen_neg<mode>2 (r1, operands[1]));
646 + emit_insn (gen_and<mode>3 (r2, operands[1], r1));
647 + emit_insn (gen_clz<mode>2 (r3, r2));
648 + emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
649 + emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
650 + DONE;
651 +})
652 +
653 ;;
654 ;; ....................
655 ;;
656 @@ -3248,6 +3277,25 @@
657 (set_attr "compression" "micromips,*")
658 (set_attr "mode" "<MODE>")])
659 \f
660 +(define_expand "rotl<mode>3"
661 + [(set (match_operand:GPR 0 "register_operand")
662 + (rotate:GPR (match_operand:GPR 1 "register_operand")
663 + (match_operand:SI 2 "arith_operand")))]
664 + "ISA_HAS_ROR"
665 +{
666 + rtx temp;
667 +
668 + if (GET_CODE (operands[2]) == CONST_INT)
669 + temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
670 + else
671 + {
672 + temp = gen_reg_rtx (<MODE>mode);
673 + emit_insn (gen_neg<mode>2 (temp, operands[2]));
674 + }
675 + emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
676 + DONE;
677 +})
678 +\f
679 ;;
680 ;; ....................
681 ;;
682 @@ -7282,7 +7330,7 @@
683 (const_int 0)])
684 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
685 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
686 - "ISA_HAS_CONDMOVE"
687 + "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
688 "@
689 mov%T4\t%0,%z2,%1
690 mov%t4\t%0,%z3,%1"
691 @@ -7360,7 +7408,7 @@
692 (if_then_else:GPR (match_dup 5)
693 (match_operand:GPR 2 "reg_or_0_operand")
694 (match_operand:GPR 3 "reg_or_0_operand")))]
695 - "ISA_HAS_CONDMOVE || ISA_HAS_SEL"
696 + "ISA_HAS_CONDMOVE || ISA_HAS_SEL || ISA_HAS_INT_CONDMOVE"
697 {
698 if (!ISA_HAS_FP_CONDMOVE
699 && !INTEGRAL_MODE_P (GET_MODE (XEXP (operands[1], 0))))
700 @@ -7780,6 +7828,9 @@
701 ; The MIPS MSA Instructions.
702 (include "mips-msa.md")
704 +; Sony ALLEGREX instructions.
705 +(include "allegrex.md")
706 +
707 (define_c_enum "unspec" [
708 UNSPEC_ADDRESS_FIRST
709 ])
710 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
711 index 817a4823d99..de367180953 100644
712 --- a/gcc/config/mips/mips.opt
713 +++ b/gcc/config/mips/mips.opt
714 @@ -440,6 +440,10 @@ mframe-header-opt
715 Target Report Var(flag_frame_header_optimization) Optimization
716 Optimize frame header.
718 +mpreferred-stack-boundary=
719 +Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
720 +Attempt to keep stack aligned to this power of 2
721 +
722 noasmopt
723 Driver
725 diff --git a/gcc/config/mips/psp.h b/gcc/config/mips/psp.h
726 new file mode 100644
727 index 00000000000..ac41a93db38
728 --- /dev/null
729 +++ b/gcc/config/mips/psp.h
730 @@ -0,0 +1,33 @@
731 +/* Support for Sony's Playstation Portable (PSP).
732 + Copyright (C) 2005 Free Software Foundation, Inc.
733 + Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
734 +
735 +This file is part of GCC.
736 +
737 +GCC is free software; you can redistribute it and/or modify
738 +it under the terms of the GNU General Public License as published by
739 +the Free Software Foundation; either version 2, or (at your option)
740 +any later version.
741 +
742 +GCC is distributed in the hope that it will be useful,
743 +but WITHOUT ANY WARRANTY; without even the implied warranty of
744 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
745 +GNU General Public License for more details.
746 +
747 +You should have received a copy of the GNU General Public License
748 +along with GCC; see the file COPYING. If not, write to
749 +the Free Software Foundation, 59 Temple Place - Suite 330,
750 +Boston, MA 02111-1307, USA. */
751 +
752 +/* Override the startfile spec to include crt0.o. */
753 +#undef STARTFILE_SPEC
754 +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
755 +
756 +#undef SUBTARGET_CPP_SPEC
757 +#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
758 +
759 +/* Get rid of the .pdr section. */
760 +#undef SUBTARGET_ASM_SPEC
761 +#define SUBTARGET_ASM_SPEC "-mno-pdr"
762 +
763 +#include "../newlib-stdint.h"
764 diff --git a/gcc/config/mips/t-allegrex b/gcc/config/mips/t-allegrex
765 new file mode 100644
766 index 00000000000..89450d118c3
767 --- /dev/null
768 +++ b/gcc/config/mips/t-allegrex
769 @@ -0,0 +1,29 @@
770 +# Suppress building libgcc1.a, since the MIPS compiler port is complete
771 +# and does not need anything from libgcc1.a.
772 +LIBGCC1 =
773 +CROSS_LIBGCC1 =
774 +
775 +EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
776 +# Don't let CTOR_LIST end up in sdata section.
777 +CRTSTUFF_T_CFLAGS = -G 0
778 +
779 +# Assemble startup files.
780 +$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
781 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
782 + -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
783 +
784 +$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
785 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
786 + -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
787 +
788 +# We must build libgcc2.a with -G 0, in case the user wants to link
789 +# without the $gp register.
790 +TARGET_LIBGCC2_CFLAGS = -G 0
791 +
792 +# Build the libraries for both hard and soft floating point
793 +
794 +MULTILIB_OPTIONS =
795 +MULTILIB_DIRNAMES =
796 +
797 +LIBGCC = stmp-multilib
798 +INSTALL_LIBGCC = install-multilib
799 diff --git a/libcpp/Makefile.in b/libcpp/Makefile.in
800 index 81be1fd67ec..a7cba2c21a9 100644
801 --- a/libcpp/Makefile.in
802 +++ b/libcpp/Makefile.in
803 @@ -208,8 +208,8 @@ ifeq ($(DEPMODE),depmode=gcc3)
804 # Note that we put the dependencies into a .Tpo file, then move them
805 # into place if the compile succeeds. We need this because gcc does
806 # not atomically write the dependency output file.
807 -COMPILE = $(COMPILE.base) -o $@ -MT $@ -MMD -MP -MF $(DEPDIR)/$*.Tpo
808 -POSTCOMPILE = @mv $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
809 +COMPILE = $(COMPILE.base) -o $@
810 +POSTCOMPILE =
811 else
812 COMPILE = source='$<' object='$@' libtool=no DEPDIR=$(DEPDIR) $(DEPMODE) \
813 $(depcomp) $(COMPILE.base)
814 diff --git a/libgcc/config.host b/libgcc/config.host
815 index 0f15fda3612..ccff9d5c695 100644
816 --- a/libgcc/config.host
817 +++ b/libgcc/config.host
818 @@ -147,11 +147,15 @@ microblaze*-*-*)
819 cpu_type=microblaze
820 ;;
821 mips*-*-*)
822 - # All MIPS targets provide a full set of FP routines.
823 cpu_type=mips
824 tmake_file="mips/t-mips"
825 if test "${libgcc_cv_mips_hard_float}" = yes; then
826 - tmake_file="${tmake_file} t-hardfp-sfdf t-hardfp"
827 + if test "${libgcc_cv_mips_single_float}" = yes; then
828 + tmake_file="${tmake_file} t-hardfp-sf"
829 + else
830 + tmake_file="${tmake_file} t-hardfp-sfdf"
831 + fi
832 + tmake_file="${tmake_file} t-hardfp"
833 else
834 tmake_file="${tmake_file} t-softfp-sfdf"
835 fi
836 @@ -987,6 +991,14 @@ mips-wrs-vxworks)
837 mipstx39-*-elf* | mipstx39el-*-elf*)
838 tmake_file="$tmake_file mips/t-crtstuff mips/t-mips16"
839 ;;
840 +mips*-psp*)
841 + tmake_file="${tmake_file} mips/t-allegrex"
842 + target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
843 + tm_file="${tm_file} mips/psp.h"
844 + extra_parts="$extra_parts crti.o crtn.o"
845 + use_fixproto=yes
846 + tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
847 + ;;
848 mmix-knuth-mmixware)
849 extra_parts="crti.o crtn.o crtbegin.o crtend.o"
850 tmake_file="${tmake_file} ${cpu_type}/t-${cpu_type}"
851 diff --git a/libgcc/config/mips/psp.h b/libgcc/config/mips/psp.h
852 new file mode 100644
853 index 00000000000..c5e4b5d93d0
854 --- /dev/null
855 +++ b/libgcc/config/mips/psp.h
856 @@ -0,0 +1,31 @@
857 +/* Support for Sony's Playstation Portable (PSP).
858 + Copyright (C) 2005 Free Software Foundation, Inc.
859 + Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
860 +
861 +This file is part of GCC.
862 +
863 +GCC is free software; you can redistribute it and/or modify
864 +it under the terms of the GNU General Public License as published by
865 +the Free Software Foundation; either version 2, or (at your option)
866 +any later version.
867 +
868 +GCC is distributed in the hope that it will be useful,
869 +but WITHOUT ANY WARRANTY; without even the implied warranty of
870 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
871 +GNU General Public License for more details.
872 +
873 +You should have received a copy of the GNU General Public License
874 +along with GCC; see the file COPYING. If not, write to
875 +the Free Software Foundation, 59 Temple Place - Suite 330,
876 +Boston, MA 02111-1307, USA. */
877 +
878 +/* Override the startfile spec to include crt0.o. */
879 +#undef STARTFILE_SPEC
880 +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
881 +
882 +#undef SUBTARGET_CPP_SPEC
883 +#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
884 +
885 +/* Get rid of the .pdr section. */
886 +#undef SUBTARGET_ASM_SPEC
887 +#define SUBTARGET_ASM_SPEC "-mno-pdr"
888 diff --git a/libgcc/config/mips/t-allegrex b/libgcc/config/mips/t-allegrex
889 new file mode 100644
890 index 00000000000..1722e19abe9
891 --- /dev/null
892 +++ b/libgcc/config/mips/t-allegrex
893 @@ -0,0 +1,20 @@
894 +# Suppress building libgcc1.a, since the MIPS compiler port is complete
895 +# and does not need anything from libgcc1.a.
896 +LIBGCC1 =
897 +CROSS_LIBGCC1 =
898 +
899 +EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
900 +# Don't let CTOR_LIST end up in sdata section.
901 +CRTSTUFF_T_CFLAGS = -G 0
902 +
903 +# We must build libgcc2.a with -G 0, in case the user wants to link
904 +# without the $gp register.
905 +TARGET_LIBGCC2_CFLAGS = -G 0
906 +
907 +# Build the libraries for both hard and soft floating point
908 +
909 +MULTILIB_OPTIONS =
910 +MULTILIB_DIRNAMES =
911 +
912 +LIBGCC = stmp-multilib
913 +INSTALL_LIBGCC = install-multilib
914 diff --git a/libgcc/config/t-hardfp-sf b/libgcc/config/t-hardfp-sf
915 new file mode 100644
916 index 00000000000..10682690219
917 --- /dev/null
918 +++ b/libgcc/config/t-hardfp-sf
919 @@ -0,0 +1,32 @@
920 +# Copyright (C) 2014 Free Software Foundation, Inc.
921 +
922 +# This file is part of GCC.
923 +
924 +# GCC is free software; you can redistribute it and/or modify
925 +# it under the terms of the GNU General Public License as published by
926 +# the Free Software Foundation; either version 3, or (at your option)
927 +# any later version.
928 +
929 +# GCC is distributed in the hope that it will be useful,
930 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
931 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
932 +# GNU General Public License for more details.
933 +
934 +# You should have received a copy of the GNU General Public License
935 +# along with GCC; see the file COPYING3. If not see
936 +# <http://www.gnu.org/licenses/>.
937 +
938 +hardfp_float_modes := sf
939 +# di and ti are provided by libgcc2.c where needed.
940 +hardfp_int_modes := si
941 +hardfp_extensions :=
942 +hardfp_truncations :=
943 +
944 +# Emulate 64 bit float:
945 +FPBIT = true
946 +DPBIT = true
947 +# Don't build functions handled by 32 bit hardware:
948 +LIB2FUNCS_EXCLUDE = _addsub_sf _mul_sf _div_sf \
949 + _fpcmp_parts_sf _compare_sf _eq_sf _ne_sf _gt_sf _ge_sf \
950 + _lt_sf _le_sf _unord_sf _si_to_sf _sf_to_si _negate_sf \
951 + _thenan_sf _sf_to_usi _usi_to_sf
952 diff --git a/libgcc/configure b/libgcc/configure
953 index 36dbbc1f699..92517a1f931 100644
954 --- a/libgcc/configure
955 +++ b/libgcc/configure
956 @@ -5036,6 +5036,26 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
957 fi
958 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_hard_float" >&5
959 $as_echo "$libgcc_cv_mips_hard_float" >&6; }
960 + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the target is single-float" >&5
961 +$as_echo_n "checking whether the target is single-float... " >&6; }
962 +if test "${libgcc_cv_mips_single_float+set}" = set; then :
963 + $as_echo_n "(cached) " >&6
964 +else
965 + cat confdefs.h - <<_ACEOF >conftest.$ac_ext
966 +/* end confdefs.h. */
967 +#ifndef __mips_single_float
968 + #error FOO
969 + #endif
970 +_ACEOF
971 +if ac_fn_c_try_compile "$LINENO"; then :
972 + libgcc_cv_mips_single_float=yes
973 +else
974 + libgcc_cv_mips_single_float=no
975 +fi
976 +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
977 +fi
978 +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_single_float" >&5
979 +$as_echo "$libgcc_cv_mips_single_float" >&6; }
980 esac
982 case ${host} in
983 diff --git a/libgcc/configure.ac b/libgcc/configure.ac
984 index 8e96cafdf8b..77af122b546 100644
985 --- a/libgcc/configure.ac
986 +++ b/libgcc/configure.ac
987 @@ -302,6 +302,14 @@ mips*-*-*)
988 ])],
989 [libgcc_cv_mips_hard_float=yes],
990 [libgcc_cv_mips_hard_float=no])])
991 + AC_CACHE_CHECK([whether the target is single-float],
992 + [libgcc_cv_mips_single_float],
993 + [AC_COMPILE_IFELSE(
994 + [#ifndef __mips_single_float
995 + #error FOO
996 + #endif],
997 + [libgcc_cv_mips_single_float=yes],
998 + [libgcc_cv_mips_single_float=no])])
999 esac
1001 case ${host} in
1002 diff --git a/libgcc/crtstuff.c b/libgcc/crtstuff.c
1003 index 4927a9f8977..2a79e3e137d 100644
1004 --- a/libgcc/crtstuff.c
1005 +++ b/libgcc/crtstuff.c
1006 @@ -47,7 +47,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
1008 /* Target machine header files require this define. */
1009 #define IN_LIBGCC2
1010 -
1011 +#define USED_FOR_TARGET
1012 /* FIXME: Including auto-host is incorrect, but until we have
1013 identified the set of defines that need to go into auto-target.h,
1014 this will have to do. */