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bump gcc11.2 - psp patch to latest upstream
[rofl0r-mmix-cross.git] / patches / gcc-11.2.0-psp.diff
blob7eac6e6de0c94ba33af460128aece83e902848a7
1 diff --git a/config.sub b/config.sub
2 index 63c1f1c8b5e..195468dba3f 100755
3 --- a/config.sub
4 +++ b/config.sub
5 @@ -476,10 +476,6 @@ case $1 in
6 basic_machine=hppa-unknown
7 basic_os=linux
8 ;;
9 - psp)
10 - basic_machine=mipsallegrexel-sony
11 - basic_os=psp
12 - ;;
13 pw32)
14 basic_machine=i586-unknown
15 basic_os=pw32
16 @@ -632,6 +628,10 @@ case $1 in
17 basic_machine=ymp-cray
18 basic_os=unicos
19 ;;
20 + psp)
21 + basic_machine=mipsallegrexel-psp
22 + os=elf
23 + ;;
24 *)
25 basic_machine=$1
26 basic_os=
27 @@ -644,6 +644,10 @@ esac
28 case $basic_machine in
29 # Here we handle the default manufacturer of certain CPU types. It is in
30 # some cases the only manufacturer, in others, it is the most popular.
31 + mipsallegrexel-*)
32 + cpu=mipsallegrexel
33 + vendor=psp
34 + ;;
35 w89k)
36 cpu=hppa1.1
37 vendor=winbond
38 @@ -1144,10 +1148,6 @@ case $cpu-$vendor in
39 cpu=nsx
40 vendor=tandem
41 ;;
42 - mipsallegrexel-sony)
43 - cpu=mipsallegrexel
44 - vendor=sony
45 - ;;
46 tile*-*)
47 basic_os=${basic_os:-linux-gnu}
48 ;;
49 @@ -1212,6 +1212,7 @@ case $cpu-$vendor in
50 | mipsisa64sr71k | mipsisa64sr71kel \
51 | mipsr5900 | mipsr5900el \
52 | mipstx39 | mipstx39el \
53 + | mipsallegrex | mipsallegrexel \
54 | mmix \
55 | mn10200 | mn10300 \
56 | moxie \
57 diff --git a/gcc/config.gcc b/gcc/config.gcc
58 index 357b0bed067..e07e302523e 100644
59 --- a/gcc/config.gcc
60 +++ b/gcc/config.gcc
61 @@ -2741,6 +2741,17 @@ mipstx39-*-elf* | mipstx39el-*-elf*)
62 tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
63 tmake_file="mips/t-r3900"
64 ;;
65 +mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
66 + tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h"
67 + tmake_file="mips/t-elf"
68 + target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
69 + tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
70 + case ${target} in
71 + mipsallegrex*-psp-elf*)
72 + tm_file="${tm_file} mips/psp.h"
73 + ;;
74 + esac
75 + ;;
76 mmix-knuth-mmixware)
77 tm_file="${tm_file} newlib-stdint.h"
78 use_gcc_stdint=wrap
79 @@ -4097,8 +4108,9 @@ fi
80 # Infer a default setting for --with-fpu.
81 if test x$with_fpu = x; then
82 case ${target} in
83 - mips64r5900-*-* | mips64r5900el-*-* | mipsr5900-*-* | mipsr5900el-*-*)
84 - # The R5900 FPU only supports single precision.
85 + mips64r5900-*-* | mips64r5900el-*-* | mipsr5900-*-* | mipsr5900el-*-* | \
86 + mipsallegrex-*-* | mipsallegrexel-*-*)
87 + # The R5900 and Allegrex FPU only supports single precision.
88 with_fpu=single
89 ;;
90 esac
91 diff --git a/gcc/config/mips/allegrex.md b/gcc/config/mips/allegrex.md
92 new file mode 100644
93 index 00000000000..e9ae897bb18
94 --- /dev/null
95 +++ b/gcc/config/mips/allegrex.md
96 @@ -0,0 +1,145 @@
97 +;; Sony ALLEGREX instructions.
98 +;; Copyright (C) 2005 Free Software Foundation, Inc.
99 +;;
100 +;; This file is part of GCC.
101 +;;
102 +;; GCC is free software; you can redistribute it and/or modify
103 +;; it under the terms of the GNU General Public License as published by
104 +;; the Free Software Foundation; either version 2, or (at your option)
105 +;; any later version.
106 +;;
107 +;; GCC is distributed in the hope that it will be useful,
108 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
109 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
110 +;; GNU General Public License for more details.
111 +;;
112 +;; You should have received a copy of the GNU General Public License
113 +;; along with GCC; see the file COPYING. If not, write to
114 +;; the Free Software Foundation, 59 Temple Place - Suite 330,
115 +;; Boston, MA 02111-1307, USA.
116 +
117 +(define_c_enum "unspec" [
118 + UNSPEC_CLO
119 + UNSPEC_CTO
120 + UNSPEC_CACHE
121 + UNSPEC_CEIL_W_S
122 + UNSPEC_FLOOR_W_S
123 + UNSPEC_ROUND_W_S
124 +])
125 +
126 +;; Min and max.
127 +
128 +(define_insn "sminsi3"
129 + [(set (match_operand:SI 0 "register_operand" "=d")
130 + (smin:SI (match_operand:SI 1 "register_operand" "d")
131 + (match_operand:SI 2 "register_operand" "d")))]
132 + "TARGET_ALLEGREX"
133 + "min\t%0,%1,%2"
134 + [(set_attr "type" "arith")
135 + (set_attr "mode" "SI")])
136 +
137 +(define_insn "smaxsi3"
138 + [(set (match_operand:SI 0 "register_operand" "=d")
139 + (smax:SI (match_operand:SI 1 "register_operand" "d")
140 + (match_operand:SI 2 "register_operand" "d")))]
141 + "TARGET_ALLEGREX"
142 + "max\t%0,%1,%2"
143 + [(set_attr "type" "arith")
144 + (set_attr "mode" "SI")])
145 +
146 +
147 +;; Extended shift instructions.
148 +
149 +(define_insn "allegrex_bitrevsi2"
150 + [(set (match_operand:SI 0 "register_operand" "=d")
151 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
152 + UNSPEC_BITREV))]
153 + "TARGET_ALLEGREX"
154 + "bitrev\t%0,%1"
155 + [(set_attr "type" "arith")
156 + (set_attr "mode" "SI")])
157 +
158 +
159 +;; Count leading ones, count trailing zeros, and count trailing ones (clz is
160 +;; already defined).
161 +
162 +(define_insn "allegrex_closi2"
163 + [(set (match_operand:SI 0 "register_operand" "=d")
164 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
165 + UNSPEC_CLO))]
166 + "TARGET_ALLEGREX"
167 + "clo\t%0,%1"
168 + [(set_attr "type" "clz")
169 + (set_attr "mode" "SI")])
170 +
171 +
172 +(define_expand "allegrex_ctzsi2"
173 + [(set (match_operand:SI 0 "register_operand")
174 + (ctz:SI (match_operand:SI 1 "register_operand")))]
175 + "TARGET_ALLEGREX"
176 +{
177 + emit_insn (gen_allegrex_bitrevsi2 (operands[0], operands[1]));
178 + emit_insn (gen_clzsi2 (operands[0], operands[0]));
179 + DONE;
180 +})
181 +
182 +(define_expand "allegrex_ctosi2"
183 + [(set (match_operand:SI 0 "register_operand")
184 + (unspec:SI [(match_operand:SI 1 "register_operand")]
185 + UNSPEC_CTO))]
186 + "TARGET_ALLEGREX"
187 +{
188 + emit_insn (gen_allegrex_bitrevsi2 (operands[0], operands[1]));
189 + emit_insn (gen_allegrex_closi2 (operands[0], operands[0]));
190 + DONE;
191 +})
192 +
193 +
194 +;; Misc.
195 +
196 +(define_insn "allegrex_sync"
197 + [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
198 + "TARGET_ALLEGREX"
199 + "sync"
200 + [(set_attr "type" "unknown")
201 + (set_attr "mode" "none")])
202 +
203 +(define_insn "allegrex_cache"
204 + [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
205 + (match_operand:SI 1 "register_operand" "d")]
206 + UNSPEC_CACHE)]
207 + "TARGET_ALLEGREX"
208 + "cache\t%0,0(%1)"
209 + [(set_attr "type" "unknown")
210 + (set_attr "mode" "none")])
211 +
212 +
213 +;; Floating-point builtins.
214 +
215 +(define_insn "allegrex_ceilsfsi2"
216 + [(set (match_operand:SI 0 "register_operand" "=f")
217 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
218 + UNSPEC_CEIL_W_S))]
219 + "TARGET_ALLEGREX"
220 + "ceil.w.s\t%0,%1"
221 + [(set_attr "type" "fcvt")
222 + (set_attr "mode" "SF")])
223 +
224 +(define_insn "allegrex_floorsfsi2"
225 + [(set (match_operand:SI 0 "register_operand" "=f")
226 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
227 + UNSPEC_FLOOR_W_S))]
228 + "TARGET_ALLEGREX"
229 + "floor.w.s\t%0,%1"
230 + [(set_attr "type" "fcvt")
231 + (set_attr "mode" "SF")])
232 +
233 +(define_insn "allegrex_roundsfsi2"
234 + [(set (match_operand:SI 0 "register_operand" "=f")
235 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
236 + UNSPEC_ROUND_W_S))]
237 + "TARGET_ALLEGREX"
238 + "round.w.s\t%0,%1"
239 + [(set_attr "type" "fcvt")
240 + (set_attr "mode" "SF")])
241 +
242 diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
243 index b02294be4b9..95ec0c8b4b3 100644
244 --- a/gcc/config/mips/mips-cpus.def
245 +++ b/gcc/config/mips/mips-cpus.def
246 @@ -62,6 +62,7 @@ MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
247
248 /* MIPS II processors. */
249 MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
250 +MIPS_CPU ("allegrex", PROCESSOR_ALLEGREX, 2, 0)
251
252 /* MIPS III processors. */
253 MIPS_CPU ("r4000", PROCESSOR_R4000, 3, 0)
254 diff --git a/gcc/config/mips/mips-ftypes.def b/gcc/config/mips/mips-ftypes.def
255 index 74f21f16f6c..231282c0080 100644
256 --- a/gcc/config/mips/mips-ftypes.def
257 +++ b/gcc/config/mips/mips-ftypes.def
258 @@ -48,6 +48,8 @@ DEF_MIPS_FTYPE (2, (DI, SI, SI))
259 DEF_MIPS_FTYPE (2, (DI, USI, USI))
260 DEF_MIPS_FTYPE (2, (DI, V2DI, UQI))
261
262 +DEF_MIPS_FTYPE (1, (HI, HI))
263 +
264 DEF_MIPS_FTYPE (2, (INT, DF, DF))
265 DEF_MIPS_FTYPE (2, (INT, SF, SF))
266 DEF_MIPS_FTYPE (2, (INT, V2SF, V2SF))
267 @@ -59,7 +61,10 @@ DEF_MIPS_FTYPE (1, (SF, V2SF))
268 DEF_MIPS_FTYPE (1, (SF, V4SF))
269
270 DEF_MIPS_FTYPE (2, (SI, DI, SI))
271 +DEF_MIPS_FTYPE (1, (SI, HI))
272 DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
273 +DEF_MIPS_FTYPE (1, (SI, QI))
274 +DEF_MIPS_FTYPE (1, (SI, SF))
275 DEF_MIPS_FTYPE (1, (SI, SI))
276 DEF_MIPS_FTYPE (2, (SI, SI, SI))
277 DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
278 @@ -284,3 +289,4 @@ DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
279 DEF_MIPS_FTYPE (3, (VOID, V4SF, POINTER, SI))
280 DEF_MIPS_FTYPE (3, (VOID, V4SI, CVPOINTER, SI))
281 DEF_MIPS_FTYPE (3, (VOID, V8HI, CVPOINTER, SI))
282 +DEF_MIPS_FTYPE (1, (VOID, VOID))
283 diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt
284 index aef12f02dc7..2bf599c4fe2 100644
285 --- a/gcc/config/mips/mips-tables.opt
286 +++ b/gcc/config/mips/mips-tables.opt
287 @@ -160,554 +160,557 @@ EnumValue
288 Enum(mips_arch_opt_value) String(6k) Value(17)
289
290 EnumValue
291 -Enum(mips_arch_opt_value) String(r4000) Value(18) Canonical
292 +Enum(mips_arch_opt_value) String(allegrex) Value(18) Canonical
293
294 EnumValue
295 -Enum(mips_arch_opt_value) String(r4k) Value(18)
296 +Enum(mips_arch_opt_value) String(r4000) Value(19) Canonical
297
298 EnumValue
299 -Enum(mips_arch_opt_value) String(4000) Value(18)
300 +Enum(mips_arch_opt_value) String(r4k) Value(19)
301
302 EnumValue
303 -Enum(mips_arch_opt_value) String(4k) Value(18)
304 +Enum(mips_arch_opt_value) String(4000) Value(19)
305
306 EnumValue
307 -Enum(mips_arch_opt_value) String(vr4100) Value(19) Canonical
308 +Enum(mips_arch_opt_value) String(4k) Value(19)
309
310 EnumValue
311 -Enum(mips_arch_opt_value) String(4100) Value(19)
312 +Enum(mips_arch_opt_value) String(vr4100) Value(20) Canonical
313
314 EnumValue
315 -Enum(mips_arch_opt_value) String(r4100) Value(19)
316 +Enum(mips_arch_opt_value) String(4100) Value(20)
317
318 EnumValue
319 -Enum(mips_arch_opt_value) String(vr4111) Value(20) Canonical
320 +Enum(mips_arch_opt_value) String(r4100) Value(20)
321
322 EnumValue
323 -Enum(mips_arch_opt_value) String(4111) Value(20)
324 +Enum(mips_arch_opt_value) String(vr4111) Value(21) Canonical
325
326 EnumValue
327 -Enum(mips_arch_opt_value) String(r4111) Value(20)
328 +Enum(mips_arch_opt_value) String(4111) Value(21)
329
330 EnumValue
331 -Enum(mips_arch_opt_value) String(vr4120) Value(21) Canonical
332 +Enum(mips_arch_opt_value) String(r4111) Value(21)
333
334 EnumValue
335 -Enum(mips_arch_opt_value) String(4120) Value(21)
336 +Enum(mips_arch_opt_value) String(vr4120) Value(22) Canonical
337
338 EnumValue
339 -Enum(mips_arch_opt_value) String(r4120) Value(21)
340 +Enum(mips_arch_opt_value) String(4120) Value(22)
341
342 EnumValue
343 -Enum(mips_arch_opt_value) String(vr4130) Value(22) Canonical
344 +Enum(mips_arch_opt_value) String(r4120) Value(22)
345
346 EnumValue
347 -Enum(mips_arch_opt_value) String(4130) Value(22)
348 +Enum(mips_arch_opt_value) String(vr4130) Value(23) Canonical
349
350 EnumValue
351 -Enum(mips_arch_opt_value) String(r4130) Value(22)
352 +Enum(mips_arch_opt_value) String(4130) Value(23)
353
354 EnumValue
355 -Enum(mips_arch_opt_value) String(vr4300) Value(23) Canonical
356 +Enum(mips_arch_opt_value) String(r4130) Value(23)
357
358 EnumValue
359 -Enum(mips_arch_opt_value) String(4300) Value(23)
360 +Enum(mips_arch_opt_value) String(vr4300) Value(24) Canonical
361
362 EnumValue
363 -Enum(mips_arch_opt_value) String(r4300) Value(23)
364 +Enum(mips_arch_opt_value) String(4300) Value(24)
365
366 EnumValue
367 -Enum(mips_arch_opt_value) String(r4400) Value(24) Canonical
368 +Enum(mips_arch_opt_value) String(r4300) Value(24)
369
370 EnumValue
371 -Enum(mips_arch_opt_value) String(4400) Value(24)
372 +Enum(mips_arch_opt_value) String(r4400) Value(25) Canonical
373
374 EnumValue
375 -Enum(mips_arch_opt_value) String(r4600) Value(25) Canonical
376 +Enum(mips_arch_opt_value) String(4400) Value(25)
377
378 EnumValue
379 -Enum(mips_arch_opt_value) String(4600) Value(25)
380 +Enum(mips_arch_opt_value) String(r4600) Value(26) Canonical
381
382 EnumValue
383 -Enum(mips_arch_opt_value) String(orion) Value(26) Canonical
384 +Enum(mips_arch_opt_value) String(4600) Value(26)
385
386 EnumValue
387 -Enum(mips_arch_opt_value) String(r4650) Value(27) Canonical
388 +Enum(mips_arch_opt_value) String(orion) Value(27) Canonical
389
390 EnumValue
391 -Enum(mips_arch_opt_value) String(4650) Value(27)
392 +Enum(mips_arch_opt_value) String(r4650) Value(28) Canonical
393
394 EnumValue
395 -Enum(mips_arch_opt_value) String(r4700) Value(28) Canonical
396 +Enum(mips_arch_opt_value) String(4650) Value(28)
397
398 EnumValue
399 -Enum(mips_arch_opt_value) String(4700) Value(28)
400 +Enum(mips_arch_opt_value) String(r4700) Value(29) Canonical
401
402 EnumValue
403 -Enum(mips_arch_opt_value) String(r5900) Value(29) Canonical
404 +Enum(mips_arch_opt_value) String(4700) Value(29)
405
406 EnumValue
407 -Enum(mips_arch_opt_value) String(5900) Value(29)
408 +Enum(mips_arch_opt_value) String(r5900) Value(30) Canonical
409
410 EnumValue
411 -Enum(mips_arch_opt_value) String(loongson2e) Value(30) Canonical
412 +Enum(mips_arch_opt_value) String(5900) Value(30)
413
414 EnumValue
415 -Enum(mips_arch_opt_value) String(loongson2f) Value(31) Canonical
416 +Enum(mips_arch_opt_value) String(loongson2e) Value(31) Canonical
417
418 EnumValue
419 -Enum(mips_arch_opt_value) String(r8000) Value(32) Canonical
420 +Enum(mips_arch_opt_value) String(loongson2f) Value(32) Canonical
421
422 EnumValue
423 -Enum(mips_arch_opt_value) String(r8k) Value(32)
424 +Enum(mips_arch_opt_value) String(r8000) Value(33) Canonical
425
426 EnumValue
427 -Enum(mips_arch_opt_value) String(8000) Value(32)
428 +Enum(mips_arch_opt_value) String(r8k) Value(33)
429
430 EnumValue
431 -Enum(mips_arch_opt_value) String(8k) Value(32)
432 +Enum(mips_arch_opt_value) String(8000) Value(33)
433
434 EnumValue
435 -Enum(mips_arch_opt_value) String(r10000) Value(33) Canonical
436 +Enum(mips_arch_opt_value) String(8k) Value(33)
437
438 EnumValue
439 -Enum(mips_arch_opt_value) String(r10k) Value(33)
440 +Enum(mips_arch_opt_value) String(r10000) Value(34) Canonical
441
442 EnumValue
443 -Enum(mips_arch_opt_value) String(10000) Value(33)
444 +Enum(mips_arch_opt_value) String(r10k) Value(34)
445
446 EnumValue
447 -Enum(mips_arch_opt_value) String(10k) Value(33)
448 +Enum(mips_arch_opt_value) String(10000) Value(34)
449
450 EnumValue
451 -Enum(mips_arch_opt_value) String(r12000) Value(34) Canonical
452 +Enum(mips_arch_opt_value) String(10k) Value(34)
453
454 EnumValue
455 -Enum(mips_arch_opt_value) String(r12k) Value(34)
456 +Enum(mips_arch_opt_value) String(r12000) Value(35) Canonical
457
458 EnumValue
459 -Enum(mips_arch_opt_value) String(12000) Value(34)
460 +Enum(mips_arch_opt_value) String(r12k) Value(35)
461
462 EnumValue
463 -Enum(mips_arch_opt_value) String(12k) Value(34)
464 +Enum(mips_arch_opt_value) String(12000) Value(35)
465
466 EnumValue
467 -Enum(mips_arch_opt_value) String(r14000) Value(35) Canonical
468 +Enum(mips_arch_opt_value) String(12k) Value(35)
469
470 EnumValue
471 -Enum(mips_arch_opt_value) String(r14k) Value(35)
472 +Enum(mips_arch_opt_value) String(r14000) Value(36) Canonical
473
474 EnumValue
475 -Enum(mips_arch_opt_value) String(14000) Value(35)
476 +Enum(mips_arch_opt_value) String(r14k) Value(36)
477
478 EnumValue
479 -Enum(mips_arch_opt_value) String(14k) Value(35)
480 +Enum(mips_arch_opt_value) String(14000) Value(36)
481
482 EnumValue
483 -Enum(mips_arch_opt_value) String(r16000) Value(36) Canonical
484 +Enum(mips_arch_opt_value) String(14k) Value(36)
485
486 EnumValue
487 -Enum(mips_arch_opt_value) String(r16k) Value(36)
488 +Enum(mips_arch_opt_value) String(r16000) Value(37) Canonical
489
490 EnumValue
491 -Enum(mips_arch_opt_value) String(16000) Value(36)
492 +Enum(mips_arch_opt_value) String(r16k) Value(37)
493
494 EnumValue
495 -Enum(mips_arch_opt_value) String(16k) Value(36)
496 +Enum(mips_arch_opt_value) String(16000) Value(37)
497
498 EnumValue
499 -Enum(mips_arch_opt_value) String(vr5000) Value(37) Canonical
500 +Enum(mips_arch_opt_value) String(16k) Value(37)
501
502 EnumValue
503 -Enum(mips_arch_opt_value) String(vr5k) Value(37)
504 +Enum(mips_arch_opt_value) String(vr5000) Value(38) Canonical
505
506 EnumValue
507 -Enum(mips_arch_opt_value) String(5000) Value(37)
508 +Enum(mips_arch_opt_value) String(vr5k) Value(38)
509
510 EnumValue
511 -Enum(mips_arch_opt_value) String(5k) Value(37)
512 +Enum(mips_arch_opt_value) String(5000) Value(38)
513
514 EnumValue
515 -Enum(mips_arch_opt_value) String(r5000) Value(37)
516 +Enum(mips_arch_opt_value) String(5k) Value(38)
517
518 EnumValue
519 -Enum(mips_arch_opt_value) String(r5k) Value(37)
520 +Enum(mips_arch_opt_value) String(r5000) Value(38)
521
522 EnumValue
523 -Enum(mips_arch_opt_value) String(vr5400) Value(38) Canonical
524 +Enum(mips_arch_opt_value) String(r5k) Value(38)
525
526 EnumValue
527 -Enum(mips_arch_opt_value) String(5400) Value(38)
528 +Enum(mips_arch_opt_value) String(vr5400) Value(39) Canonical
529
530 EnumValue
531 -Enum(mips_arch_opt_value) String(r5400) Value(38)
532 +Enum(mips_arch_opt_value) String(5400) Value(39)
533
534 EnumValue
535 -Enum(mips_arch_opt_value) String(vr5500) Value(39) Canonical
536 +Enum(mips_arch_opt_value) String(r5400) Value(39)
537
538 EnumValue
539 -Enum(mips_arch_opt_value) String(5500) Value(39)
540 +Enum(mips_arch_opt_value) String(vr5500) Value(40) Canonical
541
542 EnumValue
543 -Enum(mips_arch_opt_value) String(r5500) Value(39)
544 +Enum(mips_arch_opt_value) String(5500) Value(40)
545
546 EnumValue
547 -Enum(mips_arch_opt_value) String(rm7000) Value(40) Canonical
548 +Enum(mips_arch_opt_value) String(r5500) Value(40)
549
550 EnumValue
551 -Enum(mips_arch_opt_value) String(rm7k) Value(40)
552 +Enum(mips_arch_opt_value) String(rm7000) Value(41) Canonical
553
554 EnumValue
555 -Enum(mips_arch_opt_value) String(7000) Value(40)
556 +Enum(mips_arch_opt_value) String(rm7k) Value(41)
557
558 EnumValue
559 -Enum(mips_arch_opt_value) String(7k) Value(40)
560 +Enum(mips_arch_opt_value) String(7000) Value(41)
561
562 EnumValue
563 -Enum(mips_arch_opt_value) String(r7000) Value(40)
564 +Enum(mips_arch_opt_value) String(7k) Value(41)
565
566 EnumValue
567 -Enum(mips_arch_opt_value) String(r7k) Value(40)
568 +Enum(mips_arch_opt_value) String(r7000) Value(41)
569
570 EnumValue
571 -Enum(mips_arch_opt_value) String(rm9000) Value(41) Canonical
572 +Enum(mips_arch_opt_value) String(r7k) Value(41)
573
574 EnumValue
575 -Enum(mips_arch_opt_value) String(rm9k) Value(41)
576 +Enum(mips_arch_opt_value) String(rm9000) Value(42) Canonical
577
578 EnumValue
579 -Enum(mips_arch_opt_value) String(9000) Value(41)
580 +Enum(mips_arch_opt_value) String(rm9k) Value(42)
581
582 EnumValue
583 -Enum(mips_arch_opt_value) String(9k) Value(41)
584 +Enum(mips_arch_opt_value) String(9000) Value(42)
585
586 EnumValue
587 -Enum(mips_arch_opt_value) String(r9000) Value(41)
588 +Enum(mips_arch_opt_value) String(9k) Value(42)
589
590 EnumValue
591 -Enum(mips_arch_opt_value) String(r9k) Value(41)
592 +Enum(mips_arch_opt_value) String(r9000) Value(42)
593
594 EnumValue
595 -Enum(mips_arch_opt_value) String(4kc) Value(42) Canonical
596 +Enum(mips_arch_opt_value) String(r9k) Value(42)
597
598 EnumValue
599 -Enum(mips_arch_opt_value) String(r4kc) Value(42)
600 +Enum(mips_arch_opt_value) String(4kc) Value(43) Canonical
601
602 EnumValue
603 -Enum(mips_arch_opt_value) String(4km) Value(43) Canonical
604 +Enum(mips_arch_opt_value) String(r4kc) Value(43)
605
606 EnumValue
607 -Enum(mips_arch_opt_value) String(r4km) Value(43)
608 +Enum(mips_arch_opt_value) String(4km) Value(44) Canonical
609
610 EnumValue
611 -Enum(mips_arch_opt_value) String(4kp) Value(44) Canonical
612 +Enum(mips_arch_opt_value) String(r4km) Value(44)
613
614 EnumValue
615 -Enum(mips_arch_opt_value) String(r4kp) Value(44)
616 +Enum(mips_arch_opt_value) String(4kp) Value(45) Canonical
617
618 EnumValue
619 -Enum(mips_arch_opt_value) String(4ksc) Value(45) Canonical
620 +Enum(mips_arch_opt_value) String(r4kp) Value(45)
621
622 EnumValue
623 -Enum(mips_arch_opt_value) String(r4ksc) Value(45)
624 +Enum(mips_arch_opt_value) String(4ksc) Value(46) Canonical
625
626 EnumValue
627 -Enum(mips_arch_opt_value) String(m4k) Value(46) Canonical
628 +Enum(mips_arch_opt_value) String(r4ksc) Value(46)
629
630 EnumValue
631 -Enum(mips_arch_opt_value) String(m14kc) Value(47) Canonical
632 +Enum(mips_arch_opt_value) String(m4k) Value(47) Canonical
633
634 EnumValue
635 -Enum(mips_arch_opt_value) String(m14k) Value(48) Canonical
636 +Enum(mips_arch_opt_value) String(m14kc) Value(48) Canonical
637
638 EnumValue
639 -Enum(mips_arch_opt_value) String(m14ke) Value(49) Canonical
640 +Enum(mips_arch_opt_value) String(m14k) Value(49) Canonical
641
642 EnumValue
643 -Enum(mips_arch_opt_value) String(m14kec) Value(50) Canonical
644 +Enum(mips_arch_opt_value) String(m14ke) Value(50) Canonical
645
646 EnumValue
647 -Enum(mips_arch_opt_value) String(4kec) Value(51) Canonical
648 +Enum(mips_arch_opt_value) String(m14kec) Value(51) Canonical
649
650 EnumValue
651 -Enum(mips_arch_opt_value) String(r4kec) Value(51)
652 +Enum(mips_arch_opt_value) String(4kec) Value(52) Canonical
653
654 EnumValue
655 -Enum(mips_arch_opt_value) String(4kem) Value(52) Canonical
656 +Enum(mips_arch_opt_value) String(r4kec) Value(52)
657
658 EnumValue
659 -Enum(mips_arch_opt_value) String(r4kem) Value(52)
660 +Enum(mips_arch_opt_value) String(4kem) Value(53) Canonical
661
662 EnumValue
663 -Enum(mips_arch_opt_value) String(4kep) Value(53) Canonical
664 +Enum(mips_arch_opt_value) String(r4kem) Value(53)
665
666 EnumValue
667 -Enum(mips_arch_opt_value) String(r4kep) Value(53)
668 +Enum(mips_arch_opt_value) String(4kep) Value(54) Canonical
669
670 EnumValue
671 -Enum(mips_arch_opt_value) String(4ksd) Value(54) Canonical
672 +Enum(mips_arch_opt_value) String(r4kep) Value(54)
673
674 EnumValue
675 -Enum(mips_arch_opt_value) String(r4ksd) Value(54)
676 +Enum(mips_arch_opt_value) String(4ksd) Value(55) Canonical
677
678 EnumValue
679 -Enum(mips_arch_opt_value) String(24kc) Value(55) Canonical
680 +Enum(mips_arch_opt_value) String(r4ksd) Value(55)
681
682 EnumValue
683 -Enum(mips_arch_opt_value) String(r24kc) Value(55)
684 +Enum(mips_arch_opt_value) String(24kc) Value(56) Canonical
685
686 EnumValue
687 -Enum(mips_arch_opt_value) String(24kf2_1) Value(56) Canonical
688 +Enum(mips_arch_opt_value) String(r24kc) Value(56)
689
690 EnumValue
691 -Enum(mips_arch_opt_value) String(r24kf2_1) Value(56)
692 +Enum(mips_arch_opt_value) String(24kf2_1) Value(57) Canonical
693
694 EnumValue
695 -Enum(mips_arch_opt_value) String(24kf) Value(57) Canonical
696 +Enum(mips_arch_opt_value) String(r24kf2_1) Value(57)
697
698 EnumValue
699 -Enum(mips_arch_opt_value) String(r24kf) Value(57)
700 +Enum(mips_arch_opt_value) String(24kf) Value(58) Canonical
701
702 EnumValue
703 -Enum(mips_arch_opt_value) String(24kf1_1) Value(58) Canonical
704 +Enum(mips_arch_opt_value) String(r24kf) Value(58)
705
706 EnumValue
707 -Enum(mips_arch_opt_value) String(r24kf1_1) Value(58)
708 +Enum(mips_arch_opt_value) String(24kf1_1) Value(59) Canonical
709
710 EnumValue
711 -Enum(mips_arch_opt_value) String(24kfx) Value(59) Canonical
712 +Enum(mips_arch_opt_value) String(r24kf1_1) Value(59)
713
714 EnumValue
715 -Enum(mips_arch_opt_value) String(r24kfx) Value(59)
716 +Enum(mips_arch_opt_value) String(24kfx) Value(60) Canonical
717
718 EnumValue
719 -Enum(mips_arch_opt_value) String(24kx) Value(60) Canonical
720 +Enum(mips_arch_opt_value) String(r24kfx) Value(60)
721
722 EnumValue
723 -Enum(mips_arch_opt_value) String(r24kx) Value(60)
724 +Enum(mips_arch_opt_value) String(24kx) Value(61) Canonical
725
726 EnumValue
727 -Enum(mips_arch_opt_value) String(24kec) Value(61) Canonical
728 +Enum(mips_arch_opt_value) String(r24kx) Value(61)
729
730 EnumValue
731 -Enum(mips_arch_opt_value) String(r24kec) Value(61)
732 +Enum(mips_arch_opt_value) String(24kec) Value(62) Canonical
733
734 EnumValue
735 -Enum(mips_arch_opt_value) String(24kef2_1) Value(62) Canonical
736 +Enum(mips_arch_opt_value) String(r24kec) Value(62)
737
738 EnumValue
739 -Enum(mips_arch_opt_value) String(r24kef2_1) Value(62)
740 +Enum(mips_arch_opt_value) String(24kef2_1) Value(63) Canonical
741
742 EnumValue
743 -Enum(mips_arch_opt_value) String(24kef) Value(63) Canonical
744 +Enum(mips_arch_opt_value) String(r24kef2_1) Value(63)
745
746 EnumValue
747 -Enum(mips_arch_opt_value) String(r24kef) Value(63)
748 +Enum(mips_arch_opt_value) String(24kef) Value(64) Canonical
749
750 EnumValue
751 -Enum(mips_arch_opt_value) String(24kef1_1) Value(64) Canonical
752 +Enum(mips_arch_opt_value) String(r24kef) Value(64)
753
754 EnumValue
755 -Enum(mips_arch_opt_value) String(r24kef1_1) Value(64)
756 +Enum(mips_arch_opt_value) String(24kef1_1) Value(65) Canonical
757
758 EnumValue
759 -Enum(mips_arch_opt_value) String(24kefx) Value(65) Canonical
760 +Enum(mips_arch_opt_value) String(r24kef1_1) Value(65)
761
762 EnumValue
763 -Enum(mips_arch_opt_value) String(r24kefx) Value(65)
764 +Enum(mips_arch_opt_value) String(24kefx) Value(66) Canonical
765
766 EnumValue
767 -Enum(mips_arch_opt_value) String(24kex) Value(66) Canonical
768 +Enum(mips_arch_opt_value) String(r24kefx) Value(66)
769
770 EnumValue
771 -Enum(mips_arch_opt_value) String(r24kex) Value(66)
772 +Enum(mips_arch_opt_value) String(24kex) Value(67) Canonical
773
774 EnumValue
775 -Enum(mips_arch_opt_value) String(34kc) Value(67) Canonical
776 +Enum(mips_arch_opt_value) String(r24kex) Value(67)
777
778 EnumValue
779 -Enum(mips_arch_opt_value) String(r34kc) Value(67)
780 +Enum(mips_arch_opt_value) String(34kc) Value(68) Canonical
781
782 EnumValue
783 -Enum(mips_arch_opt_value) String(34kf2_1) Value(68) Canonical
784 +Enum(mips_arch_opt_value) String(r34kc) Value(68)
785
786 EnumValue
787 -Enum(mips_arch_opt_value) String(r34kf2_1) Value(68)
788 +Enum(mips_arch_opt_value) String(34kf2_1) Value(69) Canonical
789
790 EnumValue
791 -Enum(mips_arch_opt_value) String(34kf) Value(69) Canonical
792 +Enum(mips_arch_opt_value) String(r34kf2_1) Value(69)
793
794 EnumValue
795 -Enum(mips_arch_opt_value) String(r34kf) Value(69)
796 +Enum(mips_arch_opt_value) String(34kf) Value(70) Canonical
797
798 EnumValue
799 -Enum(mips_arch_opt_value) String(34kf1_1) Value(70) Canonical
800 +Enum(mips_arch_opt_value) String(r34kf) Value(70)
801
802 EnumValue
803 -Enum(mips_arch_opt_value) String(r34kf1_1) Value(70)
804 +Enum(mips_arch_opt_value) String(34kf1_1) Value(71) Canonical
805
806 EnumValue
807 -Enum(mips_arch_opt_value) String(34kfx) Value(71) Canonical
808 +Enum(mips_arch_opt_value) String(r34kf1_1) Value(71)
809
810 EnumValue
811 -Enum(mips_arch_opt_value) String(r34kfx) Value(71)
812 +Enum(mips_arch_opt_value) String(34kfx) Value(72) Canonical
813
814 EnumValue
815 -Enum(mips_arch_opt_value) String(34kx) Value(72) Canonical
816 +Enum(mips_arch_opt_value) String(r34kfx) Value(72)
817
818 EnumValue
819 -Enum(mips_arch_opt_value) String(r34kx) Value(72)
820 +Enum(mips_arch_opt_value) String(34kx) Value(73) Canonical
821
822 EnumValue
823 -Enum(mips_arch_opt_value) String(34kn) Value(73) Canonical
824 +Enum(mips_arch_opt_value) String(r34kx) Value(73)
825
826 EnumValue
827 -Enum(mips_arch_opt_value) String(r34kn) Value(73)
828 +Enum(mips_arch_opt_value) String(34kn) Value(74) Canonical
829
830 EnumValue
831 -Enum(mips_arch_opt_value) String(74kc) Value(74) Canonical
832 +Enum(mips_arch_opt_value) String(r34kn) Value(74)
833
834 EnumValue
835 -Enum(mips_arch_opt_value) String(r74kc) Value(74)
836 +Enum(mips_arch_opt_value) String(74kc) Value(75) Canonical
837
838 EnumValue
839 -Enum(mips_arch_opt_value) String(74kf2_1) Value(75) Canonical
840 +Enum(mips_arch_opt_value) String(r74kc) Value(75)
841
842 EnumValue
843 -Enum(mips_arch_opt_value) String(r74kf2_1) Value(75)
844 +Enum(mips_arch_opt_value) String(74kf2_1) Value(76) Canonical
845
846 EnumValue
847 -Enum(mips_arch_opt_value) String(74kf) Value(76) Canonical
848 +Enum(mips_arch_opt_value) String(r74kf2_1) Value(76)
849
850 EnumValue
851 -Enum(mips_arch_opt_value) String(r74kf) Value(76)
852 +Enum(mips_arch_opt_value) String(74kf) Value(77) Canonical
853
854 EnumValue
855 -Enum(mips_arch_opt_value) String(74kf1_1) Value(77) Canonical
856 +Enum(mips_arch_opt_value) String(r74kf) Value(77)
857
858 EnumValue
859 -Enum(mips_arch_opt_value) String(r74kf1_1) Value(77)
860 +Enum(mips_arch_opt_value) String(74kf1_1) Value(78) Canonical
861
862 EnumValue
863 -Enum(mips_arch_opt_value) String(74kfx) Value(78) Canonical
864 +Enum(mips_arch_opt_value) String(r74kf1_1) Value(78)
865
866 EnumValue
867 -Enum(mips_arch_opt_value) String(r74kfx) Value(78)
868 +Enum(mips_arch_opt_value) String(74kfx) Value(79) Canonical
869
870 EnumValue
871 -Enum(mips_arch_opt_value) String(74kx) Value(79) Canonical
872 +Enum(mips_arch_opt_value) String(r74kfx) Value(79)
873
874 EnumValue
875 -Enum(mips_arch_opt_value) String(r74kx) Value(79)
876 +Enum(mips_arch_opt_value) String(74kx) Value(80) Canonical
877
878 EnumValue
879 -Enum(mips_arch_opt_value) String(74kf3_2) Value(80) Canonical
880 +Enum(mips_arch_opt_value) String(r74kx) Value(80)
881
882 EnumValue
883 -Enum(mips_arch_opt_value) String(r74kf3_2) Value(80)
884 +Enum(mips_arch_opt_value) String(74kf3_2) Value(81) Canonical
885
886 EnumValue
887 -Enum(mips_arch_opt_value) String(1004kc) Value(81) Canonical
888 +Enum(mips_arch_opt_value) String(r74kf3_2) Value(81)
889
890 EnumValue
891 -Enum(mips_arch_opt_value) String(r1004kc) Value(81)
892 +Enum(mips_arch_opt_value) String(1004kc) Value(82) Canonical
893
894 EnumValue
895 -Enum(mips_arch_opt_value) String(1004kf2_1) Value(82) Canonical
896 +Enum(mips_arch_opt_value) String(r1004kc) Value(82)
897
898 EnumValue
899 -Enum(mips_arch_opt_value) String(r1004kf2_1) Value(82)
900 +Enum(mips_arch_opt_value) String(1004kf2_1) Value(83) Canonical
901
902 EnumValue
903 -Enum(mips_arch_opt_value) String(1004kf) Value(83) Canonical
904 +Enum(mips_arch_opt_value) String(r1004kf2_1) Value(83)
905
906 EnumValue
907 -Enum(mips_arch_opt_value) String(r1004kf) Value(83)
908 +Enum(mips_arch_opt_value) String(1004kf) Value(84) Canonical
909
910 EnumValue
911 -Enum(mips_arch_opt_value) String(1004kf1_1) Value(84) Canonical
912 +Enum(mips_arch_opt_value) String(r1004kf) Value(84)
913
914 EnumValue
915 -Enum(mips_arch_opt_value) String(r1004kf1_1) Value(84)
916 +Enum(mips_arch_opt_value) String(1004kf1_1) Value(85) Canonical
917
918 EnumValue
919 -Enum(mips_arch_opt_value) String(interaptiv) Value(85) Canonical
920 +Enum(mips_arch_opt_value) String(r1004kf1_1) Value(85)
921
922 EnumValue
923 -Enum(mips_arch_opt_value) String(p5600) Value(86) Canonical
924 +Enum(mips_arch_opt_value) String(interaptiv) Value(86) Canonical
925
926 EnumValue
927 -Enum(mips_arch_opt_value) String(m5100) Value(87) Canonical
928 +Enum(mips_arch_opt_value) String(p5600) Value(87) Canonical
929
930 EnumValue
931 -Enum(mips_arch_opt_value) String(m5101) Value(88) Canonical
932 +Enum(mips_arch_opt_value) String(m5100) Value(88) Canonical
933
934 EnumValue
935 -Enum(mips_arch_opt_value) String(5kc) Value(89) Canonical
936 +Enum(mips_arch_opt_value) String(m5101) Value(89) Canonical
937
938 EnumValue
939 -Enum(mips_arch_opt_value) String(r5kc) Value(89)
940 +Enum(mips_arch_opt_value) String(5kc) Value(90) Canonical
941
942 EnumValue
943 -Enum(mips_arch_opt_value) String(5kf) Value(90) Canonical
944 +Enum(mips_arch_opt_value) String(r5kc) Value(90)
945
946 EnumValue
947 -Enum(mips_arch_opt_value) String(r5kf) Value(90)
948 +Enum(mips_arch_opt_value) String(5kf) Value(91) Canonical
949
950 EnumValue
951 -Enum(mips_arch_opt_value) String(20kc) Value(91) Canonical
952 +Enum(mips_arch_opt_value) String(r5kf) Value(91)
953
954 EnumValue
955 -Enum(mips_arch_opt_value) String(r20kc) Value(91)
956 +Enum(mips_arch_opt_value) String(20kc) Value(92) Canonical
957
958 EnumValue
959 -Enum(mips_arch_opt_value) String(sb1) Value(92) Canonical
960 +Enum(mips_arch_opt_value) String(r20kc) Value(92)
961
962 EnumValue
963 -Enum(mips_arch_opt_value) String(sb1a) Value(93) Canonical
964 +Enum(mips_arch_opt_value) String(sb1) Value(93) Canonical
965
966 EnumValue
967 -Enum(mips_arch_opt_value) String(sr71000) Value(94) Canonical
968 +Enum(mips_arch_opt_value) String(sb1a) Value(94) Canonical
969
970 EnumValue
971 -Enum(mips_arch_opt_value) String(sr71k) Value(94)
972 +Enum(mips_arch_opt_value) String(sr71000) Value(95) Canonical
973
974 EnumValue
975 -Enum(mips_arch_opt_value) String(xlr) Value(95) Canonical
976 +Enum(mips_arch_opt_value) String(sr71k) Value(95)
977
978 EnumValue
979 -Enum(mips_arch_opt_value) String(loongson3a) Value(96) Canonical
980 +Enum(mips_arch_opt_value) String(xlr) Value(96) Canonical
981
982 EnumValue
983 -Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical
984 +Enum(mips_arch_opt_value) String(loongson3a) Value(97) Canonical
985
986 EnumValue
987 -Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical
988 +Enum(mips_arch_opt_value) String(gs464) Value(98) Canonical
989
990 EnumValue
991 -Enum(mips_arch_opt_value) String(gs264e) Value(99) Canonical
992 +Enum(mips_arch_opt_value) String(gs464e) Value(99) Canonical
993
994 EnumValue
995 -Enum(mips_arch_opt_value) String(octeon) Value(100) Canonical
996 +Enum(mips_arch_opt_value) String(gs264e) Value(100) Canonical
997
998 EnumValue
999 -Enum(mips_arch_opt_value) String(octeon+) Value(101) Canonical
1000 +Enum(mips_arch_opt_value) String(octeon) Value(101) Canonical
1001
1002 EnumValue
1003 -Enum(mips_arch_opt_value) String(octeon2) Value(102) Canonical
1004 +Enum(mips_arch_opt_value) String(octeon+) Value(102) Canonical
1005
1006 EnumValue
1007 -Enum(mips_arch_opt_value) String(octeon3) Value(103) Canonical
1008 +Enum(mips_arch_opt_value) String(octeon2) Value(103) Canonical
1009
1010 EnumValue
1011 -Enum(mips_arch_opt_value) String(xlp) Value(104) Canonical
1012 +Enum(mips_arch_opt_value) String(octeon3) Value(104) Canonical
1013
1014 EnumValue
1015 -Enum(mips_arch_opt_value) String(i6400) Value(105) Canonical
1016 +Enum(mips_arch_opt_value) String(xlp) Value(105) Canonical
1017
1018 EnumValue
1019 -Enum(mips_arch_opt_value) String(i6500) Value(106) Canonical
1020 +Enum(mips_arch_opt_value) String(i6400) Value(106) Canonical
1021
1022 EnumValue
1023 -Enum(mips_arch_opt_value) String(p6600) Value(107) Canonical
1024 +Enum(mips_arch_opt_value) String(i6500) Value(107) Canonical
1025 +
1026 +EnumValue
1027 +Enum(mips_arch_opt_value) String(p6600) Value(108) Canonical
1028
1029 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
1030 index 315545966f8..29d51acfc6b 100644
1031 --- a/gcc/config/mips/mips.c
1032 +++ b/gcc/config/mips/mips.c
1033 @@ -263,7 +263,12 @@ enum mips_builtin_type {
1034 MIPS_BUILTIN_MSA_TEST_BRANCH,
1035
1036 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
1037 - MIPS_BUILTIN_BPOSGE32
1038 + MIPS_BUILTIN_BPOSGE32,
1039 +
1040 + /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0
1041 + is the function code (must be less than 32) and operand 1 is the base
1042 + address. */
1043 + MIPS_BUILTIN_CACHE
1044 };
1045
1046 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
1047 @@ -470,6 +475,10 @@ struct mips_asm_switch mips_noat = { "at", 0 };
1048 normal branch. */
1049 static bool mips_branch_likely;
1050
1051 +/* Preferred stack boundary for proper stack vars alignment */
1052 +unsigned int mips_preferred_stack_boundary;
1053 +unsigned int mips_preferred_stack_align;
1054 +
1055 /* The current instruction-set architecture. */
1056 enum processor mips_arch;
1057 const struct mips_cpu_info *mips_arch_info;
1058 @@ -830,6 +839,9 @@ static const struct mips_rtx_cost_data
1059 1, /* branch_cost */
1060 4 /* memory_latency */
1061 },
1062 + { /* Allegrex */
1063 + DEFAULT_COSTS
1064 + },
1065 { /* Loongson-2E */
1066 DEFAULT_COSTS
1067 },
1068 @@ -15266,6 +15278,7 @@ AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
1069 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
1070 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI)
1071 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
1072 +AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
1073 AVAIL_NON_MIPS16 (msa, TARGET_MSA)
1074
1075 /* Construct a mips_builtin_description from the given arguments.
1076 @@ -15372,6 +15385,24 @@ AVAIL_NON_MIPS16 (msa, TARGET_MSA)
1077 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
1078 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL, false)
1079
1080 +/* Same as the above, but mapped to an instruction that doesn't share the
1081 + NAME. NAME is the name of the builtin without the builtin prefix. */
1082 +#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
1083 + { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME, \
1084 + MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
1085 +
1086 +/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
1087 + CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
1088 + builtin_description fields. */
1089 +#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
1090 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
1091 + MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex, false }
1092 +
1093 +/* Define a builtin with a specific function TYPE. */
1094 +#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
1095 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
1096 + MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
1097 +
1098 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
1099 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
1100 builtin_description field. */
1101 @@ -15855,6 +15886,37 @@ static const struct mips_builtin_description mips_builtins[] = {
1102 DIRECT_BUILTIN_PURE (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
1103 DIRECT_BUILTIN_PURE (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
1104
1105 + /* Builtin functions for the Sony ALLEGREX processor.
1106 + These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
1107 + to maintain compatibility with Sony's ALLEGREX GCC port.
1108 + Some of the builtins may seem redundant, but they are the same as the
1109 + builtins defined in the Sony compiler. I chose to map redundant and
1110 + trivial builtins to the original instruction instead of creating
1111 + duplicate patterns specifically for the ALLEGREX (as Sony does). */
1112 +
1113 + DIRECT_ALLEGREX_NAMED_BUILTIN(bitrev, allegrex_bitrevsi2, MIPS_SI_FTYPE_SI, 0),
1114 + DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
1115 + DIRECT_ALLEGREX_NAMED_BUILTIN(clo, allegrex_closi2, MIPS_SI_FTYPE_SI, 0),
1116 + DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, allegrex_ctzsi2, MIPS_SI_FTYPE_SI, 0),
1117 + DIRECT_ALLEGREX_NAMED_BUILTIN(cto, allegrex_ctosi2, MIPS_SI_FTYPE_SI, 0),
1118 + DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
1119 +
1120 + DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
1121 + DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
1122 + DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
1123 + DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
1124 + DIRECT_ALLEGREX_NAMED_BUILTIN(wsbw, bswapsi2, MIPS_SI_FTYPE_SI, 0),
1125 + DIRECT_ALLEGREX_NAMED_BUILTIN(wsbh, bswaphi2, MIPS_HI_FTYPE_HI, 0),
1126 +
1127 + DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
1128 + SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
1129 +
1130 + DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
1131 + DIRECT_ALLEGREX_NAMED_BUILTIN(ceil_w_s, allegrex_ceilsfsi2, MIPS_SI_FTYPE_SF, 0),
1132 + DIRECT_ALLEGREX_NAMED_BUILTIN(floor_w_s, allegrex_floorsfsi2, MIPS_SI_FTYPE_SF, 0),
1133 + DIRECT_ALLEGREX_NAMED_BUILTIN(round_w_s, allegrex_roundsfsi2, MIPS_SI_FTYPE_SF, 0),
1134 + DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
1135 +
1136 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
1137 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
1138 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
1139 @@ -17249,6 +17311,26 @@ mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
1140 const1_rtx, const0_rtx);
1141 }
1142
1143 +/* Expand a __builtin_allegrex_cache() function. Make sure the passed
1144 + cache function code is less than 32. */
1145 +
1146 +static rtx
1147 +mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
1148 +{
1149 + int argno;
1150 + struct expand_operand ops[2];
1151 +
1152 + for (argno = 0; argno < 2; argno++)
1153 + mips_prepare_builtin_arg (&ops[argno], exp, argno);
1154 +
1155 + if (GET_CODE(ops[0].value) != CONST_INT ||
1156 + INTVAL(ops[0].value) < 0 || INTVAL(ops[0].value) > 0x1f)
1157 + error("Invalid first argument for cache builtin (0 <= arg <= 31)");
1158 +
1159 + emit_insn(mips_expand_builtin_insn (icode, 2, ops, false));
1160 + return target;
1161 +}
1162 +
1163 /* Implement TARGET_EXPAND_BUILTIN. */
1164
1165 static rtx
1166 @@ -17297,6 +17379,9 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
1167
1168 case MIPS_BUILTIN_BPOSGE32:
1169 return mips_expand_builtin_bposge (d->builtin_type, target);
1170 +
1171 + case MIPS_BUILTIN_CACHE:
1172 + return mips_expand_builtin_cache (d->icode, target, exp);
1173 }
1174 gcc_unreachable ();
1175 }
1176 @@ -20443,6 +20528,22 @@ mips_option_override (void)
1177 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
1178 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
1179
1180 + /* Validate -mpreferred-stack-boundary= value, or provide default.
1181 + The default of 128-bit is for newABI else 64-bit. */
1182 + mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
1183 + mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
1184 + if (mips_preferred_stack_boundary_string)
1185 + {
1186 + i = atoi (mips_preferred_stack_boundary_string);
1187 + if (i < 2 || i > 12)
1188 + error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
1189 + else
1190 + {
1191 + mips_preferred_stack_align = (1 << i);
1192 + mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
1193 + }
1194 + }
1195 +
1196 mips_register_frame_header_opt ();
1197 }
1198
1199 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
1200 index 47aac9d3d61..3dfbc6152b4 100644
1201 --- a/gcc/config/mips/mips.h
1202 +++ b/gcc/config/mips/mips.h
1203 @@ -288,6 +288,7 @@ struct mips_cpu_info {
1204 || mips_arch == PROCESSOR_SB1A)
1205 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
1206 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
1207 +#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX)
1208
1209 /* Scheduling target defines. */
1210 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
1211 @@ -322,6 +323,7 @@ struct mips_cpu_info {
1212 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
1213 #define TUNE_I6400 (mips_tune == PROCESSOR_I6400)
1214 #define TUNE_P6600 (mips_tune == PROCESSOR_P6600)
1215 +#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX)
1216
1217 /* True if the pre-reload scheduler should try to create chains of
1218 multiply-add or multiply-subtract instructions. For example,
1219 @@ -1052,6 +1054,7 @@ struct mips_cpu_info {
1220 ST Loongson 2E/2F. */
1221 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
1222 || TARGET_MIPS5900 \
1223 + || TARGET_ALLEGREX \
1224 || TARGET_LOONGSON_2EF)
1225
1226 /* ISA has LDC1 and SDC1. */
1227 @@ -1094,11 +1097,13 @@ struct mips_cpu_info {
1228
1229 /* ISA has conditional trap instructions. */
1230 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
1231 + && !TARGET_ALLEGREX \
1232 && !TARGET_MIPS16)
1233
1234 /* ISA has conditional trap with immediate instructions. */
1235 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
1236 && mips_isa_rev <= 5 \
1237 + && !TARGET_ALLEGREX \
1238 && !TARGET_MIPS16)
1239
1240 /* ISA has integer multiply-accumulate instructions, madd and msub. */
1241 @@ -1157,7 +1162,8 @@ struct mips_cpu_info {
1242 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1243
1244 /* ISA has count leading zeroes/ones instruction (not implemented). */
1245 -#define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
1246 +#define ISA_HAS_CLZ_CLO ((mips_isa_rev >= 1 && !TARGET_MIPS16) \
1247 + || TARGET_ALLEGREX)
1248
1249 /* ISA has count trailing zeroes/ones instruction. */
1250 #define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2)
1251 @@ -1199,6 +1205,7 @@ struct mips_cpu_info {
1252
1253 /* ISA has the "ror" (rotate right) instructions. */
1254 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
1255 + || TARGET_ALLEGREX \
1256 || TARGET_MIPS5400 \
1257 || TARGET_MIPS5500 \
1258 || TARGET_SR71K \
1259 @@ -1207,7 +1214,11 @@ struct mips_cpu_info {
1260
1261 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1262 64-bit targets also provide DSBH and DSHD. */
1263 -#define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1264 +#define ISA_HAS_WSBH ((mips_isa_rev >= 2 && !TARGET_MIPS16) \
1265 + || TARGET_ALLEGREX)
1266 +
1267 +/* Similar to WSBH but for 32 bit words. */
1268 +#define ISA_HAS_WSBW (TARGET_ALLEGREX)
1269
1270 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1271 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1272 @@ -1233,10 +1244,12 @@ struct mips_cpu_info {
1273 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1274
1275 /* ISA includes the MIPS32r2 seb and seh instructions. */
1276 -#define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1277 +#define ISA_HAS_SEB_SEH ((mips_isa_rev >= 2 && !TARGET_MIPS16) \
1278 + || TARGET_ALLEGREX)
1279
1280 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1281 -#define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1282 +#define ISA_HAS_EXT_INS ((mips_isa_rev >= 2 && !TARGET_MIPS16) \
1283 + || TARGET_ALLEGREX)
1284
1285 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1286 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1287 @@ -1297,6 +1310,7 @@ struct mips_cpu_info {
1288 earlier-ISA CPUs for which CPU documentation declares that the
1289 instructions are really interlocked. */
1290 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1291 + || TARGET_ALLEGREX \
1292 || TARGET_MIPS5500 \
1293 || TARGET_MIPS5900 \
1294 || TARGET_LOONGSON_2EF)
1295 @@ -2399,7 +2413,7 @@ enum reg_class
1296 `crtl->outgoing_args_size'. */
1297 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1298
1299 -#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1300 +#define STACK_BOUNDARY (mips_preferred_stack_boundary)
1301 \f
1302 /* Symbolic macros for the registers used to return integer and floating
1303 point values. */
1304 @@ -2526,7 +2540,7 @@ typedef struct mips_args {
1305 /* Treat LOC as a byte offset from the stack pointer and round it up
1306 to the next fully-aligned offset. */
1307 #define MIPS_STACK_ALIGN(LOC) \
1308 - (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
1309 + (ROUND_UP ((LOC), mips_preferred_stack_align))
1310
1311 \f
1312 /* Output assembler code to FILE to increment profiler label # LABELNO
1313 @@ -3175,6 +3189,9 @@ while (0)
1314 " TEXT_SECTION_ASM_OP);
1315 #endif
1316
1317 +extern unsigned int mips_preferred_stack_boundary;
1318 +extern unsigned int mips_preferred_stack_align;
1319 +
1320 #ifndef HAVE_AS_TLS
1321 #define HAVE_AS_TLS 0
1322 #endif
1323 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
1324 index eef3cfd50a8..e8fc4fbcafa 100644
1325 --- a/gcc/config/mips/mips.md
1326 +++ b/gcc/config/mips/mips.md
1327 @@ -35,6 +35,7 @@
1328 74kf2_1
1329 74kf1_1
1330 74kf3_2
1331 + allegrex
1332 loongson_2e
1333 loongson_2f
1334 gs464
1335 @@ -819,7 +820,8 @@
1336 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
1337 (CC "TARGET_HARD_FLOAT
1338 && !TARGET_LOONGSON_2EF
1339 - && !TARGET_MIPS5900")])
1340 + && !TARGET_MIPS5900
1341 + && !TARGET_ALLEGREX")])
1342
1343 ;; This mode iterator allows :FPCC to be used anywhere that an FP condition
1344 ;; is needed.
1345 @@ -2260,11 +2262,11 @@
1346 (mult:DI
1347 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1348 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1349 - "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
1350 + "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)"
1351 {
1352 if (ISA_HAS_DSP_MULT)
1353 return "msub<u>\t%q0,%1,%2";
1354 - else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1355 + else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX)
1356 return "msub<u>\t%1,%2";
1357 else
1358 return "msac<u>\t$0,%1,%2";
1359 @@ -2543,14 +2545,14 @@
1360 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1361 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1362 (match_operand:DI 3 "muldiv_target_operand" "0")))]
1363 - "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
1364 + "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)
1365 && !TARGET_64BIT"
1366 {
1367 if (TARGET_MAD)
1368 return "mad<u>\t%1,%2";
1369 else if (ISA_HAS_DSP_MULT)
1370 return "madd<u>\t%q0,%1,%2";
1371 - else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
1372 + else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX)
1373 return "madd<u>\t%1,%2";
1374 else
1375 /* See comment in *macc. */
1376 @@ -5866,12 +5868,19 @@
1377 "wsbh\t%0,%1"
1378 [(set_attr "type" "shift")])
1379
1380 -(define_insn_and_split "bswapsi2"
1381 +(define_insn "bswapsi2"
1382 + [(set (match_operand:SI 0 "register_operand" "=d")
1383 + (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
1384 + "ISA_HAS_WSBW"
1385 + "wsbw\t%0,%1"
1386 + [(set_attr "type" "shift")])
1387 +
1388 +(define_insn_and_split "bswapsi2_split"
1389 [(set (match_operand:SI 0 "register_operand" "=d")
1390 (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
1391 "ISA_HAS_WSBH && ISA_HAS_ROR"
1392 "#"
1393 - ""
1394 + "&& !ISA_HAS_WSBW"
1395 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH))
1396 (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
1397 ""
1398 @@ -7805,6 +7814,9 @@
1399 ; The MIPS MSA Instructions.
1400 (include "mips-msa.md")
1401
1402 +; Sony ALLEGREX instructions.
1403 +(include "allegrex.md")
1404 +
1405 (define_c_enum "unspec" [
1406 UNSPEC_ADDRESS_FIRST
1407 ])
1408 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
1409 index 6af8037e9bd..d1e6c41a699 100644
1410 --- a/gcc/config/mips/mips.opt
1411 +++ b/gcc/config/mips/mips.opt
1412 @@ -475,3 +475,7 @@ Use Loongson EXTension (EXT) instructions.
1413 mloongson-ext2
1414 Target Var(TARGET_LOONGSON_EXT2)
1415 Use Loongson EXTension R2 (EXT2) instructions.
1416 +
1417 +mpreferred-stack-boundary=
1418 +Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
1419 +Attempt to keep stack aligned to this power of 2
1420 diff --git a/gcc/config/mips/psp.h b/gcc/config/mips/psp.h
1421 new file mode 100644
1422 index 00000000000..ebe54af60ed
1423 --- /dev/null
1424 +++ b/gcc/config/mips/psp.h
1425 @@ -0,0 +1,42 @@
1426 +/* Support for Sony's Playstation Portable (PSP).
1427 + Copyright (C) 2005 Free Software Foundation, Inc.
1428 + Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
1429 +
1430 +This file is part of GCC.
1431 +
1432 +GCC is free software; you can redistribute it and/or modify
1433 +it under the terms of the GNU General Public License as published by
1434 +the Free Software Foundation; either version 2, or (at your option)
1435 +any later version.
1436 +
1437 +GCC is distributed in the hope that it will be useful,
1438 +but WITHOUT ANY WARRANTY; without even the implied warranty of
1439 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1440 +GNU General Public License for more details.
1441 +
1442 +You should have received a copy of the GNU General Public License
1443 +along with GCC; see the file COPYING. If not, write to
1444 +the Free Software Foundation, 59 Temple Place - Suite 330,
1445 +Boston, MA 02111-1307, USA. */
1446 +
1447 +#undef LIB_SPEC
1448 +#define LIB_SPEC " \
1449 + -lm \
1450 + --start-group \
1451 + -lpthreadglue \
1452 + -lpthread \
1453 + -lcglue \
1454 + %{g:-lg} %{!g:-lc} \
1455 + --end-group \
1456 + -lpsputility -lpsprtc -lpspnet_inet -lpspnet_resolver \
1457 + -lpspsdk -lpspmodinfo -lpspuser -lpspkernel"
1458 +
1459 +/* Override the startfile spec to include crt0.o. */
1460 +#undef STARTFILE_SPEC
1461 +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
1462 +
1463 +#undef SUBTARGET_CPP_SPEC
1464 +#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__PSP__=1 -D_PSP=1 -D__psp__=1"
1465 +
1466 +#undef ENDFILE_SPEC
1467 +#define ENDFILE_SPEC "crtend%O%s crtn%O%s"
1468 diff --git a/gcc/optabs.c b/gcc/optabs.c
1469 index f4614a39458..8f40b6225ad 100644
1470 --- a/gcc/optabs.c
1471 +++ b/gcc/optabs.c
1472 @@ -7779,6 +7779,8 @@ maybe_gen_insn (enum insn_code icode, unsigned int nops,
1473
1474 switch (nops)
1475 {
1476 + case 0:
1477 + return GEN_FCN (icode) ();
1478 case 1:
1479 return GEN_FCN (icode) (ops[0].value);
1480 case 2:
1481 diff --git a/libatomic/configure b/libatomic/configure
1482 index 5867e69ac14..b12740dc246 100755
1483 --- a/libatomic/configure
1484 +++ b/libatomic/configure
1485 @@ -1264,6 +1264,13 @@ build=$build_alias
1486 host=$host_alias
1487 target=$target_alias
1488
1489 +# PSP SPECIFIC CODE
1490 +# Skipping some Tests for PSP platform because pspsdk libraries aren't ready yet.
1491 +skipTests=0
1492 +if [ "$target" == "psp" ]; then
1493 + skipTests=1
1494 +fi
1495 +
1496 # FIXME: To remove some day.
1497 if test "x$host_alias" != x; then
1498 if test "x$build_alias" = x; then
1499 @@ -3816,7 +3823,7 @@ test "$ac_cv_exeext" = no && ac_cv_exeext=
1500 else
1501 ac_file=''
1502 fi
1503 -if test -z "$ac_file"; then :
1504 +if [test -z "$ac_file"] && [ "$skipTests" -eq "0" ]; then :
1505 { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
1506 $as_echo "no" >&6; }
1507 $as_echo "$as_me: failed program was:" >&5
1508 @@ -3864,7 +3871,7 @@ for ac_file in conftest.exe conftest conftest.*; do
1509 * ) break;;
1510 esac
1511 done
1512 -else
1513 +elif "$skipTests" -eq "0"; then :
1514 { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
1515 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
1516 as_fn_error $? "cannot compute suffix of executables: cannot compile and link
1517 @@ -14895,7 +14902,7 @@ pthread_t t; pthread_create(&t,NULL,g,NULL);
1518 _ACEOF
1519 if ac_fn_c_try_link "$LINENO"; then :
1520
1521 -else
1522 +elif "$skipTests" -eq "0"; then :
1523 as_fn_error $? "Pthreads are required to build libatomic" "$LINENO" 5
1524 fi
1525 rm -f core conftest.err conftest.$ac_objext \
1526 diff --git a/libatomic/configure.tgt b/libatomic/configure.tgt
1527 index 670b0d72cfe..efb1d639f42 100644
1528 --- a/libatomic/configure.tgt
1529 +++ b/libatomic/configure.tgt
1530 @@ -148,7 +148,7 @@ case "${target}" in
1531 tmake_file="t-aix"
1532 ;;
1533
1534 - *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu \
1535 + *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu | *-psp-elf* \
1536 | *-*-netbsd* | *-*-freebsd* | *-*-openbsd* | *-*-dragonfly* \
1537 | *-*-solaris2* | *-*-sysv4* | *-*-irix6* | *-*-osf* | *-*-hpux11* \
1538 | *-*-darwin* | *-*-aix* | *-*-cygwin*)
1539 diff --git a/libgcc/config.host b/libgcc/config.host
1540 index 50f00062232..f3ccd37fd4f 100644
1541 --- a/libgcc/config.host
1542 +++ b/libgcc/config.host
1543 @@ -148,10 +148,16 @@ microblaze*-*-*)
1544 ;;
1545 mips*-*-*)
1546 # All MIPS targets provide a full set of FP routines.
1547 + # (except for allegrex and R5900)
1548 cpu_type=mips
1549 tmake_file="mips/t-mips"
1550 if test "${libgcc_cv_mips_hard_float}" = yes; then
1551 - tmake_file="${tmake_file} t-hardfp-sfdf t-hardfp"
1552 + if test "${libgcc_cv_mips_single_float}" = yes; then
1553 + tmake_file="${tmake_file} t-hardfp-sf"
1554 + else
1555 + tmake_file="${tmake_file} t-hardfp-sfdf"
1556 + fi
1557 + tmake_file="${tmake_file} t-hardfp"
1558 else
1559 tmake_file="${tmake_file} t-softfp-sfdf"
1560 fi
1561 @@ -1053,6 +1059,12 @@ mips-wrs-vxworks)
1562 mipstx39-*-elf* | mipstx39el-*-elf*)
1563 tmake_file="$tmake_file mips/t-crtstuff mips/t-mips16"
1564 ;;
1565 +mips*-psp*)
1566 + tmake_file="${tmake_file} mips/t-elf mips/t-crtstuff"
1567 + target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
1568 + tm_file="${tm_file}"
1569 + extra_parts="$extra_parts crti.o crtn.o"
1570 + ;;
1571 mmix-knuth-mmixware)
1572 extra_parts="crti.o crtn.o crtbegin.o crtend.o"
1573 tmake_file="${tmake_file} ${cpu_type}/t-${cpu_type}"
1574 diff --git a/libgcc/config/t-hardfp-sf b/libgcc/config/t-hardfp-sf
1575 new file mode 100644
1576 index 00000000000..da50f354db3
1577 --- /dev/null
1578 +++ b/libgcc/config/t-hardfp-sf
1579 @@ -0,0 +1,32 @@
1580 +# Copyright (C) 2014-2021 Free Software Foundation, Inc.
1581 +
1582 +# This file is part of GCC.
1583 +
1584 +# GCC is free software; you can redistribute it and/or modify
1585 +# it under the terms of the GNU General Public License as published by
1586 +# the Free Software Foundation; either version 3, or (at your option)
1587 +# any later version.
1588 +
1589 +# GCC is distributed in the hope that it will be useful,
1590 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
1591 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1592 +# GNU General Public License for more details.
1593 +
1594 +# You should have received a copy of the GNU General Public License
1595 +# along with GCC; see the file COPYING3. If not see
1596 +# <http://www.gnu.org/licenses/>.
1597 +
1598 +hardfp_float_modes := sf
1599 +# di and ti are provided by libgcc2.c where needed.
1600 +hardfp_int_modes := si
1601 +hardfp_extensions :=
1602 +hardfp_truncations :=
1603 +
1604 +# Emulate 64 bit float:
1605 +FPBIT = true
1606 +DPBIT = true
1607 +# Don't build functions handled by 32 bit hardware:
1608 +LIB2FUNCS_EXCLUDE = _addsub_sf _mul_sf _div_sf \
1609 + _fpcmp_parts_sf _compare_sf _eq_sf _ne_sf _gt_sf _ge_sf \
1610 + _lt_sf _le_sf _unord_sf _si_to_sf _sf_to_si _negate_sf \
1611 + _thenan_sf _sf_to_usi _usi_to_sf
1612 diff --git a/libgcc/configure b/libgcc/configure
1613 index 4919a56f518..ab29cf04729 100755
1614 --- a/libgcc/configure
1615 +++ b/libgcc/configure
1616 @@ -675,6 +675,7 @@ infodir
1617 docdir
1618 oldincludedir
1619 includedir
1620 +runstatedir
1621 localstatedir
1622 sharedstatedir
1623 sysconfdir
1624 @@ -766,6 +767,7 @@ datadir='${datarootdir}'
1625 sysconfdir='${prefix}/etc'
1626 sharedstatedir='${prefix}/com'
1627 localstatedir='${prefix}/var'
1628 +runstatedir='${localstatedir}/run'
1629 includedir='${prefix}/include'
1630 oldincludedir='/usr/include'
1631 docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
1632 @@ -1018,6 +1020,15 @@ do
1633 | -silent | --silent | --silen | --sile | --sil)
1634 silent=yes ;;
1635
1636 + -runstatedir | --runstatedir | --runstatedi | --runstated \
1637 + | --runstate | --runstat | --runsta | --runst | --runs \
1638 + | --run | --ru | --r)
1639 + ac_prev=runstatedir ;;
1640 + -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
1641 + | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
1642 + | --run=* | --ru=* | --r=*)
1643 + runstatedir=$ac_optarg ;;
1644 +
1645 -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
1646 ac_prev=sbindir ;;
1647 -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
1648 @@ -1155,7 +1166,7 @@ fi
1649 for ac_var in exec_prefix prefix bindir sbindir libexecdir datarootdir \
1650 datadir sysconfdir sharedstatedir localstatedir includedir \
1651 oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
1652 - libdir localedir mandir
1653 + libdir localedir mandir runstatedir
1654 do
1655 eval ac_val=\$$ac_var
1656 # Remove trailing slashes.
1657 @@ -1308,6 +1319,7 @@ Fine tuning of the installation directories:
1658 --sysconfdir=DIR read-only single-machine data [PREFIX/etc]
1659 --sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com]
1660 --localstatedir=DIR modifiable single-machine data [PREFIX/var]
1661 + --runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run]
1662 --libdir=DIR object code libraries [EPREFIX/lib]
1663 --includedir=DIR C header files [PREFIX/include]
1664 --oldincludedir=DIR C header files for non-gcc [/usr/include]
1665 @@ -5098,6 +5110,28 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
1666 fi
1667 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_hard_float" >&5
1668 $as_echo "$libgcc_cv_mips_hard_float" >&6; }
1669 +
1670 + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the target is single-float" >&5
1671 +$as_echo_n "checking whether the target is single-float... " >&6; }
1672 +if ${libgcc_cv_mips_single_float+:} false; then :
1673 + $as_echo_n "(cached) " >&6
1674 +else
1675 + cat confdefs.h - <<_ACEOF >conftest.$ac_ext
1676 +/* end confdefs.h. */
1677 +#ifndef __mips_single_float
1678 + #error FOO
1679 + #endif
1680 +
1681 +_ACEOF
1682 +if ac_fn_c_try_compile "$LINENO"; then :
1683 + libgcc_cv_mips_single_float=yes
1684 +else
1685 + libgcc_cv_mips_single_float=no
1686 +fi
1687 +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
1688 +fi
1689 +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_single_float" >&5
1690 +$as_echo "$libgcc_cv_mips_single_float" >&6; }
1691 esac
1692
1693 case ${host} in
1694 diff --git a/libgcc/configure.ac b/libgcc/configure.ac
1695 index 13a80b2551b..1437af13b30 100644
1696 --- a/libgcc/configure.ac
1697 +++ b/libgcc/configure.ac
1698 @@ -337,6 +337,16 @@ mips*-*-*)
1699 ])],
1700 [libgcc_cv_mips_hard_float=yes],
1701 [libgcc_cv_mips_hard_float=no])])
1702 +
1703 + AC_CACHE_CHECK([whether the target is single-float],
1704 + [libgcc_cv_mips_single_float],
1705 + [AC_COMPILE_IFELSE(
1706 + [AC_LANG_SOURCE([#ifndef __mips_single_float
1707 + #error FOO
1708 + #endif
1709 + ])],
1710 + [libgcc_cv_mips_single_float=yes],
1711 + [libgcc_cv_mips_single_float=no])])
1712 esac
1713
1714 case ${host} in
1715 diff --git a/libgcc/gthr.h b/libgcc/gthr.h
1716 index cca3f294b7b..e50685df038 100644
1717 --- a/libgcc/gthr.h
1718 +++ b/libgcc/gthr.h
1719 @@ -144,6 +144,17 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
1720 #ifndef GTHREAD_USE_WEAK
1721 #define GTHREAD_USE_WEAK 1
1722 #endif
1723 +
1724 +/* *** PSP Specific change for std::thread ***
1725 + This file is modified by running sed commands on the
1726 + libstdc++-v3/include/Makefile.am
1727 + These sed commands add prefix to the existing macros
1728 + this is why we CAN'T add here an #if __PSP__
1729 + As solution we force here GTHREAD_USE_WEAK to be 0
1730 +*/
1731 +#undef GTHREAD_USE_WEAK
1732 +#define GTHREAD_USE_WEAK 0
1733 +
1734 #endif
1735 #include "gthr-default.h"
1736
1737 diff --git a/libobjc/Makefile.in b/libobjc/Makefile.in
1738 index 792f34269b0..7baf3466add 100644
1739 --- a/libobjc/Makefile.in
1740 +++ b/libobjc/Makefile.in
1741 @@ -71,7 +71,7 @@ AR_FLAGS = rc
1742 RANLIB = @RANLIB@
1743
1744 CC = @CC@
1745 -CFLAGS = @CFLAGS@
1746 +CFLAGS = -G0 @CFLAGS@
1747 XCFLAGS = @XCFLAGS@
1748 WARN_CFLAGS = -W -Wall -Wwrite-strings -Wstrict-prototypes
1749 ALL_CFLAGS = -I. -I$(srcdir) $(CPPFLAGS) $(DEFS) \