patches/gcc-11.2.0-psp.diff

   1 From 1530c47ced6f7fc2a1479d74389b58ef0fb6fc36 Mon Sep 17 00:00:00 2001
   2 From: David Guillen Fandos <david@davidgf.net>
   3 Date: Fri, 17 Dec 2021 17:19:47 +0100
   4 Subject: [PATCH 1/3] Allegrex gcc 11.2.0
   5
   6 Added support for bswap instructions
   7 ---
   8  config.sub                      |  17 ++--
   9  gcc/config.gcc                  |  16 +++-
  10  gcc/config/mips/allegrex.md     | 145 ++++++++++++++++++++++++++++++++
  11  gcc/config/mips/mips-cpus.def   |   1 +
  12  gcc/config/mips/mips-ftypes.def |   6 ++
  13  gcc/config/mips/mips.c          | 103 ++++++++++++++++++++++-
  14  gcc/config/mips/mips.h          |  29 +++++--
  15  gcc/config/mips/mips.md         |  26 ++++--
  16  gcc/config/mips/mips.opt        |   4 +
  17  gcc/config/mips/psp.h           |  31 +++++++
  18  libgcc/config.host              |  14 ++-
  19  libgcc/config/t-hardfp-sf       |  32 +++++++
  20  libgcc/configure                |  36 +++++++-
  21  libgcc/configure.ac             |  10 +++
  22  libobjc/Makefile.in             |   2 +-
  23  15 files changed, 445 insertions(+), 27 deletions(-)
  24  create mode 100644 gcc/config/mips/allegrex.md
  25  create mode 100644 gcc/config/mips/psp.h
  26  create mode 100644 libgcc/config/t-hardfp-sf
  27
  28 diff --git a/config.sub b/config.sub
  29 index 63c1f1c8b5e2..195468dba3f6 100755
  30 --- a/config.sub
  31 +++ b/config.sub
  32 @@ -476,10 +476,6 @@ case $1 in
  33                                 basic_machine=hppa-unknown
  34                                 basic_os=linux
  35                                 ;;
  36 -                       psp)
  37 -                               basic_machine=mipsallegrexel-sony
  38 -                               basic_os=psp
  39 -                               ;;
  40                         pw32)
  41                                 basic_machine=i586-unknown
  42                                 basic_os=pw32
  43 @@ -632,6 +628,10 @@ case $1 in
  44                                 basic_machine=ymp-cray
  45                                 basic_os=unicos
  46                                 ;;
  47 +                       psp)
  48 +                               basic_machine=mipsallegrexel-psp
  49 +                               os=elf
  50 +                               ;;
  51                         *)
  52                                 basic_machine=$1
  53                                 basic_os=
  54 @@ -644,6 +644,10 @@ esac
  55  case $basic_machine in
  56         # Here we handle the default manufacturer of certain CPU types.  It is in
  57         # some cases the only manufacturer, in others, it is the most popular.
  58 +       mipsallegrexel-*)
  59 +               cpu=mipsallegrexel
  60 +               vendor=psp
  61 +               ;;
  62         w89k)
  63                 cpu=hppa1.1
  64                 vendor=winbond
  65 @@ -1144,10 +1148,6 @@ case $cpu-$vendor in
  66                 cpu=nsx
  67                 vendor=tandem
  68                 ;;
  69 -       mipsallegrexel-sony)
  70 -               cpu=mipsallegrexel
  71 -               vendor=sony
  72 -               ;;
  73         tile*-*)
  74                 basic_os=${basic_os:-linux-gnu}
  75                 ;;
  76 @@ -1212,6 +1212,7 @@ case $cpu-$vendor in
  77                         | mipsisa64sr71k | mipsisa64sr71kel \
  78                         | mipsr5900 | mipsr5900el \
  79                         | mipstx39 | mipstx39el \
  80 +                       | mipsallegrex | mipsallegrexel \
  81                         | mmix \
  82                         | mn10200 | mn10300 \
  83                         | moxie \
  84 diff --git a/gcc/config.gcc b/gcc/config.gcc
  85 index 357b0bed0673..e07e302523e2 100644
  86 --- a/gcc/config.gcc
  87 +++ b/gcc/config.gcc
  88 @@ -2741,6 +2741,17 @@ mipstx39-*-elf* | mipstx39el-*-elf*)
  89         tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
  90         tmake_file="mips/t-r3900"
  91         ;;
  92 +mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
  93 +       tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h"
  94 +       tmake_file="mips/t-elf"
  95 +       target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
  96 +       tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
  97 +       case ${target} in
  98 +       mipsallegrex*-psp-elf*)
  99 +               tm_file="${tm_file} mips/psp.h"
 100 +               ;;
 101 +       esac
 102 +       ;;
 103  mmix-knuth-mmixware)
 104         tm_file="${tm_file} newlib-stdint.h"
 105         use_gcc_stdint=wrap
 106 @@ -4097,8 +4108,9 @@ fi
 107  # Infer a default setting for --with-fpu.
 108  if test x$with_fpu = x; then
 109    case ${target} in
 110 -    mips64r5900-*-* | mips64r5900el-*-* | mipsr5900-*-* | mipsr5900el-*-*)
 111 -      # The R5900 FPU only supports single precision.
 112 +    mips64r5900-*-* | mips64r5900el-*-* | mipsr5900-*-* | mipsr5900el-*-* | \
 113 +    mipsallegrex-*-* | mipsallegrexel-*-*)
 114 +      # The R5900 and Allegrex FPU only supports single precision.
 115        with_fpu=single
 116        ;;
 117    esac
 118 diff --git a/gcc/config/mips/allegrex.md b/gcc/config/mips/allegrex.md
 119 new file mode 100644
 120 index 000000000000..e9ae897bb18f
 121 --- /dev/null
 122 +++ b/gcc/config/mips/allegrex.md
 123 @@ -0,0 +1,145 @@
 124 +;; Sony ALLEGREX instructions.
 125 +;; Copyright (C) 2005 Free Software Foundation, Inc.
 126 +;;
 127 +;; This file is part of GCC.
 128 +;;
 129 +;; GCC is free software; you can redistribute it and/or modify
 130 +;; it under the terms of the GNU General Public License as published by
 131 +;; the Free Software Foundation; either version 2, or (at your option)
 132 +;; any later version.
 133 +;;
 134 +;; GCC is distributed in the hope that it will be useful,
 135 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
 136 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 137 +;; GNU General Public License for more details.
 138 +;;
 139 +;; You should have received a copy of the GNU General Public License
 140 +;; along with GCC; see the file COPYING.  If not, write to
 141 +;; the Free Software Foundation, 59 Temple Place - Suite 330,
 142 +;; Boston, MA 02111-1307, USA.
 143 +
 144 +(define_c_enum "unspec" [
 145 +  UNSPEC_CLO
 146 +  UNSPEC_CTO
 147 +  UNSPEC_CACHE
 148 +  UNSPEC_CEIL_W_S
 149 +  UNSPEC_FLOOR_W_S
 150 +  UNSPEC_ROUND_W_S
 151 +])
 152 +
 153 +;; Min and max.
 154 +
 155 +(define_insn "sminsi3"
 156 +  [(set (match_operand:SI 0 "register_operand" "=d")
 157 +        (smin:SI (match_operand:SI 1 "register_operand" "d")
 158 +                 (match_operand:SI 2 "register_operand" "d")))]
 159 +  "TARGET_ALLEGREX"
 160 +  "min\t%0,%1,%2"
 161 +  [(set_attr "type"    "arith")
 162 +   (set_attr "mode"    "SI")])
 163 +
 164 +(define_insn "smaxsi3"
 165 +  [(set (match_operand:SI 0 "register_operand" "=d")
 166 +        (smax:SI (match_operand:SI 1 "register_operand" "d")
 167 +                 (match_operand:SI 2 "register_operand" "d")))]
 168 +  "TARGET_ALLEGREX"
 169 +  "max\t%0,%1,%2"
 170 +  [(set_attr "type"    "arith")
 171 +   (set_attr "mode"    "SI")])
 172 +
 173 +
 174 +;; Extended shift instructions.
 175 +
 176 +(define_insn "allegrex_bitrevsi2"
 177 +  [(set (match_operand:SI 0 "register_operand" "=d")
 178 +   (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
 179 +          UNSPEC_BITREV))]
 180 +  "TARGET_ALLEGREX"
 181 +  "bitrev\t%0,%1"
 182 +  [(set_attr "type"    "arith")
 183 +   (set_attr "mode"    "SI")])
 184 +
 185 +
 186 +;; Count leading ones, count trailing zeros, and count trailing ones (clz is
 187 +;; already defined).
 188 +
 189 +(define_insn "allegrex_closi2"
 190 +  [(set (match_operand:SI 0 "register_operand" "=d")
 191 +       (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
 192 +          UNSPEC_CLO))]
 193 +  "TARGET_ALLEGREX"
 194 +  "clo\t%0,%1"
 195 +  [(set_attr "type"    "clz")
 196 +   (set_attr "mode"    "SI")])
 197 +
 198 +
 199 +(define_expand "allegrex_ctzsi2"
 200 +  [(set (match_operand:SI 0 "register_operand")
 201 +       (ctz:SI (match_operand:SI 1 "register_operand")))]
 202 +  "TARGET_ALLEGREX"
 203 +{
 204 +  emit_insn (gen_allegrex_bitrevsi2 (operands[0], operands[1]));
 205 +  emit_insn (gen_clzsi2 (operands[0], operands[0]));
 206 +  DONE;
 207 +})
 208 +
 209 +(define_expand "allegrex_ctosi2"
 210 +  [(set (match_operand:SI 0 "register_operand")
 211 +       (unspec:SI [(match_operand:SI 1 "register_operand")]
 212 +          UNSPEC_CTO))]
 213 +  "TARGET_ALLEGREX"
 214 +{
 215 +  emit_insn (gen_allegrex_bitrevsi2 (operands[0], operands[1]));
 216 +  emit_insn (gen_allegrex_closi2 (operands[0], operands[0]));
 217 +  DONE;
 218 +})
 219 +
 220 +
 221 +;; Misc.
 222 +
 223 +(define_insn "allegrex_sync"
 224 +  [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
 225 +  "TARGET_ALLEGREX"
 226 +  "sync"
 227 +  [(set_attr "type"    "unknown")
 228 +   (set_attr "mode"    "none")])
 229 +
 230 +(define_insn "allegrex_cache"
 231 +  [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
 232 +            (match_operand:SI 1 "register_operand" "d")]
 233 +           UNSPEC_CACHE)]
 234 +  "TARGET_ALLEGREX"
 235 +  "cache\t%0,0(%1)"
 236 +  [(set_attr "type"    "unknown")
 237 +   (set_attr "mode"    "none")])
 238 +
 239 +
 240 +;; Floating-point builtins.
 241 +
 242 +(define_insn "allegrex_ceilsfsi2"
 243 +  [(set (match_operand:SI 0 "register_operand" "=f")
 244 +       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
 245 +          UNSPEC_CEIL_W_S))]
 246 +  "TARGET_ALLEGREX"
 247 +  "ceil.w.s\t%0,%1"
 248 +  [(set_attr "type"    "fcvt")
 249 +   (set_attr "mode"    "SF")])
 250 +
 251 +(define_insn "allegrex_floorsfsi2"
 252 +  [(set (match_operand:SI 0 "register_operand" "=f")
 253 +       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
 254 +          UNSPEC_FLOOR_W_S))]
 255 +  "TARGET_ALLEGREX"
 256 +  "floor.w.s\t%0,%1"
 257 +  [(set_attr "type"    "fcvt")
 258 +   (set_attr "mode"    "SF")])
 259 +
 260 +(define_insn "allegrex_roundsfsi2"
 261 +  [(set (match_operand:SI 0 "register_operand" "=f")
 262 +       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
 263 +          UNSPEC_ROUND_W_S))]
 264 +  "TARGET_ALLEGREX"
 265 +  "round.w.s\t%0,%1"
 266 +  [(set_attr "type"    "fcvt")
 267 +   (set_attr "mode"    "SF")])
 268 +
 269 diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
 270 index b02294be4b9a..95ec0c8b4b30 100644
 271 --- a/gcc/config/mips/mips-cpus.def
 272 +++ b/gcc/config/mips/mips-cpus.def
 273 @@ -62,6 +62,7 @@ MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
 274
 275  /* MIPS II processors.  */
 276  MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
 277 +MIPS_CPU ("allegrex", PROCESSOR_ALLEGREX, 2, 0)
 278
 279  /* MIPS III processors.  */
 280  MIPS_CPU ("r4000", PROCESSOR_R4000, 3, 0)
 281 diff --git a/gcc/config/mips/mips-ftypes.def b/gcc/config/mips/mips-ftypes.def
 282 index 74f21f16f6cb..231282c0080e 100644
 283 --- a/gcc/config/mips/mips-ftypes.def
 284 +++ b/gcc/config/mips/mips-ftypes.def
 285 @@ -48,6 +48,8 @@ DEF_MIPS_FTYPE (2, (DI, SI, SI))
 286  DEF_MIPS_FTYPE (2, (DI, USI, USI))
 287  DEF_MIPS_FTYPE (2, (DI, V2DI, UQI))
 288
 289 +DEF_MIPS_FTYPE (1, (HI, HI))
 290 +
 291  DEF_MIPS_FTYPE (2, (INT, DF, DF))
 292  DEF_MIPS_FTYPE (2, (INT, SF, SF))
 293  DEF_MIPS_FTYPE (2, (INT, V2SF, V2SF))
 294 @@ -59,7 +61,10 @@ DEF_MIPS_FTYPE (1, (SF, V2SF))
 295  DEF_MIPS_FTYPE (1, (SF, V4SF))
 296
 297  DEF_MIPS_FTYPE (2, (SI, DI, SI))
 298 +DEF_MIPS_FTYPE (1, (SI, HI))
 299  DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
 300 +DEF_MIPS_FTYPE (1, (SI, QI))
 301 +DEF_MIPS_FTYPE (1, (SI, SF))
 302  DEF_MIPS_FTYPE (1, (SI, SI))
 303  DEF_MIPS_FTYPE (2, (SI, SI, SI))
 304  DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
 305 @@ -284,3 +289,4 @@ DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
 306  DEF_MIPS_FTYPE (3, (VOID, V4SF, POINTER, SI))
 307  DEF_MIPS_FTYPE (3, (VOID, V4SI, CVPOINTER, SI))
 308  DEF_MIPS_FTYPE (3, (VOID, V8HI, CVPOINTER, SI))
 309 +DEF_MIPS_FTYPE (1, (VOID, VOID))
 310 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
 311 index 315545966f88..2196e07821ed 100644
 312 --- a/gcc/config/mips/mips.c
 313 +++ b/gcc/config/mips/mips.c
 314 @@ -263,7 +263,12 @@ enum mips_builtin_type {
 315    MIPS_BUILTIN_MSA_TEST_BRANCH,
 316
 317    /* For generating bposge32 branch instructions in MIPS32 DSP ASE.  */
 318 -  MIPS_BUILTIN_BPOSGE32
 319 +  MIPS_BUILTIN_BPOSGE32,
 320 +
 321 +  /* The builtin corresponds to the ALLEGREX cache instruction.  Operand 0
 322 +     is the function code (must be less than 32) and operand 1 is the base
 323 +     address.  */
 324 +  MIPS_BUILTIN_CACHE
 325  };
 326
 327  /* Invoke MACRO (COND) for each C.cond.fmt condition.  */
 328 @@ -470,6 +475,10 @@ struct mips_asm_switch mips_noat = { "at", 0 };
 329     normal branch.  */
 330  static bool mips_branch_likely;
 331
 332 +/* Preferred stack boundary for proper stack vars alignment */
 333 +unsigned int mips_preferred_stack_boundary;
 334 +unsigned int mips_preferred_stack_align;
 335 +
 336  /* The current instruction-set architecture.  */
 337  enum processor mips_arch;
 338  const struct mips_cpu_info *mips_arch_info;
 339 @@ -830,6 +839,9 @@ static const struct mips_rtx_cost_data
 340                      1,           /* branch_cost */
 341                      4            /* memory_latency */
 342    },
 343 +  { /* Allegrex */
 344 +    DEFAULT_COSTS
 345 +  },
 346    { /* Loongson-2E */
 347      DEFAULT_COSTS
 348    },
 349 @@ -15266,6 +15278,7 @@ AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
 350  AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
 351  AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI)
 352  AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
 353 +AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
 354  AVAIL_NON_MIPS16 (msa, TARGET_MSA)
 355
 356  /* Construct a mips_builtin_description from the given arguments.
 357 @@ -15372,6 +15385,24 @@ AVAIL_NON_MIPS16 (msa, TARGET_MSA)
 358    MIPS_BUILTIN (bposge, f, "bposge" #VALUE,                            \
 359                 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL, false)
 360
 361 +/* Same as the above, but mapped to an instruction that doesn't share the
 362 +   NAME.  NAME is the name of the builtin without the builtin prefix.  */
 363 +#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
 364 +  { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME,             \
 365 +    MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
 366 +
 367 +/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
 368 +   CODE_FOR_allegrex_<INSN>.  FUNCTION_TYPE and TARGET_FLAGS are
 369 +   builtin_description fields.  */
 370 +#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS)   \
 371 +  { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN,            \
 372 +    MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex }
 373 +
 374 +/* Define a builtin with a specific function TYPE.  */
 375 +#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS)  \
 376 +  { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN,            \
 377 +    MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
 378 +
 379  /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
 380     for instruction CODE_FOR_loongson_<INSN>.  FUNCTION_TYPE is a
 381     builtin_description field.  */
 382 @@ -15855,6 +15886,37 @@ static const struct mips_builtin_description mips_builtins[] = {
 383    DIRECT_BUILTIN_PURE (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
 384    DIRECT_BUILTIN_PURE (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
 385
 386 +  /* Builtin functions for the Sony ALLEGREX processor.
 387 +   These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
 388 +   to maintain compatibility with Sony's ALLEGREX GCC port.
 389 +   Some of the builtins may seem redundant, but they are the same as the
 390 +   builtins defined in the Sony compiler.  I chose to map redundant and
 391 +   trivial builtins to the original instruction instead of creating
 392 +   duplicate patterns specifically for the ALLEGREX (as Sony does).  */
 393 +
 394 +  DIRECT_ALLEGREX_NAMED_BUILTIN(bitrev, allegrex_bitrevsi2, MIPS_SI_FTYPE_SI, 0),
 395 +  DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
 396 +  DIRECT_ALLEGREX_NAMED_BUILTIN(clo, allegrex_closi2, MIPS_SI_FTYPE_SI, 0),
 397 +  DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, allegrex_ctzsi2, MIPS_SI_FTYPE_SI, 0),
 398 +  DIRECT_ALLEGREX_NAMED_BUILTIN(cto, allegrex_ctosi2, MIPS_SI_FTYPE_SI, 0),
 399 +  DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
 400 +
 401 +  DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
 402 +  DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
 403 +  DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
 404 +  DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
 405 +  DIRECT_ALLEGREX_NAMED_BUILTIN(wsbw, bswapsi2, MIPS_SI_FTYPE_SI, 0),
 406 +  DIRECT_ALLEGREX_NAMED_BUILTIN(wsbh, bswaphi2, MIPS_HI_FTYPE_HI, 0),
 407 +
 408 +  DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
 409 +  SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
 410 +
 411 +  DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
 412 +  DIRECT_ALLEGREX_NAMED_BUILTIN(ceil_w_s, allegrex_ceilsfsi2, MIPS_SI_FTYPE_SF, 0),
 413 +  DIRECT_ALLEGREX_NAMED_BUILTIN(floor_w_s, allegrex_floorsfsi2, MIPS_SI_FTYPE_SF, 0),
 414 +  DIRECT_ALLEGREX_NAMED_BUILTIN(round_w_s, allegrex_roundsfsi2, MIPS_SI_FTYPE_SF, 0),
 415 +  DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
 416 +
 417    /* Builtin functions for ST Microelectronics Loongson-2E/2F cores.  */
 418    LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
 419    LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
 420 @@ -17249,6 +17311,26 @@ mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
 421                                        const1_rtx, const0_rtx);
 422  }
 423
 424 +/* Expand a __builtin_allegrex_cache() function.  Make sure the passed
 425 +   cache function code is less than 32.  */
 426 +
 427 +static rtx
 428 +mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
 429 +{
 430 +  int argno;
 431 +  struct expand_operand ops[2];
 432 +
 433 +  for (argno = 0; argno < 2; argno++)
 434 +    mips_prepare_builtin_arg (&ops[argno], exp, argno);
 435 +
 436 +  if (GET_CODE(ops[0].value) != CONST_INT ||
 437 +      INTVAL(ops[0].value) < 0 || INTVAL(ops[0].value) > 0x1f)
 438 +    error("Invalid first argument for cache builtin (0 <= arg <= 31)");
 439 +
 440 +  emit_insn(mips_expand_builtin_insn (icode, 2, ops, false));
 441 +  return target;
 442 +}
 443 +
 444  /* Implement TARGET_EXPAND_BUILTIN.  */
 445
 446  static rtx
 447 @@ -17297,6 +17379,9 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
 448
 449      case MIPS_BUILTIN_BPOSGE32:
 450        return mips_expand_builtin_bposge (d->builtin_type, target);
 451 +
 452 +    case MIPS_BUILTIN_CACHE:
 453 +      return mips_expand_builtin_cache (d->icode, target, exp);
 454      }
 455    gcc_unreachable ();
 456  }
 457 @@ -20443,6 +20528,22 @@ mips_option_override (void)
 458    if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
 459      REAL_MODE_FORMAT (SFmode) = &spu_single_format;
 460
 461 +  /* Validate -mpreferred-stack-boundary= value, or provide default.
 462 +     The default of 128-bit is for newABI else 64-bit.  */
 463 +  mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
 464 +  mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
 465 +  if (mips_preferred_stack_boundary_string)
 466 +    {
 467 +      i = atoi (mips_preferred_stack_boundary_string);
 468 +      if (i < 2 || i > 12)
 469 +       error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
 470 +      else
 471 +        {
 472 +          mips_preferred_stack_align = (1 << i);
 473 +          mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
 474 +        }
 475 +    }
 476 +
 477    mips_register_frame_header_opt ();
 478  }
 479
 480 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
 481 index 47aac9d3d612..3dfbc6152b4b 100644
 482 --- a/gcc/config/mips/mips.h
 483 +++ b/gcc/config/mips/mips.h
 484 @@ -288,6 +288,7 @@ struct mips_cpu_info {
 485                                      || mips_arch == PROCESSOR_SB1A)
 486  #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
 487  #define TARGET_XLP                  (mips_arch == PROCESSOR_XLP)
 488 +#define TARGET_ALLEGREX             (mips_arch == PROCESSOR_ALLEGREX)
 489
 490  /* Scheduling target defines.  */
 491  #define TUNE_20KC                  (mips_tune == PROCESSOR_20KC)
 492 @@ -322,6 +323,7 @@ struct mips_cpu_info {
 493  #define TUNE_P5600                  (mips_tune == PROCESSOR_P5600)
 494  #define TUNE_I6400                  (mips_tune == PROCESSOR_I6400)
 495  #define TUNE_P6600                  (mips_tune == PROCESSOR_P6600)
 496 +#define TUNE_ALLEGREX               (mips_tune == PROCESSOR_ALLEGREX)
 497
 498  /* True if the pre-reload scheduler should try to create chains of
 499     multiply-add or multiply-subtract instructions.  For example,
 500 @@ -1052,6 +1054,7 @@ struct mips_cpu_info {
 501     ST Loongson 2E/2F.  */
 502  #define ISA_HAS_CONDMOVE        (ISA_HAS_FP_CONDMOVE                   \
 503                                  || TARGET_MIPS5900                     \
 504 +                                || TARGET_ALLEGREX                     \
 505                                  || TARGET_LOONGSON_2EF)
 506
 507  /* ISA has LDC1 and SDC1.  */
 508 @@ -1094,11 +1097,13 @@ struct mips_cpu_info {
 509
 510  /* ISA has conditional trap instructions.  */
 511  #define ISA_HAS_COND_TRAP      (!ISA_MIPS1                             \
 512 +                                && !TARGET_ALLEGREX                    \
 513                                  && !TARGET_MIPS16)
 514
 515  /* ISA has conditional trap with immediate instructions.  */
 516  #define ISA_HAS_COND_TRAPI     (!ISA_MIPS1                             \
 517                                  && mips_isa_rev <= 5                   \
 518 +                                && !TARGET_ALLEGREX                    \
 519                                  && !TARGET_MIPS16)
 520
 521  /* ISA has integer multiply-accumulate instructions, madd and msub.  */
 522 @@ -1157,7 +1162,8 @@ struct mips_cpu_info {
 523  #define ISA_HAS_IEEE_754_2008  (mips_isa_rev >= 2)
 524
 525  /* ISA has count leading zeroes/ones instruction (not implemented).  */
 526 -#define ISA_HAS_CLZ_CLO                (mips_isa_rev >= 1 && !TARGET_MIPS16)
 527 +#define ISA_HAS_CLZ_CLO                ((mips_isa_rev >= 1 && !TARGET_MIPS16)   \
 528 +                                 || TARGET_ALLEGREX)
 529
 530  /* ISA has count trailing zeroes/ones instruction.  */
 531  #define ISA_HAS_CTZ_CTO                (TARGET_LOONGSON_EXT2)
 532 @@ -1199,6 +1205,7 @@ struct mips_cpu_info {
 533
 534  /* ISA has the "ror" (rotate right) instructions.  */
 535  #define ISA_HAS_ROR            ((mips_isa_rev >= 2                     \
 536 +                                 || TARGET_ALLEGREX                    \
 537                                   || TARGET_MIPS5400                    \
 538                                   || TARGET_MIPS5500                    \
 539                                   || TARGET_SR71K                       \
 540 @@ -1207,7 +1214,11 @@ struct mips_cpu_info {
 541
 542  /* ISA has the WSBH (word swap bytes within halfwords) instruction.
 543     64-bit targets also provide DSBH and DSHD.  */
 544 -#define ISA_HAS_WSBH           (mips_isa_rev >= 2 && !TARGET_MIPS16)
 545 +#define ISA_HAS_WSBH           ((mips_isa_rev >= 2 && !TARGET_MIPS16)  \
 546 +                                 || TARGET_ALLEGREX)
 547 +
 548 +/* Similar to WSBH but for 32 bit words. */
 549 +#define ISA_HAS_WSBW           (TARGET_ALLEGREX)
 550
 551  /* ISA has data prefetch instructions.  This controls use of 'pref'.  */
 552  #define ISA_HAS_PREFETCH       ((ISA_MIPS4                             \
 553 @@ -1233,10 +1244,12 @@ struct mips_cpu_info {
 554  #define ISA_HAS_TRUNC_W                (!ISA_MIPS1)
 555
 556  /* ISA includes the MIPS32r2 seb and seh instructions.  */
 557 -#define ISA_HAS_SEB_SEH                (mips_isa_rev >= 2 && !TARGET_MIPS16)
 558 +#define ISA_HAS_SEB_SEH                ((mips_isa_rev >= 2 && !TARGET_MIPS16)  \
 559 +                                 || TARGET_ALLEGREX)
 560
 561  /* ISA includes the MIPS32/64 rev 2 ext and ins instructions.  */
 562 -#define ISA_HAS_EXT_INS                (mips_isa_rev >= 2 && !TARGET_MIPS16)
 563 +#define ISA_HAS_EXT_INS                ((mips_isa_rev >= 2 && !TARGET_MIPS16)  \
 564 +                                 || TARGET_ALLEGREX)
 565
 566  /* ISA has instructions for accessing top part of 64-bit fp regs.  */
 567  #define ISA_HAS_MXHC1          (!TARGET_FLOAT32        \
 568 @@ -1297,6 +1310,7 @@ struct mips_cpu_info {
 569     earlier-ISA CPUs for which CPU documentation declares that the
 570     instructions are really interlocked.  */
 571  #define ISA_HAS_HILO_INTERLOCKS        (mips_isa_rev >= 1                      \
 572 +                                || TARGET_ALLEGREX                     \
 573                                  || TARGET_MIPS5500                     \
 574                                  || TARGET_MIPS5900                     \
 575                                  || TARGET_LOONGSON_2EF)
 576 @@ -2399,7 +2413,7 @@ enum reg_class
 577     `crtl->outgoing_args_size'.  */
 578  #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 579
 580 -#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
 581 +#define STACK_BOUNDARY (mips_preferred_stack_boundary)
 582  \f
 583  /* Symbolic macros for the registers used to return integer and floating
 584     point values.  */
 585 @@ -2526,7 +2540,7 @@ typedef struct mips_args {
 586  /* Treat LOC as a byte offset from the stack pointer and round it up
 587     to the next fully-aligned offset.  */
 588  #define MIPS_STACK_ALIGN(LOC) \
 589 -  (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
 590 +  (ROUND_UP ((LOC), mips_preferred_stack_align))
 591
 592  \f
 593  /* Output assembler code to FILE to increment profiler label # LABELNO
 594 @@ -3175,6 +3189,9 @@ while (0)
 595         " TEXT_SECTION_ASM_OP);
 596  #endif
 597
 598 +extern unsigned int mips_preferred_stack_boundary;
 599 +extern unsigned int mips_preferred_stack_align;
 600 +
 601  #ifndef HAVE_AS_TLS
 602  #define HAVE_AS_TLS 0
 603  #endif
 604 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
 605 index eef3cfd50a84..e8fc4fbcafa9 100644
 606 --- a/gcc/config/mips/mips.md
 607 +++ b/gcc/config/mips/mips.md
 608 @@ -35,6 +35,7 @@
 609    74kf2_1
 610    74kf1_1
 611    74kf3_2
 612 +  allegrex
 613    loongson_2e
 614    loongson_2f
 615    gs464
 616 @@ -819,7 +820,8 @@
 617  (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
 618                                (CC "TARGET_HARD_FLOAT
 619                                    && !TARGET_LOONGSON_2EF
 620 -                                  && !TARGET_MIPS5900")])
 621 +                                  && !TARGET_MIPS5900
 622 +                                  && !TARGET_ALLEGREX")])
 623
 624  ;; This mode iterator allows :FPCC to be used anywhere that an FP condition
 625  ;; is needed.
 626 @@ -2260,11 +2262,11 @@
 627            (mult:DI
 628               (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
 629               (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
 630 -  "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
 631 +  "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)"
 632  {
 633    if (ISA_HAS_DSP_MULT)
 634      return "msub<u>\t%q0,%1,%2";
 635 -  else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
 636 +  else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX)
 637      return "msub<u>\t%1,%2";
 638    else
 639      return "msac<u>\t$0,%1,%2";
 640 @@ -2543,14 +2545,14 @@
 641          (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
 642                   (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
 643          (match_operand:DI 3 "muldiv_target_operand" "0")))]
 644 -  "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
 645 +  "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)
 646     && !TARGET_64BIT"
 647  {
 648    if (TARGET_MAD)
 649      return "mad<u>\t%1,%2";
 650    else if (ISA_HAS_DSP_MULT)
 651      return "madd<u>\t%q0,%1,%2";
 652 -  else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
 653 +  else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX)
 654      return "madd<u>\t%1,%2";
 655    else
 656      /* See comment in *macc.  */
 657 @@ -5866,12 +5868,19 @@
 658    "wsbh\t%0,%1"
 659    [(set_attr "type" "shift")])
 660
 661 -(define_insn_and_split "bswapsi2"
 662 +(define_insn "bswapsi2"
 663 +  [(set (match_operand:SI 0 "register_operand" "=d")
 664 +       (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
 665 +  "ISA_HAS_WSBW"
 666 +  "wsbw\t%0,%1"
 667 +  [(set_attr "type" "shift")])
 668 +
 669 +(define_insn_and_split "bswapsi2_split"
 670    [(set (match_operand:SI 0 "register_operand" "=d")
 671         (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
 672    "ISA_HAS_WSBH && ISA_HAS_ROR"
 673    "#"
 674 -  ""
 675 +  "&& !ISA_HAS_WSBW"
 676    [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH))
 677     (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
 678    ""
 679 @@ -7805,6 +7814,9 @@
 680  ; The MIPS MSA Instructions.
 681  (include "mips-msa.md")
 682
 683 +; Sony ALLEGREX instructions.
 684 +(include "allegrex.md")
 685 +
 686  (define_c_enum "unspec" [
 687    UNSPEC_ADDRESS_FIRST
 688  ])
 689 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
 690 index 6af8037e9bdf..d1e6c41a699e 100644
 691 --- a/gcc/config/mips/mips.opt
 692 +++ b/gcc/config/mips/mips.opt
 693 @@ -475,3 +475,7 @@ Use Loongson EXTension (EXT) instructions.
 694  mloongson-ext2
 695  Target Var(TARGET_LOONGSON_EXT2)
 696  Use Loongson EXTension R2 (EXT2) instructions.
 697 +
 698 +mpreferred-stack-boundary=
 699 +Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
 700 +Attempt to keep stack aligned to this power of 2
 701 diff --git a/gcc/config/mips/psp.h b/gcc/config/mips/psp.h
 702 new file mode 100644
 703 index 000000000000..c5e4b5d93d03
 704 --- /dev/null
 705 +++ b/gcc/config/mips/psp.h
 706 @@ -0,0 +1,31 @@
 707 +/* Support for Sony's Playstation Portable (PSP).
 708 +   Copyright (C) 2005 Free Software Foundation, Inc.
 709 +   Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
 710 +
 711 +This file is part of GCC.
 712 +
 713 +GCC is free software; you can redistribute it and/or modify
 714 +it under the terms of the GNU General Public License as published by
 715 +the Free Software Foundation; either version 2, or (at your option)
 716 +any later version.
 717 +
 718 +GCC is distributed in the hope that it will be useful,
 719 +but WITHOUT ANY WARRANTY; without even the implied warranty of
 720 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 721 +GNU General Public License for more details.
 722 +
 723 +You should have received a copy of the GNU General Public License
 724 +along with GCC; see the file COPYING.  If not, write to
 725 +the Free Software Foundation, 59 Temple Place - Suite 330,
 726 +Boston, MA 02111-1307, USA.  */
 727 +
 728 +/* Override the startfile spec to include crt0.o. */
 729 +#undef STARTFILE_SPEC
 730 +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
 731 +
 732 +#undef SUBTARGET_CPP_SPEC
 733 +#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
 734 +
 735 +/* Get rid of the .pdr section. */
 736 +#undef SUBTARGET_ASM_SPEC
 737 +#define SUBTARGET_ASM_SPEC "-mno-pdr"
 738 diff --git a/libgcc/config.host b/libgcc/config.host
 739 index 50f00062232b..f3ccd37fd4f6 100644
 740 --- a/libgcc/config.host
 741 +++ b/libgcc/config.host
 742 @@ -148,10 +148,16 @@ microblaze*-*-*)
 743         ;;
 744  mips*-*-*)
 745         # All MIPS targets provide a full set of FP routines.
 746 +       # (except for allegrex and R5900)
 747         cpu_type=mips
 748         tmake_file="mips/t-mips"
 749         if test "${libgcc_cv_mips_hard_float}" = yes; then
 750 -               tmake_file="${tmake_file} t-hardfp-sfdf t-hardfp"
 751 +               if test "${libgcc_cv_mips_single_float}" = yes; then
 752 +                       tmake_file="${tmake_file} t-hardfp-sf"
 753 +               else
 754 +                       tmake_file="${tmake_file} t-hardfp-sfdf"
 755 +               fi
 756 +               tmake_file="${tmake_file} t-hardfp"
 757         else
 758                 tmake_file="${tmake_file} t-softfp-sfdf"
 759         fi
 760 @@ -1053,6 +1059,12 @@ mips-wrs-vxworks)
 761  mipstx39-*-elf* | mipstx39el-*-elf*)
 762         tmake_file="$tmake_file mips/t-crtstuff mips/t-mips16"
 763         ;;
 764 +mips*-psp*)
 765 +       tmake_file="${tmake_file} mips/t-elf mips/t-crtstuff"
 766 +       target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
 767 +       tm_file="${tm_file}"
 768 +       extra_parts="$extra_parts crti.o crtn.o"
 769 +       ;;
 770  mmix-knuth-mmixware)
 771         extra_parts="crti.o crtn.o crtbegin.o crtend.o"
 772         tmake_file="${tmake_file} ${cpu_type}/t-${cpu_type}"
 773 diff --git a/libgcc/config/t-hardfp-sf b/libgcc/config/t-hardfp-sf
 774 new file mode 100644
 775 index 000000000000..da50f354db36
 776 --- /dev/null
 777 +++ b/libgcc/config/t-hardfp-sf
 778 @@ -0,0 +1,32 @@
 779 +# Copyright (C) 2014-2021 Free Software Foundation, Inc.
 780 +
 781 +# This file is part of GCC.
 782 +
 783 +# GCC is free software; you can redistribute it and/or modify
 784 +# it under the terms of the GNU General Public License as published by
 785 +# the Free Software Foundation; either version 3, or (at your option)
 786 +# any later version.
 787 +
 788 +# GCC is distributed in the hope that it will be useful,
 789 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
 790 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 791 +# GNU General Public License for more details.
 792 +
 793 +# You should have received a copy of the GNU General Public License
 794 +# along with GCC; see the file COPYING3.  If not see
 795 +# <http://www.gnu.org/licenses/>.
 796 +
 797 +hardfp_float_modes := sf
 798 +# di and ti are provided by libgcc2.c where needed.
 799 +hardfp_int_modes := si
 800 +hardfp_extensions :=
 801 +hardfp_truncations :=
 802 +
 803 +# Emulate 64 bit float:
 804 +FPBIT = true
 805 +DPBIT = true
 806 +# Don't build functions handled by 32 bit hardware:
 807 +LIB2FUNCS_EXCLUDE = _addsub_sf _mul_sf _div_sf \
 808 +    _fpcmp_parts_sf _compare_sf _eq_sf _ne_sf _gt_sf _ge_sf \
 809 +    _lt_sf _le_sf _unord_sf _si_to_sf _sf_to_si _negate_sf \
 810 +    _thenan_sf _sf_to_usi _usi_to_sf
 811 diff --git a/libgcc/configure b/libgcc/configure
 812 index 4919a56f5181..ab29cf047290 100755
 813 --- a/libgcc/configure
 814 +++ b/libgcc/configure
 815 @@ -675,6 +675,7 @@ infodir
 816  docdir
 817  oldincludedir
 818  includedir
 819 +runstatedir
 820  localstatedir
 821  sharedstatedir
 822  sysconfdir
 823 @@ -766,6 +767,7 @@ datadir='${datarootdir}'
 824  sysconfdir='${prefix}/etc'
 825  sharedstatedir='${prefix}/com'
 826  localstatedir='${prefix}/var'
 827 +runstatedir='${localstatedir}/run'
 828  includedir='${prefix}/include'
 829  oldincludedir='/usr/include'
 830  docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
 831 @@ -1018,6 +1020,15 @@ do
 832    | -silent | --silent | --silen | --sile | --sil)
 833      silent=yes ;;
 834
 835 +  -runstatedir | --runstatedir | --runstatedi | --runstated \
 836 +  | --runstate | --runstat | --runsta | --runst | --runs \
 837 +  | --run | --ru | --r)
 838 +    ac_prev=runstatedir ;;
 839 +  -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
 840 +  | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
 841 +  | --run=* | --ru=* | --r=*)
 842 +    runstatedir=$ac_optarg ;;
 843 +
 844    -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
 845      ac_prev=sbindir ;;
 846    -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
 847 @@ -1155,7 +1166,7 @@ fi
 848  for ac_var in  exec_prefix prefix bindir sbindir libexecdir datarootdir \
 849                 datadir sysconfdir sharedstatedir localstatedir includedir \
 850                 oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
 851 -               libdir localedir mandir
 852 +               libdir localedir mandir runstatedir
 853  do
 854    eval ac_val=\$$ac_var
 855    # Remove trailing slashes.
 856 @@ -1308,6 +1319,7 @@ Fine tuning of the installation directories:
 857    --sysconfdir=DIR        read-only single-machine data [PREFIX/etc]
 858    --sharedstatedir=DIR    modifiable architecture-independent data [PREFIX/com]
 859    --localstatedir=DIR     modifiable single-machine data [PREFIX/var]
 860 +  --runstatedir=DIR       modifiable per-process data [LOCALSTATEDIR/run]
 861    --libdir=DIR            object code libraries [EPREFIX/lib]
 862    --includedir=DIR        C header files [PREFIX/include]
 863    --oldincludedir=DIR     C header files for non-gcc [/usr/include]
 864 @@ -5098,6 +5110,28 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
 865  fi
 866  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_hard_float" >&5
 867  $as_echo "$libgcc_cv_mips_hard_float" >&6; }
 868 +
 869 +  { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the target is single-float" >&5
 870 +$as_echo_n "checking whether the target is single-float... " >&6; }
 871 +if ${libgcc_cv_mips_single_float+:} false; then :
 872 +  $as_echo_n "(cached) " >&6
 873 +else
 874 +  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 875 +/* end confdefs.h.  */
 876 +#ifndef __mips_single_float
 877 +     #error FOO
 878 +     #endif
 879 +
 880 +_ACEOF
 881 +if ac_fn_c_try_compile "$LINENO"; then :
 882 +  libgcc_cv_mips_single_float=yes
 883 +else
 884 +  libgcc_cv_mips_single_float=no
 885 +fi
 886 +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
 887 +fi
 888 +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_single_float" >&5
 889 +$as_echo "$libgcc_cv_mips_single_float" >&6; }
 890  esac
 891
 892  case ${host} in
 893 diff --git a/libgcc/configure.ac b/libgcc/configure.ac
 894 index 13a80b2551bc..1437af13b30d 100644
 895 --- a/libgcc/configure.ac
 896 +++ b/libgcc/configure.ac
 897 @@ -337,6 +337,16 @@ mips*-*-*)
 898      ])],
 899      [libgcc_cv_mips_hard_float=yes],
 900      [libgcc_cv_mips_hard_float=no])])
 901 +
 902 +  AC_CACHE_CHECK([whether the target is single-float],
 903 +                [libgcc_cv_mips_single_float],
 904 +                [AC_COMPILE_IFELSE(
 905 +    [AC_LANG_SOURCE([#ifndef __mips_single_float
 906 +     #error FOO
 907 +     #endif
 908 +    ])],
 909 +    [libgcc_cv_mips_single_float=yes],
 910 +    [libgcc_cv_mips_single_float=no])])
 911  esac
 912
 913  case ${host} in
 914 diff --git a/libobjc/Makefile.in b/libobjc/Makefile.in
 915 index 792f34269b05..7baf3466adde 100644
 916 --- a/libobjc/Makefile.in
 917 +++ b/libobjc/Makefile.in
 918 @@ -71,7 +71,7 @@ AR_FLAGS = rc
 919  RANLIB = @RANLIB@
 920
 921  CC = @CC@
 922 -CFLAGS = @CFLAGS@
 923 +CFLAGS = -G0 @CFLAGS@
 924  XCFLAGS = @XCFLAGS@
 925  WARN_CFLAGS = -W -Wall -Wwrite-strings -Wstrict-prototypes
 926  ALL_CFLAGS = -I. -I$(srcdir) $(CPPFLAGS) $(DEFS) \
 927
 928 From 1f0c0a9090cb81baf7ba5b6803dba64513de5d99 Mon Sep 17 00:00:00 2001
 929 From: David Guillen Fandos <david@davidgf.net>
 930 Date: Wed, 12 Jan 2022 18:44:04 +0100
 931 Subject: [PATCH 2/3] Add updated mips-tables.opt since it is not automatically
 932  regenerated
 933
 934 This file should not be checked in or updated on every update of
 935 `mips-cpus.def` so here it goes.
 936 ---
 937  gcc/config/mips/mips-tables.opt | 371 ++++++++++++++++----------------
 938  1 file changed, 187 insertions(+), 184 deletions(-)
 939
 940 diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt
 941 index aef12f02dc75..2bf599c4fe28 100644
 942 --- a/gcc/config/mips/mips-tables.opt
 943 +++ b/gcc/config/mips/mips-tables.opt
 944 @@ -160,554 +160,557 @@ EnumValue
 945  Enum(mips_arch_opt_value) String(6k) Value(17)
 946
 947  EnumValue
 948 -Enum(mips_arch_opt_value) String(r4000) Value(18) Canonical
 949 +Enum(mips_arch_opt_value) String(allegrex) Value(18) Canonical
 950
 951  EnumValue
 952 -Enum(mips_arch_opt_value) String(r4k) Value(18)
 953 +Enum(mips_arch_opt_value) String(r4000) Value(19) Canonical
 954
 955  EnumValue
 956 -Enum(mips_arch_opt_value) String(4000) Value(18)
 957 +Enum(mips_arch_opt_value) String(r4k) Value(19)
 958
 959  EnumValue
 960 -Enum(mips_arch_opt_value) String(4k) Value(18)
 961 +Enum(mips_arch_opt_value) String(4000) Value(19)
 962
 963  EnumValue
 964 -Enum(mips_arch_opt_value) String(vr4100) Value(19) Canonical
 965 +Enum(mips_arch_opt_value) String(4k) Value(19)
 966
 967  EnumValue
 968 -Enum(mips_arch_opt_value) String(4100) Value(19)
 969 +Enum(mips_arch_opt_value) String(vr4100) Value(20) Canonical
 970
 971  EnumValue
 972 -Enum(mips_arch_opt_value) String(r4100) Value(19)
 973 +Enum(mips_arch_opt_value) String(4100) Value(20)
 974
 975  EnumValue
 976 -Enum(mips_arch_opt_value) String(vr4111) Value(20) Canonical
 977 +Enum(mips_arch_opt_value) String(r4100) Value(20)
 978
 979  EnumValue
 980 -Enum(mips_arch_opt_value) String(4111) Value(20)
 981 +Enum(mips_arch_opt_value) String(vr4111) Value(21) Canonical
 982
 983  EnumValue
 984 -Enum(mips_arch_opt_value) String(r4111) Value(20)
 985 +Enum(mips_arch_opt_value) String(4111) Value(21)
 986
 987  EnumValue
 988 -Enum(mips_arch_opt_value) String(vr4120) Value(21) Canonical
 989 +Enum(mips_arch_opt_value) String(r4111) Value(21)
 990
 991  EnumValue
 992 -Enum(mips_arch_opt_value) String(4120) Value(21)
 993 +Enum(mips_arch_opt_value) String(vr4120) Value(22) Canonical
 994
 995  EnumValue
 996 -Enum(mips_arch_opt_value) String(r4120) Value(21)
 997 +Enum(mips_arch_opt_value) String(4120) Value(22)
 998
 999  EnumValue
1000 -Enum(mips_arch_opt_value) String(vr4130) Value(22) Canonical
1001 +Enum(mips_arch_opt_value) String(r4120) Value(22)
1002
1003  EnumValue
1004 -Enum(mips_arch_opt_value) String(4130) Value(22)
1005 +Enum(mips_arch_opt_value) String(vr4130) Value(23) Canonical
1006
1007  EnumValue
1008 -Enum(mips_arch_opt_value) String(r4130) Value(22)
1009 +Enum(mips_arch_opt_value) String(4130) Value(23)
1010
1011  EnumValue
1012 -Enum(mips_arch_opt_value) String(vr4300) Value(23) Canonical
1013 +Enum(mips_arch_opt_value) String(r4130) Value(23)
1014
1015  EnumValue
1016 -Enum(mips_arch_opt_value) String(4300) Value(23)
1017 +Enum(mips_arch_opt_value) String(vr4300) Value(24) Canonical
1018
1019  EnumValue
1020 -Enum(mips_arch_opt_value) String(r4300) Value(23)
1021 +Enum(mips_arch_opt_value) String(4300) Value(24)
1022
1023  EnumValue
1024 -Enum(mips_arch_opt_value) String(r4400) Value(24) Canonical
1025 +Enum(mips_arch_opt_value) String(r4300) Value(24)
1026
1027  EnumValue
1028 -Enum(mips_arch_opt_value) String(4400) Value(24)
1029 +Enum(mips_arch_opt_value) String(r4400) Value(25) Canonical
1030
1031  EnumValue
1032 -Enum(mips_arch_opt_value) String(r4600) Value(25) Canonical
1033 +Enum(mips_arch_opt_value) String(4400) Value(25)
1034
1035  EnumValue
1036 -Enum(mips_arch_opt_value) String(4600) Value(25)
1037 +Enum(mips_arch_opt_value) String(r4600) Value(26) Canonical
1038
1039  EnumValue
1040 -Enum(mips_arch_opt_value) String(orion) Value(26) Canonical
1041 +Enum(mips_arch_opt_value) String(4600) Value(26)
1042
1043  EnumValue
1044 -Enum(mips_arch_opt_value) String(r4650) Value(27) Canonical
1045 +Enum(mips_arch_opt_value) String(orion) Value(27) Canonical
1046
1047  EnumValue
1048 -Enum(mips_arch_opt_value) String(4650) Value(27)
1049 +Enum(mips_arch_opt_value) String(r4650) Value(28) Canonical
1050
1051  EnumValue
1052 -Enum(mips_arch_opt_value) String(r4700) Value(28) Canonical
1053 +Enum(mips_arch_opt_value) String(4650) Value(28)
1054
1055  EnumValue
1056 -Enum(mips_arch_opt_value) String(4700) Value(28)
1057 +Enum(mips_arch_opt_value) String(r4700) Value(29) Canonical
1058
1059  EnumValue
1060 -Enum(mips_arch_opt_value) String(r5900) Value(29) Canonical
1061 +Enum(mips_arch_opt_value) String(4700) Value(29)
1062
1063  EnumValue
1064 -Enum(mips_arch_opt_value) String(5900) Value(29)
1065 +Enum(mips_arch_opt_value) String(r5900) Value(30) Canonical
1066
1067  EnumValue
1068 -Enum(mips_arch_opt_value) String(loongson2e) Value(30) Canonical
1069 +Enum(mips_arch_opt_value) String(5900) Value(30)
1070
1071  EnumValue
1072 -Enum(mips_arch_opt_value) String(loongson2f) Value(31) Canonical
1073 +Enum(mips_arch_opt_value) String(loongson2e) Value(31) Canonical
1074
1075  EnumValue
1076 -Enum(mips_arch_opt_value) String(r8000) Value(32) Canonical
1077 +Enum(mips_arch_opt_value) String(loongson2f) Value(32) Canonical
1078
1079  EnumValue
1080 -Enum(mips_arch_opt_value) String(r8k) Value(32)
1081 +Enum(mips_arch_opt_value) String(r8000) Value(33) Canonical
1082
1083  EnumValue
1084 -Enum(mips_arch_opt_value) String(8000) Value(32)
1085 +Enum(mips_arch_opt_value) String(r8k) Value(33)
1086
1087  EnumValue
1088 -Enum(mips_arch_opt_value) String(8k) Value(32)
1089 +Enum(mips_arch_opt_value) String(8000) Value(33)
1090
1091  EnumValue
1092 -Enum(mips_arch_opt_value) String(r10000) Value(33) Canonical
1093 +Enum(mips_arch_opt_value) String(8k) Value(33)
1094
1095  EnumValue
1096 -Enum(mips_arch_opt_value) String(r10k) Value(33)
1097 +Enum(mips_arch_opt_value) String(r10000) Value(34) Canonical
1098
1099  EnumValue
1100 -Enum(mips_arch_opt_value) String(10000) Value(33)
1101 +Enum(mips_arch_opt_value) String(r10k) Value(34)
1102
1103  EnumValue
1104 -Enum(mips_arch_opt_value) String(10k) Value(33)
1105 +Enum(mips_arch_opt_value) String(10000) Value(34)
1106
1107  EnumValue
1108 -Enum(mips_arch_opt_value) String(r12000) Value(34) Canonical
1109 +Enum(mips_arch_opt_value) String(10k) Value(34)
1110
1111  EnumValue
1112 -Enum(mips_arch_opt_value) String(r12k) Value(34)
1113 +Enum(mips_arch_opt_value) String(r12000) Value(35) Canonical
1114
1115  EnumValue
1116 -Enum(mips_arch_opt_value) String(12000) Value(34)
1117 +Enum(mips_arch_opt_value) String(r12k) Value(35)
1118
1119  EnumValue
1120 -Enum(mips_arch_opt_value) String(12k) Value(34)
1121 +Enum(mips_arch_opt_value) String(12000) Value(35)
1122
1123  EnumValue
1124 -Enum(mips_arch_opt_value) String(r14000) Value(35) Canonical
1125 +Enum(mips_arch_opt_value) String(12k) Value(35)
1126
1127  EnumValue
1128 -Enum(mips_arch_opt_value) String(r14k) Value(35)
1129 +Enum(mips_arch_opt_value) String(r14000) Value(36) Canonical
1130
1131  EnumValue
1132 -Enum(mips_arch_opt_value) String(14000) Value(35)
1133 +Enum(mips_arch_opt_value) String(r14k) Value(36)
1134
1135  EnumValue
1136 -Enum(mips_arch_opt_value) String(14k) Value(35)
1137 +Enum(mips_arch_opt_value) String(14000) Value(36)
1138
1139  EnumValue
1140 -Enum(mips_arch_opt_value) String(r16000) Value(36) Canonical
1141 +Enum(mips_arch_opt_value) String(14k) Value(36)
1142
1143  EnumValue
1144 -Enum(mips_arch_opt_value) String(r16k) Value(36)
1145 +Enum(mips_arch_opt_value) String(r16000) Value(37) Canonical
1146
1147  EnumValue
1148 -Enum(mips_arch_opt_value) String(16000) Value(36)
1149 +Enum(mips_arch_opt_value) String(r16k) Value(37)
1150
1151  EnumValue
1152 -Enum(mips_arch_opt_value) String(16k) Value(36)
1153 +Enum(mips_arch_opt_value) String(16000) Value(37)
1154
1155  EnumValue
1156 -Enum(mips_arch_opt_value) String(vr5000) Value(37) Canonical
1157 +Enum(mips_arch_opt_value) String(16k) Value(37)
1158
1159  EnumValue
1160 -Enum(mips_arch_opt_value) String(vr5k) Value(37)
1161 +Enum(mips_arch_opt_value) String(vr5000) Value(38) Canonical
1162
1163  EnumValue
1164 -Enum(mips_arch_opt_value) String(5000) Value(37)
1165 +Enum(mips_arch_opt_value) String(vr5k) Value(38)
1166
1167  EnumValue
1168 -Enum(mips_arch_opt_value) String(5k) Value(37)
1169 +Enum(mips_arch_opt_value) String(5000) Value(38)
1170
1171  EnumValue
1172 -Enum(mips_arch_opt_value) String(r5000) Value(37)
1173 +Enum(mips_arch_opt_value) String(5k) Value(38)
1174
1175  EnumValue
1176 -Enum(mips_arch_opt_value) String(r5k) Value(37)
1177 +Enum(mips_arch_opt_value) String(r5000) Value(38)
1178
1179  EnumValue
1180 -Enum(mips_arch_opt_value) String(vr5400) Value(38) Canonical
1181 +Enum(mips_arch_opt_value) String(r5k) Value(38)
1182
1183  EnumValue
1184 -Enum(mips_arch_opt_value) String(5400) Value(38)
1185 +Enum(mips_arch_opt_value) String(vr5400) Value(39) Canonical
1186
1187  EnumValue
1188 -Enum(mips_arch_opt_value) String(r5400) Value(38)
1189 +Enum(mips_arch_opt_value) String(5400) Value(39)
1190
1191  EnumValue
1192 -Enum(mips_arch_opt_value) String(vr5500) Value(39) Canonical
1193 +Enum(mips_arch_opt_value) String(r5400) Value(39)
1194
1195  EnumValue
1196 -Enum(mips_arch_opt_value) String(5500) Value(39)
1197 +Enum(mips_arch_opt_value) String(vr5500) Value(40) Canonical
1198
1199  EnumValue
1200 -Enum(mips_arch_opt_value) String(r5500) Value(39)
1201 +Enum(mips_arch_opt_value) String(5500) Value(40)
1202
1203  EnumValue
1204 -Enum(mips_arch_opt_value) String(rm7000) Value(40) Canonical
1205 +Enum(mips_arch_opt_value) String(r5500) Value(40)
1206
1207  EnumValue
1208 -Enum(mips_arch_opt_value) String(rm7k) Value(40)
1209 +Enum(mips_arch_opt_value) String(rm7000) Value(41) Canonical
1210
1211  EnumValue
1212 -Enum(mips_arch_opt_value) String(7000) Value(40)
1213 +Enum(mips_arch_opt_value) String(rm7k) Value(41)
1214
1215  EnumValue
1216 -Enum(mips_arch_opt_value) String(7k) Value(40)
1217 +Enum(mips_arch_opt_value) String(7000) Value(41)
1218
1219  EnumValue
1220 -Enum(mips_arch_opt_value) String(r7000) Value(40)
1221 +Enum(mips_arch_opt_value) String(7k) Value(41)
1222
1223  EnumValue
1224 -Enum(mips_arch_opt_value) String(r7k) Value(40)
1225 +Enum(mips_arch_opt_value) String(r7000) Value(41)
1226
1227  EnumValue
1228 -Enum(mips_arch_opt_value) String(rm9000) Value(41) Canonical
1229 +Enum(mips_arch_opt_value) String(r7k) Value(41)
1230
1231  EnumValue
1232 -Enum(mips_arch_opt_value) String(rm9k) Value(41)
1233 +Enum(mips_arch_opt_value) String(rm9000) Value(42) Canonical
1234
1235  EnumValue
1236 -Enum(mips_arch_opt_value) String(9000) Value(41)
1237 +Enum(mips_arch_opt_value) String(rm9k) Value(42)
1238
1239  EnumValue
1240 -Enum(mips_arch_opt_value) String(9k) Value(41)
1241 +Enum(mips_arch_opt_value) String(9000) Value(42)
1242
1243  EnumValue
1244 -Enum(mips_arch_opt_value) String(r9000) Value(41)
1245 +Enum(mips_arch_opt_value) String(9k) Value(42)
1246
1247  EnumValue
1248 -Enum(mips_arch_opt_value) String(r9k) Value(41)
1249 +Enum(mips_arch_opt_value) String(r9000) Value(42)
1250
1251  EnumValue
1252 -Enum(mips_arch_opt_value) String(4kc) Value(42) Canonical
1253 +Enum(mips_arch_opt_value) String(r9k) Value(42)
1254
1255  EnumValue
1256 -Enum(mips_arch_opt_value) String(r4kc) Value(42)
1257 +Enum(mips_arch_opt_value) String(4kc) Value(43) Canonical
1258
1259  EnumValue
1260 -Enum(mips_arch_opt_value) String(4km) Value(43) Canonical
1261 +Enum(mips_arch_opt_value) String(r4kc) Value(43)
1262
1263  EnumValue
1264 -Enum(mips_arch_opt_value) String(r4km) Value(43)
1265 +Enum(mips_arch_opt_value) String(4km) Value(44) Canonical
1266
1267  EnumValue
1268 -Enum(mips_arch_opt_value) String(4kp) Value(44) Canonical
1269 +Enum(mips_arch_opt_value) String(r4km) Value(44)
1270
1271  EnumValue
1272 -Enum(mips_arch_opt_value) String(r4kp) Value(44)
1273 +Enum(mips_arch_opt_value) String(4kp) Value(45) Canonical
1274
1275  EnumValue
1276 -Enum(mips_arch_opt_value) String(4ksc) Value(45) Canonical
1277 +Enum(mips_arch_opt_value) String(r4kp) Value(45)
1278
1279  EnumValue
1280 -Enum(mips_arch_opt_value) String(r4ksc) Value(45)
1281 +Enum(mips_arch_opt_value) String(4ksc) Value(46) Canonical
1282
1283  EnumValue
1284 -Enum(mips_arch_opt_value) String(m4k) Value(46) Canonical
1285 +Enum(mips_arch_opt_value) String(r4ksc) Value(46)
1286
1287  EnumValue
1288 -Enum(mips_arch_opt_value) String(m14kc) Value(47) Canonical
1289 +Enum(mips_arch_opt_value) String(m4k) Value(47) Canonical
1290
1291  EnumValue
1292 -Enum(mips_arch_opt_value) String(m14k) Value(48) Canonical
1293 +Enum(mips_arch_opt_value) String(m14kc) Value(48) Canonical
1294
1295  EnumValue
1296 -Enum(mips_arch_opt_value) String(m14ke) Value(49) Canonical
1297 +Enum(mips_arch_opt_value) String(m14k) Value(49) Canonical
1298
1299  EnumValue
1300 -Enum(mips_arch_opt_value) String(m14kec) Value(50) Canonical
1301 +Enum(mips_arch_opt_value) String(m14ke) Value(50) Canonical
1302
1303  EnumValue
1304 -Enum(mips_arch_opt_value) String(4kec) Value(51) Canonical
1305 +Enum(mips_arch_opt_value) String(m14kec) Value(51) Canonical
1306
1307  EnumValue
1308 -Enum(mips_arch_opt_value) String(r4kec) Value(51)
1309 +Enum(mips_arch_opt_value) String(4kec) Value(52) Canonical
1310
1311  EnumValue
1312 -Enum(mips_arch_opt_value) String(4kem) Value(52) Canonical
1313 +Enum(mips_arch_opt_value) String(r4kec) Value(52)
1314
1315  EnumValue
1316 -Enum(mips_arch_opt_value) String(r4kem) Value(52)
1317 +Enum(mips_arch_opt_value) String(4kem) Value(53) Canonical
1318
1319  EnumValue
1320 -Enum(mips_arch_opt_value) String(4kep) Value(53) Canonical
1321 +Enum(mips_arch_opt_value) String(r4kem) Value(53)
1322
1323  EnumValue
1324 -Enum(mips_arch_opt_value) String(r4kep) Value(53)
1325 +Enum(mips_arch_opt_value) String(4kep) Value(54) Canonical
1326
1327  EnumValue
1328 -Enum(mips_arch_opt_value) String(4ksd) Value(54) Canonical
1329 +Enum(mips_arch_opt_value) String(r4kep) Value(54)
1330
1331  EnumValue
1332 -Enum(mips_arch_opt_value) String(r4ksd) Value(54)
1333 +Enum(mips_arch_opt_value) String(4ksd) Value(55) Canonical
1334
1335  EnumValue
1336 -Enum(mips_arch_opt_value) String(24kc) Value(55) Canonical
1337 +Enum(mips_arch_opt_value) String(r4ksd) Value(55)
1338
1339  EnumValue
1340 -Enum(mips_arch_opt_value) String(r24kc) Value(55)
1341 +Enum(mips_arch_opt_value) String(24kc) Value(56) Canonical
1342
1343  EnumValue
1344 -Enum(mips_arch_opt_value) String(24kf2_1) Value(56) Canonical
1345 +Enum(mips_arch_opt_value) String(r24kc) Value(56)
1346
1347  EnumValue
1348 -Enum(mips_arch_opt_value) String(r24kf2_1) Value(56)
1349 +Enum(mips_arch_opt_value) String(24kf2_1) Value(57) Canonical
1350
1351  EnumValue
1352 -Enum(mips_arch_opt_value) String(24kf) Value(57) Canonical
1353 +Enum(mips_arch_opt_value) String(r24kf2_1) Value(57)
1354
1355  EnumValue
1356 -Enum(mips_arch_opt_value) String(r24kf) Value(57)
1357 +Enum(mips_arch_opt_value) String(24kf) Value(58) Canonical
1358
1359  EnumValue
1360 -Enum(mips_arch_opt_value) String(24kf1_1) Value(58) Canonical
1361 +Enum(mips_arch_opt_value) String(r24kf) Value(58)
1362
1363  EnumValue
1364 -Enum(mips_arch_opt_value) String(r24kf1_1) Value(58)
1365 +Enum(mips_arch_opt_value) String(24kf1_1) Value(59) Canonical
1366
1367  EnumValue
1368 -Enum(mips_arch_opt_value) String(24kfx) Value(59) Canonical
1369 +Enum(mips_arch_opt_value) String(r24kf1_1) Value(59)
1370
1371  EnumValue
1372 -Enum(mips_arch_opt_value) String(r24kfx) Value(59)
1373 +Enum(mips_arch_opt_value) String(24kfx) Value(60) Canonical
1374
1375  EnumValue
1376 -Enum(mips_arch_opt_value) String(24kx) Value(60) Canonical
1377 +Enum(mips_arch_opt_value) String(r24kfx) Value(60)
1378
1379  EnumValue
1380 -Enum(mips_arch_opt_value) String(r24kx) Value(60)
1381 +Enum(mips_arch_opt_value) String(24kx) Value(61) Canonical
1382
1383  EnumValue
1384 -Enum(mips_arch_opt_value) String(24kec) Value(61) Canonical
1385 +Enum(mips_arch_opt_value) String(r24kx) Value(61)
1386
1387  EnumValue
1388 -Enum(mips_arch_opt_value) String(r24kec) Value(61)
1389 +Enum(mips_arch_opt_value) String(24kec) Value(62) Canonical
1390
1391  EnumValue
1392 -Enum(mips_arch_opt_value) String(24kef2_1) Value(62) Canonical
1393 +Enum(mips_arch_opt_value) String(r24kec) Value(62)
1394
1395  EnumValue
1396 -Enum(mips_arch_opt_value) String(r24kef2_1) Value(62)
1397 +Enum(mips_arch_opt_value) String(24kef2_1) Value(63) Canonical
1398
1399  EnumValue
1400 -Enum(mips_arch_opt_value) String(24kef) Value(63) Canonical
1401 +Enum(mips_arch_opt_value) String(r24kef2_1) Value(63)
1402
1403  EnumValue
1404 -Enum(mips_arch_opt_value) String(r24kef) Value(63)
1405 +Enum(mips_arch_opt_value) String(24kef) Value(64) Canonical
1406
1407  EnumValue
1408 -Enum(mips_arch_opt_value) String(24kef1_1) Value(64) Canonical
1409 +Enum(mips_arch_opt_value) String(r24kef) Value(64)
1410
1411  EnumValue
1412 -Enum(mips_arch_opt_value) String(r24kef1_1) Value(64)
1413 +Enum(mips_arch_opt_value) String(24kef1_1) Value(65) Canonical
1414
1415  EnumValue
1416 -Enum(mips_arch_opt_value) String(24kefx) Value(65) Canonical
1417 +Enum(mips_arch_opt_value) String(r24kef1_1) Value(65)
1418
1419  EnumValue
1420 -Enum(mips_arch_opt_value) String(r24kefx) Value(65)
1421 +Enum(mips_arch_opt_value) String(24kefx) Value(66) Canonical
1422
1423  EnumValue
1424 -Enum(mips_arch_opt_value) String(24kex) Value(66) Canonical
1425 +Enum(mips_arch_opt_value) String(r24kefx) Value(66)
1426
1427  EnumValue
1428 -Enum(mips_arch_opt_value) String(r24kex) Value(66)
1429 +Enum(mips_arch_opt_value) String(24kex) Value(67) Canonical
1430
1431  EnumValue
1432 -Enum(mips_arch_opt_value) String(34kc) Value(67) Canonical
1433 +Enum(mips_arch_opt_value) String(r24kex) Value(67)
1434
1435  EnumValue
1436 -Enum(mips_arch_opt_value) String(r34kc) Value(67)
1437 +Enum(mips_arch_opt_value) String(34kc) Value(68) Canonical
1438
1439  EnumValue
1440 -Enum(mips_arch_opt_value) String(34kf2_1) Value(68) Canonical
1441 +Enum(mips_arch_opt_value) String(r34kc) Value(68)
1442
1443  EnumValue
1444 -Enum(mips_arch_opt_value) String(r34kf2_1) Value(68)
1445 +Enum(mips_arch_opt_value) String(34kf2_1) Value(69) Canonical
1446
1447  EnumValue
1448 -Enum(mips_arch_opt_value) String(34kf) Value(69) Canonical
1449 +Enum(mips_arch_opt_value) String(r34kf2_1) Value(69)
1450
1451  EnumValue
1452 -Enum(mips_arch_opt_value) String(r34kf) Value(69)
1453 +Enum(mips_arch_opt_value) String(34kf) Value(70) Canonical
1454
1455  EnumValue
1456 -Enum(mips_arch_opt_value) String(34kf1_1) Value(70) Canonical
1457 +Enum(mips_arch_opt_value) String(r34kf) Value(70)
1458
1459  EnumValue
1460 -Enum(mips_arch_opt_value) String(r34kf1_1) Value(70)
1461 +Enum(mips_arch_opt_value) String(34kf1_1) Value(71) Canonical
1462
1463  EnumValue
1464 -Enum(mips_arch_opt_value) String(34kfx) Value(71) Canonical
1465 +Enum(mips_arch_opt_value) String(r34kf1_1) Value(71)
1466
1467  EnumValue
1468 -Enum(mips_arch_opt_value) String(r34kfx) Value(71)
1469 +Enum(mips_arch_opt_value) String(34kfx) Value(72) Canonical
1470
1471  EnumValue
1472 -Enum(mips_arch_opt_value) String(34kx) Value(72) Canonical
1473 +Enum(mips_arch_opt_value) String(r34kfx) Value(72)
1474
1475  EnumValue
1476 -Enum(mips_arch_opt_value) String(r34kx) Value(72)
1477 +Enum(mips_arch_opt_value) String(34kx) Value(73) Canonical
1478
1479  EnumValue
1480 -Enum(mips_arch_opt_value) String(34kn) Value(73) Canonical
1481 +Enum(mips_arch_opt_value) String(r34kx) Value(73)
1482
1483  EnumValue
1484 -Enum(mips_arch_opt_value) String(r34kn) Value(73)
1485 +Enum(mips_arch_opt_value) String(34kn) Value(74) Canonical
1486
1487  EnumValue
1488 -Enum(mips_arch_opt_value) String(74kc) Value(74) Canonical
1489 +Enum(mips_arch_opt_value) String(r34kn) Value(74)
1490
1491  EnumValue
1492 -Enum(mips_arch_opt_value) String(r74kc) Value(74)
1493 +Enum(mips_arch_opt_value) String(74kc) Value(75) Canonical
1494
1495  EnumValue
1496 -Enum(mips_arch_opt_value) String(74kf2_1) Value(75) Canonical
1497 +Enum(mips_arch_opt_value) String(r74kc) Value(75)
1498
1499  EnumValue
1500 -Enum(mips_arch_opt_value) String(r74kf2_1) Value(75)
1501 +Enum(mips_arch_opt_value) String(74kf2_1) Value(76) Canonical
1502
1503  EnumValue
1504 -Enum(mips_arch_opt_value) String(74kf) Value(76) Canonical
1505 +Enum(mips_arch_opt_value) String(r74kf2_1) Value(76)
1506
1507  EnumValue
1508 -Enum(mips_arch_opt_value) String(r74kf) Value(76)
1509 +Enum(mips_arch_opt_value) String(74kf) Value(77) Canonical
1510
1511  EnumValue
1512 -Enum(mips_arch_opt_value) String(74kf1_1) Value(77) Canonical
1513 +Enum(mips_arch_opt_value) String(r74kf) Value(77)
1514
1515  EnumValue
1516 -Enum(mips_arch_opt_value) String(r74kf1_1) Value(77)
1517 +Enum(mips_arch_opt_value) String(74kf1_1) Value(78) Canonical
1518
1519  EnumValue
1520 -Enum(mips_arch_opt_value) String(74kfx) Value(78) Canonical
1521 +Enum(mips_arch_opt_value) String(r74kf1_1) Value(78)
1522
1523  EnumValue
1524 -Enum(mips_arch_opt_value) String(r74kfx) Value(78)
1525 +Enum(mips_arch_opt_value) String(74kfx) Value(79) Canonical
1526
1527  EnumValue
1528 -Enum(mips_arch_opt_value) String(74kx) Value(79) Canonical
1529 +Enum(mips_arch_opt_value) String(r74kfx) Value(79)
1530
1531  EnumValue
1532 -Enum(mips_arch_opt_value) String(r74kx) Value(79)
1533 +Enum(mips_arch_opt_value) String(74kx) Value(80) Canonical
1534
1535  EnumValue
1536 -Enum(mips_arch_opt_value) String(74kf3_2) Value(80) Canonical
1537 +Enum(mips_arch_opt_value) String(r74kx) Value(80)
1538
1539  EnumValue
1540 -Enum(mips_arch_opt_value) String(r74kf3_2) Value(80)
1541 +Enum(mips_arch_opt_value) String(74kf3_2) Value(81) Canonical
1542
1543  EnumValue
1544 -Enum(mips_arch_opt_value) String(1004kc) Value(81) Canonical
1545 +Enum(mips_arch_opt_value) String(r74kf3_2) Value(81)
1546
1547  EnumValue
1548 -Enum(mips_arch_opt_value) String(r1004kc) Value(81)
1549 +Enum(mips_arch_opt_value) String(1004kc) Value(82) Canonical
1550
1551  EnumValue
1552 -Enum(mips_arch_opt_value) String(1004kf2_1) Value(82) Canonical
1553 +Enum(mips_arch_opt_value) String(r1004kc) Value(82)
1554
1555  EnumValue
1556 -Enum(mips_arch_opt_value) String(r1004kf2_1) Value(82)
1557 +Enum(mips_arch_opt_value) String(1004kf2_1) Value(83) Canonical
1558
1559  EnumValue
1560 -Enum(mips_arch_opt_value) String(1004kf) Value(83) Canonical
1561 +Enum(mips_arch_opt_value) String(r1004kf2_1) Value(83)
1562
1563  EnumValue
1564 -Enum(mips_arch_opt_value) String(r1004kf) Value(83)
1565 +Enum(mips_arch_opt_value) String(1004kf) Value(84) Canonical
1566
1567  EnumValue
1568 -Enum(mips_arch_opt_value) String(1004kf1_1) Value(84) Canonical
1569 +Enum(mips_arch_opt_value) String(r1004kf) Value(84)
1570
1571  EnumValue
1572 -Enum(mips_arch_opt_value) String(r1004kf1_1) Value(84)
1573 +Enum(mips_arch_opt_value) String(1004kf1_1) Value(85) Canonical
1574
1575  EnumValue
1576 -Enum(mips_arch_opt_value) String(interaptiv) Value(85) Canonical
1577 +Enum(mips_arch_opt_value) String(r1004kf1_1) Value(85)
1578
1579  EnumValue
1580 -Enum(mips_arch_opt_value) String(p5600) Value(86) Canonical
1581 +Enum(mips_arch_opt_value) String(interaptiv) Value(86) Canonical
1582
1583  EnumValue
1584 -Enum(mips_arch_opt_value) String(m5100) Value(87) Canonical
1585 +Enum(mips_arch_opt_value) String(p5600) Value(87) Canonical
1586
1587  EnumValue
1588 -Enum(mips_arch_opt_value) String(m5101) Value(88) Canonical
1589 +Enum(mips_arch_opt_value) String(m5100) Value(88) Canonical
1590
1591  EnumValue
1592 -Enum(mips_arch_opt_value) String(5kc) Value(89) Canonical
1593 +Enum(mips_arch_opt_value) String(m5101) Value(89) Canonical
1594
1595  EnumValue
1596 -Enum(mips_arch_opt_value) String(r5kc) Value(89)
1597 +Enum(mips_arch_opt_value) String(5kc) Value(90) Canonical
1598
1599  EnumValue
1600 -Enum(mips_arch_opt_value) String(5kf) Value(90) Canonical
1601 +Enum(mips_arch_opt_value) String(r5kc) Value(90)
1602
1603  EnumValue
1604 -Enum(mips_arch_opt_value) String(r5kf) Value(90)
1605 +Enum(mips_arch_opt_value) String(5kf) Value(91) Canonical
1606
1607  EnumValue
1608 -Enum(mips_arch_opt_value) String(20kc) Value(91) Canonical
1609 +Enum(mips_arch_opt_value) String(r5kf) Value(91)
1610
1611  EnumValue
1612 -Enum(mips_arch_opt_value) String(r20kc) Value(91)
1613 +Enum(mips_arch_opt_value) String(20kc) Value(92) Canonical
1614
1615  EnumValue
1616 -Enum(mips_arch_opt_value) String(sb1) Value(92) Canonical
1617 +Enum(mips_arch_opt_value) String(r20kc) Value(92)
1618
1619  EnumValue
1620 -Enum(mips_arch_opt_value) String(sb1a) Value(93) Canonical
1621 +Enum(mips_arch_opt_value) String(sb1) Value(93) Canonical
1622
1623  EnumValue
1624 -Enum(mips_arch_opt_value) String(sr71000) Value(94) Canonical
1625 +Enum(mips_arch_opt_value) String(sb1a) Value(94) Canonical
1626
1627  EnumValue
1628 -Enum(mips_arch_opt_value) String(sr71k) Value(94)
1629 +Enum(mips_arch_opt_value) String(sr71000) Value(95) Canonical
1630
1631  EnumValue
1632 -Enum(mips_arch_opt_value) String(xlr) Value(95) Canonical
1633 +Enum(mips_arch_opt_value) String(sr71k) Value(95)
1634
1635  EnumValue
1636 -Enum(mips_arch_opt_value) String(loongson3a) Value(96) Canonical
1637 +Enum(mips_arch_opt_value) String(xlr) Value(96) Canonical
1638
1639  EnumValue
1640 -Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical
1641 +Enum(mips_arch_opt_value) String(loongson3a) Value(97) Canonical
1642
1643  EnumValue
1644 -Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical
1645 +Enum(mips_arch_opt_value) String(gs464) Value(98) Canonical
1646
1647  EnumValue
1648 -Enum(mips_arch_opt_value) String(gs264e) Value(99) Canonical
1649 +Enum(mips_arch_opt_value) String(gs464e) Value(99) Canonical
1650
1651  EnumValue
1652 -Enum(mips_arch_opt_value) String(octeon) Value(100) Canonical
1653 +Enum(mips_arch_opt_value) String(gs264e) Value(100) Canonical
1654
1655  EnumValue
1656 -Enum(mips_arch_opt_value) String(octeon+) Value(101) Canonical
1657 +Enum(mips_arch_opt_value) String(octeon) Value(101) Canonical
1658
1659  EnumValue
1660 -Enum(mips_arch_opt_value) String(octeon2) Value(102) Canonical
1661 +Enum(mips_arch_opt_value) String(octeon+) Value(102) Canonical
1662
1663  EnumValue
1664 -Enum(mips_arch_opt_value) String(octeon3) Value(103) Canonical
1665 +Enum(mips_arch_opt_value) String(octeon2) Value(103) Canonical
1666
1667  EnumValue
1668 -Enum(mips_arch_opt_value) String(xlp) Value(104) Canonical
1669 +Enum(mips_arch_opt_value) String(octeon3) Value(104) Canonical
1670
1671  EnumValue
1672 -Enum(mips_arch_opt_value) String(i6400) Value(105) Canonical
1673 +Enum(mips_arch_opt_value) String(xlp) Value(105) Canonical
1674
1675  EnumValue
1676 -Enum(mips_arch_opt_value) String(i6500) Value(106) Canonical
1677 +Enum(mips_arch_opt_value) String(i6400) Value(106) Canonical
1678
1679  EnumValue
1680 -Enum(mips_arch_opt_value) String(p6600) Value(107) Canonical
1681 +Enum(mips_arch_opt_value) String(i6500) Value(107) Canonical
1682 +
1683 +EnumValue
1684 +Enum(mips_arch_opt_value) String(p6600) Value(108) Canonical
1685
1686
1687 From 873f9ff28c1ce079d48ca53f845fe0c88fa6961b Mon Sep 17 00:00:00 2001
1688 From: David Guillen Fandos <david@davidgf.net>
1689 Date: Wed, 12 Jan 2022 21:44:15 +0100
1690 Subject: [PATCH 3/3] Add default libraries to LIB_SPEC
1691
1692 ---
1693  gcc/config/mips/psp.h | 17 +++++++++++++----
1694  1 file changed, 13 insertions(+), 4 deletions(-)
1695
1696 diff --git a/gcc/config/mips/psp.h b/gcc/config/mips/psp.h
1697 index c5e4b5d93d03..49849fb6bd46 100644
1698 --- a/gcc/config/mips/psp.h
1699 +++ b/gcc/config/mips/psp.h
1700 @@ -19,13 +19,22 @@ along with GCC; see the file COPYING.  If not, write to
1701  the Free Software Foundation, 59 Temple Place - Suite 330,
1702  Boston, MA 02111-1307, USA.  */
1703
1704 +#undef  LIB_SPEC
1705 +#define LIB_SPEC " \
1706 +    -lm \
1707 +    --start-group \
1708 +    -lcglue \
1709 +    %{g:-lg} %{!g:-lc} \
1710 +    --end-group \
1711 +    -lpsputility -lpsprtc -lpspnet_inet -lpspnet_resolver \
1712 +    -lpspmodinfo -lpspuser -lpspkernel"
1713 +
1714  /* Override the startfile spec to include crt0.o. */
1715  #undef STARTFILE_SPEC
1716  #define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
1717
1718  #undef SUBTARGET_CPP_SPEC
1719 -#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
1720 +#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__PSP__=1 -D_PSP=1 -D__psp__=1"
1721
1722 -/* Get rid of the .pdr section. */
1723 -#undef SUBTARGET_ASM_SPEC
1724 -#define SUBTARGET_ASM_SPEC "-mno-pdr"
1725 +#undef ENDFILE_SPEC
1726 +#define ENDFILE_SPEC "crtend%O%s crtn%O%s"