| blob | aa61046c948a227a407885c627286e915f882f28 |
1 From bb3c42bbdf68a727b067fc952a3f7841927cdaf0 Mon Sep 17 00:00:00 2001
2 From: rofl0r <rofl0r@users.noreply.github.com>
3 Date: Thu, 17 Mar 2022 15:39:48 +0000
4 Subject: [PATCH] second try at psp patch
6 ---
7 config.sub | 6 +
8 gcc/config.gcc | 12 ++
9 gcc/config/mips/allegrex.md | 191 ++++++++++++++++++++++++++++++++
10 gcc/config/mips/mips-cpus.def | 1 +
11 gcc/config/mips/mips-ftypes.def | 4 +
12 gcc/config/mips/mips.c | 114 ++++++++++++++++++-
13 gcc/config/mips/mips.h | 20 +++-
14 gcc/config/mips/mips.md | 68 ++++++++++--
15 gcc/config/mips/mips.opt | 4 +
16 gcc/config/mips/psp.h | 31 ++++++
17 gcc/config/mips/t-allegrex | 29 +++++
18 libcpp/Makefile.in | 4 +-
19 libgcc/config.host | 2 +
20 libgcc/crtstuff.c | 2 +-
21 14 files changed, 474 insertions(+), 14 deletions(-)
22 create mode 100644 gcc/config/mips/allegrex.md
23 create mode 100644 gcc/config/mips/psp.h
24 create mode 100644 gcc/config/mips/t-allegrex
26 diff --git a/config.sub b/config.sub
27 index 78176a440..a7dfd6135 100755
28 --- a/config.sub
29 +++ b/config.sub
30 @@ -283,6 +283,7 @@ case $basic_machine in
31 | mipsisa64sb1 | mipsisa64sb1el \
32 | mipsisa64sr71k | mipsisa64sr71kel \
33 | mipstx39 | mipstx39el \
34 + | mipsallegrex | mipsallegrexel \
35 | mn10200 | mn10300 \
36 | moxie \
37 | mt \
38 @@ -396,6 +397,7 @@ case $basic_machine in
39 | mipsisa64sb1-* | mipsisa64sb1el-* \
40 | mipsisa64sr71k-* | mipsisa64sr71kel-* \
41 | mipstx39-* | mipstx39el-* \
42 + | mipsallegrex-* | mipsallegrexel-* \
43 | mmix-* \
44 | mt-* \
45 | msp430-* \
46 @@ -795,6 +797,10 @@ case $basic_machine in
47 basic_machine=m68k-atari
48 os=-mint
49 ;;
50 + psp)
51 + basic_machine=mipsallegrexel-psp
52 + os=-elf
53 + ;;
54 mips3*-*)
55 basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
56 ;;
57 diff --git a/gcc/config.gcc b/gcc/config.gcc
58 index 9503b96cf..c1fe5d38b 100644
59 --- a/gcc/config.gcc
60 +++ b/gcc/config.gcc
61 @@ -1931,6 +1931,18 @@ mipstx39-*-elf* | mipstx39el-*-elf*)
62 tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
63 tmake_file="mips/t-r3900"
64 ;;
65 +mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
66 + tm_file="elfos.h ${tm_file} mips/elf.h"
67 + tmake_file=mips/t-allegrex
68 + target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
69 + tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
70 + case ${target} in
71 + mipsallegrex*-psp-elf*)
72 + tm_file="${tm_file} mips/psp.h"
73 + ;;
74 + esac
75 + use_fixproto=yes
76 + ;;
77 mmix-knuth-mmixware)
78 tm_file="${tm_file} newlib-stdint.h"
79 need_64bit_hwint=yes
80 diff --git a/gcc/config/mips/allegrex.md b/gcc/config/mips/allegrex.md
81 new file mode 100644
82 index 000000000..f5a7d798b
83 --- /dev/null
84 +++ b/gcc/config/mips/allegrex.md
85 @@ -0,0 +1,191 @@
86 +;; Sony ALLEGREX instructions.
87 +;; Copyright (C) 2005 Free Software Foundation, Inc.
88 +;;
89 +;; This file is part of GCC.
90 +;;
91 +;; GCC is free software; you can redistribute it and/or modify
92 +;; it under the terms of the GNU General Public License as published by
93 +;; the Free Software Foundation; either version 2, or (at your option)
94 +;; any later version.
95 +;;
96 +;; GCC is distributed in the hope that it will be useful,
97 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
98 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
99 +;; GNU General Public License for more details.
100 +;;
101 +;; You should have received a copy of the GNU General Public License
102 +;; along with GCC; see the file COPYING. If not, write to
103 +;; the Free Software Foundation, 59 Temple Place - Suite 330,
104 +;; Boston, MA 02111-1307, USA.
105 +
106 +(define_c_enum "unspec" [
107 + UNSPEC_WSBH
108 + UNSPEC_CLO
109 + UNSPEC_CTO
110 + UNSPEC_CACHE
111 + UNSPEC_CEIL_W_S
112 + UNSPEC_FLOOR_W_S
113 + UNSPEC_ROUND_W_S
114 +])
115 +
116 +;; Multiply Add and Subtract.
117 +;; Note: removed clobbering for madd and msub (testing needed)
118 +
119 +(define_insn "allegrex_madd"
120 + [(set (match_operand:SI 0 "register_operand" "+l")
121 + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
122 + (match_operand:SI 2 "register_operand" "d"))
123 + (match_dup 0)))]
124 + "TARGET_ALLEGREX"
125 + "madd\t%1,%2"
126 + [(set_attr "type" "imadd")
127 + (set_attr "mode" "SI")])
128 +
129 +(define_insn "allegrex_msub"
130 + [(set (match_operand:SI 0 "register_operand" "+l")
131 + (minus:SI (match_dup 0)
132 + (mult:SI (match_operand:SI 1 "register_operand" "d")
133 + (match_operand:SI 2 "register_operand" "d"))))]
134 + "TARGET_ALLEGREX"
135 + "msub\t%1,%2"
136 + [(set_attr "type" "imadd")
137 + (set_attr "mode" "SI")])
138 +
139 +
140 +;; Min and max.
141 +
142 +(define_insn "sminsi3"
143 + [(set (match_operand:SI 0 "register_operand" "=d")
144 + (smin:SI (match_operand:SI 1 "register_operand" "d")
145 + (match_operand:SI 2 "register_operand" "d")))]
146 + "TARGET_ALLEGREX"
147 + "min\t%0,%1,%2"
148 + [(set_attr "type" "arith")
149 + (set_attr "mode" "SI")])
150 +
151 +(define_insn "smaxsi3"
152 + [(set (match_operand:SI 0 "register_operand" "=d")
153 + (smax:SI (match_operand:SI 1 "register_operand" "d")
154 + (match_operand:SI 2 "register_operand" "d")))]
155 + "TARGET_ALLEGREX"
156 + "max\t%0,%1,%2"
157 + [(set_attr "type" "arith")
158 + (set_attr "mode" "SI")])
159 +
160 +
161 +;; Extended shift instructions.
162 +
163 +(define_insn "allegrex_bitrev"
164 + [(set (match_operand:SI 0 "register_operand" "=d")
165 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
166 + UNSPEC_BITREV))]
167 + "TARGET_ALLEGREX"
168 + "bitrev\t%0,%1"
169 + [(set_attr "type" "arith")
170 + (set_attr "mode" "SI")])
171 +
172 +(define_insn "allegrex_wsbh"
173 + [(set (match_operand:SI 0 "register_operand" "=d")
174 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
175 + UNSPEC_WSBH))]
176 + "TARGET_ALLEGREX"
177 + "wsbh\t%0,%1"
178 + [(set_attr "type" "arith")
179 + (set_attr "mode" "SI")])
180 +
181 +(define_insn "bswapsi2"
182 + [(set (match_operand:SI 0 "register_operand" "=d")
183 + (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
184 + "TARGET_ALLEGREX"
185 + "wsbw\t%0,%1"
186 + [(set_attr "type" "shift")
187 + (set_attr "mode" "SI")])
188 +
189 +
190 +;; Count leading ones, count trailing zeros, and count trailing ones (clz is
191 +;; already defined).
192 +
193 +(define_insn "allegrex_clo"
194 + [(set (match_operand:SI 0 "register_operand" "=d")
195 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
196 + UNSPEC_CLO))]
197 + "TARGET_ALLEGREX"
198 + "clo\t%0,%1"
199 + [(set_attr "type" "clz")
200 + (set_attr "mode" "SI")])
201 +
202 +(define_expand "ctzsi2"
203 + [(set (match_operand:SI 0 "register_operand")
204 + (ctz:SI (match_operand:SI 1 "register_operand")))]
205 + "TARGET_ALLEGREX"
206 +{
207 + rtx r1;
208 +
209 + r1 = gen_reg_rtx (SImode);
210 + emit_insn (gen_allegrex_bitrev (r1, operands[1]));
211 + emit_insn (gen_clzsi2 (operands[0], r1));
212 + DONE;
213 +})
214 +
215 +(define_expand "allegrex_cto"
216 + [(set (match_operand:SI 0 "register_operand")
217 + (unspec:SI [(match_operand:SI 1 "register_operand")]
218 + UNSPEC_CTO))]
219 + "TARGET_ALLEGREX"
220 +{
221 + rtx r1;
222 +
223 + r1 = gen_reg_rtx (SImode);
224 + emit_insn (gen_allegrex_bitrev (r1, operands[1]));
225 + emit_insn (gen_allegrex_clo (operands[0], r1));
226 + DONE;
227 +})
228 +
229 +
230 +;; Misc.
231 +
232 +(define_insn "allegrex_sync"
233 + [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
234 + "TARGET_ALLEGREX"
235 + "sync"
236 + [(set_attr "type" "unknown")
237 + (set_attr "mode" "none")])
238 +
239 +(define_insn "allegrex_cache"
240 + [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
241 + (match_operand:SI 1 "register_operand" "d")]
242 + UNSPEC_CACHE)]
243 + "TARGET_ALLEGREX"
244 + "cache\t%0,0(%1)"
245 + [(set_attr "type" "unknown")
246 + (set_attr "mode" "none")])
247 +
248 +
249 +;; Floating-point builtins.
250 +
251 +(define_insn "allegrex_ceil_w_s"
252 + [(set (match_operand:SI 0 "register_operand" "=f")
253 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
254 + UNSPEC_CEIL_W_S))]
255 + "TARGET_ALLEGREX"
256 + "ceil.w.s\t%0,%1"
257 + [(set_attr "type" "fcvt")
258 + (set_attr "mode" "SF")])
259 +
260 +(define_insn "allegrex_floor_w_s"
261 + [(set (match_operand:SI 0 "register_operand" "=f")
262 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
263 + UNSPEC_FLOOR_W_S))]
264 + "TARGET_ALLEGREX"
265 + "floor.w.s\t%0,%1"
266 + [(set_attr "type" "fcvt")
267 + (set_attr "mode" "SF")])
268 +
269 +(define_insn "allegrex_round_w_s"
270 + [(set (match_operand:SI 0 "register_operand" "=f")
271 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
272 + UNSPEC_ROUND_W_S))]
273 + "TARGET_ALLEGREX"
274 + "round.w.s\t%0,%1"
275 + [(set_attr "type" "fcvt")
276 + (set_attr "mode" "SF")])
277 diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
278 index 98b915a1b..faa5e4cee 100644
279 --- a/gcc/config/mips/mips-cpus.def
280 +++ b/gcc/config/mips/mips-cpus.def
281 @@ -58,6 +58,7 @@ MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
283 /* MIPS II processors. */
284 MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
285 +MIPS_CPU ("allegrex", PROCESSOR_ALLEGREX, 2, 0)
287 /* MIPS III processors. */
288 MIPS_CPU ("r4000", PROCESSOR_R4000, 3, 0)
289 diff --git a/gcc/config/mips/mips-ftypes.def b/gcc/config/mips/mips-ftypes.def
290 index cd1d1da7a..ff02a8891 100644
291 --- a/gcc/config/mips/mips-ftypes.def
292 +++ b/gcc/config/mips/mips-ftypes.def
293 @@ -54,9 +54,12 @@ DEF_MIPS_FTYPE (4, (INT, V2SF, V2SF, V2SF, V2SF))
294 DEF_MIPS_FTYPE (2, (SI, DI, SI))
295 DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
296 DEF_MIPS_FTYPE (2, (DI, POINTER, SI))
297 +DEF_MIPS_FTYPE (1, (SI, HI))
298 +DEF_MIPS_FTYPE (1, (SI, SF))
299 DEF_MIPS_FTYPE (1, (SI, SI))
300 DEF_MIPS_FTYPE (2, (SI, SI, SI))
301 DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
302 +DEF_MIPS_FTYPE (1, (SI, QI))
303 DEF_MIPS_FTYPE (1, (SI, V2HI))
304 DEF_MIPS_FTYPE (2, (SI, V2HI, V2HI))
305 DEF_MIPS_FTYPE (1, (SI, V4QI))
306 @@ -125,3 +128,4 @@ DEF_MIPS_FTYPE (2, (VOID, SI, CVPOINTER))
307 DEF_MIPS_FTYPE (2, (VOID, SI, SI))
308 DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
309 DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
310 +DEF_MIPS_FTYPE (1, (VOID, VOID))
311 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
312 index 02e757b5b..a8891a8f1 100644
313 --- a/gcc/config/mips/mips.c
314 +++ b/gcc/config/mips/mips.c
315 @@ -233,7 +233,12 @@ enum mips_builtin_type {
316 MIPS_BUILTIN_CMP_SINGLE,
318 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
319 - MIPS_BUILTIN_BPOSGE32
320 + MIPS_BUILTIN_BPOSGE32,
321 +
322 + /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0
323 + is the function code (must be less than 32) and operand 1 is the base
324 + address. */
325 + MIPS_BUILTIN_CACHE
326 };
328 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
329 @@ -525,6 +530,10 @@ struct mips_asm_switch mips_noat = { "at", 0 };
330 normal branch. */
331 static bool mips_branch_likely;
333 +/* Preferred stack boundary for proper stack vars alignment */
334 +unsigned int mips_preferred_stack_boundary;
335 +unsigned int mips_preferred_stack_align;
336 +
337 /* The current instruction-set architecture. */
338 enum processor mips_arch;
339 const struct mips_cpu_info *mips_arch_info;
340 @@ -871,6 +880,9 @@ static const struct mips_rtx_cost_data
341 1, /* branch_cost */
342 4 /* memory_latency */
343 },
344 + { /* Allegrex */
345 + DEFAULT_COSTS
346 + },
347 { /* Loongson-2E */
348 DEFAULT_COSTS
349 },
350 @@ -12979,6 +12991,7 @@ AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
351 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
352 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
353 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
354 +AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
356 /* Construct a mips_builtin_description from the given arguments.
358 @@ -13075,6 +13088,30 @@ AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
359 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
360 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
362 +/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
363 + FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
364 +#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
365 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
366 + MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
367 +
368 +/* Same as the above, but mapped to an instruction that doesn't share the
369 + NAME. NAME is the name of the builtin without the builtin prefix. */
370 +#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
371 + { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME, \
372 + MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
373 +
374 +/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
375 + CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
376 + builtin_description fields. */
377 +#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
378 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
379 + MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex }
380 +
381 +/* Define a builtin with a specific function TYPE. */
382 +#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
383 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
384 + MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
385 +
386 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
387 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
388 builtin_description field. */
389 @@ -13316,6 +13353,40 @@ static const struct mips_builtin_description mips_builtins[] = {
390 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
391 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
393 +/* Builtin functions for the Sony ALLEGREX processor.
394 +
395 + These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
396 + to maintain compatibility with Sony's ALLEGREX GCC port.
397 +
398 + Some of the builtins may seem redundant, but they are the same as the
399 + builtins defined in the Sony compiler. I chose to map redundant and
400 + trivial builtins to the original instruction instead of creating
401 + duplicate patterns specifically for the ALLEGREX (as Sony does). */
402 +
403 + DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
404 + DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0),
405 + DIRECT_ALLEGREX_NAMED_BUILTIN(wsbw, bswapsi2, MIPS_SI_FTYPE_SI, 0),
406 + DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
407 + DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
408 + DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
409 + DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
410 + DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
411 + DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
412 +
413 + DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
414 + DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
415 + DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
416 + DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
417 +
418 + DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
419 + SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
420 +
421 + DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
422 + DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
423 + DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
424 + DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
425 + DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
426 +
427 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
428 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
429 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
430 @@ -13467,6 +13538,8 @@ mips_build_cvpointer_type (void)
431 /* Standard mode-based argument types. */
432 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
433 #define MIPS_ATYPE_SI intSI_type_node
434 +#define MIPS_ATYPE_HI intHI_type_node
435 +#define MIPS_ATYPE_QI intQI_type_node
436 #define MIPS_ATYPE_USI unsigned_intSI_type_node
437 #define MIPS_ATYPE_DI intDI_type_node
438 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
439 @@ -13768,6 +13841,26 @@ mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
440 const1_rtx, const0_rtx);
441 }
443 +/* Expand a __builtin_allegrex_cache() function. Make sure the passed
444 + cache function code is less than 32. */
445 +
446 +static rtx
447 +mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
448 +{
449 + int argno;
450 + struct expand_operand ops[2];
451 +
452 + for (argno = 0; argno < 2; argno++)
453 + mips_prepare_builtin_arg (&ops[argno], exp, argno);
454 +
455 + if (GET_CODE(ops[0].value) != CONST_INT ||
456 + INTVAL(ops[0].value) < 0 || INTVAL(ops[0].value) > 0x1f)
457 + error("Invalid first argument for cache builtin (0 <= arg <= 31)");
458 +
459 + emit_insn(mips_expand_builtin_insn (icode, 2, ops, false));
460 + return target;
461 +}
462 +
463 /* Implement TARGET_EXPAND_BUILTIN. */
465 static rtx
466 @@ -13813,6 +13906,9 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
468 case MIPS_BUILTIN_BPOSGE32:
469 return mips_expand_builtin_bposge (d->builtin_type, target);
470 +
471 + case MIPS_BUILTIN_CACHE:
472 + return mips_expand_builtin_cache (d->icode, target, exp);
473 }
474 gcc_unreachable ();
475 }
476 @@ -16172,6 +16268,22 @@ mips_option_override (void)
477 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
478 MIPS16 mode afterwards if need be. */
479 mips_set_mips16_mode (false);
480 +
481 + /* Validate -mpreferred-stack-boundary= value, or provide default.
482 + The default of 128-bit is for newABI else 64-bit. */
483 + mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
484 + mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
485 + if (mips_preferred_stack_boundary_string)
486 + {
487 + i = atoi (mips_preferred_stack_boundary_string);
488 + if (i < 2 || i > 12)
489 + error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
490 + else
491 + {
492 + mips_preferred_stack_align = (1 << i);
493 + mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
494 + }
495 + }
496 }
498 /* Swap the register information for registers I and I + 1, which
499 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
500 index 1c19f8b2d..9aa4c136a 100644
501 --- a/gcc/config/mips/mips.h
502 +++ b/gcc/config/mips/mips.h
503 @@ -229,6 +229,7 @@ struct mips_cpu_info {
504 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
505 || mips_arch == PROCESSOR_SB1A)
506 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
507 +#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX)
509 /* Scheduling target defines. */
510 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
511 @@ -257,6 +258,7 @@ struct mips_cpu_info {
512 || mips_tune == PROCESSOR_OCTEON2)
513 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
514 || mips_tune == PROCESSOR_SB1A)
515 +#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX)
517 /* Whether vector modes and intrinsics for ST Microelectronics
518 Loongson-2E/2F processors should be enabled. In o32 pairs of
519 @@ -849,6 +851,9 @@ struct mips_cpu_info {
520 /* ISA has LDC1 and SDC1. */
521 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
523 +/* ISA has just the integer condition move instructions (movn,movz) */
524 +#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX)
525 +
526 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
527 branch on CC, and move (both FP and non-FP) on CC. */
528 #define ISA_HAS_8CC (ISA_MIPS4 \
529 @@ -871,6 +876,7 @@ struct mips_cpu_info {
531 /* ISA has conditional trap instructions. */
532 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
533 + && !TARGET_ALLEGREX \
534 && !TARGET_MIPS16)
536 /* ISA has integer multiply-accumulate instructions, madd and msub. */
537 @@ -907,6 +913,7 @@ struct mips_cpu_info {
538 /* ISA has count leading zeroes/ones instruction (not implemented). */
539 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
540 || ISA_MIPS32R2 \
541 + || TARGET_ALLEGREX \
542 || ISA_MIPS64 \
543 || ISA_MIPS64R2) \
544 && !TARGET_MIPS16)
545 @@ -952,6 +959,7 @@ struct mips_cpu_info {
546 || TARGET_MIPS5400 \
547 || TARGET_MIPS5500 \
548 || TARGET_SR71K \
549 + || TARGET_ALLEGREX \
550 || TARGET_SMARTMIPS) \
551 && !TARGET_MIPS16)
553 @@ -981,11 +989,13 @@ struct mips_cpu_info {
555 /* ISA includes the MIPS32r2 seb and seh instructions. */
556 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
557 + || TARGET_ALLEGREX \
558 || ISA_MIPS64R2) \
559 && !TARGET_MIPS16)
561 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
562 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
563 + || TARGET_ALLEGREX \
564 || ISA_MIPS64R2) \
565 && !TARGET_MIPS16)
567 @@ -1045,7 +1055,8 @@ struct mips_cpu_info {
568 || ISA_MIPS64 \
569 || ISA_MIPS64R2 \
570 || TARGET_MIPS5500 \
571 - || TARGET_LOONGSON_2EF)
572 + || TARGET_LOONGSON_2EF \
573 + || TARGET_ALLEGREX)
575 /* ISA includes synci, jr.hb and jalr.hb. */
576 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
577 @@ -2130,7 +2141,7 @@ enum reg_class
578 `crtl->outgoing_args_size'. */
579 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
581 -#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
582 +#define STACK_BOUNDARY (mips_preferred_stack_boundary)
583 \f
584 /* Symbolic macros for the registers used to return integer and floating
585 point values. */
586 @@ -2242,7 +2253,7 @@ typedef struct mips_args {
587 /* Treat LOC as a byte offset from the stack pointer and round it up
588 to the next fully-aligned offset. */
589 #define MIPS_STACK_ALIGN(LOC) \
590 - (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
591 + (((LOC) + (mips_preferred_stack_align - 1)) & -(mips_preferred_stack_align))
593 \f
594 /* Output assembler code to FILE to increment profiler label # LABELNO
595 @@ -2841,6 +2852,9 @@ while (0)
596 #endif
597 #endif
599 +extern unsigned int mips_preferred_stack_boundary;
600 +extern unsigned int mips_preferred_stack_align;
601 +
602 #ifndef HAVE_AS_TLS
603 #define HAVE_AS_TLS 0
604 #endif
605 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
606 index e5d716dfa..046019278 100644
607 --- a/gcc/config/mips/mips.md
608 +++ b/gcc/config/mips/mips.md
609 @@ -38,6 +38,7 @@
610 74kf2_1
611 74kf1_1
612 74kf3_2
613 + allegrex
614 loongson_2e
615 loongson_2f
616 loongson_3a
617 @@ -604,7 +605,7 @@
618 ;; This mode iterator allows :MOVECC to be used anywhere that a
619 ;; conditional-move-type condition is needed.
620 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
621 - (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
622 + (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF && !TARGET_ALLEGREX")])
624 ;; 32-bit integer moves for which we provide move patterns.
625 (define_mode_iterator IMOVE32
626 @@ -1917,11 +1918,11 @@
627 (mult:DI
628 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
629 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
630 - "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
631 + "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)"
632 {
633 if (ISA_HAS_DSP_MULT)
634 return "msub<u>\t%q0,%1,%2";
635 - else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
636 + else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX)
637 return "msub<u>\t%1,%2";
638 else
639 return "msac<u>\t$0,%1,%2";
640 @@ -2157,14 +2158,14 @@
641 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
642 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
643 (match_operand:DI 3 "muldiv_target_operand" "0")))]
644 - "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
645 + "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)
646 && !TARGET_64BIT"
647 {
648 if (TARGET_MAD)
649 return "mad<u>\t%1,%2";
650 else if (ISA_HAS_DSP_MULT)
651 return "madd<u>\t%q0,%1,%2";
652 - else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
653 + else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX)
654 return "madd<u>\t%1,%2";
655 else
656 /* See comment in *macc. */
657 @@ -2629,6 +2630,33 @@
658 [(set_attr "type" "pop")
659 (set_attr "mode" "<MODE>")])
660 \f
661 +;;
662 +;; ....................
663 +;;
664 +;; FIND FIRST BIT INSTRUCTION
665 +;;
666 +;; ....................
667 +;;
668 +
669 +(define_expand "ffs<mode>2"
670 + [(set (match_operand:GPR 0 "register_operand" "")
671 + (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
672 + "ISA_HAS_CLZ_CLO"
673 +{
674 + rtx r1, r2, r3, r4;
675 +
676 + r1 = gen_reg_rtx (<MODE>mode);
677 + r2 = gen_reg_rtx (<MODE>mode);
678 + r3 = gen_reg_rtx (<MODE>mode);
679 + r4 = gen_reg_rtx (<MODE>mode);
680 + emit_insn (gen_neg<mode>2 (r1, operands[1]));
681 + emit_insn (gen_and<mode>3 (r2, operands[1], r1));
682 + emit_insn (gen_clz<mode>2 (r3, r2));
683 + emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
684 + emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
685 + DONE;
686 +})
687 +
688 ;;
689 ;; ....................
690 ;;
691 @@ -2682,6 +2710,25 @@
692 [(set_attr "alu_type" "not")
693 (set_attr "mode" "<MODE>")])
694 \f
695 +(define_expand "rotl<mode>3"
696 + [(set (match_operand:GPR 0 "register_operand")
697 + (rotate:GPR (match_operand:GPR 1 "register_operand")
698 + (match_operand:SI 2 "arith_operand")))]
699 + "ISA_HAS_ROR"
700 +{
701 + rtx temp;
702 +
703 + if (GET_CODE (operands[2]) == CONST_INT)
704 + temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
705 + else
706 + {
707 + temp = gen_reg_rtx (<MODE>mode);
708 + emit_insn (gen_neg<mode>2 (temp, operands[2]));
709 + }
710 + emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
711 + DONE;
712 +})
713 +\f
714 ;;
715 ;; ....................
716 ;;
717 @@ -6451,7 +6498,7 @@
718 (const_int 0)])
719 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
720 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
721 - "ISA_HAS_CONDMOVE"
722 + "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
723 "@
724 mov%T4\t%0,%z2,%1
725 mov%t4\t%0,%z3,%1"
726 @@ -6481,8 +6528,12 @@
727 (if_then_else:GPR (match_dup 5)
728 (match_operand:GPR 2 "reg_or_0_operand")
729 (match_operand:GPR 3 "reg_or_0_operand")))]
730 - "ISA_HAS_CONDMOVE"
731 + "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
732 {
733 + if (ISA_HAS_INT_CONDMOVE
734 + && GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT)
735 + FAIL;
736 +
737 mips_expand_conditional_move (operands);
738 DONE;
739 })
740 @@ -6682,6 +6733,9 @@
741 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
742 (include "loongson.md")
744 +; Sony ALLEGREX instructions.
745 +(include "allegrex.md")
746 +
747 (define_c_enum "unspec" [
748 UNSPEC_ADDRESS_FIRST
749 ])
750 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
751 index e3294a7f7..36a1dc11a 100644
752 --- a/gcc/config/mips/mips.opt
753 +++ b/gcc/config/mips/mips.opt
754 @@ -354,5 +354,9 @@ mxgot
755 Target Report Var(TARGET_XGOT)
756 Lift restrictions on GOT size
758 +mpreferred-stack-boundary=
759 +Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
760 +Attempt to keep stack aligned to this power of 2
761 +
762 noasmopt
763 Driver
764 diff --git a/gcc/config/mips/psp.h b/gcc/config/mips/psp.h
765 new file mode 100644
766 index 000000000..224e7a096
767 --- /dev/null
768 +++ b/gcc/config/mips/psp.h
769 @@ -0,0 +1,31 @@
770 +/* Support for Sony's Playstation Portable (PSP).
771 + Copyright (C) 2005 Free Software Foundation, Inc.
772 + Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
773 +
774 +This file is part of GCC.
775 +
776 +GCC is free software; you can redistribute it and/or modify
777 +it under the terms of the GNU General Public License as published by
778 +the Free Software Foundation; either version 2, or (at your option)
779 +any later version.
780 +
781 +GCC is distributed in the hope that it will be useful,
782 +but WITHOUT ANY WARRANTY; without even the implied warranty of
783 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
784 +GNU General Public License for more details.
785 +
786 +You should have received a copy of the GNU General Public License
787 +along with GCC; see the file COPYING. If not, write to
788 +the Free Software Foundation, 59 Temple Place - Suite 330,
789 +Boston, MA 02111-1307, USA. */
790 +
791 +/* Override the startfile spec to include crt0.o. */
792 +#undef STARTFILE_SPEC
793 +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
794 +
795 +#undef SUBTARGET_CPP_SPEC
796 +#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1 -D__INTPTR_TYPE__=int -D__INT32_TYPE__=int -D__INT8_TYPE__=char -D__INT16_TYPE__=short"
797 +
798 +/* Get rid of the .pdr section. */
799 +#undef SUBTARGET_ASM_SPEC
800 +#define SUBTARGET_ASM_SPEC "-mno-pdr"
801 diff --git a/gcc/config/mips/t-allegrex b/gcc/config/mips/t-allegrex
802 new file mode 100644
803 index 000000000..89450d118
804 --- /dev/null
805 +++ b/gcc/config/mips/t-allegrex
806 @@ -0,0 +1,29 @@
807 +# Suppress building libgcc1.a, since the MIPS compiler port is complete
808 +# and does not need anything from libgcc1.a.
809 +LIBGCC1 =
810 +CROSS_LIBGCC1 =
811 +
812 +EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
813 +# Don't let CTOR_LIST end up in sdata section.
814 +CRTSTUFF_T_CFLAGS = -G 0
815 +
816 +# Assemble startup files.
817 +$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
818 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
819 + -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
820 +
821 +$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
822 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
823 + -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
824 +
825 +# We must build libgcc2.a with -G 0, in case the user wants to link
826 +# without the $gp register.
827 +TARGET_LIBGCC2_CFLAGS = -G 0
828 +
829 +# Build the libraries for both hard and soft floating point
830 +
831 +MULTILIB_OPTIONS =
832 +MULTILIB_DIRNAMES =
833 +
834 +LIBGCC = stmp-multilib
835 +INSTALL_LIBGCC = install-multilib
836 diff --git a/libcpp/Makefile.in b/libcpp/Makefile.in
837 index d6df46d62..7dcbf35f5 100644
838 --- a/libcpp/Makefile.in
839 +++ b/libcpp/Makefile.in
840 @@ -214,8 +214,8 @@ ifeq ($(DEPMODE),depmode=gcc3)
841 # Note that we put the dependencies into a .Tpo file, then move them
842 # into place if the compile succeeds. We need this because gcc does
843 # not atomically write the dependency output file.
844 -COMPILE = $(COMPILE.base) -o $@ -MT $@ -MMD -MP -MF $(DEPDIR)/$*.Tpo
845 -POSTCOMPILE = @mv $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
846 +COMPILE = $(COMPILE.base) -o $@
847 +POSTCOMPILE =
848 else
849 COMPILE = source='$<' object='$@' libtool=no DEPDIR=$(DEPDIR) $(DEPMODE) \
850 $(depcomp) $(COMPILE.base)
851 diff --git a/libgcc/config.host b/libgcc/config.host
852 index b64da4a26..5aa528db7 100644
853 --- a/libgcc/config.host
854 +++ b/libgcc/config.host
855 @@ -811,6 +811,8 @@ mips-wrs-vxworks)
856 mipstx39-*-elf* | mipstx39el-*-elf*)
857 tmake_file="$tmake_file mips/t-crtstuff mips/t-mips16"
858 ;;
859 +mips*-psp-elf*)
860 + ;;
861 mmix-knuth-mmixware)
862 extra_parts="crti.o crtn.o crtbegin.o crtend.o"
863 tmake_file="${tmake_file} ${cpu_type}/t-${cpu_type}"
864 diff --git a/libgcc/crtstuff.c b/libgcc/crtstuff.c
865 index 5d820fa45..1d72c0e5f 100644
866 --- a/libgcc/crtstuff.c
867 +++ b/libgcc/crtstuff.c
868 @@ -49,7 +49,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
870 /* Target machine header files require this define. */
871 #define IN_LIBGCC2
872 -
873 +#define USED_FOR_TARGET
874 /* FIXME: Including auto-host is incorrect, but until we have
875 identified the set of defines that need to go into auto-target.h,
876 this will have to do. */
877 --
878 2.31.1