| blob | 612388bd70a9b36c76c34696b3da4adc26d6c887 |
1 From 9fb2d15369716f49a4b9530a636ea434dce2d092 Mon Sep 17 00:00:00 2001
2 From: Carsten Teibes <dev@f4ke.de>
3 Date: Thu, 9 Jul 2020 21:50:17 +0200
4 Subject: [PATCH] Add gcc-4.9.3-PSP.patch
6 ---
7 config.sub | 6 ++
8 gcc/config.gcc | 12 +++
9 gcc/config/mips/allegrex.md | 172 ++++++++++++++++++++++++++++++++
10 gcc/config/mips/mips-cpus.def | 1 +
11 gcc/config/mips/mips-ftypes.def | 4 +
12 gcc/config/mips/mips.c | 112 ++++++++++++++++++++-
13 gcc/config/mips/mips.h | 20 +++-
14 gcc/config/mips/mips.md | 67 +++++++++++--
15 gcc/config/mips/mips.opt | 4 +
16 gcc/config/mips/psp.h | 31 ++++++
17 gcc/config/mips/t-allegrex | 29 ++++++
18 libcpp/Makefile.in | 4 +-
19 libgcc/config.host | 16 ++-
20 libgcc/config/mips/psp.h | 31 ++++++
21 libgcc/config/mips/t-allegrex | 20 ++++
22 libgcc/config/t-hardfp-sf | 32 ++++++
23 libgcc/configure | 20 ++++
24 libgcc/configure.ac | 8 ++
25 libgcc/crtstuff.c | 2 +-
26 19 files changed, 576 insertions(+), 15 deletions(-)
27 create mode 100644 gcc/config/mips/allegrex.md
28 create mode 100644 gcc/config/mips/psp.h
29 create mode 100644 gcc/config/mips/t-allegrex
30 create mode 100644 libgcc/config/mips/psp.h
31 create mode 100644 libgcc/config/mips/t-allegrex
32 create mode 100644 libgcc/config/t-hardfp-sf
34 diff --git a/config.sub b/config.sub
35 index 61cb4bc22db..5a6100f84ba 100755
36 --- a/config.sub
37 +++ b/config.sub
38 @@ -289,6 +289,7 @@ case $basic_machine in
39 | mipsisa64sr71k | mipsisa64sr71kel \
40 | mipsr5900 | mipsr5900el \
41 | mipstx39 | mipstx39el \
42 + | mipsallegrex | mipsallegrexel \
43 | mn10200 | mn10300 \
44 | moxie \
45 | mt \
46 @@ -408,6 +409,7 @@ case $basic_machine in
47 | mipsisa64sr71k-* | mipsisa64sr71kel-* \
48 | mipsr5900-* | mipsr5900el-* \
49 | mipstx39-* | mipstx39el-* \
50 + | mipsallegrex-* | mipsallegrexel-* \
51 | mmix-* \
52 | mt-* \
53 | msp430-* \
54 @@ -810,6 +812,10 @@ case $basic_machine in
55 basic_machine=m68k-atari
56 os=-mint
57 ;;
58 + psp)
59 + basic_machine=mipsallegrexel-psp
60 + os=-elf
61 + ;;
62 mips3*-*)
63 basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
64 ;;
65 diff --git a/gcc/config.gcc b/gcc/config.gcc
66 index 7ade8e5d5f6..061145fd130 100644
67 --- a/gcc/config.gcc
68 +++ b/gcc/config.gcc
69 @@ -2118,6 +2118,18 @@ mipstx39-*-elf* | mipstx39el-*-elf*)
70 tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
71 tmake_file="mips/t-r3900"
72 ;;
73 +mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
74 + tm_file="elfos.h ${tm_file} mips/elf.h"
75 + tmake_file=mips/t-allegrex
76 + target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
77 + tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
78 + case ${target} in
79 + mipsallegrex*-psp-elf*)
80 + tm_file="${tm_file} mips/psp.h"
81 + ;;
82 + esac
83 + use_fixproto=yes
84 + ;;
85 mmix-knuth-mmixware)
86 tm_file="${tm_file} newlib-stdint.h"
87 need_64bit_hwint=yes
88 diff --git a/gcc/config/mips/allegrex.md b/gcc/config/mips/allegrex.md
89 new file mode 100644
90 index 00000000000..8499aa77679
91 --- /dev/null
92 +++ b/gcc/config/mips/allegrex.md
93 @@ -0,0 +1,172 @@
94 +;; Sony ALLEGREX instructions.
95 +;; Copyright (C) 2005 Free Software Foundation, Inc.
96 +;;
97 +;; This file is part of GCC.
98 +;;
99 +;; GCC is free software; you can redistribute it and/or modify
100 +;; it under the terms of the GNU General Public License as published by
101 +;; the Free Software Foundation; either version 2, or (at your option)
102 +;; any later version.
103 +;;
104 +;; GCC is distributed in the hope that it will be useful,
105 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
106 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
107 +;; GNU General Public License for more details.
108 +;;
109 +;; You should have received a copy of the GNU General Public License
110 +;; along with GCC; see the file COPYING. If not, write to
111 +;; the Free Software Foundation, 59 Temple Place - Suite 330,
112 +;; Boston, MA 02111-1307, USA.
113 +
114 +(define_c_enum "unspec" [
115 + UNSPEC_CLO
116 + UNSPEC_CTO
117 + UNSPEC_CACHE
118 + UNSPEC_CEIL_W_S
119 + UNSPEC_FLOOR_W_S
120 + UNSPEC_ROUND_W_S
121 +])
122 +
123 +;; Multiply Add and Subtract.
124 +;; Note: removed clobbering for madd and msub (testing needed)
125 +
126 +(define_insn "allegrex_madd"
127 + [(set (match_operand:SI 0 "register_operand" "+l")
128 + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
129 + (match_operand:SI 2 "register_operand" "d"))
130 + (match_dup 0)))]
131 + "TARGET_ALLEGREX"
132 + "madd\t%1,%2"
133 + [(set_attr "type" "imadd")
134 + (set_attr "mode" "SI")])
135 +
136 +(define_insn "allegrex_msub"
137 + [(set (match_operand:SI 0 "register_operand" "+l")
138 + (minus:SI (match_dup 0)
139 + (mult:SI (match_operand:SI 1 "register_operand" "d")
140 + (match_operand:SI 2 "register_operand" "d"))))]
141 + "TARGET_ALLEGREX"
142 + "msub\t%1,%2"
143 + [(set_attr "type" "imadd")
144 + (set_attr "mode" "SI")])
145 +
146 +
147 +;; Min and max.
148 +
149 +(define_insn "sminsi3"
150 + [(set (match_operand:SI 0 "register_operand" "=d")
151 + (smin:SI (match_operand:SI 1 "register_operand" "d")
152 + (match_operand:SI 2 "register_operand" "d")))]
153 + "TARGET_ALLEGREX"
154 + "min\t%0,%1,%2"
155 + [(set_attr "type" "arith")
156 + (set_attr "mode" "SI")])
157 +
158 +(define_insn "smaxsi3"
159 + [(set (match_operand:SI 0 "register_operand" "=d")
160 + (smax:SI (match_operand:SI 1 "register_operand" "d")
161 + (match_operand:SI 2 "register_operand" "d")))]
162 + "TARGET_ALLEGREX"
163 + "max\t%0,%1,%2"
164 + [(set_attr "type" "arith")
165 + (set_attr "mode" "SI")])
166 +
167 +
168 +;; Extended shift instructions.
169 +
170 +(define_insn "allegrex_bitrev"
171 + [(set (match_operand:SI 0 "register_operand" "=d")
172 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
173 + UNSPEC_BITREV))]
174 + "TARGET_ALLEGREX"
175 + "bitrev\t%0,%1"
176 + [(set_attr "type" "arith")
177 + (set_attr "mode" "SI")])
178 +
179 +;; Count leading ones, count trailing zeros, and count trailing ones (clz is
180 +;; already defined).
181 +
182 +(define_insn "allegrex_clo"
183 + [(set (match_operand:SI 0 "register_operand" "=d")
184 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
185 + UNSPEC_CLO))]
186 + "TARGET_ALLEGREX"
187 + "clo\t%0,%1"
188 + [(set_attr "type" "clz")
189 + (set_attr "mode" "SI")])
190 +
191 +(define_expand "ctzsi2"
192 + [(set (match_operand:SI 0 "register_operand")
193 + (ctz:SI (match_operand:SI 1 "register_operand")))]
194 + "TARGET_ALLEGREX"
195 +{
196 + rtx r1;
197 +
198 + r1 = gen_reg_rtx (SImode);
199 + emit_insn (gen_allegrex_bitrev (r1, operands[1]));
200 + emit_insn (gen_clzsi2 (operands[0], r1));
201 + DONE;
202 +})
203 +
204 +(define_expand "allegrex_cto"
205 + [(set (match_operand:SI 0 "register_operand")
206 + (unspec:SI [(match_operand:SI 1 "register_operand")]
207 + UNSPEC_CTO))]
208 + "TARGET_ALLEGREX"
209 +{
210 + rtx r1;
211 +
212 + r1 = gen_reg_rtx (SImode);
213 + emit_insn (gen_allegrex_bitrev (r1, operands[1]));
214 + emit_insn (gen_allegrex_clo (operands[0], r1));
215 + DONE;
216 +})
217 +
218 +
219 +;; Misc.
220 +
221 +(define_insn "allegrex_sync"
222 + [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
223 + "TARGET_ALLEGREX"
224 + "sync"
225 + [(set_attr "type" "unknown")
226 + (set_attr "mode" "none")])
227 +
228 +(define_insn "allegrex_cache"
229 + [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
230 + (match_operand:SI 1 "register_operand" "d")]
231 + UNSPEC_CACHE)]
232 + "TARGET_ALLEGREX"
233 + "cache\t%0,0(%1)"
234 + [(set_attr "type" "unknown")
235 + (set_attr "mode" "none")])
236 +
237 +
238 +;; Floating-point builtins.
239 +
240 +(define_insn "allegrex_ceil_w_s"
241 + [(set (match_operand:SI 0 "register_operand" "=f")
242 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
243 + UNSPEC_CEIL_W_S))]
244 + "TARGET_ALLEGREX"
245 + "ceil.w.s\t%0,%1"
246 + [(set_attr "type" "fcvt")
247 + (set_attr "mode" "SF")])
248 +
249 +(define_insn "allegrex_floor_w_s"
250 + [(set (match_operand:SI 0 "register_operand" "=f")
251 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
252 + UNSPEC_FLOOR_W_S))]
253 + "TARGET_ALLEGREX"
254 + "floor.w.s\t%0,%1"
255 + [(set_attr "type" "fcvt")
256 + (set_attr "mode" "SF")])
257 +
258 +(define_insn "allegrex_round_w_s"
259 + [(set (match_operand:SI 0 "register_operand" "=f")
260 + (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
261 + UNSPEC_ROUND_W_S))]
262 + "TARGET_ALLEGREX"
263 + "round.w.s\t%0,%1"
264 + [(set_attr "type" "fcvt")
265 + (set_attr "mode" "SF")])
266 diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
267 index 07fbf9c7ef4..cedd21bd764 100644
268 --- a/gcc/config/mips/mips-cpus.def
269 +++ b/gcc/config/mips/mips-cpus.def
270 @@ -55,6 +55,7 @@ MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
272 /* MIPS II processors. */
273 MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
274 +MIPS_CPU ("allegrex", PROCESSOR_ALLEGREX, 2, 0)
276 /* MIPS III processors. */
277 MIPS_CPU ("r4000", PROCESSOR_R4000, 3, 0)
278 diff --git a/gcc/config/mips/mips-ftypes.def b/gcc/config/mips/mips-ftypes.def
279 index 078a595a8b1..83993473f9d 100644
280 --- a/gcc/config/mips/mips-ftypes.def
281 +++ b/gcc/config/mips/mips-ftypes.def
282 @@ -53,9 +53,12 @@ DEF_MIPS_FTYPE (4, (INT, V2SF, V2SF, V2SF, V2SF))
283 DEF_MIPS_FTYPE (2, (SI, DI, SI))
284 DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
285 DEF_MIPS_FTYPE (2, (DI, POINTER, SI))
286 +DEF_MIPS_FTYPE (1, (SI, HI))
287 +DEF_MIPS_FTYPE (1, (SI, SF))
288 DEF_MIPS_FTYPE (1, (SI, SI))
289 DEF_MIPS_FTYPE (2, (SI, SI, SI))
290 DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
291 +DEF_MIPS_FTYPE (1, (SI, QI))
292 DEF_MIPS_FTYPE (1, (SI, V2HI))
293 DEF_MIPS_FTYPE (2, (SI, V2HI, V2HI))
294 DEF_MIPS_FTYPE (1, (SI, V4QI))
295 @@ -127,3 +130,4 @@ DEF_MIPS_FTYPE (2, (VOID, SI, SI))
296 DEF_MIPS_FTYPE (1, (VOID, USI))
297 DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
298 DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
299 +DEF_MIPS_FTYPE (1, (VOID, VOID))
300 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
301 index 143169bc150..c2ac8a786f0 100644
302 --- a/gcc/config/mips/mips.c
303 +++ b/gcc/config/mips/mips.c
304 @@ -248,7 +248,12 @@ enum mips_builtin_type {
305 MIPS_BUILTIN_CMP_SINGLE,
307 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
308 - MIPS_BUILTIN_BPOSGE32
309 + MIPS_BUILTIN_BPOSGE32,
310 +
311 + /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0
312 + is the function code (must be less than 32) and operand 1 is the base
313 + address. */
314 + MIPS_BUILTIN_CACHE
315 };
317 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
318 @@ -574,6 +579,10 @@ struct mips_asm_switch mips_noat = { "at", 0 };
319 normal branch. */
320 static bool mips_branch_likely;
322 +/* Preferred stack boundary for proper stack vars alignment */
323 +unsigned int mips_preferred_stack_boundary;
324 +unsigned int mips_preferred_stack_align;
325 +
326 /* The current instruction-set architecture. */
327 enum processor mips_arch;
328 const struct mips_cpu_info *mips_arch_info;
329 @@ -919,6 +928,9 @@ static const struct mips_rtx_cost_data
330 1, /* branch_cost */
331 4 /* memory_latency */
332 },
333 + { /* Allegrex */
334 + DEFAULT_COSTS
335 + },
336 { /* Loongson-2E */
337 DEFAULT_COSTS
338 },
339 @@ -13780,6 +13792,7 @@ AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
340 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
341 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
342 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
343 +AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
345 /* Construct a mips_builtin_description from the given arguments.
347 @@ -13876,6 +13889,30 @@ AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
348 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
349 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
351 +/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
352 + FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
353 +#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
354 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
355 + MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
356 +
357 +/* Same as the above, but mapped to an instruction that doesn't share the
358 + NAME. NAME is the name of the builtin without the builtin prefix. */
359 +#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
360 + { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME, \
361 + MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
362 +
363 +/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
364 + CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
365 + builtin_description fields. */
366 +#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
367 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
368 + MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex }
369 +
370 +/* Define a builtin with a specific function TYPE. */
371 +#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
372 + { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
373 + MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
374 +
375 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
376 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
377 builtin_description field. */
378 @@ -14122,6 +14159,38 @@ static const struct mips_builtin_description mips_builtins[] = {
379 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
380 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
382 +/* Builtin functions for the Sony ALLEGREX processor.
383 +
384 + These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
385 + to maintain compatibility with Sony's ALLEGREX GCC port.
386 +
387 + Some of the builtins may seem redundant, but they are the same as the
388 + builtins defined in the Sony compiler. I chose to map redundant and
389 + trivial builtins to the original instruction instead of creating
390 + duplicate patterns specifically for the ALLEGREX (as Sony does). */
391 +
392 + DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
393 + DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
394 + DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
395 + DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
396 + DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
397 + DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
398 + DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
399 +
400 + DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
401 + DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
402 + DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
403 + DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
404 +
405 + DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
406 + SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
407 +
408 + DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
409 + DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
410 + DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
411 + DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
412 + DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
413 +
414 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
415 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
416 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
417 @@ -14273,6 +14342,8 @@ mips_build_cvpointer_type (void)
418 /* Standard mode-based argument types. */
419 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
420 #define MIPS_ATYPE_SI intSI_type_node
421 +#define MIPS_ATYPE_HI intHI_type_node
422 +#define MIPS_ATYPE_QI intQI_type_node
423 #define MIPS_ATYPE_USI unsigned_intSI_type_node
424 #define MIPS_ATYPE_DI intDI_type_node
425 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
426 @@ -14575,6 +14646,26 @@ mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
427 const1_rtx, const0_rtx);
428 }
430 +/* Expand a __builtin_allegrex_cache() function. Make sure the passed
431 + cache function code is less than 32. */
432 +
433 +static rtx
434 +mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
435 +{
436 + int argno;
437 + struct expand_operand ops[2];
438 +
439 + for (argno = 0; argno < 2; argno++)
440 + mips_prepare_builtin_arg (&ops[argno], exp, argno);
441 +
442 + if (GET_CODE(ops[0].value) != CONST_INT ||
443 + INTVAL(ops[0].value) < 0 || INTVAL(ops[0].value) > 0x1f)
444 + error("Invalid first argument for cache builtin (0 <= arg <= 31)");
445 +
446 + emit_insn(mips_expand_builtin_insn (icode, 2, ops, false));
447 + return target;
448 +}
449 +
450 /* Implement TARGET_EXPAND_BUILTIN. */
452 static rtx
453 @@ -14620,6 +14711,9 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
455 case MIPS_BUILTIN_BPOSGE32:
456 return mips_expand_builtin_bposge (d->builtin_type, target);
457 +
458 + case MIPS_BUILTIN_CACHE:
459 + return mips_expand_builtin_cache (d->icode, target, exp);
460 }
461 gcc_unreachable ();
462 }
463 @@ -17376,6 +17470,22 @@ mips_option_override (void)
465 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
466 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
467 +
468 + /* Validate -mpreferred-stack-boundary= value, or provide default.
469 + The default of 128-bit is for newABI else 64-bit. */
470 + mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
471 + mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
472 + if (mips_preferred_stack_boundary_string)
473 + {
474 + i = atoi (mips_preferred_stack_boundary_string);
475 + if (i < 2 || i > 12)
476 + error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
477 + else
478 + {
479 + mips_preferred_stack_align = (1 << i);
480 + mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
481 + }
482 + }
483 }
485 /* Swap the register information for registers I and I + 1, which
486 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
487 index ff88d9847f9..dce51104548 100644
488 --- a/gcc/config/mips/mips.h
489 +++ b/gcc/config/mips/mips.h
490 @@ -231,6 +231,7 @@ struct mips_cpu_info {
491 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
492 || mips_arch == PROCESSOR_SB1A)
493 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
494 +#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX)
495 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
497 /* Scheduling target defines. */
498 @@ -260,6 +261,7 @@ struct mips_cpu_info {
499 || mips_tune == PROCESSOR_OCTEON2)
500 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
501 || mips_tune == PROCESSOR_SB1A)
502 +#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX)
504 /* Whether vector modes and intrinsics for ST Microelectronics
505 Loongson-2E/2F processors should be enabled. In o32 pairs of
506 @@ -868,6 +870,9 @@ struct mips_cpu_info {
507 && !TARGET_MIPS5900 \
508 && !TARGET_MIPS16)
510 +/* ISA has just the integer condition move instructions (movn,movz) */
511 +#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX)
512 +
513 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
514 branch on CC, and move (both FP and non-FP) on CC. */
515 #define ISA_HAS_8CC (ISA_MIPS4 \
516 @@ -895,6 +900,7 @@ struct mips_cpu_info {
518 /* ISA has conditional trap instructions. */
519 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
520 + && !TARGET_ALLEGREX \
521 && !TARGET_MIPS16)
523 /* ISA has integer multiply-accumulate instructions, madd and msub. */
524 @@ -938,6 +944,7 @@ struct mips_cpu_info {
525 /* ISA has count leading zeroes/ones instruction (not implemented). */
526 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
527 || ISA_MIPS32R2 \
528 + || TARGET_ALLEGREX \
529 || ISA_MIPS64 \
530 || ISA_MIPS64R2) \
531 && !TARGET_MIPS16)
532 @@ -983,6 +990,7 @@ struct mips_cpu_info {
533 || TARGET_MIPS5400 \
534 || TARGET_MIPS5500 \
535 || TARGET_SR71K \
536 + || TARGET_ALLEGREX \
537 || TARGET_SMARTMIPS) \
538 && !TARGET_MIPS16)
540 @@ -1014,11 +1022,13 @@ struct mips_cpu_info {
542 /* ISA includes the MIPS32r2 seb and seh instructions. */
543 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
544 + || TARGET_ALLEGREX \
545 || ISA_MIPS64R2) \
546 && !TARGET_MIPS16)
548 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
549 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
550 + || TARGET_ALLEGREX \
551 || ISA_MIPS64R2) \
552 && !TARGET_MIPS16)
554 @@ -1084,7 +1094,8 @@ struct mips_cpu_info {
555 || ISA_MIPS64R2 \
556 || TARGET_MIPS5500 \
557 || TARGET_MIPS5900 \
558 - || TARGET_LOONGSON_2EF)
559 + || TARGET_LOONGSON_2EF \
560 + || TARGET_ALLEGREX)
562 /* ISA includes synci, jr.hb and jalr.hb. */
563 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
564 @@ -2209,7 +2220,7 @@ enum reg_class
565 `crtl->outgoing_args_size'. */
566 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
568 -#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
569 +#define STACK_BOUNDARY (mips_preferred_stack_boundary)
570 \f
571 /* Symbolic macros for the registers used to return integer and floating
572 point values. */
573 @@ -2321,7 +2332,7 @@ typedef struct mips_args {
574 /* Treat LOC as a byte offset from the stack pointer and round it up
575 to the next fully-aligned offset. */
576 #define MIPS_STACK_ALIGN(LOC) \
577 - (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
578 + (((LOC) + (mips_preferred_stack_align - 1)) & -(mips_preferred_stack_align))
580 \f
581 /* Output assembler code to FILE to increment profiler label # LABELNO
582 @@ -2937,6 +2948,9 @@ while (0)
583 " TEXT_SECTION_ASM_OP);
584 #endif
586 +extern unsigned int mips_preferred_stack_boundary;
587 +extern unsigned int mips_preferred_stack_align;
588 +
589 #ifndef HAVE_AS_TLS
590 #define HAVE_AS_TLS 0
591 #endif
592 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
593 index 1e3e9e65957..9e4c1e7a448 100644
594 --- a/gcc/config/mips/mips.md
595 +++ b/gcc/config/mips/mips.md
596 @@ -35,6 +35,7 @@
597 74kf2_1
598 74kf1_1
599 74kf3_2
600 + allegrex
601 loongson_2e
602 loongson_2f
603 loongson_3a
604 @@ -756,6 +757,7 @@
605 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
606 (CC "TARGET_HARD_FLOAT
607 && !TARGET_LOONGSON_2EF
608 + && !TARGET_ALLEGREX
609 && !TARGET_MIPS5900")])
611 ;; 32-bit integer moves for which we provide move patterns.
612 @@ -2070,11 +2072,11 @@
613 (mult:DI
614 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
615 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
616 - "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
617 + "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)"
618 {
619 if (ISA_HAS_DSP_MULT)
620 return "msub<u>\t%q0,%1,%2";
621 - else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
622 + else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX)
623 return "msub<u>\t%1,%2";
624 else
625 return "msac<u>\t$0,%1,%2";
626 @@ -2312,14 +2314,14 @@
627 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
628 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
629 (match_operand:DI 3 "muldiv_target_operand" "0")))]
630 - "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
631 + "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)
632 && !TARGET_64BIT"
633 {
634 if (TARGET_MAD)
635 return "mad<u>\t%1,%2";
636 else if (ISA_HAS_DSP_MULT)
637 return "madd<u>\t%q0,%1,%2";
638 - else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
639 + else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX)
640 return "madd<u>\t%1,%2";
641 else
642 /* See comment in *macc. */
643 @@ -2854,6 +2856,33 @@
644 [(set_attr "type" "pop")
645 (set_attr "mode" "SI")])
646 \f
647 +;;
648 +;; ....................
649 +;;
650 +;; FIND FIRST BIT INSTRUCTION
651 +;;
652 +;; ....................
653 +;;
654 +
655 +(define_expand "ffs<mode>2"
656 + [(set (match_operand:GPR 0 "register_operand" "")
657 + (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
658 + "ISA_HAS_CLZ_CLO"
659 +{
660 + rtx r1, r2, r3, r4;
661 +
662 + r1 = gen_reg_rtx (<MODE>mode);
663 + r2 = gen_reg_rtx (<MODE>mode);
664 + r3 = gen_reg_rtx (<MODE>mode);
665 + r4 = gen_reg_rtx (<MODE>mode);
666 + emit_insn (gen_neg<mode>2 (r1, operands[1]));
667 + emit_insn (gen_and<mode>3 (r2, operands[1], r1));
668 + emit_insn (gen_clz<mode>2 (r3, r2));
669 + emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
670 + emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
671 + DONE;
672 +})
673 +
674 ;;
675 ;; ....................
676 ;;
677 @@ -2909,6 +2938,25 @@
678 (set_attr "compression" "micromips,*")
679 (set_attr "mode" "<MODE>")])
680 \f
681 +(define_expand "rotl<mode>3"
682 + [(set (match_operand:GPR 0 "register_operand")
683 + (rotate:GPR (match_operand:GPR 1 "register_operand")
684 + (match_operand:SI 2 "arith_operand")))]
685 + "ISA_HAS_ROR"
686 +{
687 + rtx temp;
688 +
689 + if (GET_CODE (operands[2]) == CONST_INT)
690 + temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
691 + else
692 + {
693 + temp = gen_reg_rtx (<MODE>mode);
694 + emit_insn (gen_neg<mode>2 (temp, operands[2]));
695 + }
696 + emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
697 + DONE;
698 +})
699 +\f
700 ;;
701 ;; ....................
702 ;;
703 @@ -6869,7 +6917,7 @@
704 (const_int 0)])
705 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
706 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
707 - "ISA_HAS_CONDMOVE"
708 + "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
709 "@
710 mov%T4\t%0,%z2,%1
711 mov%t4\t%0,%z3,%1"
712 @@ -6912,8 +6960,12 @@
713 (if_then_else:GPR (match_dup 5)
714 (match_operand:GPR 2 "reg_or_0_operand")
715 (match_operand:GPR 3 "reg_or_0_operand")))]
716 - "ISA_HAS_CONDMOVE"
717 + "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
718 {
719 + if (ISA_HAS_INT_CONDMOVE
720 + && GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT)
721 + FAIL;
722 +
723 mips_expand_conditional_move (operands);
724 DONE;
725 })
726 @@ -7185,6 +7237,9 @@
727 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
728 (include "loongson.md")
730 +; Sony ALLEGREX instructions.
731 +(include "allegrex.md")
732 +
733 (define_c_enum "unspec" [
734 UNSPEC_ADDRESS_FIRST
735 ])
736 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
737 index 6ee539837bb..dfdb8b0fc46 100644
738 --- a/gcc/config/mips/mips.opt
739 +++ b/gcc/config/mips/mips.opt
740 @@ -400,5 +400,9 @@ mxgot
741 Target Report Var(TARGET_XGOT)
742 Lift restrictions on GOT size
744 +mpreferred-stack-boundary=
745 +Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
746 +Attempt to keep stack aligned to this power of 2
747 +
748 noasmopt
749 Driver
750 diff --git a/gcc/config/mips/psp.h b/gcc/config/mips/psp.h
751 new file mode 100644
752 index 00000000000..c5e4b5d93d0
753 --- /dev/null
754 +++ b/gcc/config/mips/psp.h
755 @@ -0,0 +1,31 @@
756 +/* Support for Sony's Playstation Portable (PSP).
757 + Copyright (C) 2005 Free Software Foundation, Inc.
758 + Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
759 +
760 +This file is part of GCC.
761 +
762 +GCC is free software; you can redistribute it and/or modify
763 +it under the terms of the GNU General Public License as published by
764 +the Free Software Foundation; either version 2, or (at your option)
765 +any later version.
766 +
767 +GCC is distributed in the hope that it will be useful,
768 +but WITHOUT ANY WARRANTY; without even the implied warranty of
769 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
770 +GNU General Public License for more details.
771 +
772 +You should have received a copy of the GNU General Public License
773 +along with GCC; see the file COPYING. If not, write to
774 +the Free Software Foundation, 59 Temple Place - Suite 330,
775 +Boston, MA 02111-1307, USA. */
776 +
777 +/* Override the startfile spec to include crt0.o. */
778 +#undef STARTFILE_SPEC
779 +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
780 +
781 +#undef SUBTARGET_CPP_SPEC
782 +#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1 -D__INTPTR_TYPE__=int -D__INT32_TYPE__=int -D__INT8_TYPE__=char -D__INT16_TYPE__=short"
783 +
784 +/* Get rid of the .pdr section. */
785 +#undef SUBTARGET_ASM_SPEC
786 +#define SUBTARGET_ASM_SPEC "-mno-pdr"
787 diff --git a/gcc/config/mips/t-allegrex b/gcc/config/mips/t-allegrex
788 new file mode 100644
789 index 00000000000..89450d118c3
790 --- /dev/null
791 +++ b/gcc/config/mips/t-allegrex
792 @@ -0,0 +1,29 @@
793 +# Suppress building libgcc1.a, since the MIPS compiler port is complete
794 +# and does not need anything from libgcc1.a.
795 +LIBGCC1 =
796 +CROSS_LIBGCC1 =
797 +
798 +EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
799 +# Don't let CTOR_LIST end up in sdata section.
800 +CRTSTUFF_T_CFLAGS = -G 0
801 +
802 +# Assemble startup files.
803 +$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
804 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
805 + -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
806 +
807 +$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
808 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
809 + -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
810 +
811 +# We must build libgcc2.a with -G 0, in case the user wants to link
812 +# without the $gp register.
813 +TARGET_LIBGCC2_CFLAGS = -G 0
814 +
815 +# Build the libraries for both hard and soft floating point
816 +
817 +MULTILIB_OPTIONS =
818 +MULTILIB_DIRNAMES =
819 +
820 +LIBGCC = stmp-multilib
821 +INSTALL_LIBGCC = install-multilib
822 diff --git a/libcpp/Makefile.in b/libcpp/Makefile.in
823 index 5561c972fe2..4dd8e867741 100644
824 --- a/libcpp/Makefile.in
825 +++ b/libcpp/Makefile.in
826 @@ -208,8 +208,8 @@ ifeq ($(DEPMODE),depmode=gcc3)
827 # Note that we put the dependencies into a .Tpo file, then move them
828 # into place if the compile succeeds. We need this because gcc does
829 # not atomically write the dependency output file.
830 -COMPILE = $(COMPILE.base) -o $@ -MT $@ -MMD -MP -MF $(DEPDIR)/$*.Tpo
831 -POSTCOMPILE = @mv $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
832 +COMPILE = $(COMPILE.base) -o $@
833 +POSTCOMPILE =
834 else
835 COMPILE = source='$<' object='$@' libtool=no DEPDIR=$(DEPDIR) $(DEPMODE) \
836 $(depcomp) $(COMPILE.base)
837 diff --git a/libgcc/config.host b/libgcc/config.host
838 index f4a74287293..d74613a1dbc 100644
839 --- a/libgcc/config.host
840 +++ b/libgcc/config.host
841 @@ -140,11 +140,15 @@ microblaze*-*-*)
842 cpu_type=microblaze
843 ;;
844 mips*-*-*)
845 - # All MIPS targets provide a full set of FP routines.
846 cpu_type=mips
847 tmake_file="mips/t-mips"
848 if test "${libgcc_cv_mips_hard_float}" = yes; then
849 - tmake_file="${tmake_file} t-hardfp-sfdf t-hardfp"
850 + if test "${libgcc_cv_mips_single_float}" = yes; then
851 + tmake_file="${tmake_file} t-hardfp-sf"
852 + else
853 + tmake_file="${tmake_file} t-hardfp-sfdf"
854 + fi
855 + tmake_file="${tmake_file} t-hardfp"
856 else
857 tmake_file="${tmake_file} t-softfp-sfdf"
858 fi
859 @@ -860,6 +864,14 @@ mips-wrs-vxworks)
860 mipstx39-*-elf* | mipstx39el-*-elf*)
861 tmake_file="$tmake_file mips/t-crtstuff mips/t-mips16"
862 ;;
863 +mips*-psp*)
864 + tmake_file="${tmake_file} mips/t-allegrex"
865 + target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
866 + tm_file="${tm_file} mips/psp.h"
867 + extra_parts="$extra_parts crti.o crtn.o"
868 + use_fixproto=yes
869 + tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
870 + ;;
871 mmix-knuth-mmixware)
872 extra_parts="crti.o crtn.o crtbegin.o crtend.o"
873 tmake_file="${tmake_file} ${cpu_type}/t-${cpu_type}"
874 diff --git a/libgcc/config/mips/psp.h b/libgcc/config/mips/psp.h
875 new file mode 100644
876 index 00000000000..c5e4b5d93d0
877 --- /dev/null
878 +++ b/libgcc/config/mips/psp.h
879 @@ -0,0 +1,31 @@
880 +/* Support for Sony's Playstation Portable (PSP).
881 + Copyright (C) 2005 Free Software Foundation, Inc.
882 + Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
883 +
884 +This file is part of GCC.
885 +
886 +GCC is free software; you can redistribute it and/or modify
887 +it under the terms of the GNU General Public License as published by
888 +the Free Software Foundation; either version 2, or (at your option)
889 +any later version.
890 +
891 +GCC is distributed in the hope that it will be useful,
892 +but WITHOUT ANY WARRANTY; without even the implied warranty of
893 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
894 +GNU General Public License for more details.
895 +
896 +You should have received a copy of the GNU General Public License
897 +along with GCC; see the file COPYING. If not, write to
898 +the Free Software Foundation, 59 Temple Place - Suite 330,
899 +Boston, MA 02111-1307, USA. */
900 +
901 +/* Override the startfile spec to include crt0.o. */
902 +#undef STARTFILE_SPEC
903 +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
904 +
905 +#undef SUBTARGET_CPP_SPEC
906 +#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
907 +
908 +/* Get rid of the .pdr section. */
909 +#undef SUBTARGET_ASM_SPEC
910 +#define SUBTARGET_ASM_SPEC "-mno-pdr"
911 diff --git a/libgcc/config/mips/t-allegrex b/libgcc/config/mips/t-allegrex
912 new file mode 100644
913 index 00000000000..1722e19abe9
914 --- /dev/null
915 +++ b/libgcc/config/mips/t-allegrex
916 @@ -0,0 +1,20 @@
917 +# Suppress building libgcc1.a, since the MIPS compiler port is complete
918 +# and does not need anything from libgcc1.a.
919 +LIBGCC1 =
920 +CROSS_LIBGCC1 =
921 +
922 +EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
923 +# Don't let CTOR_LIST end up in sdata section.
924 +CRTSTUFF_T_CFLAGS = -G 0
925 +
926 +# We must build libgcc2.a with -G 0, in case the user wants to link
927 +# without the $gp register.
928 +TARGET_LIBGCC2_CFLAGS = -G 0
929 +
930 +# Build the libraries for both hard and soft floating point
931 +
932 +MULTILIB_OPTIONS =
933 +MULTILIB_DIRNAMES =
934 +
935 +LIBGCC = stmp-multilib
936 +INSTALL_LIBGCC = install-multilib
937 diff --git a/libgcc/config/t-hardfp-sf b/libgcc/config/t-hardfp-sf
938 new file mode 100644
939 index 00000000000..10682690219
940 --- /dev/null
941 +++ b/libgcc/config/t-hardfp-sf
942 @@ -0,0 +1,32 @@
943 +# Copyright (C) 2014 Free Software Foundation, Inc.
944 +
945 +# This file is part of GCC.
946 +
947 +# GCC is free software; you can redistribute it and/or modify
948 +# it under the terms of the GNU General Public License as published by
949 +# the Free Software Foundation; either version 3, or (at your option)
950 +# any later version.
951 +
952 +# GCC is distributed in the hope that it will be useful,
953 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
954 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
955 +# GNU General Public License for more details.
956 +
957 +# You should have received a copy of the GNU General Public License
958 +# along with GCC; see the file COPYING3. If not see
959 +# <http://www.gnu.org/licenses/>.
960 +
961 +hardfp_float_modes := sf
962 +# di and ti are provided by libgcc2.c where needed.
963 +hardfp_int_modes := si
964 +hardfp_extensions :=
965 +hardfp_truncations :=
966 +
967 +# Emulate 64 bit float:
968 +FPBIT = true
969 +DPBIT = true
970 +# Don't build functions handled by 32 bit hardware:
971 +LIB2FUNCS_EXCLUDE = _addsub_sf _mul_sf _div_sf \
972 + _fpcmp_parts_sf _compare_sf _eq_sf _ne_sf _gt_sf _ge_sf \
973 + _lt_sf _le_sf _unord_sf _si_to_sf _sf_to_si _negate_sf \
974 + _thenan_sf _sf_to_usi _usi_to_sf
975 diff --git a/libgcc/configure b/libgcc/configure
976 index 35896deb7bf..b04e158e155 100644
977 --- a/libgcc/configure
978 +++ b/libgcc/configure
979 @@ -4352,6 +4352,26 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
980 fi
981 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_hard_float" >&5
982 $as_echo "$libgcc_cv_mips_hard_float" >&6; }
983 + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the target is single-float" >&5
984 +$as_echo_n "checking whether the target is single-float... " >&6; }
985 +if test "${libgcc_cv_mips_single_float+set}" = set; then :
986 + $as_echo_n "(cached) " >&6
987 +else
988 + cat confdefs.h - <<_ACEOF >conftest.$ac_ext
989 +/* end confdefs.h. */
990 +#ifndef __mips_single_float
991 + #error FOO
992 + #endif
993 +_ACEOF
994 +if ac_fn_c_try_compile "$LINENO"; then :
995 + libgcc_cv_mips_single_float=yes
996 +else
997 + libgcc_cv_mips_single_float=no
998 +fi
999 +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
1000 +fi
1001 +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_single_float" >&5
1002 +$as_echo "$libgcc_cv_mips_single_float" >&6; }
1003 esac
1005 # Collect host-machine-specific information.
1006 diff --git a/libgcc/configure.ac b/libgcc/configure.ac
1007 index d877d21c092..312bf264679 100644
1008 --- a/libgcc/configure.ac
1009 +++ b/libgcc/configure.ac
1010 @@ -302,6 +302,14 @@ mips*-*-*)
1011 #endif],
1012 [libgcc_cv_mips_hard_float=yes],
1013 [libgcc_cv_mips_hard_float=no])])
1014 + AC_CACHE_CHECK([whether the target is single-float],
1015 + [libgcc_cv_mips_single_float],
1016 + [AC_COMPILE_IFELSE(
1017 + [#ifndef __mips_single_float
1018 + #error FOO
1019 + #endif],
1020 + [libgcc_cv_mips_single_float=yes],
1021 + [libgcc_cv_mips_single_float=no])])
1022 esac
1024 # Collect host-machine-specific information.
1025 diff --git a/libgcc/crtstuff.c b/libgcc/crtstuff.c
1026 index 12bed4b351d..c5adeafb0ae 100644
1027 --- a/libgcc/crtstuff.c
1028 +++ b/libgcc/crtstuff.c
1029 @@ -47,7 +47,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
1031 /* Target machine header files require this define. */
1032 #define IN_LIBGCC2
1033 -
1034 +#define USED_FOR_TARGET
1035 /* FIXME: Including auto-host is incorrect, but until we have
1036 identified the set of defines that need to go into auto-target.h,
1037 this will have to do. */