include/lib_AT91RM9200.h

   1 //*----------------------------------------------------------------------------
   2 //*         ATMEL Microcontroller Software Support  -  ROUSSET  -
   3 //*----------------------------------------------------------------------------
   4 //* The software is delivered "AS IS" without warranty or condition of any
   5 //* kind, either express, implied or statutory. This includes without
   6 //* limitation any warranty or condition with respect to merchantability or
   7 //* fitness for any particular purpose, or against the infringements of
   8 //* intellectual property rights of others.
   9 //*----------------------------------------------------------------------------
  10 //* File Name           : lib_AT91RM9200.h
  11 //* Object              : AT91RM9200 inlined functions
  12 //* Generated           : AT91 SW Application Group  07/04/2003 (11:05:04)
  13 //*
  14 //* CVS Reference       : /lib_pdc.h/1.2/Tue Jul 02 11:29:40 2002//
  15 //* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 11:18:40 2003//
  16 //* CVS Reference       : /lib_rtc_1245d.h/1.1/Fri Jan 31 11:19:12 2003//
  17 //* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 11:19:20 2003//
  18 //* CVS Reference       : /lib_spi_AT91RMxxxx.h/1.2/Fri Jan 31 11:19:30 2003//
  19 //* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 11:20:02 2003//
  20 //* CVS Reference       : /lib_pmc.h/1.3/Thu Nov 14 06:40:44 2002//
  21 //* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 11:18:56 2003//
  22 //* CVS Reference       : /lib_twi.h/1.2/Fri Jan 31 11:19:38 2003//
  23 //* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 15:01:52 2002//
  24 //* CVS Reference       : /lib_mci.h/1.2/Wed Nov 20 13:18:54 2002//
  25 //* CVS Reference       : /lib_aic.h/1.3/Fri Jul 12 06:46:10 2002//
  26 //* CVS Reference       : /lib_udp.h/1.3/Fri Jan 31 11:19:48 2003//
  27 //* CVS Reference       : /lib_st.h/1.4/Fri Jan 31 11:20:12 2003//
  28 //*----------------------------------------------------------------------------
  29
  30 #ifndef lib_AT91RM9200_H
  31 #define lib_AT91RM9200_H
  32
  33 /* *****************************************************************************
  34                 SOFTWARE API FOR PDC
  35    ***************************************************************************** */
  36 //*----------------------------------------------------------------------------
  37 //* \fn    AT91F_PDC_SetNextRx
  38 //* \brief Set the next receive transfer descriptor
  39 //*----------------------------------------------------------------------------
  40 __inline void AT91F_PDC_SetNextRx (
  41         AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
  42         char *address,       // \arg address to the next bloc to be received
  43         unsigned int bytes)  // \arg number of bytes to be received
  44 {
  45         pPDC->PDC_RNPR = (unsigned int) address;
  46         pPDC->PDC_RNCR = bytes;
  47 }
  48
  49 //*----------------------------------------------------------------------------
  50 //* \fn    AT91F_PDC_SetNextTx
  51 //* \brief Set the next transmit transfer descriptor
  52 //*----------------------------------------------------------------------------
  53 __inline void AT91F_PDC_SetNextTx (
  54         AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
  55         char *address,         // \arg address to the next bloc to be transmitted
  56         unsigned int bytes)    // \arg number of bytes to be transmitted
  57 {
  58         pPDC->PDC_TNPR = (unsigned int) address;
  59         pPDC->PDC_TNCR = bytes;
  60 }
  61
  62 //*----------------------------------------------------------------------------
  63 //* \fn    AT91F_PDC_SetRx
  64 //* \brief Set the receive transfer descriptor
  65 //*----------------------------------------------------------------------------
  66 __inline void AT91F_PDC_SetRx (
  67         AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
  68         char *address,         // \arg address to the next bloc to be received
  69         unsigned int bytes)    // \arg number of bytes to be received
  70 {
  71         pPDC->PDC_RPR = (unsigned int) address;
  72         pPDC->PDC_RCR = bytes;
  73 }
  74
  75 //*----------------------------------------------------------------------------
  76 //* \fn    AT91F_PDC_SetTx
  77 //* \brief Set the transmit transfer descriptor
  78 //*----------------------------------------------------------------------------
  79 __inline void AT91F_PDC_SetTx (
  80         AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
  81         char *address,         // \arg address to the next bloc to be transmitted
  82         unsigned int bytes)    // \arg number of bytes to be transmitted
  83 {
  84         pPDC->PDC_TPR = (unsigned int) address;
  85         pPDC->PDC_TCR = bytes;
  86 }
  87
  88 //*----------------------------------------------------------------------------
  89 //* \fn    AT91F_PDC_EnableTx
  90 //* \brief Enable transmit
  91 //*----------------------------------------------------------------------------
  92 __inline void AT91F_PDC_EnableTx (
  93         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
  94 {
  95         pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
  96 }
  97
  98 //*----------------------------------------------------------------------------
  99 //* \fn    AT91F_PDC_EnableRx
 100 //* \brief Enable receive
 101 //*----------------------------------------------------------------------------
 102 __inline void AT91F_PDC_EnableRx (
 103         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 104 {
 105         pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
 106 }
 107
 108 //*----------------------------------------------------------------------------
 109 //* \fn    AT91F_PDC_DisableTx
 110 //* \brief Disable transmit
 111 //*----------------------------------------------------------------------------
 112 __inline void AT91F_PDC_DisableTx (
 113         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 114 {
 115         pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
 116 }
 117
 118 //*----------------------------------------------------------------------------
 119 //* \fn    AT91F_PDC_DisableRx
 120 //* \brief Disable receive
 121 //*----------------------------------------------------------------------------
 122 __inline void AT91F_PDC_DisableRx (
 123         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 124 {
 125         pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
 126 }
 127
 128 //*----------------------------------------------------------------------------
 129 //* \fn    AT91F_PDC_IsTxEmpty
 130 //* \brief Test if the current transfer descriptor has been sent
 131 //*----------------------------------------------------------------------------
 132 __inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
 133         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 134 {
 135         return !(pPDC->PDC_TCR);
 136 }
 137
 138 //*----------------------------------------------------------------------------
 139 //* \fn    AT91F_PDC_IsNextTxEmpty
 140 //* \brief Test if the next transfer descriptor has been moved to the current td
 141 //*----------------------------------------------------------------------------
 142 __inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
 143         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 144 {
 145         return !(pPDC->PDC_TNCR);
 146 }
 147
 148 //*----------------------------------------------------------------------------
 149 //* \fn    AT91F_PDC_IsRxEmpty
 150 //* \brief Test if the current transfer descriptor has been filled
 151 //*----------------------------------------------------------------------------
 152 __inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
 153         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 154 {
 155         return !(pPDC->PDC_RCR);
 156 }
 157
 158 //*----------------------------------------------------------------------------
 159 //* \fn    AT91F_PDC_IsNextRxEmpty
 160 //* \brief Test if the next transfer descriptor has been moved to the current td
 161 //*----------------------------------------------------------------------------
 162 __inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
 163         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 164 {
 165         return !(pPDC->PDC_RNCR);
 166 }
 167
 168 //*----------------------------------------------------------------------------
 169 //* \fn    AT91F_PDC_Open
 170 //* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
 171 //*----------------------------------------------------------------------------
 172 __inline void AT91F_PDC_Open (
 173         AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
 174 {
 175     //* Disable the RX and TX PDC transfer requests
 176         AT91F_PDC_DisableRx(pPDC);
 177         AT91F_PDC_DisableTx(pPDC);
 178
 179         //* Reset all Counter register Next buffer first
 180         AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
 181         AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
 182         AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
 183         AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
 184
 185     //* Enable the RX and TX PDC transfer requests
 186         AT91F_PDC_EnableRx(pPDC);
 187         AT91F_PDC_EnableTx(pPDC);
 188 }
 189
 190 //*----------------------------------------------------------------------------
 191 //* \fn    AT91F_PDC_Close
 192 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 193 //*----------------------------------------------------------------------------
 194 __inline void AT91F_PDC_Close (
 195         AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
 196 {
 197     //* Disable the RX and TX PDC transfer requests
 198         AT91F_PDC_DisableRx(pPDC);
 199         AT91F_PDC_DisableTx(pPDC);
 200
 201         //* Reset all Counter register Next buffer first
 202         AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
 203         AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
 204         AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
 205         AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
 206
 207 }
 208
 209 //*----------------------------------------------------------------------------
 210 //* \fn    AT91F_PDC_SendFrame
 211 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 212 //*----------------------------------------------------------------------------
 213 __inline unsigned int AT91F_PDC_SendFrame(
 214         AT91PS_PDC pPDC,
 215         char *pBuffer,
 216         unsigned int szBuffer,
 217         char *pNextBuffer,
 218         unsigned int szNextBuffer )
 219 {
 220         if (AT91F_PDC_IsTxEmpty(pPDC)) {
 221                 //* Buffer and next buffer can be initialized
 222                 AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
 223                 AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
 224                 return 2;
 225         }
 226         else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
 227                 //* Only one buffer can be initialized
 228                 AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
 229                 return 1;
 230         }
 231         else {
 232                 //* All buffer are in use...
 233                 return 0;
 234         }
 235 }
 236
 237 //*----------------------------------------------------------------------------
 238 //* \fn    AT91F_PDC_ReceiveFrame
 239 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 240 //*----------------------------------------------------------------------------
 241 __inline unsigned int AT91F_PDC_ReceiveFrame (
 242         AT91PS_PDC pPDC,
 243         char *pBuffer,
 244         unsigned int szBuffer,
 245         char *pNextBuffer,
 246         unsigned int szNextBuffer )
 247 {
 248         if (AT91F_PDC_IsRxEmpty(pPDC)) {
 249                 //* Buffer and next buffer can be initialized
 250                 AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
 251                 AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
 252                 return 2;
 253         }
 254         else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
 255                 //* Only one buffer can be initialized
 256                 AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
 257                 return 1;
 258         }
 259         else {
 260                 //* All buffer are in use...
 261                 return 0;
 262         }
 263 }
 264 /* *****************************************************************************
 265                 SOFTWARE API FOR DBGU
 266    ***************************************************************************** */
 267 //*----------------------------------------------------------------------------
 268 //* \fn    AT91F_DBGU_InterruptEnable
 269 //* \brief Enable DBGU Interrupt
 270 //*----------------------------------------------------------------------------
 271 __inline void AT91F_DBGU_InterruptEnable(
 272         AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
 273         unsigned int flag) // \arg  dbgu interrupt to be enabled
 274 {
 275         pDbgu->DBGU_IER = flag;
 276 }
 277
 278 //*----------------------------------------------------------------------------
 279 //* \fn    AT91F_DBGU_InterruptDisable
 280 //* \brief Disable DBGU Interrupt
 281 //*----------------------------------------------------------------------------
 282 __inline void AT91F_DBGU_InterruptDisable(
 283         AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
 284         unsigned int flag) // \arg  dbgu interrupt to be disabled
 285 {
 286         pDbgu->DBGU_IDR = flag;
 287 }
 288
 289 //*----------------------------------------------------------------------------
 290 //* \fn    AT91F_DBGU_GetInterruptMaskStatus
 291 //* \brief Return DBGU Interrupt Mask Status
 292 //*----------------------------------------------------------------------------
 293 __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
 294         AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
 295 {
 296         return pDbgu->DBGU_IMR;
 297 }
 298
 299 //*----------------------------------------------------------------------------
 300 //* \fn    AT91F_DBGU_IsInterruptMasked
 301 //* \brief Test if DBGU Interrupt is Masked
 302 //*----------------------------------------------------------------------------
 303 __inline int AT91F_DBGU_IsInterruptMasked(
 304         AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
 305         unsigned int flag) // \arg  flag to be tested
 306 {
 307         return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
 308 }
 309
 310 /* *****************************************************************************
 311                 SOFTWARE API FOR RTC
 312    ***************************************************************************** */
 313 //*----------------------------------------------------------------------------
 314 //* \fn    AT91F_RTC_InterruptEnable
 315 //* \brief Enable RTC Interrupt
 316 //*----------------------------------------------------------------------------
 317 __inline void AT91F_RTC_InterruptEnable(
 318         AT91PS_RTC pRtc,   // \arg  pointer to a RTC controller
 319         unsigned int flag) // \arg  RTC interrupt to be enabled
 320 {
 321         pRtc->RTC_IER = flag;
 322 }
 323
 324 //*----------------------------------------------------------------------------
 325 //* \fn    AT91F_RTC_InterruptDisable
 326 //* \brief Disable RTC Interrupt
 327 //*----------------------------------------------------------------------------
 328 __inline void AT91F_RTC_InterruptDisable(
 329         AT91PS_RTC pRtc,   // \arg  pointer to a RTC controller
 330         unsigned int flag) // \arg  RTC interrupt to be disabled
 331 {
 332         pRtc->RTC_IDR = flag;
 333 }
 334
 335 //*----------------------------------------------------------------------------
 336 //* \fn    AT91F_RTC_GetInterruptMaskStatus
 337 //* \brief Return RTC Interrupt Mask Status
 338 //*----------------------------------------------------------------------------
 339 __inline unsigned int AT91F_RTC_GetInterruptMaskStatus( // \return RTC Interrupt Mask Status
 340         AT91PS_RTC pRtc) // \arg  pointer to a RTC controller
 341 {
 342         return pRtc->RTC_IMR;
 343 }
 344
 345 //*----------------------------------------------------------------------------
 346 //* \fn    AT91F_RTC_IsInterruptMasked
 347 //* \brief Test if RTC Interrupt is Masked
 348 //*----------------------------------------------------------------------------
 349 __inline int AT91F_RTC_IsInterruptMasked(
 350         AT91PS_RTC pRtc,   // \arg  pointer to a RTC controller
 351         unsigned int flag) // \arg  flag to be tested
 352 {
 353         return (AT91F_RTC_GetInterruptMaskStatus(pRtc) & flag);
 354 }
 355
 356 /* *****************************************************************************
 357                 SOFTWARE API FOR SSC
 358    ***************************************************************************** */
 359 //* Define the standard I2S mode configuration
 360
 361 //* Configuration to set in the SSC Transmit Clock Mode Register
 362 //* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
 363 //*                       nb_slot_by_frame : number of channels
 364 #define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( AT91C_SSC_CKS_DIV + AT91C_SSC_CKO_CONTINOUS + AT91C_SSC_CKG_NONE + AT91C_SSC_START_FALL_RF + AT91C_SSC_STTOUT + ((1<<16) & AT91C_SSC_STTDLY) + (nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
 365
 366 //* Configuration to set in the SSC Transmit Frame Mode Register
 367 //* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
 368 //*                      nb_slot_by_frame : number of channels
 369 #define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)((nb_bit_by_slot-1) + AT91C_SSC_MSBF + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) + AT91C_SSC_FSOS_NEGATIVE)
 370
 371
 372 //*----------------------------------------------------------------------------
 373 //* \fn    AT91F_SSC_SetBaudrate
 374 //* \brief Set the baudrate according to the CPU clock
 375 //*----------------------------------------------------------------------------
 376 __inline void AT91F_SSC_SetBaudrate (
 377         AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
 378         unsigned int mainClock, // \arg peripheral clock
 379         unsigned int speed)     // \arg SSC baudrate
 380 {
 381         unsigned int baud_value;
 382         //* Define the baud rate divisor register
 383         if (speed == 0)
 384            baud_value = 0;
 385         else
 386         {
 387            baud_value = (unsigned int) (mainClock * 10)/(2*speed);
 388            if ((baud_value % 10) >= 5)
 389                   baud_value = (baud_value / 10) + 1;
 390            else
 391                   baud_value /= 10;
 392         }
 393
 394         pSSC->SSC_CMR = baud_value;
 395 }
 396
 397 //*----------------------------------------------------------------------------
 398 //* \fn    AT91F_SSC_Configure
 399 //* \brief Configure SSC
 400 //*----------------------------------------------------------------------------
 401 __inline void AT91F_SSC_Configure (
 402              AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
 403              unsigned int syst_clock,  // \arg System Clock Frequency
 404              unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
 405              unsigned int clock_rx,    // \arg Receiver Clock Parameters
 406              unsigned int mode_rx,     // \arg mode Register to be programmed
 407              unsigned int clock_tx,    // \arg Transmitter Clock Parameters
 408              unsigned int mode_tx)     // \arg mode Register to be programmed
 409 {
 410     //* Disable interrupts
 411         pSSC->SSC_IDR = (unsigned int) -1;
 412
 413     //* Reset receiver and transmitter
 414         pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
 415
 416     //* Define the Clock Mode Register
 417         AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
 418
 419      //* Write the Receive Clock Mode Register
 420         pSSC->SSC_RCMR =  clock_rx;
 421
 422      //* Write the Transmit Clock Mode Register
 423         pSSC->SSC_TCMR =  clock_tx;
 424
 425      //* Write the Receive Frame Mode Register
 426         pSSC->SSC_RFMR =  mode_rx;
 427
 428      //* Write the Transmit Frame Mode Register
 429         pSSC->SSC_TFMR =  mode_tx;
 430
 431     //* Clear Transmit and Receive Counters
 432         AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
 433
 434
 435 }
 436
 437 //*----------------------------------------------------------------------------
 438 //* \fn    AT91F_SSC_EnableRx
 439 //* \brief Enable receiving datas
 440 //*----------------------------------------------------------------------------
 441 __inline void AT91F_SSC_EnableRx (
 442         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
 443 {
 444     //* Enable receiver
 445     pSSC->SSC_CR = AT91C_SSC_RXEN;
 446 }
 447
 448 //*----------------------------------------------------------------------------
 449 //* \fn    AT91F_SSC_DisableRx
 450 //* \brief Disable receiving datas
 451 //*----------------------------------------------------------------------------
 452 __inline void AT91F_SSC_DisableRx (
 453         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
 454 {
 455     //* Disable receiver
 456     pSSC->SSC_CR = AT91C_SSC_RXDIS;
 457 }
 458
 459 //*----------------------------------------------------------------------------
 460 //* \fn    AT91F_SSC_EnableTx
 461 //* \brief Enable sending datas
 462 //*----------------------------------------------------------------------------
 463 __inline void AT91F_SSC_EnableTx (
 464         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
 465 {
 466     //* Enable  transmitter
 467     pSSC->SSC_CR = AT91C_SSC_TXEN;
 468 }
 469
 470 //*----------------------------------------------------------------------------
 471 //* \fn    AT91F_SSC_DisableTx
 472 //* \brief Disable sending datas
 473 //*----------------------------------------------------------------------------
 474 __inline void AT91F_SSC_DisableTx (
 475         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
 476 {
 477     //* Disable  transmitter
 478     pSSC->SSC_CR = AT91C_SSC_TXDIS;
 479 }
 480
 481 //*----------------------------------------------------------------------------
 482 //* \fn    AT91F_SSC_EnableIt
 483 //* \brief Enable SSC IT
 484 //*----------------------------------------------------------------------------
 485 __inline void AT91F_SSC_EnableIt (
 486         AT91PS_SSC pSSC, // \arg pointer to a SSC controller
 487         unsigned int flag)   // \arg IT to be enabled
 488 {
 489         //* Write to the IER register
 490         pSSC->SSC_IER = flag;
 491 }
 492
 493 //*----------------------------------------------------------------------------
 494 //* \fn    AT91F_SSC_DisableIt
 495 //* \brief Disable SSC IT
 496 //*----------------------------------------------------------------------------
 497 __inline void AT91F_SSC_DisableIt (
 498         AT91PS_SSC pSSC, // \arg pointer to a SSC controller
 499         unsigned int flag)   // \arg IT to be disabled
 500 {
 501         //* Write to the IDR register
 502         pSSC->SSC_IDR = flag;
 503 }
 504
 505 //*----------------------------------------------------------------------------
 506 //* \fn    AT91F_SSC_ReceiveFrame
 507 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
 508 //*----------------------------------------------------------------------------
 509 __inline unsigned int AT91F_SSC_ReceiveFrame (
 510         AT91PS_SSC pSSC,
 511         char *pBuffer,
 512         unsigned int szBuffer,
 513         char *pNextBuffer,
 514         unsigned int szNextBuffer )
 515 {
 516         return AT91F_PDC_ReceiveFrame(
 517                 (AT91PS_PDC) &(pSSC->SSC_RPR),
 518                 pBuffer,
 519                 szBuffer,
 520                 pNextBuffer,
 521                 szNextBuffer);
 522 }
 523
 524 //*----------------------------------------------------------------------------
 525 //* \fn    AT91F_SSC_SendFrame
 526 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
 527 //*----------------------------------------------------------------------------
 528 __inline unsigned int AT91F_SSC_SendFrame(
 529         AT91PS_SSC pSSC,
 530         char *pBuffer,
 531         unsigned int szBuffer,
 532         char *pNextBuffer,
 533         unsigned int szNextBuffer )
 534 {
 535         return AT91F_PDC_SendFrame(
 536                 (AT91PS_PDC) &(pSSC->SSC_RPR),
 537                 pBuffer,
 538                 szBuffer,
 539                 pNextBuffer,
 540                 szNextBuffer);
 541 }
 542
 543 //*----------------------------------------------------------------------------
 544 //* \fn    AT91F_SSC_GetInterruptMaskStatus
 545 //* \brief Return SSC Interrupt Mask Status
 546 //*----------------------------------------------------------------------------
 547 __inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
 548         AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
 549 {
 550         return pSsc->SSC_IMR;
 551 }
 552
 553 //*----------------------------------------------------------------------------
 554 //* \fn    AT91F_SSC_IsInterruptMasked
 555 //* \brief Test if SSC Interrupt is Masked
 556 //*----------------------------------------------------------------------------
 557 __inline int AT91F_SSC_IsInterruptMasked(
 558         AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
 559         unsigned int flag) // \arg  flag to be tested
 560 {
 561         return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
 562 }
 563
 564 /* *****************************************************************************
 565                 SOFTWARE API FOR SPI
 566    ***************************************************************************** */
 567 //*----------------------------------------------------------------------------
 568 //* \fn    AT91F_SPI_Open
 569 //* \brief Open a SPI Port
 570 //*----------------------------------------------------------------------------
 571 __inline unsigned int AT91F_SPI_Open (
 572         const unsigned int null)  // \arg
 573 {
 574         /* NOT DEFINED AT THIS MOMENT */
 575         return ( 0 );
 576 }
 577
 578 //*----------------------------------------------------------------------------
 579 //* \fn    AT91F_SPI_CfgCs
 580 //* \brief Configure SPI chip select register
 581 //*----------------------------------------------------------------------------
 582 __inline void AT91F_SPI_CfgCs (
 583         int cs,     // SPI cs number (0 to 3)
 584         int val)   //  chip select register
 585 {
 586         //* Write to the CSR register
 587         *(AT91C_SPI_CSR + cs) = val;
 588 }
 589
 590 //*----------------------------------------------------------------------------
 591 //* \fn    AT91F_SPI_EnableIt
 592 //* \brief Enable SPI interrupt
 593 //*----------------------------------------------------------------------------
 594 __inline void AT91F_SPI_EnableIt (
 595         AT91PS_SPI pSPI,     // pointer to a SPI controller
 596         unsigned int flag)   // IT to be enabled
 597 {
 598         //* Write to the IER register
 599         pSPI->SPI_IER = flag;
 600 }
 601
 602 //*----------------------------------------------------------------------------
 603 //* \fn    AT91F_SPI_DisableIt
 604 //* \brief Disable SPI interrupt
 605 //*----------------------------------------------------------------------------
 606 __inline void AT91F_SPI_DisableIt (
 607         AT91PS_SPI pSPI, // pointer to a SPI controller
 608         unsigned int flag) // IT to be disabled
 609 {
 610         //* Write to the IDR register
 611         pSPI->SPI_IDR = flag;
 612 }
 613
 614 //*----------------------------------------------------------------------------
 615 //* \fn    AT91F_SPI_Reset
 616 //* \brief Reset the SPI controller
 617 //*----------------------------------------------------------------------------
 618 __inline void AT91F_SPI_Reset (
 619         AT91PS_SPI pSPI // pointer to a SPI controller
 620         )
 621 {
 622         //* Write to the CR register
 623         pSPI->SPI_CR = AT91C_SPI_SWRST;
 624 }
 625
 626 //*----------------------------------------------------------------------------
 627 //* \fn    AT91F_SPI_Enable
 628 //* \brief Enable the SPI controller
 629 //*----------------------------------------------------------------------------
 630 __inline void AT91F_SPI_Enable (
 631         AT91PS_SPI pSPI // pointer to a SPI controller
 632         )
 633 {
 634         //* Write to the CR register
 635         pSPI->SPI_CR = AT91C_SPI_SPIEN;
 636 }
 637
 638 //*----------------------------------------------------------------------------
 639 //* \fn    AT91F_SPI_Disable
 640 //* \brief Disable the SPI controller
 641 //*----------------------------------------------------------------------------
 642 __inline void AT91F_SPI_Disable (
 643         AT91PS_SPI pSPI // pointer to a SPI controller
 644         )
 645 {
 646         //* Write to the CR register
 647         pSPI->SPI_CR = AT91C_SPI_SPIDIS;
 648 }
 649
 650 //*----------------------------------------------------------------------------
 651 //* \fn    AT91F_SPI_CfgMode
 652 //* \brief Enable the SPI controller
 653 //*----------------------------------------------------------------------------
 654 __inline void AT91F_SPI_CfgMode (
 655         AT91PS_SPI pSPI, // pointer to a SPI controller
 656         int mode)        // mode register
 657 {
 658         //* Write to the MR register
 659         pSPI->SPI_MR = mode;
 660 }
 661
 662 //*----------------------------------------------------------------------------
 663 //* \fn    AT91F_SPI_CfgPCS
 664 //* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
 665 //*----------------------------------------------------------------------------
 666 __inline void AT91F_SPI_CfgPCS (
 667         AT91PS_SPI pSPI, // pointer to a SPI controller
 668         char PCS_Device) // PCS of the Device
 669 {
 670         //* Write to the MR register
 671         pSPI->SPI_MR &= 0xFFF0FFFF;
 672         pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
 673 }
 674
 675 //*----------------------------------------------------------------------------
 676 //* \fn    AT91F_SPI_ReceiveFrame
 677 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
 678 //*----------------------------------------------------------------------------
 679 __inline unsigned int AT91F_SPI_ReceiveFrame (
 680         AT91PS_SPI pSPI,
 681         char *pBuffer,
 682         unsigned int szBuffer,
 683         char *pNextBuffer,
 684         unsigned int szNextBuffer )
 685 {
 686         return AT91F_PDC_ReceiveFrame(
 687                 (AT91PS_PDC) &(pSPI->SPI_RPR),
 688                 pBuffer,
 689                 szBuffer,
 690                 pNextBuffer,
 691                 szNextBuffer);
 692 }
 693
 694 //*----------------------------------------------------------------------------
 695 //* \fn    AT91F_SPI_SendFrame
 696 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
 697 //*----------------------------------------------------------------------------
 698 __inline unsigned int AT91F_SPI_SendFrame(
 699         AT91PS_SPI pSPI,
 700         char *pBuffer,
 701         unsigned int szBuffer,
 702         char *pNextBuffer,
 703         unsigned int szNextBuffer )
 704 {
 705         return AT91F_PDC_SendFrame(
 706                 (AT91PS_PDC) &(pSPI->SPI_RPR),
 707                 pBuffer,
 708                 szBuffer,
 709                 pNextBuffer,
 710                 szNextBuffer);
 711 }
 712
 713 //*----------------------------------------------------------------------------
 714 //* \fn    AT91F_SPI_Close
 715 //* \brief Close SPI: disable IT disable transfert, close PDC
 716 //*----------------------------------------------------------------------------
 717 __inline void AT91F_SPI_Close (
 718         AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
 719 {
 720     //* Reset all the Chip Select register
 721     pSPI->SPI_CSR[0] = 0 ;
 722     pSPI->SPI_CSR[1] = 0 ;
 723     pSPI->SPI_CSR[2] = 0 ;
 724     pSPI->SPI_CSR[3] = 0 ;
 725
 726     //* Reset the SPI mode
 727     pSPI->SPI_MR = 0  ;
 728
 729     //* Disable all interrupts
 730     pSPI->SPI_IDR = 0xFFFFFFFF ;
 731
 732     //* Abort the Peripheral Data Transfers
 733     AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
 734
 735     //* Disable receiver and transmitter and stop any activity immediately
 736     pSPI->SPI_CR = AT91C_SPI_SPIDIS;
 737 }
 738
 739 //*----------------------------------------------------------------------------
 740 //* \fn    AT91F_SPI_PutChar
 741 //* \brief Send a character,does not check if ready to send
 742 //*----------------------------------------------------------------------------
 743 __inline void AT91F_SPI_PutChar (
 744         AT91PS_SPI pSPI,
 745         unsigned int character,
 746              unsigned int cs_number )
 747 {
 748     unsigned int value_for_cs;
 749     value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
 750     pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
 751 }
 752
 753 //*----------------------------------------------------------------------------
 754 //* \fn    AT91F_SPI_GetChar
 755 //* \brief Receive a character,does not check if a character is available
 756 //*----------------------------------------------------------------------------
 757 __inline int AT91F_SPI_GetChar (
 758         const AT91PS_SPI pSPI)
 759 {
 760     return((pSPI->SPI_RDR) & 0xFFFF);
 761 }
 762
 763 //*----------------------------------------------------------------------------
 764 //* \fn    AT91F_SPI_GetInterruptMaskStatus
 765 //* \brief Return SPI Interrupt Mask Status
 766 //*----------------------------------------------------------------------------
 767 __inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
 768         AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
 769 {
 770         return pSpi->SPI_IMR;
 771 }
 772
 773 //*----------------------------------------------------------------------------
 774 //* \fn    AT91F_SPI_IsInterruptMasked
 775 //* \brief Test if SPI Interrupt is Masked
 776 //*----------------------------------------------------------------------------
 777 __inline int AT91F_SPI_IsInterruptMasked(
 778         AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
 779         unsigned int flag) // \arg  flag to be tested
 780 {
 781         return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
 782 }
 783
 784 /* *****************************************************************************
 785                 SOFTWARE API FOR TC
 786    ***************************************************************************** */
 787 //*----------------------------------------------------------------------------
 788 //* \fn    AT91F_TC_InterruptEnable
 789 //* \brief Enable TC Interrupt
 790 //*----------------------------------------------------------------------------
 791 __inline void AT91F_TC_InterruptEnable(
 792         AT91PS_TC pTc,   // \arg  pointer to a TC controller
 793         unsigned int flag) // \arg  TC interrupt to be enabled
 794 {
 795         pTc->TC_IER = flag;
 796 }
 797
 798 //*----------------------------------------------------------------------------
 799 //* \fn    AT91F_TC_InterruptDisable
 800 //* \brief Disable TC Interrupt
 801 //*----------------------------------------------------------------------------
 802 __inline void AT91F_TC_InterruptDisable(
 803         AT91PS_TC pTc,   // \arg  pointer to a TC controller
 804         unsigned int flag) // \arg  TC interrupt to be disabled
 805 {
 806         pTc->TC_IDR = flag;
 807 }
 808
 809 //*----------------------------------------------------------------------------
 810 //* \fn    AT91F_TC_GetInterruptMaskStatus
 811 //* \brief Return TC Interrupt Mask Status
 812 //*----------------------------------------------------------------------------
 813 __inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
 814         AT91PS_TC pTc) // \arg  pointer to a TC controller
 815 {
 816         return pTc->TC_IMR;
 817 }
 818
 819 //*----------------------------------------------------------------------------
 820 //* \fn    AT91F_TC_IsInterruptMasked
 821 //* \brief Test if TC Interrupt is Masked
 822 //*----------------------------------------------------------------------------
 823 __inline int AT91F_TC_IsInterruptMasked(
 824         AT91PS_TC pTc,   // \arg  pointer to a TC controller
 825         unsigned int flag) // \arg  flag to be tested
 826 {
 827         return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
 828 }
 829
 830 /* *****************************************************************************
 831                 SOFTWARE API FOR PMC
 832    ***************************************************************************** */
 833 //*----------------------------------------------------------------------------
 834 //* \fn    AT91F_CKGR_GetMainClock
 835 //* \brief Return Main clock in Hz
 836 //*----------------------------------------------------------------------------
 837 __inline unsigned int AT91F_CKGR_GetMainClock (
 838         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
 839         unsigned int slowClock)  // \arg slowClock in Hz
 840 {
 841         return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
 842 }
 843
 844 //*----------------------------------------------------------------------------
 845 //* \fn    AT91F_PMC_GetProcessorClock
 846 //* \brief Return processor clock in Hz (for AT91RM3400 and AT91RM9200)
 847 //*----------------------------------------------------------------------------
 848 __inline unsigned int AT91F_PMC_GetProcessorClock (
 849         AT91PS_PMC pPMC, // \arg pointer to PMC controller
 850         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
 851         unsigned int slowClock)  // \arg slowClock in Hz
 852 {
 853         unsigned int reg = pPMC->PMC_MCKR;
 854         unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
 855         unsigned int pllDivider, pllMultiplier;
 856
 857         switch (reg & AT91C_PMC_CSS) {
 858                 case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
 859                         return slowClock / prescaler;
 860                 case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
 861                         return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
 862                 case AT91C_PMC_CSS_PLLA_CLK: // PLLA clock is selected
 863                         reg = pCKGR->CKGR_PLLAR;
 864                         pllDivider    = (reg  & AT91C_CKGR_DIVA);
 865                         pllMultiplier = ((reg  & AT91C_CKGR_MULA) >> 16) + 1;
 866                         if (reg & AT91C_CKGR_SRCA) // Source is Main clock
 867                                 return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
 868                         else                       // Source is Slow clock
 869                                 return slowClock / pllDivider * pllMultiplier / prescaler;
 870                 case AT91C_PMC_CSS_PLLB_CLK: // PLLB clock is selected
 871                         reg = pCKGR->CKGR_PLLBR;
 872                         pllDivider    = (reg  & AT91C_CKGR_DIVB);
 873                         pllMultiplier = ((reg  & AT91C_CKGR_MULB) >> 16) + 1;
 874                         return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
 875         }
 876         return 0;
 877 }
 878
 879 //*----------------------------------------------------------------------------
 880 //* \fn    AT91F_PMC_GetMasterClock
 881 //* \brief Return master clock in Hz (just for AT91RM9200)
 882 //*----------------------------------------------------------------------------
 883 __inline unsigned int AT91F_PMC_GetMasterClock (
 884         AT91PS_PMC pPMC, // \arg pointer to PMC controller
 885         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
 886         unsigned int slowClock)  // \arg slowClock in Hz
 887 {
 888         return AT91F_PMC_GetProcessorClock(pPMC, pCKGR, slowClock) /
 889                 (((pPMC->PMC_MCKR & AT91C_PMC_MDIV) >> 8)+1);
 890 }
 891
 892 //*----------------------------------------------------------------------------
 893 //* \fn    AT91F_PMC_EnablePeriphClock
 894 //* \brief Enable peripheral clock
 895 //*----------------------------------------------------------------------------
 896 __inline void AT91F_PMC_EnablePeriphClock (
 897         AT91PS_PMC pPMC, // \arg pointer to PMC controller
 898         unsigned int periphIds)  // \arg IDs of peripherals to enable
 899 {
 900         pPMC->PMC_PCER = periphIds;
 901 }
 902
 903 //*----------------------------------------------------------------------------
 904 //* \fn    AT91F_PMC_DisablePeriphClock
 905 //* \brief Enable peripheral clock
 906 //*----------------------------------------------------------------------------
 907 __inline void AT91F_PMC_DisablePeriphClock (
 908         AT91PS_PMC pPMC, // \arg pointer to PMC controller
 909         unsigned int periphIds)  // \arg IDs of peripherals to enable
 910 {
 911         pPMC->PMC_PCDR = periphIds;
 912 }
 913
 914 //*----------------------------------------------------------------------------
 915 //* \fn    AT91F_PMC_EnablePCK
 916 //* \brief Enable peripheral clock
 917 //*----------------------------------------------------------------------------
 918 __inline void AT91F_PMC_EnablePCK (
 919         AT91PS_PMC pPMC, // \arg pointer to PMC controller
 920         unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
 921         unsigned int ccs,  // \arg clock selection: AT91C_PMC_CSS_SLOW_CLK, AT91C_PMC_CSS_MAIN_CLK, AT91C_PMC_CSS_PLLA_CLK, AT91C_PMC_CSS_PLLB_CLK
 922         unsigned int pres) // \arg Programmable clock prescalar AT91C_PMC_PRES_CLK, AT91C_PMC_PRES_CLK_2, ..., AT91C_PMC_PRES_CLK_64
 923 {
 924         pPMC->PMC_PCKR[pck] = ccs | pres;
 925         pPMC->PMC_SCER = (1 << pck) << 8;
 926 }
 927
 928 //*----------------------------------------------------------------------------
 929 //* \fn    AT91F_PMC_DisablePCK
 930 //* \brief Enable peripheral clock
 931 //*----------------------------------------------------------------------------
 932 __inline void AT91F_PMC_DisablePCK (
 933         AT91PS_PMC pPMC, // \arg pointer to PMC controller
 934         unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
 935 {
 936         pPMC->PMC_SCDR = (1 << pck) << 8;
 937 }
 938
 939 /* *****************************************************************************
 940                 SOFTWARE API FOR PIO
 941    ***************************************************************************** */
 942 //*----------------------------------------------------------------------------
 943 //* \fn    AT91F_PIO_CfgPeriph
 944 //* \brief Enable pins to be drived by peripheral
 945 //*----------------------------------------------------------------------------
 946 __inline void AT91F_PIO_CfgPeriph(
 947         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 948         unsigned int periphAEnable,  // \arg PERIPH A to enable
 949         unsigned int periphBEnable)  // \arg PERIPH B to enable
 950
 951 {
 952         pPio->PIO_ASR = periphAEnable;
 953         pPio->PIO_BSR = periphBEnable;
 954         pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
 955 }
 956
 957 //*----------------------------------------------------------------------------
 958 //* \fn    AT91F_PIO_CfgOutput
 959 //* \brief Enable PIO in output mode
 960 //*----------------------------------------------------------------------------
 961 __inline void AT91F_PIO_CfgOutput(
 962         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 963         unsigned int pioEnable)      // \arg PIO to be enabled
 964 {
 965         pPio->PIO_PER = pioEnable; // Set in PIO mode
 966         pPio->PIO_OER = pioEnable; // Configure in Output
 967 }
 968
 969 //*----------------------------------------------------------------------------
 970 //* \fn    AT91F_PIO_CfgInput
 971 //* \brief Enable PIO in input mode
 972 //*----------------------------------------------------------------------------
 973 __inline void AT91F_PIO_CfgInput(
 974         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 975         unsigned int inputEnable)      // \arg PIO to be enabled
 976 {
 977         // Disable output
 978         pPio->PIO_ODR  = inputEnable;
 979         pPio->PIO_PER  = inputEnable;
 980 }
 981
 982 //*----------------------------------------------------------------------------
 983 //* \fn    AT91F_PIO_CfgOpendrain
 984 //* \brief Configure PIO in open drain
 985 //*----------------------------------------------------------------------------
 986 __inline void AT91F_PIO_CfgOpendrain(
 987         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 988         unsigned int multiDrvEnable) // \arg pio to be configured in open drain
 989 {
 990         // Configure the multi-drive option
 991         pPio->PIO_MDDR = ~multiDrvEnable;
 992         pPio->PIO_MDER = multiDrvEnable;
 993 }
 994
 995 //*----------------------------------------------------------------------------
 996 //* \fn    AT91F_PIO_CfgPullup
 997 //* \brief Enable pullup on PIO
 998 //*----------------------------------------------------------------------------
 999 __inline void AT91F_PIO_CfgPullup(
1000         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
1001         unsigned int pullupEnable)   // \arg enable pullup on PIO
1002 {
1003                 // Connect or not Pullup
1004         pPio->PIO_PPUDR = ~pullupEnable;
1005         pPio->PIO_PPUER = pullupEnable;
1006 }
1007
1008 //*----------------------------------------------------------------------------
1009 //* \fn    AT91F_PIO_CfgDirectDrive
1010 //* \brief Enable direct drive on PIO
1011 //*----------------------------------------------------------------------------
1012 __inline void AT91F_PIO_CfgDirectDrive(
1013         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
1014         unsigned int directDrive)    // \arg PIO to be configured with direct drive
1015
1016 {
1017         // Configure the Direct Drive
1018         pPio->PIO_OWDR  = ~directDrive;
1019         pPio->PIO_OWER  = directDrive;
1020 }
1021
1022 //*----------------------------------------------------------------------------
1023 //* \fn    AT91F_PIO_CfgInputFilter
1024 //* \brief Enable input filter on input PIO
1025 //*----------------------------------------------------------------------------
1026 __inline void AT91F_PIO_CfgInputFilter(
1027         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
1028         unsigned int inputFilter)    // \arg PIO to be configured with input filter
1029
1030 {
1031         // Configure the Direct Drive
1032         pPio->PIO_IFDR  = ~inputFilter;
1033         pPio->PIO_IFER  = inputFilter;
1034 }
1035
1036 //*----------------------------------------------------------------------------
1037 //* \fn    AT91F_PIO_GetInput
1038 //* \brief Return PIO input value
1039 //*----------------------------------------------------------------------------
1040 __inline unsigned int AT91F_PIO_GetInput( // \return PIO input
1041         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1042 {
1043         return pPio->PIO_PDSR;
1044 }
1045
1046 //*----------------------------------------------------------------------------
1047 //* \fn    AT91F_PIO_IsInputSet
1048 //* \brief Test if PIO is input flag is active
1049 //*----------------------------------------------------------------------------
1050 __inline int AT91F_PIO_IsInputSet(
1051         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1052         unsigned int flag) // \arg  flag to be tested
1053 {
1054         return (AT91F_PIO_GetInput(pPio) & flag);
1055 }
1056
1057
1058 //*----------------------------------------------------------------------------
1059 //* \fn    AT91F_PIO_SetOutput
1060 //* \brief Set to 1 output PIO
1061 //*----------------------------------------------------------------------------
1062 __inline void AT91F_PIO_SetOutput(
1063         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1064         unsigned int flag) // \arg  output to be set
1065 {
1066         pPio->PIO_SODR = flag;
1067 }
1068
1069 //*----------------------------------------------------------------------------
1070 //* \fn    AT91F_PIO_ClearOutput
1071 //* \brief Set to 0 output PIO
1072 //*----------------------------------------------------------------------------
1073 __inline void AT91F_PIO_ClearOutput(
1074         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1075         unsigned int flag) // \arg  output to be cleared
1076 {
1077         pPio->PIO_CODR = flag;
1078 }
1079
1080 //*----------------------------------------------------------------------------
1081 //* \fn    AT91F_PIO_ForceOutput
1082 //* \brief Force output when Direct drive option is enabled
1083 //*----------------------------------------------------------------------------
1084 __inline void AT91F_PIO_ForceOutput(
1085         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1086         unsigned int flag) // \arg  output to be forced
1087 {
1088         pPio->PIO_ODSR = flag;
1089 }
1090
1091 //*----------------------------------------------------------------------------
1092 //* \fn    AT91F_PIO_Enable
1093 //* \brief Enable PIO
1094 //*----------------------------------------------------------------------------
1095 __inline void AT91F_PIO_Enable(
1096         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1097         unsigned int flag) // \arg  pio to be enabled
1098 {
1099         pPio->PIO_PER = flag;
1100 }
1101
1102 //*----------------------------------------------------------------------------
1103 //* \fn    AT91F_PIO_Disable
1104 //* \brief Disable PIO
1105 //*----------------------------------------------------------------------------
1106 __inline void AT91F_PIO_Disable(
1107         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1108         unsigned int flag) // \arg  pio to be disabled
1109 {
1110         pPio->PIO_PDR = flag;
1111 }
1112
1113 //*----------------------------------------------------------------------------
1114 //* \fn    AT91F_PIO_GetStatus
1115 //* \brief Return PIO Status
1116 //*----------------------------------------------------------------------------
1117 __inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
1118         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1119 {
1120         return pPio->PIO_PSR;
1121 }
1122
1123 //*----------------------------------------------------------------------------
1124 //* \fn    AT91F_PIO_IsSet
1125 //* \brief Test if PIO is Set
1126 //*----------------------------------------------------------------------------
1127 __inline int AT91F_PIO_IsSet(
1128         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1129         unsigned int flag) // \arg  flag to be tested
1130 {
1131         return (AT91F_PIO_GetStatus(pPio) & flag);
1132 }
1133
1134 //*----------------------------------------------------------------------------
1135 //* \fn    AT91F_PIO_OutputEnable
1136 //* \brief Output Enable PIO
1137 //*----------------------------------------------------------------------------
1138 __inline void AT91F_PIO_OutputEnable(
1139         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1140         unsigned int flag) // \arg  pio output to be enabled
1141 {
1142         pPio->PIO_OER = flag;
1143 }
1144
1145 //*----------------------------------------------------------------------------
1146 //* \fn    AT91F_PIO_OutputDisable
1147 //* \brief Output Enable PIO
1148 //*----------------------------------------------------------------------------
1149 __inline void AT91F_PIO_OutputDisable(
1150         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1151         unsigned int flag) // \arg  pio output to be disabled
1152 {
1153         pPio->PIO_ODR = flag;
1154 }
1155
1156 //*----------------------------------------------------------------------------
1157 //* \fn    AT91F_PIO_GetOutputStatus
1158 //* \brief Return PIO Output Status
1159 //*----------------------------------------------------------------------------
1160 __inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
1161         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1162 {
1163         return pPio->PIO_OSR;
1164 }
1165
1166 //*----------------------------------------------------------------------------
1167 //* \fn    AT91F_PIO_IsOuputSet
1168 //* \brief Test if PIO Output is Set
1169 //*----------------------------------------------------------------------------
1170 __inline int AT91F_PIO_IsOutputSet(
1171         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1172         unsigned int flag) // \arg  flag to be tested
1173 {
1174         return (AT91F_PIO_GetOutputStatus(pPio) & flag);
1175 }
1176
1177 //*----------------------------------------------------------------------------
1178 //* \fn    AT91F_PIO_InputFilterEnable
1179 //* \brief Input Filter Enable PIO
1180 //*----------------------------------------------------------------------------
1181 __inline void AT91F_PIO_InputFilterEnable(
1182         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1183         unsigned int flag) // \arg  pio input filter to be enabled
1184 {
1185         pPio->PIO_IFER = flag;
1186 }
1187
1188 //*----------------------------------------------------------------------------
1189 //* \fn    AT91F_PIO_InputFilterDisable
1190 //* \brief Input Filter Disable PIO
1191 //*----------------------------------------------------------------------------
1192 __inline void AT91F_PIO_InputFilterDisable(
1193         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1194         unsigned int flag) // \arg  pio input filter to be disabled
1195 {
1196         pPio->PIO_IFDR = flag;
1197 }
1198
1199 //*----------------------------------------------------------------------------
1200 //* \fn    AT91F_PIO_GetInputFilterStatus
1201 //* \brief Return PIO Input Filter Status
1202 //*----------------------------------------------------------------------------
1203 __inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
1204         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1205 {
1206         return pPio->PIO_IFSR;
1207 }
1208
1209 //*----------------------------------------------------------------------------
1210 //* \fn    AT91F_PIO_IsInputFilterSet
1211 //* \brief Test if PIO Input filter is Set
1212 //*----------------------------------------------------------------------------
1213 __inline int AT91F_PIO_IsInputFilterSet(
1214         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1215         unsigned int flag) // \arg  flag to be tested
1216 {
1217         return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
1218 }
1219
1220 //*----------------------------------------------------------------------------
1221 //* \fn    AT91F_PIO_GetOutputDataStatus
1222 //* \brief Return PIO Output Data Status
1223 //*----------------------------------------------------------------------------
1224 __inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
1225         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1226 {
1227         return pPio->PIO_ODSR;
1228 }
1229
1230 //*----------------------------------------------------------------------------
1231 //* \fn    AT91F_PIO_InterruptEnable
1232 //* \brief Enable PIO Interrupt
1233 //*----------------------------------------------------------------------------
1234 __inline void AT91F_PIO_InterruptEnable(
1235         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1236         unsigned int flag) // \arg  pio interrupt to be enabled
1237 {
1238         pPio->PIO_IER = flag;
1239 }
1240
1241 //*----------------------------------------------------------------------------
1242 //* \fn    AT91F_PIO_InterruptDisable
1243 //* \brief Disable PIO Interrupt
1244 //*----------------------------------------------------------------------------
1245 __inline void AT91F_PIO_InterruptDisable(
1246         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1247         unsigned int flag) // \arg  pio interrupt to be disabled
1248 {
1249         pPio->PIO_IDR = flag;
1250 }
1251
1252 //*----------------------------------------------------------------------------
1253 //* \fn    AT91F_PIO_GetInterruptMaskStatus
1254 //* \brief Return PIO Interrupt Mask Status
1255 //*----------------------------------------------------------------------------
1256 __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
1257         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1258 {
1259         return pPio->PIO_IMR;
1260 }
1261
1262 //*----------------------------------------------------------------------------
1263 //* \fn    AT91F_PIO_GetInterruptStatus
1264 //* \brief Return PIO Interrupt Status
1265 //*----------------------------------------------------------------------------
1266 __inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
1267         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1268 {
1269         return pPio->PIO_ISR;
1270 }
1271
1272 //*----------------------------------------------------------------------------
1273 //* \fn    AT91F_PIO_IsInterruptMasked
1274 //* \brief Test if PIO Interrupt is Masked
1275 //*----------------------------------------------------------------------------
1276 __inline int AT91F_PIO_IsInterruptMasked(
1277         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1278         unsigned int flag) // \arg  flag to be tested
1279 {
1280         return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
1281 }
1282
1283 //*----------------------------------------------------------------------------
1284 //* \fn    AT91F_PIO_IsInterruptSet
1285 //* \brief Test if PIO Interrupt is Set
1286 //*----------------------------------------------------------------------------
1287 __inline int AT91F_PIO_IsInterruptSet(
1288         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1289         unsigned int flag) // \arg  flag to be tested
1290 {
1291         return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
1292 }
1293
1294 //*----------------------------------------------------------------------------
1295 //* \fn    AT91F_PIO_MultiDriverEnable
1296 //* \brief Multi Driver Enable PIO
1297 //*----------------------------------------------------------------------------
1298 __inline void AT91F_PIO_MultiDriverEnable(
1299         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1300         unsigned int flag) // \arg  pio to be enabled
1301 {
1302         pPio->PIO_MDER = flag;
1303 }
1304
1305 //*----------------------------------------------------------------------------
1306 //* \fn    AT91F_PIO_MultiDriverDisable
1307 //* \brief Multi Driver Disable PIO
1308 //*----------------------------------------------------------------------------
1309 __inline void AT91F_PIO_MultiDriverDisable(
1310         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1311         unsigned int flag) // \arg  pio to be disabled
1312 {
1313         pPio->PIO_MDDR = flag;
1314 }
1315
1316 //*----------------------------------------------------------------------------
1317 //* \fn    AT91F_PIO_GetMultiDriverStatus
1318 //* \brief Return PIO Multi Driver Status
1319 //*----------------------------------------------------------------------------
1320 __inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
1321         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1322 {
1323         return pPio->PIO_MDSR;
1324 }
1325
1326 //*----------------------------------------------------------------------------
1327 //* \fn    AT91F_PIO_IsMultiDriverSet
1328 //* \brief Test if PIO MultiDriver is Set
1329 //*----------------------------------------------------------------------------
1330 __inline int AT91F_PIO_IsMultiDriverSet(
1331         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1332         unsigned int flag) // \arg  flag to be tested
1333 {
1334         return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
1335 }
1336
1337 //*----------------------------------------------------------------------------
1338 //* \fn    AT91F_PIO_A_RegisterSelection
1339 //* \brief PIO A Register Selection
1340 //*----------------------------------------------------------------------------
1341 __inline void AT91F_PIO_A_RegisterSelection(
1342         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1343         unsigned int flag) // \arg  pio A register selection
1344 {
1345         pPio->PIO_ASR = flag;
1346 }
1347
1348 //*----------------------------------------------------------------------------
1349 //* \fn    AT91F_PIO_B_RegisterSelection
1350 //* \brief PIO B Register Selection
1351 //*----------------------------------------------------------------------------
1352 __inline void AT91F_PIO_B_RegisterSelection(
1353         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1354         unsigned int flag) // \arg  pio B register selection
1355 {
1356         pPio->PIO_BSR = flag;
1357 }
1358
1359 //*----------------------------------------------------------------------------
1360 //* \fn    AT91F_PIO_Get_AB_RegisterStatus
1361 //* \brief Return PIO Interrupt Status
1362 //*----------------------------------------------------------------------------
1363 __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
1364         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1365 {
1366         return pPio->PIO_ABSR;
1367 }
1368
1369 //*----------------------------------------------------------------------------
1370 //* \fn    AT91F_PIO_IsAB_RegisterSet
1371 //* \brief Test if PIO AB Register is Set
1372 //*----------------------------------------------------------------------------
1373 __inline int AT91F_PIO_IsAB_RegisterSet(
1374         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1375         unsigned int flag) // \arg  flag to be tested
1376 {
1377         return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
1378 }
1379
1380 //*----------------------------------------------------------------------------
1381 //* \fn    AT91F_PIO_OutputWriteEnable
1382 //* \brief Output Write Enable PIO
1383 //*----------------------------------------------------------------------------
1384 __inline void AT91F_PIO_OutputWriteEnable(
1385         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1386         unsigned int flag) // \arg  pio output write to be enabled
1387 {
1388         pPio->PIO_OWER = flag;
1389 }
1390
1391 //*----------------------------------------------------------------------------
1392 //* \fn    AT91F_PIO_OutputWriteDisable
1393 //* \brief Output Write Disable PIO
1394 //*----------------------------------------------------------------------------
1395 __inline void AT91F_PIO_OutputWriteDisable(
1396         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1397         unsigned int flag) // \arg  pio output write to be disabled
1398 {
1399         pPio->PIO_OWDR = flag;
1400 }
1401
1402 //*----------------------------------------------------------------------------
1403 //* \fn    AT91F_PIO_GetOutputWriteStatus
1404 //* \brief Return PIO Output Write Status
1405 //*----------------------------------------------------------------------------
1406 __inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
1407         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1408 {
1409         return pPio->PIO_OWSR;
1410 }
1411
1412 //*----------------------------------------------------------------------------
1413 //* \fn    AT91F_PIO_IsOutputWriteSet
1414 //* \brief Test if PIO OutputWrite is Set
1415 //*----------------------------------------------------------------------------
1416 __inline int AT91F_PIO_IsOutputWriteSet(
1417         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1418         unsigned int flag) // \arg  flag to be tested
1419 {
1420         return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
1421 }
1422
1423 //*----------------------------------------------------------------------------
1424 //* \fn    AT91F_PIO_GetCfgPullup
1425 //* \brief Return PIO Configuration Pullup
1426 //*----------------------------------------------------------------------------
1427 __inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
1428         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1429 {
1430         return pPio->PIO_PPUSR;
1431 }
1432
1433 //*----------------------------------------------------------------------------
1434 //* \fn    AT91F_PIO_IsOutputDataStatusSet
1435 //* \brief Test if PIO Output Data Status is Set
1436 //*----------------------------------------------------------------------------
1437 __inline int AT91F_PIO_IsOutputDataStatusSet(
1438         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1439         unsigned int flag) // \arg  flag to be tested
1440 {
1441         return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
1442 }
1443
1444 //*----------------------------------------------------------------------------
1445 //* \fn    AT91F_PIO_IsCfgPullupStatusSet
1446 //* \brief Test if PIO Configuration Pullup Status is Set
1447 //*----------------------------------------------------------------------------
1448 __inline int AT91F_PIO_IsCfgPullupStatusSet(
1449         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1450         unsigned int flag) // \arg  flag to be tested
1451 {
1452         return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
1453 }
1454
1455 /* *****************************************************************************
1456                 SOFTWARE API FOR TWI
1457    ***************************************************************************** */
1458 //*----------------------------------------------------------------------------
1459 //* \fn    AT91F_TWI_EnableIt
1460 //* \brief Enable TWI IT
1461 //*----------------------------------------------------------------------------
1462 __inline void AT91F_TWI_EnableIt (
1463         AT91PS_TWI pTWI, // \arg pointer to a TWI controller
1464         unsigned int flag)   // \arg IT to be enabled
1465 {
1466         //* Write to the IER register
1467         pTWI->TWI_IER = flag;
1468 }
1469
1470 //*----------------------------------------------------------------------------
1471 //* \fn    AT91F_TWI_DisableIt
1472 //* \brief Disable TWI IT
1473 //*----------------------------------------------------------------------------
1474 __inline void AT91F_TWI_DisableIt (
1475         AT91PS_TWI pTWI, // \arg pointer to a TWI controller
1476         unsigned int flag)   // \arg IT to be disabled
1477 {
1478         //* Write to the IDR register
1479         pTWI->TWI_IDR = flag;
1480 }
1481
1482 //*----------------------------------------------------------------------------
1483 //* \fn    AT91F_TWI_Configure
1484 //* \brief Configure TWI in master mode
1485 //*----------------------------------------------------------------------------
1486 __inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
1487 {
1488     //* Disable interrupts
1489         pTWI->TWI_IDR = (unsigned int) -1;
1490
1491     //* Reset peripheral
1492         pTWI->TWI_CR = AT91C_TWI_SWRST;
1493
1494         //* Set Master mode
1495         pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
1496
1497 }
1498
1499 //*----------------------------------------------------------------------------
1500 //* \fn    AT91F_TWI_GetInterruptMaskStatus
1501 //* \brief Return TWI Interrupt Mask Status
1502 //*----------------------------------------------------------------------------
1503 __inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
1504         AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
1505 {
1506         return pTwi->TWI_IMR;
1507 }
1508
1509 //*----------------------------------------------------------------------------
1510 //* \fn    AT91F_TWI_IsInterruptMasked
1511 //* \brief Test if TWI Interrupt is Masked
1512 //*----------------------------------------------------------------------------
1513 __inline int AT91F_TWI_IsInterruptMasked(
1514         AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
1515         unsigned int flag) // \arg  flag to be tested
1516 {
1517         return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
1518 }
1519
1520 /* *****************************************************************************
1521                 SOFTWARE API FOR USART
1522    ***************************************************************************** */
1523 //*----------------------------------------------------------------------------
1524 //* \fn    AT91F_US_Baudrate
1525 //* \brief Calculate the baudrate
1526 //* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
1527 #define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL + AT91C_US_NBSTOP_1_BIT + AT91C_US_PAR_NONE + AT91C_US_CHRL_8_BITS + AT91C_US_CLKS_CLOCK )
1528
1529 //* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
1530 #define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + AT91C_US_NBSTOP_1_BIT + AT91C_US_PAR_NONE + AT91C_US_CHRL_8_BITS + AT91C_US_CLKS_EXT )
1531
1532 //* Standard Synchronous Mode : 8 bits , 1 stop , no parity
1533 #define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + AT91C_US_USMODE_NORMAL + AT91C_US_NBSTOP_1_BIT + AT91C_US_PAR_NONE + AT91C_US_CHRL_8_BITS + AT91C_US_CLKS_CLOCK )
1534
1535 //* SCK used Label
1536 #define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
1537
1538 //* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
1539 #define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + AT91C_US_CLKS_CLOCK + AT91C_US_NBSTOP_1_BIT + AT91C_US_PAR_EVEN + AT91C_US_CHRL_8_BITS + AT91C_US_CKLO + AT91C_US_OVER)
1540
1541 //* Standard IRDA mode
1542 #define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + AT91C_US_NBSTOP_1_BIT + AT91C_US_PAR_NONE + AT91C_US_CHRL_8_BITS + AT91C_US_CLKS_CLOCK )
1543
1544 //*----------------------------------------------------------------------------
1545 //* \fn    AT91F_US_Baudrate
1546 //* \brief Caluculate baud_value according to the main clock and the baud rate
1547 //*----------------------------------------------------------------------------
1548 __inline unsigned int AT91F_US_Baudrate (
1549         const unsigned int main_clock, // \arg peripheral clock
1550         const unsigned int baud_rate)  // \arg UART baudrate
1551 {
1552         unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
1553         if ((baud_value % 10) >= 5)
1554                 baud_value = (baud_value / 10) + 1;
1555         else
1556                 baud_value /= 10;
1557         return baud_value;
1558 }
1559
1560 //*----------------------------------------------------------------------------
1561 //* \fn    AT91F_US_SetBaudrate
1562 //* \brief Set the baudrate according to the CPU clock
1563 //*----------------------------------------------------------------------------
1564 __inline void AT91F_US_SetBaudrate (
1565         AT91PS_USART pUSART,    // \arg pointer to a USART controller
1566         unsigned int mainClock, // \arg peripheral clock
1567         unsigned int speed)     // \arg UART baudrate
1568 {
1569         //* Define the baud rate divisor register
1570         pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
1571 }
1572
1573 //*----------------------------------------------------------------------------
1574 //* \fn    AT91F_US_SetTimeguard
1575 //* \brief Set USART timeguard
1576 //*----------------------------------------------------------------------------
1577 __inline void AT91F_US_SetTimeguard (
1578         AT91PS_USART pUSART,    // \arg pointer to a USART controller
1579         unsigned int timeguard) // \arg timeguard value
1580 {
1581         //* Write the Timeguard Register
1582         pUSART->US_TTGR = timeguard ;
1583 }
1584
1585 //*----------------------------------------------------------------------------
1586 //* \fn    AT91F_US_EnableIt
1587 //* \brief Enable USART IT
1588 //*----------------------------------------------------------------------------
1589 __inline void AT91F_US_EnableIt (
1590         AT91PS_USART pUSART, // \arg pointer to a USART controller
1591         unsigned int flag)   // \arg IT to be enabled
1592 {
1593         //* Write to the IER register
1594         pUSART->US_IER = flag;
1595 }
1596
1597 //*----------------------------------------------------------------------------
1598 //* \fn    AT91F_US_DisableIt
1599 //* \brief Disable USART IT
1600 //*----------------------------------------------------------------------------
1601 __inline void AT91F_US_DisableIt (
1602         AT91PS_USART pUSART, // \arg pointer to a USART controller
1603         unsigned int flag)   // \arg IT to be disabled
1604 {
1605         //* Write to the IER register
1606         pUSART->US_IDR = flag;
1607 }
1608
1609 //*----------------------------------------------------------------------------
1610 //* \fn    AT91F_US_Configure
1611 //* \brief Configure USART
1612 //*----------------------------------------------------------------------------
1613 __inline void AT91F_US_Configure (
1614         AT91PS_USART pUSART,     // \arg pointer to a USART controller
1615         unsigned int mainClock,  // \arg peripheral clock
1616         unsigned int mode ,      // \arg mode Register to be programmed
1617         unsigned int baudRate ,  // \arg baudrate to be programmed
1618         unsigned int timeguard ) // \arg timeguard to be programmed
1619 {
1620     //* Disable interrupts
1621     pUSART->US_IDR = (unsigned int) -1;
1622
1623     //* Reset receiver and transmitter
1624     pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
1625
1626         //* Define the baud rate divisor register
1627         AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
1628
1629         //* Write the Timeguard Register
1630         AT91F_US_SetTimeguard(pUSART, timeguard);
1631
1632     //* Clear Transmit and Receive Counters
1633     AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
1634
1635     //* Define the USART mode
1636     pUSART->US_MR = mode  ;
1637
1638 }
1639
1640 //*----------------------------------------------------------------------------
1641 //* \fn    AT91F_US_EnableRx
1642 //* \brief Enable receiving characters
1643 //*----------------------------------------------------------------------------
1644 __inline void AT91F_US_EnableRx (
1645         AT91PS_USART pUSART)     // \arg pointer to a USART controller
1646 {
1647     //* Enable receiver
1648     pUSART->US_CR = AT91C_US_RXEN;
1649 }
1650
1651 //*----------------------------------------------------------------------------
1652 //* \fn    AT91F_US_EnableTx
1653 //* \brief Enable sending characters
1654 //*----------------------------------------------------------------------------
1655 __inline void AT91F_US_EnableTx (
1656         AT91PS_USART pUSART)     // \arg pointer to a USART controller
1657 {
1658     //* Enable  transmitter
1659     pUSART->US_CR = AT91C_US_TXEN;
1660 }
1661
1662 //*----------------------------------------------------------------------------
1663 //* \fn    AT91F_US_ResetRx
1664 //* \brief Reset Receiver and re-enable it
1665 //*----------------------------------------------------------------------------
1666 __inline void AT91F_US_ResetRx (
1667         AT91PS_USART pUSART)     // \arg pointer to a USART controller
1668 {
1669         //* Reset receiver
1670         pUSART->US_CR = AT91C_US_RSTRX;
1671     //* Re-Enable receiver
1672     pUSART->US_CR = AT91C_US_RXEN;
1673 }
1674
1675 //*----------------------------------------------------------------------------
1676 //* \fn    AT91F_US_ResetTx
1677 //* \brief Reset Transmitter and re-enable it
1678 //*----------------------------------------------------------------------------
1679 __inline void AT91F_US_ResetTx (
1680         AT91PS_USART pUSART)     // \arg pointer to a USART controller
1681 {
1682         //* Reset transmitter
1683         pUSART->US_CR = AT91C_US_RSTTX;
1684     //* Enable transmitter
1685     pUSART->US_CR = AT91C_US_TXEN;
1686 }
1687
1688 //*----------------------------------------------------------------------------
1689 //* \fn    AT91F_US_DisableRx
1690 //* \brief Disable Receiver
1691 //*----------------------------------------------------------------------------
1692 __inline void AT91F_US_DisableRx (
1693         AT91PS_USART pUSART)     // \arg pointer to a USART controller
1694 {
1695     //* Disable receiver
1696     pUSART->US_CR = AT91C_US_RXDIS;
1697 }
1698
1699 //*----------------------------------------------------------------------------
1700 //* \fn    AT91F_US_DisableTx
1701 //* \brief Disable Transmitter
1702 //*----------------------------------------------------------------------------
1703 __inline void AT91F_US_DisableTx (
1704         AT91PS_USART pUSART)     // \arg pointer to a USART controller
1705 {
1706     //* Disable transmitter
1707     pUSART->US_CR = AT91C_US_TXDIS;
1708 }
1709
1710 //*----------------------------------------------------------------------------
1711 //* \fn    AT91F_US_Close
1712 //* \brief Close USART: disable IT disable receiver and transmitter, close PDC
1713 //*----------------------------------------------------------------------------
1714 __inline void AT91F_US_Close (
1715         AT91PS_USART pUSART)     // \arg pointer to a USART controller
1716 {
1717     //* Reset the baud rate divisor register
1718     pUSART->US_BRGR = 0 ;
1719
1720     //* Reset the USART mode
1721     pUSART->US_MR = 0  ;
1722
1723     //* Reset the Timeguard Register
1724     pUSART->US_TTGR = 0;
1725
1726     //* Disable all interrupts
1727     pUSART->US_IDR = 0xFFFFFFFF ;
1728
1729     //* Abort the Peripheral Data Transfers
1730     AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
1731
1732     //* Disable receiver and transmitter and stop any activity immediately
1733     pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
1734 }
1735
1736 //*----------------------------------------------------------------------------
1737 //* \fn    AT91F_US_TxReady
1738 //* \brief Return 1 if a character can be written in US_THR
1739 //*----------------------------------------------------------------------------
1740 __inline unsigned int AT91F_US_TxReady (
1741         AT91PS_USART pUSART )     // \arg pointer to a USART controller
1742 {
1743     return (pUSART->US_CSR & AT91C_US_TXRDY);
1744 }
1745
1746 //*----------------------------------------------------------------------------
1747 //* \fn    AT91F_US_RxReady
1748 //* \brief Return 1 if a character can be read in US_RHR
1749 //*----------------------------------------------------------------------------
1750 __inline unsigned int AT91F_US_RxReady (
1751         AT91PS_USART pUSART )     // \arg pointer to a USART controller
1752 {
1753     return (pUSART->US_CSR & AT91C_US_RXRDY);
1754 }
1755
1756 //*----------------------------------------------------------------------------
1757 //* \fn    AT91F_US_Error
1758 //* \brief Return the error flag
1759 //*----------------------------------------------------------------------------
1760 __inline unsigned int AT91F_US_Error (
1761         AT91PS_USART pUSART )     // \arg pointer to a USART controller
1762 {
1763     return (pUSART->US_CSR &
1764         (AT91C_US_OVRE |  // Overrun error
1765          AT91C_US_FRAME | // Framing error
1766          AT91C_US_PARE));  // Parity error
1767 }
1768
1769 //*----------------------------------------------------------------------------
1770 //* \fn    AT91F_US_PutChar
1771 //* \brief Send a character,does not check if ready to send
1772 //*----------------------------------------------------------------------------
1773 __inline void AT91F_US_PutChar (
1774         AT91PS_USART pUSART,
1775         int character )
1776 {
1777     pUSART->US_THR = (character & 0x1FF);
1778 }
1779
1780 //*----------------------------------------------------------------------------
1781 //* \fn    AT91F_US_GetChar
1782 //* \brief Receive a character,does not check if a character is available
1783 //*----------------------------------------------------------------------------
1784 __inline int AT91F_US_GetChar (
1785         const AT91PS_USART pUSART)
1786 {
1787     return((pUSART->US_RHR) & 0x1FF);
1788 }
1789
1790 //*----------------------------------------------------------------------------
1791 //* \fn    AT91F_US_SendFrame
1792 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
1793 //*----------------------------------------------------------------------------
1794 __inline unsigned int AT91F_US_SendFrame(
1795         AT91PS_USART pUSART,
1796         char *pBuffer,
1797         unsigned int szBuffer,
1798         char *pNextBuffer,
1799         unsigned int szNextBuffer )
1800 {
1801         return AT91F_PDC_SendFrame(
1802                 (AT91PS_PDC) &(pUSART->US_RPR),
1803                 pBuffer,
1804                 szBuffer,
1805                 pNextBuffer,
1806                 szNextBuffer);
1807 }
1808
1809 //*----------------------------------------------------------------------------
1810 //* \fn    AT91F_US_ReceiveFrame
1811 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
1812 //*----------------------------------------------------------------------------
1813 __inline unsigned int AT91F_US_ReceiveFrame (
1814         AT91PS_USART pUSART,
1815         char *pBuffer,
1816         unsigned int szBuffer,
1817         char *pNextBuffer,
1818         unsigned int szNextBuffer )
1819 {
1820         return AT91F_PDC_ReceiveFrame(
1821                 (AT91PS_PDC) &(pUSART->US_RPR),
1822                 pBuffer,
1823                 szBuffer,
1824                 pNextBuffer,
1825                 szNextBuffer);
1826 }
1827
1828 //*----------------------------------------------------------------------------
1829 //* \fn    AT91F_US_SetIrdaFilter
1830 //* \brief Set the value of IrDa filter tregister
1831 //*----------------------------------------------------------------------------
1832 __inline void AT91F_US_SetIrdaFilter (
1833         AT91PS_USART pUSART,
1834         unsigned char value
1835 )
1836 {
1837         pUSART->US_IF = value;
1838 }
1839
1840 /* *****************************************************************************
1841                 SOFTWARE API FOR MCI
1842    ***************************************************************************** */
1843 //* Classic MCI Mode Register Configuration with PDC mode enabled and MCK = MCI Clock
1844 #define AT91C_MCI_MR_PDCMODE    (AT91C_MCI_CLKDIV | AT91C_MCI_PWSDIV | (AT91C_MCI_PWSDIV<<1) | AT91C_MCI_PDCMODE)
1845
1846 //* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer
1847 #define AT91C_MCI_DTOR_1MEGA_CYCLES     (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL)
1848
1849 //* Classic MCI SDCard Register Configuration with 1-bit data bus on slot A
1850 #define AT91C_MCI_MMC_SLOTA     (AT91C_MCI_SCDSEL & 0x0)
1851
1852 //* Classic MCI SDCard Register Configuration with 1-bit data bus on slot B
1853 #define AT91C_MCI_MMC_SLOTB     (AT91C_MCI_SCDSEL)
1854
1855 //* Classic MCI SDCard Register Configuration with 4-bit data bus on slot A
1856 #define AT91C_MCI_SDCARD_4BITS_SLOTA    ( (AT91C_MCI_SCDSEL & 0x0) | AT91C_MCI_SCDBUS )
1857
1858 //* Classic MCI SDCard Register Configuration with 4-bit data bus on slot B
1859 #define AT91C_MCI_SDCARD_4BITS_SLOTB    (AT91C_MCI_SCDSEL | AT91C_MCI_SCDBUS)
1860
1861
1862
1863 //*----------------------------------------------------------------------------
1864 //* \fn    AT91F_MCI_Configure
1865 //* \brief Configure the MCI
1866 //*----------------------------------------------------------------------------
1867 __inline void AT91F_MCI_Configure (
1868         AT91PS_MCI pMCI,                         // \arg pointer to a MCI controller
1869         unsigned int DTOR_register,  // \arg Data Timeout Register to be programmed
1870         unsigned int MR_register,        // \arg Mode Register to be programmed
1871         unsigned int SDCR_register)  // \arg SDCard Register to be programmed
1872 {
1873     //* Reset the MCI
1874     pMCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN;
1875
1876     //* Disable all the interrupts
1877     pMCI->MCI_IDR = 0xFFFFFFFF;
1878
1879     //* Set the Data Timeout Register
1880     pMCI->MCI_DTOR = DTOR_register;
1881
1882     //* Set the Mode Register
1883     pMCI->MCI_MR = MR_register;
1884
1885     //* Set the SDCard Register
1886     pMCI->MCI_SDCR = SDCR_register;
1887 }
1888
1889 //*----------------------------------------------------------------------------
1890 //* \fn    AT91F_MCI_EnableIt
1891 //* \brief Enable MCI IT
1892 //*----------------------------------------------------------------------------
1893 __inline void AT91F_MCI_EnableIt (
1894         AT91PS_MCI pMCI, // \arg pointer to a MCI controller
1895         unsigned int flag)   // \arg IT to be enabled
1896 {
1897     //* Write to the IER register
1898     pMCI->MCI_IER = flag;
1899 }
1900
1901 //*----------------------------------------------------------------------------
1902 //* \fn    AT91F_MCI_DisableIt
1903 //* \brief Disable MCI IT
1904 //*----------------------------------------------------------------------------
1905 __inline void AT91F_MCI_DisableIt (
1906         AT91PS_MCI pMCI, // \arg pointer to a MCI controller
1907         unsigned int flag)   // \arg IT to be disabled
1908 {
1909     //* Write to the IDR register
1910     pMCI->MCI_IDR = flag;
1911 }
1912
1913 //*----------------------------------------------------------------------------
1914 //* \fn    AT91F_MCI_Enable_Interface
1915 //* \brief Enable the MCI Interface
1916 //*----------------------------------------------------------------------------
1917 __inline void AT91F_MCI_Enable_Interface (
1918         AT91PS_MCI pMCI)     // \arg pointer to a MCI controller
1919 {
1920     //* Enable the MCI
1921     pMCI->MCI_CR = AT91C_MCI_MCIEN;
1922 }
1923
1924 //*----------------------------------------------------------------------------
1925 //* \fn    AT91F_MCI_Disable_Interface
1926 //* \brief Disable the MCI Interface
1927 //*----------------------------------------------------------------------------
1928 __inline void AT91F_MCI_Disable_Interface (
1929         AT91PS_MCI pMCI)     // \arg pointer to a MCI controller
1930 {
1931     //* Disable the MCI
1932     pMCI->MCI_CR = AT91C_MCI_MCIDIS;
1933 }
1934
1935 //*----------------------------------------------------------------------------
1936 //* \fn    AT91F_MCI_Cfg_ModeRegister
1937 //* \brief Configure the MCI Mode Register
1938 //*----------------------------------------------------------------------------
1939 __inline void AT91F_MCI_Cfg_ModeRegister (
1940         AT91PS_MCI pMCI, // \arg pointer to a MCI controller
1941         unsigned int mode_register)   // \arg value to set in the mode register
1942 {
1943     //* Configure the MCI MR
1944     pMCI->MCI_MR = mode_register;
1945 }
1946 /* *****************************************************************************
1947                 SOFTWARE API FOR AIC
1948    ***************************************************************************** */
1949 #define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
1950
1951 //*----------------------------------------------------------------------------
1952 //* \fn    AT91F_AIC_ConfigureIt
1953 //* \brief Interrupt Handler Initialization
1954 //*----------------------------------------------------------------------------
1955 __inline unsigned int AT91F_AIC_ConfigureIt (
1956         AT91PS_AIC pAic,  // \arg pointer to the AIC registers
1957         unsigned int irq_id,     // \arg interrupt number to initialize
1958         unsigned int priority,   // \arg priority to give to the interrupt
1959         unsigned int src_type,   // \arg activation and sense of activation
1960         void (*newHandler) (void) ) // \arg address of the interrupt handler
1961 {
1962         unsigned int oldHandler;
1963     unsigned int mask ;
1964
1965     oldHandler = pAic->AIC_SVR[irq_id];
1966
1967     mask = 0x1 << irq_id ;
1968     //* Disable the interrupt on the interrupt controller
1969     pAic->AIC_IDCR = mask ;
1970     //* Save the interrupt handler routine pointer and the interrupt priority
1971     pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
1972     //* Store the Source Mode Register
1973     pAic->AIC_SMR[irq_id] = src_type | priority  ;
1974     //* Clear the interrupt on the interrupt controller
1975     pAic->AIC_ICCR = mask ;
1976
1977         return oldHandler;
1978 }
1979
1980 //*----------------------------------------------------------------------------
1981 //* \fn    AT91F_AIC_EnableIt
1982 //* \brief Enable corresponding IT number
1983 //*----------------------------------------------------------------------------
1984 __inline void AT91F_AIC_EnableIt (
1985         AT91PS_AIC pAic,      // \arg pointer to the AIC registers
1986         unsigned int irq_id ) // \arg interrupt number to initialize
1987 {
1988     //* Enable the interrupt on the interrupt controller
1989     pAic->AIC_IECR = 0x1 << irq_id ;
1990 }
1991
1992 //*----------------------------------------------------------------------------
1993 //* \fn    AT91F_AIC_DisableIt
1994 //* \brief Disable corresponding IT number
1995 //*----------------------------------------------------------------------------
1996 __inline void AT91F_AIC_DisableIt (
1997         AT91PS_AIC pAic,      // \arg pointer to the AIC registers
1998         unsigned int irq_id ) // \arg interrupt number to initialize
1999 {
2000     unsigned int mask = 0x1 << irq_id;
2001     //* Disable the interrupt on the interrupt controller
2002     pAic->AIC_IDCR = mask ;
2003     //* Clear the interrupt on the Interrupt Controller ( if one is pending )
2004     pAic->AIC_ICCR = mask ;
2005 }
2006
2007 //*----------------------------------------------------------------------------
2008 //* \fn    AT91F_AIC_ClearIt
2009 //* \brief Clear corresponding IT number
2010 //*----------------------------------------------------------------------------
2011 __inline void AT91F_AIC_ClearIt (
2012         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
2013         unsigned int irq_id) // \arg interrupt number to initialize
2014 {
2015     //* Clear the interrupt on the Interrupt Controller ( if one is pending )
2016     pAic->AIC_ICCR = (0x1 << irq_id);
2017 }
2018
2019 //*----------------------------------------------------------------------------
2020 //* \fn    AT91F_AIC_AcknowledgeIt
2021 //* \brief Acknowledge corresponding IT number
2022 //*----------------------------------------------------------------------------
2023 __inline void AT91F_AIC_AcknowledgeIt (
2024         AT91PS_AIC pAic)     // \arg pointer to the AIC registers
2025 {
2026     pAic->AIC_EOICR = pAic->AIC_EOICR;
2027 }
2028
2029 //*----------------------------------------------------------------------------
2030 //* \fn    AT91F_AIC_SetExceptionVector
2031 //* \brief Configure vector handler
2032 //*----------------------------------------------------------------------------
2033 __inline unsigned int  AT91F_AIC_SetExceptionVector (
2034         unsigned int *pVector, // \arg pointer to the AIC registers
2035         void (*Handler) () )   // \arg Interrupt Handler
2036 {
2037         unsigned int oldVector = *pVector;
2038
2039         if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
2040                 *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
2041         else
2042                 *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
2043
2044         return oldVector;
2045 }
2046
2047 //*----------------------------------------------------------------------------
2048 //* \fn    AT91F_AIC_Trig
2049 //* \brief Trig an IT
2050 //*----------------------------------------------------------------------------
2051 __inline void  AT91F_AIC_Trig (
2052         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
2053         unsigned int irq_id) // \arg interrupt number
2054 {
2055         pAic->AIC_ISCR = (0x1 << irq_id) ;
2056 }
2057
2058 //*----------------------------------------------------------------------------
2059 //* \fn    AT91F_AIC_IsActive
2060 //* \brief Test if an IT is active
2061 //*----------------------------------------------------------------------------
2062 __inline unsigned int  AT91F_AIC_IsActive (
2063         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
2064         unsigned int irq_id) // \arg Interrupt Number
2065 {
2066         return (pAic->AIC_ISR & (0x1 << irq_id));
2067 }
2068
2069 //*----------------------------------------------------------------------------
2070 //* \fn    AT91F_AIC_IsPending
2071 //* \brief Test if an IT is pending
2072 //*----------------------------------------------------------------------------
2073 __inline unsigned int  AT91F_AIC_IsPending (
2074         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
2075         unsigned int irq_id) // \arg Interrupt Number
2076 {
2077         return (pAic->AIC_IPR & (0x1 << irq_id));
2078 }
2079
2080 //*----------------------------------------------------------------------------
2081 //* \fn    AT91F_AIC_Open
2082 //* \brief Set exception vectors and AIC registers to default values
2083 //*----------------------------------------------------------------------------
2084 __inline void AT91F_AIC_Open(
2085         AT91PS_AIC pAic,        // \arg pointer to the AIC registers
2086         void (*IrqHandler) (),  // \arg Default IRQ vector exception
2087         void (*FiqHandler) (),  // \arg Default FIQ vector exception
2088         void (*DefaultHandler)  (), // \arg Default Handler set in ISR
2089         void (*SpuriousHandler) (), // \arg Default Spurious Handler
2090         unsigned int protectMode)   // \arg Debug Control Register
2091 {
2092         int i;
2093
2094         // Disable all interrupts and set IVR to the default handler
2095         for (i = 0; i < 32; ++i) {
2096                 AT91F_AIC_DisableIt(pAic, i);
2097                 AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);
2098         }
2099
2100         // Set the IRQ exception vector
2101         AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
2102         // Set the Fast Interrupt exception vector
2103         AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
2104
2105         pAic->AIC_SPU = (unsigned int) SpuriousHandler;
2106         pAic->AIC_DCR = protectMode;
2107 }
2108 /* *****************************************************************************
2109                 SOFTWARE API FOR UDP
2110    ***************************************************************************** */
2111 //*----------------------------------------------------------------------------
2112 //* \fn    AT91F_UDP_EnableIt
2113 //* \brief Enable UDP IT
2114 //*----------------------------------------------------------------------------
2115 __inline void AT91F_UDP_EnableIt (
2116         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2117         unsigned int flag)   // \arg IT to be enabled
2118 {
2119         //* Write to the IER register
2120         pUDP->UDP_IER = flag;
2121 }
2122
2123 //*----------------------------------------------------------------------------
2124 //* \fn    AT91F_UDP_DisableIt
2125 //* \brief Disable UDP IT
2126 //*----------------------------------------------------------------------------
2127 __inline void AT91F_UDP_DisableIt (
2128         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2129         unsigned int flag)   // \arg IT to be disabled
2130 {
2131         //* Write to the IDR register
2132         pUDP->UDP_IDR = flag;
2133 }
2134
2135 //*----------------------------------------------------------------------------
2136 //* \fn    AT91F_UDP_SetAddress
2137 //* \brief Set UDP functional address
2138 //*----------------------------------------------------------------------------
2139 __inline void AT91F_UDP_SetAddress (
2140         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2141         unsigned char address)   // \arg new UDP address
2142 {
2143         pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
2144 }
2145
2146 //*----------------------------------------------------------------------------
2147 //* \fn    AT91F_UDP_EnableEp
2148 //* \brief Enable Endpoint
2149 //*----------------------------------------------------------------------------
2150 __inline void AT91F_UDP_EnableEp (
2151         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2152         unsigned int flag)   // \arg endpoints to be enabled
2153 {
2154         pUDP->UDP_GLBSTATE  |= flag;
2155 }
2156
2157 //*----------------------------------------------------------------------------
2158 //* \fn    AT91F_UDP_DisableEp
2159 //* \brief Enable Endpoint
2160 //*----------------------------------------------------------------------------
2161 __inline void AT91F_UDP_DisableEp (
2162         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2163         unsigned int flag)   // \arg endpoints to be enabled
2164 {
2165         pUDP->UDP_GLBSTATE  &= ~(flag);
2166 }
2167
2168 //*----------------------------------------------------------------------------
2169 //* \fn    AT91F_UDP_SetState
2170 //* \brief Set UDP Device state
2171 //*----------------------------------------------------------------------------
2172 __inline void AT91F_UDP_SetState (
2173         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2174         unsigned int flag)   // \arg new UDP address
2175 {
2176         pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
2177         pUDP->UDP_GLBSTATE  |= flag;
2178 }
2179
2180 //*----------------------------------------------------------------------------
2181 //* \fn    AT91F_UDP_GetState
2182 //* \brief return UDP Device state
2183 //*----------------------------------------------------------------------------
2184 __inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
2185         AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
2186 {
2187         return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
2188 }
2189
2190 //*----------------------------------------------------------------------------
2191 //* \fn    AT91F_UDP_ResetEp
2192 //* \brief Reset UDP endpoint
2193 //*----------------------------------------------------------------------------
2194 __inline void AT91F_UDP_ResetEp ( // \return the UDP device state
2195         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2196         unsigned int flag)   // \arg Endpoints to be reset
2197 {
2198         pUDP->UDP_RSTEP = flag;
2199 }
2200
2201 //*----------------------------------------------------------------------------
2202 //* \fn    AT91F_UDP_EpStall
2203 //* \brief Endpoint will STALL requests
2204 //*----------------------------------------------------------------------------
2205 __inline void AT91F_UDP_EpStall(
2206         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2207         unsigned char endpoint)   // \arg endpoint number
2208 {
2209         pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
2210 }
2211
2212 //*----------------------------------------------------------------------------
2213 //* \fn    AT91F_UDP_EpWrite
2214 //* \brief Write value in the DPR
2215 //*----------------------------------------------------------------------------
2216 __inline void AT91F_UDP_EpWrite(
2217         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2218         unsigned char endpoint,  // \arg endpoint number
2219         unsigned char value)     // \arg value to be written in the DPR
2220 {
2221         pUDP->UDP_FDR[endpoint] = value;
2222 }
2223
2224 //*----------------------------------------------------------------------------
2225 //* \fn    AT91F_UDP_EpRead
2226 //* \brief Return value from the DPR
2227 //*----------------------------------------------------------------------------
2228 __inline unsigned int AT91F_UDP_EpRead(
2229         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2230         unsigned char endpoint)  // \arg endpoint number
2231 {
2232         return pUDP->UDP_FDR[endpoint];
2233 }
2234
2235 //*----------------------------------------------------------------------------
2236 //* \fn    AT91F_UDP_EpEndOfWr
2237 //* \brief Notify the UDP that values in DPR are ready to be sent
2238 //*----------------------------------------------------------------------------
2239 __inline void AT91F_UDP_EpEndOfWr(
2240         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2241         unsigned char endpoint)  // \arg endpoint number
2242 {
2243         pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
2244 }
2245
2246 //*----------------------------------------------------------------------------
2247 //* \fn    AT91F_UDP_EpClear
2248 //* \brief Clear flag in the endpoint CSR register
2249 //*----------------------------------------------------------------------------
2250 __inline void AT91F_UDP_EpClear(
2251         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2252         unsigned char endpoint,  // \arg endpoint number
2253         unsigned int flag)       // \arg flag to be cleared
2254 {
2255         pUDP->UDP_CSR[endpoint] &= ~(flag);
2256 }
2257
2258 //*----------------------------------------------------------------------------
2259 //* \fn    AT91F_UDP_EpSet
2260 //* \brief Set flag in the endpoint CSR register
2261 //*----------------------------------------------------------------------------
2262 __inline void AT91F_UDP_EpSet(
2263         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2264         unsigned char endpoint,  // \arg endpoint number
2265         unsigned int flag)       // \arg flag to be cleared
2266 {
2267         pUDP->UDP_CSR[endpoint] |= flag;
2268 }
2269
2270 //*----------------------------------------------------------------------------
2271 //* \fn    AT91F_UDP_EpStatus
2272 //* \brief Return the endpoint CSR register
2273 //*----------------------------------------------------------------------------
2274 __inline unsigned int AT91F_UDP_EpStatus(
2275         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2276         unsigned char endpoint)  // \arg endpoint number
2277 {
2278         return pUDP->UDP_CSR[endpoint];
2279 }
2280
2281 //*----------------------------------------------------------------------------
2282 //* \fn    AT91F_UDP_GetInterruptMaskStatus
2283 //* \brief Return UDP Interrupt Mask Status
2284 //*----------------------------------------------------------------------------
2285 __inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
2286         AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
2287 {
2288         return pUdp->UDP_IMR;
2289 }
2290
2291 //*----------------------------------------------------------------------------
2292 //* \fn    AT91F_UDP_IsInterruptMasked
2293 //* \brief Test if UDP Interrupt is Masked
2294 //*----------------------------------------------------------------------------
2295 __inline int AT91F_UDP_IsInterruptMasked(
2296         AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
2297         unsigned int flag) // \arg  flag to be tested
2298 {
2299         return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
2300 }
2301
2302 /* *****************************************************************************
2303                 SOFTWARE API FOR ST
2304    ***************************************************************************** */
2305 //*----------------------------------------------------------------------------
2306 //* \fn    AT91F_ST_SetPeriodInterval
2307 //* \brief Set Periodic Interval Interrupt (period in ms)
2308 //*----------------------------------------------------------------------------
2309 __inline void AT91F_ST_SetPeriodInterval(
2310         AT91PS_ST pSt,
2311         unsigned int period)
2312 {
2313         volatile int status;
2314         pSt->ST_IDR = AT91C_ST_PITS;                    /* Interrupt disable Register */
2315
2316         status = pSt->ST_SR;
2317     pSt->ST_PIMR = period << 5;                         /* Period Interval Mode Register == timer interval = 1ms*/
2318 }
2319
2320 //*----------------------------------------------------------------------------
2321 //* \fn    AT91F_ST_EnableIt
2322 //* \brief Enable system timer interrupt
2323 //*----------------------------------------------------------------------------
2324 __inline void AT91F_ST_EnableIt(
2325         AT91PS_ST pSt,
2326         unsigned int flag)
2327 {
2328         pSt->ST_IER = flag;
2329 }
2330
2331 //*----------------------------------------------------------------------------
2332 //* \fn    AT91F_ST_DisableIt
2333 //* \brief Disable system timer interrupt
2334 //*----------------------------------------------------------------------------
2335 __inline void AT91F_ST_DisableIt(
2336         AT91PS_ST pSt,
2337         unsigned int flag)
2338 {
2339         pSt->ST_IDR = flag;
2340 }
2341
2342 //*----------------------------------------------------------------------------
2343 //* \fn    AT91F_ST_GetInterruptMaskStatus
2344 //* \brief Return ST Interrupt Mask Status
2345 //*----------------------------------------------------------------------------
2346 __inline unsigned int AT91F_ST_GetInterruptMaskStatus( // \return ST Interrupt Mask Status
2347         AT91PS_ST pSt) // \arg  pointer to a ST controller
2348 {
2349         return pSt->ST_IMR;
2350 }
2351
2352 //*----------------------------------------------------------------------------
2353 //* \fn    AT91F_ST_IsInterruptMasked
2354 //* \brief Test if ST Interrupt is Masked
2355 //*----------------------------------------------------------------------------
2356 __inline int AT91F_ST_IsInterruptMasked(
2357         AT91PS_ST pSt,   // \arg  pointer to a ST controller
2358         unsigned int flag) // \arg  flag to be tested
2359 {
2360         return (AT91F_ST_GetInterruptMaskStatus(pSt) & flag);
2361 }
2362 //*----------------------------------------------------------------------------
2363 //* \fn    AT91F_EBI_CfgPIO
2364 //* \brief Configure PIO controllers to drive EBI signals
2365 //*----------------------------------------------------------------------------
2366 __inline void AT91F_EBI_CfgPIO (void)
2367 {
2368         // Configure PIO controllers to periph mode
2369         AT91F_PIO_CfgPeriph(
2370                 AT91C_BASE_PIOC, // PIO controller base address
2371                 ((unsigned int) AT91C_PC8_A24     ) |
2372                 ((unsigned int) AT91C_PC7_A23     ), // Peripheral A
2373                 0); // Peripheral B
2374 }
2375
2376 //*----------------------------------------------------------------------------
2377 //* \fn    AT91F_DBGU_CfgPMC
2378 //* \brief Enable Peripheral clock in PMC for  DBGU
2379 //*----------------------------------------------------------------------------
2380 __inline void AT91F_DBGU_CfgPMC (void)
2381 {
2382         AT91F_PMC_EnablePeriphClock(
2383                 AT91C_BASE_PMC, // PIO controller base address
2384                 ((unsigned int) 1 << AT91C_ID_SYS));
2385 }
2386
2387 //*----------------------------------------------------------------------------
2388 //* \fn    AT91F_DBGU_CfgPIO
2389 //* \brief Configure PIO controllers to drive DBGU signals
2390 //*----------------------------------------------------------------------------
2391 __inline void AT91F_DBGU_CfgPIO (void)
2392 {
2393         // Configure PIO controllers to periph mode
2394         AT91F_PIO_CfgPeriph(
2395                 AT91C_BASE_PIOA, // PIO controller base address
2396                 ((unsigned int) AT91C_PA31_DTXD    ) |
2397                 ((unsigned int) AT91C_PA30_DRXD    ), // Peripheral A
2398                 0); // Peripheral B
2399 }
2400
2401 //*----------------------------------------------------------------------------
2402 //* \fn    AT91F_SYS_CfgPMC
2403 //* \brief Enable Peripheral clock in PMC for  SYS
2404 //*----------------------------------------------------------------------------
2405 __inline void AT91F_SYS_CfgPMC (void)
2406 {
2407         AT91F_PMC_EnablePeriphClock(
2408                 AT91C_BASE_PMC, // PIO controller base address
2409                 ((unsigned int) 1 << AT91C_ID_SYS));
2410 }
2411
2412 //*----------------------------------------------------------------------------
2413 //* \fn    AT91F_UHP_CfgPMC
2414 //* \brief Enable Peripheral clock in PMC for  UHP
2415 //*----------------------------------------------------------------------------
2416 __inline void AT91F_UHP_CfgPMC (void)
2417 {
2418         AT91F_PMC_EnablePeriphClock(
2419                 AT91C_BASE_PMC, // PIO controller base address
2420                 ((unsigned int) 1 << AT91C_ID_UHP));
2421 }
2422
2423 //*----------------------------------------------------------------------------
2424 //* \fn    AT91F_SDRC_CfgPIO
2425 //* \brief Configure PIO controllers to drive SDRC signals
2426 //*----------------------------------------------------------------------------
2427 __inline void AT91F_SDRC_CfgPIO (void)
2428 {
2429         // Configure PIO controllers to periph mode
2430         AT91F_PIO_CfgPeriph(
2431                 AT91C_BASE_PIOC, // PIO controller base address
2432                 ((unsigned int) AT91C_PC20_D20     ) |
2433                 ((unsigned int) AT91C_PC21_D21     ) |
2434                 ((unsigned int) AT91C_PC30_D30     ) |
2435                 ((unsigned int) AT91C_PC22_D22     ) |
2436                 ((unsigned int) AT91C_PC31_D31     ) |
2437                 ((unsigned int) AT91C_PC23_D23     ) |
2438                 ((unsigned int) AT91C_PC16_D16     ) |
2439                 ((unsigned int) AT91C_PC24_D24     ) |
2440                 ((unsigned int) AT91C_PC17_D17     ) |
2441                 ((unsigned int) AT91C_PC25_D25     ) |
2442                 ((unsigned int) AT91C_PC18_D18     ) |
2443                 ((unsigned int) AT91C_PC26_D26     ) |
2444                 ((unsigned int) AT91C_PC19_D19     ) |
2445                 ((unsigned int) AT91C_PC27_D27     ) |
2446                 ((unsigned int) AT91C_PC28_D28     ) |
2447                 ((unsigned int) AT91C_PC29_D29     ), // Peripheral A
2448                 0); // Peripheral B
2449 }
2450
2451 //*----------------------------------------------------------------------------
2452 //* \fn    AT91F_EMAC_CfgPMC
2453 //* \brief Enable Peripheral clock in PMC for  EMAC
2454 //*----------------------------------------------------------------------------
2455 __inline void AT91F_EMAC_CfgPMC (void)
2456 {
2457         AT91F_PMC_EnablePeriphClock(
2458                 AT91C_BASE_PMC, // PIO controller base address
2459                 ((unsigned int) 1 << AT91C_ID_EMAC));
2460 }
2461
2462 //*----------------------------------------------------------------------------
2463 //* \fn    AT91F_EMAC_CfgPIO
2464 //* \brief Configure PIO controllers to drive EMAC signals
2465 //*----------------------------------------------------------------------------
2466 __inline void AT91F_EMAC_CfgPIO (void)
2467 {
2468         // Configure PIO controllers to periph mode
2469         AT91F_PIO_CfgPeriph(
2470                 AT91C_BASE_PIOA, // PIO controller base address
2471                 ((unsigned int) AT91C_PA14_ERXER   ) |
2472                 ((unsigned int) AT91C_PA12_ERX0    ) |
2473                 ((unsigned int) AT91C_PA13_ERX1    ) |
2474                 ((unsigned int) AT91C_PA8_ETXEN   ) |
2475                 ((unsigned int) AT91C_PA16_EMDIO   ) |
2476                 ((unsigned int) AT91C_PA9_ETX0    ) |
2477                 ((unsigned int) AT91C_PA10_ETX1    ) |
2478                 ((unsigned int) AT91C_PA11_ECRS_ECRSDV) |
2479                 ((unsigned int) AT91C_PA15_EMDC    ) |
2480                 ((unsigned int) AT91C_PA7_ETXCK_EREFCK), // Peripheral A
2481                 0); // Peripheral B
2482 }
2483
2484 //*----------------------------------------------------------------------------
2485 //* \fn    AT91F_RTC_CfgPMC
2486 //* \brief Enable Peripheral clock in PMC for  RTC
2487 //*----------------------------------------------------------------------------
2488 __inline void AT91F_RTC_CfgPMC (void)
2489 {
2490         AT91F_PMC_EnablePeriphClock(
2491                 AT91C_BASE_PMC, // PIO controller base address
2492                 ((unsigned int) 1 << AT91C_ID_SYS));
2493 }
2494
2495 //*----------------------------------------------------------------------------
2496 //* \fn    AT91F_SSC2_CfgPMC
2497 //* \brief Enable Peripheral clock in PMC for  SSC2
2498 //*----------------------------------------------------------------------------
2499 __inline void AT91F_SSC2_CfgPMC (void)
2500 {
2501         AT91F_PMC_EnablePeriphClock(
2502                 AT91C_BASE_PMC, // PIO controller base address
2503                 ((unsigned int) 1 << AT91C_ID_SSC2));
2504 }
2505
2506 //*----------------------------------------------------------------------------
2507 //* \fn    AT91F_SSC2_CfgPIO
2508 //* \brief Configure PIO controllers to drive SSC2 signals
2509 //*----------------------------------------------------------------------------
2510 __inline void AT91F_SSC2_CfgPIO (void)
2511 {
2512         // Configure PIO controllers to periph mode
2513         AT91F_PIO_CfgPeriph(
2514                 AT91C_BASE_PIOB, // PIO controller base address
2515                 ((unsigned int) AT91C_PB12_TF2     ) |
2516                 ((unsigned int) AT91C_PB17_RF2     ) |
2517                 ((unsigned int) AT91C_PB13_TK2     ) |
2518                 ((unsigned int) AT91C_PB16_RK2     ) |
2519                 ((unsigned int) AT91C_PB14_TD2     ) |
2520                 ((unsigned int) AT91C_PB15_RD2     ), // Peripheral A
2521                 0); // Peripheral B
2522 }
2523
2524 //*----------------------------------------------------------------------------
2525 //* \fn    AT91F_SSC1_CfgPMC
2526 //* \brief Enable Peripheral clock in PMC for  SSC1
2527 //*----------------------------------------------------------------------------
2528 __inline void AT91F_SSC1_CfgPMC (void)
2529 {
2530         AT91F_PMC_EnablePeriphClock(
2531                 AT91C_BASE_PMC, // PIO controller base address
2532                 ((unsigned int) 1 << AT91C_ID_SSC1));
2533 }
2534
2535 //*----------------------------------------------------------------------------
2536 //* \fn    AT91F_SSC1_CfgPIO
2537 //* \brief Configure PIO controllers to drive SSC1 signals
2538 //*----------------------------------------------------------------------------
2539 __inline void AT91F_SSC1_CfgPIO (void)
2540 {
2541         // Configure PIO controllers to periph mode
2542         AT91F_PIO_CfgPeriph(
2543                 AT91C_BASE_PIOB, // PIO controller base address
2544                 ((unsigned int) AT91C_PB11_RF1     ) |
2545                 ((unsigned int) AT91C_PB10_RK1     ) |
2546                 ((unsigned int) AT91C_PB8_TD1     ) |
2547                 ((unsigned int) AT91C_PB9_RD1     ), // Peripheral A
2548                 0); // Peripheral B
2549 }
2550
2551 //*----------------------------------------------------------------------------
2552 //* \fn    AT91F_SSC0_CfgPMC
2553 //* \brief Enable Peripheral clock in PMC for  SSC0
2554 //*----------------------------------------------------------------------------
2555 __inline void AT91F_SSC0_CfgPMC (void)
2556 {
2557         AT91F_PMC_EnablePeriphClock(
2558                 AT91C_BASE_PMC, // PIO controller base address
2559                 ((unsigned int) 1 << AT91C_ID_SSC0));
2560 }
2561
2562 //*----------------------------------------------------------------------------
2563 //* \fn    AT91F_SPI_CfgPMC
2564 //* \brief Enable Peripheral clock in PMC for  SPI
2565 //*----------------------------------------------------------------------------
2566 __inline void AT91F_SPI_CfgPMC (void)
2567 {
2568         AT91F_PMC_EnablePeriphClock(
2569                 AT91C_BASE_PMC, // PIO controller base address
2570                 ((unsigned int) 1 << AT91C_ID_SPI));
2571 }
2572
2573 //*----------------------------------------------------------------------------
2574 //* \fn    AT91F_SPI_CfgPIO
2575 //* \brief Configure PIO controllers to drive SPI signals
2576 //*----------------------------------------------------------------------------
2577 __inline void AT91F_SPI_CfgPIO (void)
2578 {
2579         // Configure PIO controllers to periph mode
2580         AT91F_PIO_CfgPeriph(
2581                 AT91C_BASE_PIOA, // PIO controller base address
2582                 ((unsigned int) AT91C_PA3_NPCS0   ) |
2583                 ((unsigned int) AT91C_PA4_NPCS1   ) |
2584                 ((unsigned int) AT91C_PA1_MOSI    ) |
2585                 ((unsigned int) AT91C_PA5_NPCS2   ) |
2586                 ((unsigned int) AT91C_PA6_NPCS3   ) |
2587                 ((unsigned int) AT91C_PA0_MISO    ) |
2588                 ((unsigned int) AT91C_PA2_SPCK    ), // Peripheral A
2589                 0); // Peripheral B
2590 }
2591
2592 //*----------------------------------------------------------------------------
2593 //* \fn    AT91F_TC5_CfgPMC
2594 //* \brief Enable Peripheral clock in PMC for  TC5
2595 //*----------------------------------------------------------------------------
2596 __inline void AT91F_TC5_CfgPMC (void)
2597 {
2598         AT91F_PMC_EnablePeriphClock(
2599                 AT91C_BASE_PMC, // PIO controller base address
2600                 ((unsigned int) 1 << AT91C_ID_TC5));
2601 }
2602
2603 //*----------------------------------------------------------------------------
2604 //* \fn    AT91F_TC4_CfgPMC
2605 //* \brief Enable Peripheral clock in PMC for  TC4
2606 //*----------------------------------------------------------------------------
2607 __inline void AT91F_TC4_CfgPMC (void)
2608 {
2609         AT91F_PMC_EnablePeriphClock(
2610                 AT91C_BASE_PMC, // PIO controller base address
2611                 ((unsigned int) 1 << AT91C_ID_TC4));
2612 }
2613
2614 //*----------------------------------------------------------------------------
2615 //* \fn    AT91F_TC3_CfgPMC
2616 //* \brief Enable Peripheral clock in PMC for  TC3
2617 //*----------------------------------------------------------------------------
2618 __inline void AT91F_TC3_CfgPMC (void)
2619 {
2620         AT91F_PMC_EnablePeriphClock(
2621                 AT91C_BASE_PMC, // PIO controller base address
2622                 ((unsigned int) 1 << AT91C_ID_TC3));
2623 }
2624
2625 //*----------------------------------------------------------------------------
2626 //* \fn    AT91F_TC2_CfgPMC
2627 //* \brief Enable Peripheral clock in PMC for  TC2
2628 //*----------------------------------------------------------------------------
2629 __inline void AT91F_TC2_CfgPMC (void)
2630 {
2631         AT91F_PMC_EnablePeriphClock(
2632                 AT91C_BASE_PMC, // PIO controller base address
2633                 ((unsigned int) 1 << AT91C_ID_TC2));
2634 }
2635
2636 //*----------------------------------------------------------------------------
2637 //* \fn    AT91F_TC1_CfgPMC
2638 //* \brief Enable Peripheral clock in PMC for  TC1
2639 //*----------------------------------------------------------------------------
2640 __inline void AT91F_TC1_CfgPMC (void)
2641 {
2642         AT91F_PMC_EnablePeriphClock(
2643                 AT91C_BASE_PMC, // PIO controller base address
2644                 ((unsigned int) 1 << AT91C_ID_TC1));
2645 }
2646
2647 //*----------------------------------------------------------------------------
2648 //* \fn    AT91F_TC0_CfgPMC
2649 //* \brief Enable Peripheral clock in PMC for  TC0
2650 //*----------------------------------------------------------------------------
2651 __inline void AT91F_TC0_CfgPMC (void)
2652 {
2653         AT91F_PMC_EnablePeriphClock(
2654                 AT91C_BASE_PMC, // PIO controller base address
2655                 ((unsigned int) 1 << AT91C_ID_TC0));
2656 }
2657
2658 //*----------------------------------------------------------------------------
2659 //* \fn    AT91F_SMC2_CfgPIO
2660 //* \brief Configure PIO controllers to drive SMC2 signals
2661 //*----------------------------------------------------------------------------
2662 __inline void AT91F_SMC2_CfgPIO (void)
2663 {
2664         // Configure PIO controllers to periph mode
2665         AT91F_PIO_CfgPeriph(
2666                 AT91C_BASE_PIOC, // PIO controller base address
2667                 ((unsigned int) AT91C_PC10_NCS4_CFCS) |
2668                 ((unsigned int) AT91C_PC9_A25_CFRNW) |
2669                 ((unsigned int) AT91C_PC12_NCS6_CFCE2) |
2670                 ((unsigned int) AT91C_PC11_NCS5_CFCE1), // Peripheral A
2671                 0); // Peripheral B
2672 }
2673
2674 //*----------------------------------------------------------------------------
2675 //* \fn    AT91F_PMC_CfgPMC
2676 //* \brief Enable Peripheral clock in PMC for  PMC
2677 //*----------------------------------------------------------------------------
2678 __inline void AT91F_PMC_CfgPMC (void)
2679 {
2680         AT91F_PMC_EnablePeriphClock(
2681                 AT91C_BASE_PMC, // PIO controller base address
2682                 ((unsigned int) 1 << AT91C_ID_SYS));
2683 }
2684
2685 //*----------------------------------------------------------------------------
2686 //* \fn    AT91F_PMC_CfgPIO
2687 //* \brief Configure PIO controllers to drive PMC signals
2688 //*----------------------------------------------------------------------------
2689 __inline void AT91F_PMC_CfgPIO (void)
2690 {
2691         // Configure PIO controllers to periph mode
2692         AT91F_PIO_CfgPeriph(
2693                 AT91C_BASE_PIOA, // PIO controller base address
2694                 0, // Peripheral A
2695                 ((unsigned int) AT91C_PA24_PCK1    )); // Peripheral B
2696         // Configure PIO controllers to periph mode
2697         AT91F_PIO_CfgPeriph(
2698                 AT91C_BASE_PIOB, // PIO controller base address
2699                 ((unsigned int) AT91C_PB27_PCK0    ), // Peripheral A
2700                 0); // Peripheral B
2701 }
2702
2703 //*----------------------------------------------------------------------------
2704 //* \fn    AT91F_PIOD_CfgPMC
2705 //* \brief Enable Peripheral clock in PMC for  PIOD
2706 //*----------------------------------------------------------------------------
2707 __inline void AT91F_PIOD_CfgPMC (void)
2708 {
2709         AT91F_PMC_EnablePeriphClock(
2710                 AT91C_BASE_PMC, // PIO controller base address
2711                 ((unsigned int) 1 << AT91C_ID_PIOD));
2712 }
2713
2714 //*----------------------------------------------------------------------------
2715 //* \fn    AT91F_PIOC_CfgPMC
2716 //* \brief Enable Peripheral clock in PMC for  PIOC
2717 //*----------------------------------------------------------------------------
2718 __inline void AT91F_PIOC_CfgPMC (void)
2719 {
2720         AT91F_PMC_EnablePeriphClock(
2721                 AT91C_BASE_PMC, // PIO controller base address
2722                 ((unsigned int) 1 << AT91C_ID_PIOC));
2723 }
2724
2725 //*----------------------------------------------------------------------------
2726 //* \fn    AT91F_PIOB_CfgPMC
2727 //* \brief Enable Peripheral clock in PMC for  PIOB
2728 //*----------------------------------------------------------------------------
2729 __inline void AT91F_PIOB_CfgPMC (void)
2730 {
2731         AT91F_PMC_EnablePeriphClock(
2732                 AT91C_BASE_PMC, // PIO controller base address
2733                 ((unsigned int) 1 << AT91C_ID_PIOB));
2734 }
2735
2736 //*----------------------------------------------------------------------------
2737 //* \fn    AT91F_PIOA_CfgPMC
2738 //* \brief Enable Peripheral clock in PMC for  PIOA
2739 //*----------------------------------------------------------------------------
2740 __inline void AT91F_PIOA_CfgPMC (void)
2741 {
2742         AT91F_PMC_EnablePeriphClock(
2743                 AT91C_BASE_PMC, // PIO controller base address
2744                 ((unsigned int) 1 << AT91C_ID_PIOA));
2745 }
2746
2747 //*----------------------------------------------------------------------------
2748 //* \fn    AT91F_TWI_CfgPMC
2749 //* \brief Enable Peripheral clock in PMC for  TWI
2750 //*----------------------------------------------------------------------------
2751 __inline void AT91F_TWI_CfgPMC (void)
2752 {
2753         AT91F_PMC_EnablePeriphClock(
2754                 AT91C_BASE_PMC, // PIO controller base address
2755                 ((unsigned int) 1 << AT91C_ID_TWI));
2756 }
2757
2758 //*----------------------------------------------------------------------------
2759 //* \fn    AT91F_TWI_CfgPIO
2760 //* \brief Configure PIO controllers to drive TWI signals
2761 //*----------------------------------------------------------------------------
2762 __inline void AT91F_TWI_CfgPIO (void)
2763 {
2764         // Configure PIO controllers to periph mode
2765         AT91F_PIO_CfgPeriph(
2766                 AT91C_BASE_PIOA, // PIO controller base address
2767                 ((unsigned int) AT91C_PA25_TWD     ) |
2768                 ((unsigned int) AT91C_PA26_TWCK    ), // Peripheral A
2769                 0); // Peripheral B
2770 }
2771
2772 //*----------------------------------------------------------------------------
2773 //* \fn    AT91F_US3_CfgPMC
2774 //* \brief Enable Peripheral clock in PMC for  US3
2775 //*----------------------------------------------------------------------------
2776 __inline void AT91F_US3_CfgPMC (void)
2777 {
2778         AT91F_PMC_EnablePeriphClock(
2779                 AT91C_BASE_PMC, // PIO controller base address
2780                 ((unsigned int) 1 << AT91C_ID_US3));
2781 }
2782
2783 //*----------------------------------------------------------------------------
2784 //* \fn    AT91F_US2_CfgPMC
2785 //* \brief Enable Peripheral clock in PMC for  US2
2786 //*----------------------------------------------------------------------------
2787 __inline void AT91F_US2_CfgPMC (void)
2788 {
2789         AT91F_PMC_EnablePeriphClock(
2790                 AT91C_BASE_PMC, // PIO controller base address
2791                 ((unsigned int) 1 << AT91C_ID_US2));
2792 }
2793
2794 //*----------------------------------------------------------------------------
2795 //* \fn    AT91F_US2_CfgPIO
2796 //* \brief Configure PIO controllers to drive US2 signals
2797 //*----------------------------------------------------------------------------
2798 __inline void AT91F_US2_CfgPIO (void)
2799 {
2800         // Configure PIO controllers to periph mode
2801         AT91F_PIO_CfgPeriph(
2802                 AT91C_BASE_PIOA, // PIO controller base address
2803                 ((unsigned int) AT91C_PA23_TXD2    ) |
2804                 ((unsigned int) AT91C_PA22_RXD2    ), // Peripheral A
2805                 0); // Peripheral B
2806 }
2807
2808 //*----------------------------------------------------------------------------
2809 //* \fn    AT91F_US1_CfgPMC
2810 //* \brief Enable Peripheral clock in PMC for  US1
2811 //*----------------------------------------------------------------------------
2812 __inline void AT91F_US1_CfgPMC (void)
2813 {
2814         AT91F_PMC_EnablePeriphClock(
2815                 AT91C_BASE_PMC, // PIO controller base address
2816                 ((unsigned int) 1 << AT91C_ID_US1));
2817 }
2818
2819 //*----------------------------------------------------------------------------
2820 //* \fn    AT91F_US1_CfgPIO
2821 //* \brief Configure PIO controllers to drive US1 signals
2822 //*----------------------------------------------------------------------------
2823 __inline void AT91F_US1_CfgPIO (void)
2824 {
2825         // Configure PIO controllers to periph mode
2826         AT91F_PIO_CfgPeriph(
2827                 AT91C_BASE_PIOB, // PIO controller base address
2828                 ((unsigned int) AT91C_PB21_RXD1    ) |
2829                 ((unsigned int) AT91C_PB26_RTS1    ) |
2830                 ((unsigned int) AT91C_PB25_DSR1    ) |
2831                 ((unsigned int) AT91C_PB24_CTS1    ) |
2832                 ((unsigned int) AT91C_PB19_DTR1    ) |
2833                 ((unsigned int) AT91C_PB23_DCD1    ) |
2834                 ((unsigned int) AT91C_PB20_TXD1    ) |
2835                 ((unsigned int) AT91C_PB18_RI1     ), // Peripheral A
2836                 0); // Peripheral B
2837 }
2838
2839 //*----------------------------------------------------------------------------
2840 //* \fn    AT91F_US0_CfgPMC
2841 //* \brief Enable Peripheral clock in PMC for  US0
2842 //*----------------------------------------------------------------------------
2843 __inline void AT91F_US0_CfgPMC (void)
2844 {
2845         AT91F_PMC_EnablePeriphClock(
2846                 AT91C_BASE_PMC, // PIO controller base address
2847                 ((unsigned int) 1 << AT91C_ID_US0));
2848 }
2849
2850 //*----------------------------------------------------------------------------
2851 //* \fn    AT91F_US0_CfgPIO
2852 //* \brief Configure PIO controllers to drive US0 signals
2853 //*----------------------------------------------------------------------------
2854 __inline void AT91F_US0_CfgPIO (void)
2855 {
2856         // Configure PIO controllers to periph mode
2857         AT91F_PIO_CfgPeriph(
2858                 AT91C_BASE_PIOA, // PIO controller base address
2859                 ((unsigned int) AT91C_PA17_TXD0    ) |
2860                 ((unsigned int) AT91C_PA21_RTS0    ) |
2861                 ((unsigned int) AT91C_PA19_SCK0    ) |
2862                 ((unsigned int) AT91C_PA20_CTS0    ), // Peripheral A
2863                 0); // Peripheral B
2864 }
2865
2866 //*----------------------------------------------------------------------------
2867 //* \fn    AT91F_MCI_CfgPMC
2868 //* \brief Enable Peripheral clock in PMC for  MCI
2869 //*----------------------------------------------------------------------------
2870 __inline void AT91F_MCI_CfgPMC (void)
2871 {
2872         AT91F_PMC_EnablePeriphClock(
2873                 AT91C_BASE_PMC, // PIO controller base address
2874                 ((unsigned int) 1 << AT91C_ID_MCI));
2875 }
2876
2877 //*----------------------------------------------------------------------------
2878 //* \fn    AT91F_MCI_CfgPIO
2879 //* \brief Configure PIO controllers to drive MCI signals
2880 //*----------------------------------------------------------------------------
2881 __inline void AT91F_MCI_CfgPIO (void)
2882 {
2883         // Configure PIO controllers to periph mode
2884         AT91F_PIO_CfgPeriph(
2885                 AT91C_BASE_PIOA, // PIO controller base address
2886                 ((unsigned int) AT91C_PA28_MCCDA   ) |
2887                 ((unsigned int) AT91C_PA29_MCDA0   ) |
2888                 ((unsigned int) AT91C_PA27_MCCK    ), // Peripheral A
2889                 0); // Peripheral B
2890         // Configure PIO controllers to periph mode
2891         AT91F_PIO_CfgPeriph(
2892                 AT91C_BASE_PIOB, // PIO controller base address
2893                 0, // Peripheral A
2894                 ((unsigned int) AT91C_PB5_MCDA3   ) |
2895                 ((unsigned int) AT91C_PB3_MCDA1   ) |
2896                 ((unsigned int) AT91C_PB4_MCDA2   )); // Peripheral B
2897 }
2898
2899 //*----------------------------------------------------------------------------
2900 //* \fn    AT91F_AIC_CfgPMC
2901 //* \brief Enable Peripheral clock in PMC for  AIC
2902 //*----------------------------------------------------------------------------
2903 __inline void AT91F_AIC_CfgPMC (void)
2904 {
2905         AT91F_PMC_EnablePeriphClock(
2906                 AT91C_BASE_PMC, // PIO controller base address
2907                 ((unsigned int) 1 << AT91C_ID_IRQ4) |
2908                 ((unsigned int) 1 << AT91C_ID_FIQ) |
2909                 ((unsigned int) 1 << AT91C_ID_IRQ5) |
2910                 ((unsigned int) 1 << AT91C_ID_IRQ6) |
2911                 ((unsigned int) 1 << AT91C_ID_IRQ0) |
2912                 ((unsigned int) 1 << AT91C_ID_IRQ1) |
2913                 ((unsigned int) 1 << AT91C_ID_IRQ2) |
2914                 ((unsigned int) 1 << AT91C_ID_IRQ3));
2915 }
2916
2917 //*----------------------------------------------------------------------------
2918 //* \fn    AT91F_UDP_CfgPMC
2919 //* \brief Enable Peripheral clock in PMC for  UDP
2920 //*----------------------------------------------------------------------------
2921 __inline void AT91F_UDP_CfgPMC (void)
2922 {
2923         AT91F_PMC_EnablePeriphClock(
2924                 AT91C_BASE_PMC, // PIO controller base address
2925                 ((unsigned int) 1 << AT91C_ID_UDP));
2926 }
2927
2928 //*----------------------------------------------------------------------------
2929 //* \fn    AT91F_ST_CfgPMC
2930 //* \brief Enable Peripheral clock in PMC for  ST
2931 //*----------------------------------------------------------------------------
2932 __inline void AT91F_ST_CfgPMC (void)
2933 {
2934         AT91F_PMC_EnablePeriphClock(
2935                 AT91C_BASE_PMC, // PIO controller base address
2936                 ((unsigned int) 1 << AT91C_ID_SYS));
2937 }
2938
2939 #endif // lib_AT91RM9200_H