sdcc/sim/ucsim/src/sims/f8.src/f8cl.h

   1 /*
   2  * Simulator of microcontrollers (f8cl.h)
   3  *
   4  * Copyright (C) 2022 Drotos Daniel
   5  *
   6  * To contact author send email to dr.dkdb@gmail.com
   7  *
   8  */
   9
  10 /* This file is part of microcontroller simulator: ucsim.
  11
  12 UCSIM is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2 of the License, or
  15 (at your option) any later version.
  16
  17 UCSIM is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with UCSIM; see the file COPYING.  If not, write to the Free
  24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  25 02111-1307, USA. */
  26 /*@1@*/
  27
  28 #ifndef F8CL_HEADER
  29 #define F8CL_HEADER
  30
  31 #include "uccl.h"
  32
  33 #include "glob.h"
  34 #include "decode.h"
  35
  36 #ifdef WORDS_BIGENDIAN
  37 #define REGPAIR(N,N16,NH,NL) union                      \
  38                       {                         \
  39                         u16_t N16;              \
  40                         struct {                \
  41                           u8_t NH;              \
  42                           u8_t NL;              \
  43                         } r;                    \
  44   } N
  45 #else
  46 #define REGPAIR(N,N16,NH,NL) union                      \
  47                       {                         \
  48                         u16_t N16;              \
  49                         struct {                \
  50                           u8_t NL;              \
  51                           u8_t NH;              \
  52                         } r;                    \
  53   } N
  54 #endif
  55
  56 #define rX (rpX.X)
  57 #define rXL (rpX.r.XL)
  58 #define rXH (rpX.r.XH)
  59 #define rY (rpY.Y)
  60 #define rYL (rpY.r.YL)
  61 #define rYH (rpY.r.YH)
  62 #define rZ (rpZ.Z)
  63 #define rZL (rpZ.r.ZL)
  64 #define rZH (rpZ.r.ZH)
  65
  66
  67 enum {
  68   flagO  = 0x01,
  69   flagZ  = 0x02,
  70   flagN  = 0x04,
  71   flagC  = 0x08,
  72   flagH  = 0x10,
  73
  74   flagA  = flagH,
  75   flagS  = flagN,
  76   flagV  = flagO,
  77
  78   flagCZ = flagC|flagZ,
  79   flagZN = flagZ|flagN,
  80   flagCZN= flagC|flagZ|flagN,
  81   flagOZN= flagO|flagZ|flagN,
  82
  83   fAll   = flagO|flagZ|flagN|flagC|flagH,
  84   fAll_H = flagO|flagZ|flagN|flagC
  85 };
  86
  87 #define COND_Z          (rF&flagZ)
  88 #define COND_NZ         (!(rF&flagZ))
  89 #define COND_C          (rF&flagC)
  90 #define COND_NC         (!(rF&flagC))
  91 #define COND_N          (rF&flagN)
  92 #define COND_NN         (!(rF&flagN))
  93 #define COND_O          (rF&flagO)
  94 #define COND_NO         (!(rF&flagO))
  95 #define COND_SGE        ((COND_N&&COND_O)||(!COND_N&&!COND_O))
  96 #define COND_SLT        ((COND_N&&!COND_O)||(!COND_N&&COND_O))
  97 #define COND_SGT        (!(COND_Z||(COND_SLT)))
  98 #define COND_SLE        (!COND_SGT)
  99 #define COND_GT         (COND_C&&!COND_Z)
 100 #define COND_LE         (!COND_C||COND_Z)
 101
 102 enum {
 103   P_NONE        = 0,
 104   P_SWAP        = 0x01, // (0) swapop
 105   P_ALT1        = 0x02, // (1) altacc1    XH
 106   P_ALT2        = 0x04, // (2) altacc2    YL  X
 107   P_ALT3        = 0x08, // (2) altacc3    ZL  Z
 108   P_ALT4        = 0x10, // (2) altacc4    YH  Z
 109   P_ALT5        = 0x20, // (2) altacc5    ZH
 110 };
 111
 112 #define IFSWAP if (prefixes&P_SWAP)
 113
 114 /*
 115  * Base of f8 processor
 116  */
 117 class cl_f8: public cl_uc
 118 {
 119 public:
 120   REGPAIR(rpX, X, XH, XL); class cl_cell8 cXH, cXL; class cl_cell16 cX;
 121   REGPAIR(rpY, Y, YH, YL); class cl_cell8 cYH, cYL; class cl_cell16 cY;
 122   REGPAIR(rpZ, Z, ZH, ZL); class cl_cell8 cZH, cZL; class cl_cell16 cZ;
 123   u16_t rSP; class cl_cell16 cSP;
 124   u8_t rF; class cl_cell8 cF;
 125   t_addr sp_limit;
 126   class cl_cell8 *acc8;
 127   class cl_cell16 *acc16;
 128   int prefixes;
 129 public:
 130   cl_f8(class cl_sim *asim);
 131   virtual int init(void);
 132   virtual const char *id_string(void);
 133   virtual void reset(void);
 134   virtual void set_PC(t_addr addr);
 135
 136   virtual void mk_hw_elements(void);
 137   virtual void make_cpu_hw(void);
 138   virtual void make_memories(void);
 139
 140   virtual double def_xtal(void) { return 25000000; }
 141   virtual int clock_per_cycle(void) { return 1; }
 142   virtual struct dis_entry *dis_tbl(void);
 143   virtual struct dis_entry *get_dis_entry(t_addr addr);
 144   virtual int inst_length(t_addr addr);
 145   virtual u8_t a8(u8_t prefs);
 146   virtual u16_t a16(u8_t prefs);
 147   virtual const char *a8_name(u8_t prefs);
 148   virtual const char *a16_name(u8_t prefs);
 149   virtual const char *a16h_name(u8_t prefs);
 150   virtual const char *a16l_name(u8_t prefs);
 151   virtual char *disassc(t_addr addr, chars *comment=NULL);
 152   virtual int longest_inst(void) { return 5; }
 153
 154   virtual void print_regs(class cl_console_base *con);
 155
 156   virtual u16_t fetch16(void) { u16_t v= fetch(); v+= fetch()*256; return v; }
 157   virtual i8_t d(void) { return fetch(); }
 158   virtual i16_t sexd(void);
 159   virtual void push1(u8_t v);
 160   virtual void push2(u16_t v);
 161   virtual void push2(u8_t h, u8_t l);
 162   virtual u8_t pop1(void);
 163   virtual u16_t pop2(void);
 164   virtual void stack_check_overflow(t_addr sp_before);
 165
 166   // memory cells addressed by 8 bit addressing modes
 167   // call necessary fetches
 168   virtual class cl_cell8 &m_i(void);
 169   virtual class cl_cell8 &m_mm(void);
 170   virtual class cl_cell8 &m_n_sp(void);
 171   virtual class cl_cell8 &m_nn_z(void);
 172   virtual class cl_cell8 &m_y(void);
 173   virtual class cl_cell8 &m_n_y(void);
 174   virtual class cl_cell8 &m_z(void);
 175
 176   // memory addresses by addressing modes
 177   // call necessary fetches
 178   virtual u16_t a_i(void);
 179   virtual u16_t a_mm(void);
 180   virtual u16_t a_n_sp(void);
 181   virtual u16_t a_nn_z(void);
 182   virtual u16_t a_y(void);
 183   virtual u16_t a_n_y();
 184   virtual u16_t a_acc16(void);
 185   virtual u16_t a_n_acc16(void);
 186   virtual u16_t a_nn_acc16(void);
 187
 188   virtual void clear_prefixes();
 189   virtual int exec_inst(void);
 190
 191   // data moves: imove.cc
 192   // 8 bit moves
 193   int ld8_a_i(u8_t op2);
 194   int ld8_a_m(class cl_cell8 &m);
 195   int ld8_m_a(class cl_cell8 &m);
 196   int ld8_a_r(class cl_cell8 &r);
 197   int LD8_A_I(t_mem code)   { return ld8_a_i(fetch()); }
 198   int LD8_A_M(t_mem code)   { return ld8_a_m(m_mm()); }
 199   int LD8_A_NSP(t_mem code) { return ld8_a_m(m_n_sp()); }
 200   int LD8_A_NNZ(t_mem code) { return ld8_a_m(m_nn_z()); }
 201   int LD8_A_Y(t_mem code)   { return ld8_a_m(m_y()); }
 202   int LD8_A_NY(t_mem code)  { return ld8_a_m(m_n_y()); }
 203   int LD8_A_XH(t_mem code)  { return ld8_a_r(cXH); }
 204   int LD8_A_YL(t_mem code)  { return ld8_a_r(cYL); }
 205   int LD8_A_YH(t_mem code)  { return ld8_a_r(cYH); }
 206   int LD8_A_ZL(t_mem code)  { return ld8_a_r(cZL); }
 207   int LD8_A_ZH(t_mem code)  { return ld8_a_r(cZH); }
 208   int LD8_M_A(t_mem code)   { return ld8_m_a(m_mm()); }
 209   int LD8_NSP_A(t_mem code) { return ld8_m_a(m_n_sp()); }
 210   int LD8_NNZ_A(t_mem code) { return ld8_m_a(m_nn_z()); }
 211   int LD8_Y_A(t_mem code)   { return ld8_m_a(m_y()); }
 212   int LD8_NY_A(t_mem code)  { return ld8_m_a(m_n_y()); }
 213   // 16 bit moves
 214   int ldw_a_i(u16_t op2);
 215   int ldw_a_m(u16_t addr);
 216   int ldw_m_a(u16_t addr);
 217   int ldw_m_r(u16_t addr, u16_t r);
 218   int ldw_a_r(u16_t r);
 219   int LDW_A_I(t_mem code)    { return ldw_a_i(fetch16()); }
 220   int LDW_A_M(t_mem code)    { return ldw_a_m(a_mm()); }
 221   int LDW_A_NSP(t_mem code)  { return ldw_a_m(a_n_sp()); }
 222   int LDW_A_NNZ(t_mem code)  { return ldw_a_m(a_nn_z()); }
 223   int LDW_A_NY(t_mem code)   { return ldw_a_m(a_n_y()); }
 224   int LDW_A_Y(t_mem code)    { return ldw_a_m(rY); }
 225   int LDW_A_X(t_mem code)    { return ldw_a_r(rX); }
 226   int LDW_A_D(t_mem code)    { return ldw_a_i(sexd()); }
 227   int LDW_M_A(t_mem code)    { return ldw_m_a(a_mm()); }
 228   int LDW_NSP_A(t_mem code)  { return ldw_m_a(a_n_sp()); }
 229   int LDW_NNZ_A(t_mem code)  { return ldw_m_a(a_nn_z()); }
 230   int LDW_X_A(t_mem code)    { cX.W(acc16->get()); return resGO; }
 231   int LDW_Z_A(t_mem code)    { cZ.W(acc16->get()); return resGO; }
 232   int LDW_AM_X(t_mem code)   { return ldw_m_r(a_acc16(), rX); }
 233   int LDW_NAM_X(t_mem code)  { return ldw_m_r(a_n_acc16(), rX); }
 234   int LDW_NNAM_X(t_mem code) { return ldw_m_r(a_nn_acc16(), rX); }
 235   int LDW_DSP_A(t_mem code);
 236   // other moves
 237   int LDI_Z_Y(t_mem code);
 238   int LDWI_Z_Y(t_mem code);
 239   int PUSH_M(t_mem code);
 240   int PUSH_NSP(t_mem code);
 241   int PUSH_A(t_mem code);
 242   int PUSH_NY(t_mem code);
 243   int PUSH_I(t_mem code);
 244   int PUSHW_M(t_mem code);
 245   int PUSHW_NSP(t_mem code);
 246   int PUSHW_NNZ(t_mem code);
 247   int PUSHW_A(t_mem code);
 248   int PUSHW_I(t_mem code);
 249   int POP_A(t_mem code);
 250   int POPW_A(t_mem code);
 251   int XCH_A_NSP(t_mem code);
 252   int XCH_A_Y(t_mem code);
 253   int XCH_A_A(t_mem code);
 254   int XCHW_Y_Z(t_mem code);
 255   int XCHW_Z_NSP(t_mem code);
 256   int CAX(t_mem code);
 257   int CAXW(t_mem code);
 258   int CLR_M(t_mem code);
 259   int CLR_NSP(t_mem code);
 260   int CLR_A(t_mem code);
 261   int CLR_NY(t_mem code);
 262   int CLRW_M(t_mem code);
 263   int CLRW_NSP(t_mem code);
 264   int CLRW_NNZ(t_mem code);
 265   int CLRW_A(t_mem code);
 266   int xchb(int b);
 267   int XCHB_0(t_mem code) { return xchb(0); }
 268   int XCHB_1(t_mem code) { return xchb(1); }
 269   int XCHB_2(t_mem code) { return xchb(2); }
 270   int XCHB_3(t_mem code) { return xchb(3); }
 271   int XCHB_4(t_mem code) { return xchb(4); }
 272   int XCHB_5(t_mem code) { return xchb(5); }
 273   int XCHB_6(t_mem code) { return xchb(6); }
 274   int XCHB_7(t_mem code) { return xchb(7); }
 275
 276   // arithmetic (ALU) instructions: ialu.cc
 277   // 8-bit 2-op-inst
 278   int add8(class cl_cell8 *op1, class cl_cell8 *op2, bool usec, bool memop);
 279   int sub8(class cl_cell8 *op1, class cl_cell8 *op2, bool usec, bool memop, bool cmp);
 280   int Or8 (class cl_cell8 *op1, class cl_cell8 *op2, bool memop);
 281   int And8(class cl_cell8 *op1, class cl_cell8 *op2, bool memop);
 282   int Xor8(class cl_cell8 *op1, class cl_cell8 *op2, bool memop);
 283   int ADD_I  (t_mem code) { return add8(acc8, &m_i()   , false, false); }
 284   int ADD_M  (t_mem code) { return add8(acc8, &m_mm()  , false, true ); }
 285   int ADD_NSP(t_mem code) { return add8(acc8, &m_n_sp(), false, true ); }
 286   int ADD_NNZ(t_mem code) { return add8(acc8, &m_nn_z(), false, true ); }
 287   int ADD_ZL (t_mem code) { return add8(acc8, &cZL     , false, false); }
 288   int ADD_XH (t_mem code) { return add8(acc8, &cXH     , false, false); }
 289   int ADD_YL (t_mem code) { return add8(acc8, &cYL     , false, false); }
 290   int ADD_YH (t_mem code) { return add8(acc8, &cYH     , false, false); }
 291   int ADC_I  (t_mem code) { return add8(acc8, &m_i()   , true , false); }
 292   int ADC_M  (t_mem code) { return add8(acc8, &m_mm()  , true , true ); }
 293   int ADC_NSP(t_mem code) { return add8(acc8, &m_n_sp(), true , true ); }
 294   int ADC_NNZ(t_mem code) { return add8(acc8, &m_nn_z(), true , true ); }
 295   int ADC_ZL (t_mem code) { return add8(acc8, &cZL     , true , false); }
 296   int ADC_XH (t_mem code) { return add8(acc8, &cXH     , true , false); }
 297   int ADC_YL (t_mem code) { return add8(acc8, &cYL     , true , false); }
 298   int ADC_YH (t_mem code) { return add8(acc8, &cYH     , true , false); }
 299   int SUB_M  (t_mem code) { return sub8(acc8, &m_mm()  , false, true , false); }
 300   int SUB_NSP(t_mem code) { return sub8(acc8, &m_n_sp(), false, true , false); }
 301   int SUB_NNZ(t_mem code) { return sub8(acc8, &m_nn_z(), false, true , false); }
 302   int SUB_ZL (t_mem code) { return sub8(acc8, &cZL     , false, false, false); }
 303   int SUB_XH (t_mem code) { return sub8(acc8, &cXH     , false, false, false); }
 304   int SUB_YL (t_mem code) { return sub8(acc8, &cYL     , false, false, false); }
 305   int SUB_YH (t_mem code) { return sub8(acc8, &cYH     , false, false, false); }
 306   int SBC_M  (t_mem code) { return sub8(acc8, &m_mm()  , true , true , false); }
 307   int SBC_NSP(t_mem code) { return sub8(acc8, &m_n_sp(), true , true , false); }
 308   int SBC_NNZ(t_mem code) { return sub8(acc8, &m_nn_z(), true , true , false); }
 309   int SBC_ZL (t_mem code) { return sub8(acc8, &cZL     , true , false, false); }
 310   int SBC_XH (t_mem code) { return sub8(acc8, &cXH     , true , false, false); }
 311   int SBC_YL (t_mem code) { return sub8(acc8, &cYL     , true , false, false); }
 312   int SBC_YH (t_mem code) { return sub8(acc8, &cYH     , true , false, false); }
 313   int CP_I   (t_mem code) { return sub8(acc8, &m_i()   , false, true , true ); }
 314   int CP_M   (t_mem code) { return sub8(acc8, &m_mm()  , false, true , true ); }
 315   int CP_NSP (t_mem code) { return sub8(acc8, &m_n_sp(), false, true , true ); }
 316   int CP_NNZ (t_mem code) { return sub8(acc8, &m_nn_z(), false, true , true ); }
 317   int CP_ZL  (t_mem code) { return sub8(acc8, &cZL     , false, false, true ); }
 318   int CP_XH  (t_mem code) { return sub8(acc8, &cXH     , false, false, true ); }
 319   int CP_YL  (t_mem code) { return sub8(acc8, &cYL     , false, false, true ); }
 320   int CP_YH  (t_mem code) { return sub8(acc8, &cYH     , false, false, true ); }
 321   int OR_I   (t_mem code) { return Or8 (acc8, &m_i()   , true  ); }
 322   int OR_M   (t_mem code) { return Or8 (acc8, &m_mm()  , true  ); }
 323   int OR_NSP (t_mem code) { return Or8 (acc8, &m_n_sp(), true  ); }
 324   int OR_NNZ (t_mem code) { return Or8 (acc8, &m_nn_z(), true  ); }
 325   int OR_ZL  (t_mem code) { return Or8 (acc8, &cZL     , false ); }
 326   int OR_XH  (t_mem code) { return Or8 (acc8, &cXH     , false ); }
 327   int OR_YL  (t_mem code) { return Or8 (acc8, &cYL     , false ); }
 328   int OR_YH  (t_mem code) { return Or8 (acc8, &cYH     , false ); }
 329   int AND_I  (t_mem code) { return And8(acc8, &m_i()   , true  ); }
 330   int AND_M  (t_mem code) { return And8(acc8, &m_mm()  , true  ); }
 331   int AND_NSP(t_mem code) { return And8(acc8, &m_n_sp(), true  ); }
 332   int AND_NNZ(t_mem code) { return And8(acc8, &m_nn_z(), true  ); }
 333   int AND_ZL (t_mem code) { return And8(acc8, &cZL     , false ); }
 334   int AND_XH (t_mem code) { return And8(acc8, &cXH     , false ); }
 335   int AND_YL (t_mem code) { return And8(acc8, &cYL     , false ); }
 336   int AND_YH (t_mem code) { return And8(acc8, &cYH     , false ); }
 337   int XOR_I  (t_mem code) { return Xor8(acc8, &m_i()   , true  ); }
 338   int XOR_M  (t_mem code) { return Xor8(acc8, &m_mm()  , true  ); }
 339   int XOR_NSP(t_mem code) { return Xor8(acc8, &m_n_sp(), true  ); }
 340   int XOR_NNZ(t_mem code) { return Xor8(acc8, &m_nn_z(), true  ); }
 341   int XOR_ZL (t_mem code) { return Xor8(acc8, &cZL     , false ); }
 342   int XOR_XH (t_mem code) { return Xor8(acc8, &cXH     , false ); }
 343   int XOR_YL (t_mem code) { return Xor8(acc8, &cYL     , false ); }
 344   int XOR_YH (t_mem code) { return Xor8(acc8, &cYH     , false ); }
 345   // 8-bit 1-op-inst
 346   int SRL_M(t_mem code);
 347   int SRL_NSP(t_mem code);
 348   int SRL_A(t_mem code);
 349   int SRL_NY(t_mem code);
 350   int SLL_M(t_mem code);
 351   int SLL_NSP(t_mem code);
 352   int SLL_A(t_mem code);
 353   int SLL_NY(t_mem code);
 354   int RRC_M(t_mem code);
 355   int RRC_NSP(t_mem code);
 356   int RRC_A(t_mem code);
 357   int RRC_NY(t_mem code);
 358   int RLC_M(t_mem code);
 359   int RLC_NSP(t_mem code);
 360   int RLC_A(t_mem code);
 361   int RLC_NY(t_mem code);
 362   int INC_M(t_mem code);
 363   int INC_NSP(t_mem code);
 364   int INC_A(t_mem code);
 365   int INC_NY(t_mem code);
 366   int DEC_M(t_mem code);
 367   int DEC_NSP(t_mem code);
 368   int DEC_A(t_mem code);
 369   int DEC_NY(t_mem code);
 370   int TST_M(t_mem code);
 371   int TST_NSP(t_mem code);
 372   int TST_A(t_mem code);
 373   int TST_NY(t_mem code);
 374
 375   // 16-bit 2-op-inst
 376   virtual u16_t add16(u16_t a, u16_t b, int c, bool sub);
 377   virtual int add16(u16_t opaddr, bool usec);
 378   virtual int add16(/*op2=x*/bool usec);
 379   virtual int sub16(u16_t opaddr, bool usec);
 380   virtual int sub16(/*op2=x*/bool usec);
 381   virtual u16_t or16(u16_t a, u16_t b);
 382   virtual int or16(u16_t opaddr);
 383   virtual int or16(void);
 384   virtual u16_t xor16(u16_t a, u16_t b);
 385   virtual int xor16(u16_t opaddr);
 386   virtual int xor16(void);
 387   int SUBW_M  (t_mem code) { return sub16(a_mm()  , false); }
 388   int SUBW_NSP(t_mem code) { return sub16(a_n_sp(), false); }
 389   int SUBW_X  (t_mem code) { return sub16(          false); }
 390   int SBCW_M  (t_mem code) { return sub16(a_mm()  , true); }
 391   int SBCW_NSP(t_mem code) { return sub16(a_n_sp(), true); }
 392   int SBCW_X  (t_mem code) { return sub16(          true); }
 393   int ADDW_I  (t_mem code) { return add16(a_i()   , false); }
 394   int ADDW_M  (t_mem code) { return add16(a_mm()  , false); }
 395   int ADDW_NSP(t_mem code) { return add16(a_n_sp(), false); }
 396   int ADDW_X  (t_mem code) { return add16(          false); }
 397   int ADCW_I  (t_mem code) { return add16(a_i()   , true); }
 398   int ADCW_M  (t_mem code) { return add16(a_mm()  , true); }
 399   int ADCW_NSP(t_mem code) { return add16(a_n_sp(), true); }
 400   int ADCW_X  (t_mem code) { return add16(          true); }
 401   int ORW_I   (t_mem code) { return or16(a_i()    ); }
 402   int ORW_M   (t_mem code) { return or16(a_mm()   ); }
 403   int ORW_NSP (t_mem code) { return or16(a_n_sp() ); }
 404   int ORW_X   (t_mem code) { return or16(         ); }
 405   int XORW_I  (t_mem code) { return xor16(a_i()   ); }
 406   int XORW_M  (t_mem code) { return xor16(a_mm()  ); }
 407   int XORW_NSP(t_mem code) { return xor16(a_n_sp()); }
 408   int XORW_X  (t_mem code) { return xor16(        ); }
 409
 410   // 16-bit 1-op-inst
 411   int INCW_M(t_mem code);
 412   int INCW_NSP(t_mem code);
 413   int INCW_NNZ(t_mem code);
 414   int INCW_A(t_mem code);
 415   int ADCW1_M(t_mem code);
 416   int ADCW1_NSP(t_mem code);
 417   int ADCW1_NNZ(t_mem code);
 418   int ADCW1_A(t_mem code);
 419   int SBCW1_M(t_mem code);
 420   int SBCW1_NSP(t_mem code);
 421   int SBCW1_NNZ(t_mem code);
 422   int SBCW1_A(t_mem code);
 423   int TSTW1_M(t_mem code);
 424   int TSTW1_NSP(t_mem code);
 425   int TSTW1_NNZ(t_mem code);
 426   int TSTW1_A(t_mem code);
 427
 428   // 8-bit 0-op-inst
 429   int mad(class cl_cell8 &op);
 430   int ROT(t_mem code);
 431   int SRA(t_mem code);
 432   int DAA(t_mem code);
 433   int BOOL_A(t_mem code);
 434   int MSK(t_mem code);
 435   int MAD_M(t_mem code)   { return mad(m_mm()); }
 436   int MAD_NSP(t_mem code) { return mad(m_n_sp()); }
 437   int MAD_NNZ(t_mem code) { return mad(m_nn_z()); }
 438   int MAD_Z(t_mem code)   { return mad(m_z()); }
 439   int XCH_F_NSP(t_mem code);
 440
 441   // 16-bit 0-op-inst
 442   int MUL(t_mem code);
 443   int NEGW(t_mem code);
 444   int BOOLW(t_mem code);
 445   int SRLW(t_mem code);
 446   int SLLW(t_mem code);
 447   int RRCW(t_mem code);
 448   int RLCW_A(t_mem code);
 449   int RLCW_NSP(t_mem code);
 450   int RRCW_NSP(t_mem code);
 451   int SRAW(t_mem code);
 452   int ADDW_SP_D(t_mem code);
 453   int ADDW_A_D(t_mem code);
 454   int LDW_A_SP(t_mem code);
 455   int CPW(t_mem code);
 456   int INCNW(t_mem code);
 457   int DECW_NSP(t_mem code);
 458   int SLLW_A_XL(t_mem code);
 459   int SEX(t_mem code);
 460   int ZEX(t_mem code);
 461
 462   // branches: ibranch.cc
 463   virtual int JP_I(t_mem code);
 464   virtual int JP_A(t_mem code);
 465   virtual int CALL_I(t_mem code);
 466   virtual int CALL_A(t_mem code);
 467   virtual int RET(t_mem code);
 468   virtual int RETI(t_mem code);
 469   virtual int jr(bool cond);
 470   virtual int JR(t_mem code)    { return jr(true); }
 471   virtual int DNJNZ(t_mem code);
 472   virtual int JRZ(t_mem code)   { return jr(COND_Z); }
 473   virtual int JRNZ(t_mem code)  { return jr(COND_NZ); }
 474   virtual int JRC(t_mem code)   { return jr(COND_C); }
 475   virtual int JRNC(t_mem code)  { return jr(COND_NC); }
 476   virtual int JRN(t_mem code)   { return jr(COND_N); }
 477   virtual int JRNN(t_mem code)  { return jr(COND_NN); }
 478   virtual int JRNO(t_mem code)  { return jr((prefixes&P_SWAP) ? COND_O : COND_NO); }
 479   virtual int JRSGE(t_mem code) { return jr(COND_SGE); }
 480   virtual int JRSLT(t_mem code) { return jr(COND_SLT); }
 481   virtual int JRSLE(t_mem code) { return jr((prefixes&P_SWAP) ? COND_SGT : COND_SLE); }
 482   virtual int JRLE(t_mem code)  { return jr((prefixes&P_SWAP) ? COND_GT : COND_LE); }
 483
 484   // other instructions: inst.cc
 485   virtual int NOP(t_mem code);
 486   virtual int TRAP(t_mem code);
 487   virtual int THRD(t_mem code);
 488 };
 489
 490
 491 enum f8cpu_confs
 492   {
 493    f8cpu_sp_limit       = 0,
 494    f8cpu_nuof           = 1
 495   };
 496
 497 class cl_f8_cpu: public cl_hw
 498 {
 499 public:
 500   cl_f8_cpu(class cl_uc *auc);
 501   virtual int init(void);
 502   virtual unsigned int cfg_size(void) { return f8cpu_nuof; }
 503   virtual const char *cfg_help(t_addr addr);
 504
 505   virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
 506 };
 507
 508
 509 #endif
 510
 511 /* End of f8.src/f8cl.h */