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HEAD
Limit regression tests in ucsim to 100000000 vclk cycles.
[sdcc.git]
/
sdcc
/
support
/
regression
/
ports
/
ucr2k
/
uCsim.cmd
blob
7ce5d7729cf3a36a8321660817334c325c3caa2a
1
set
error non
-
classified off
2
set
error unknown_code off
3
set
error memory off
4
set
error stack off
5
set
hw simif rom
0x7fff
6
vcd0_on
=
0
7
dreg0_on
=
0
8
step
100000000
vclk
9
state
10
quit