sdcc/sim/ucsim/f8.src/imove.cc

   1 /*
   2  * Simulator of microcontrollers (imove.cc)
   3  *
   4  * Copyright (C) 2022 Drotos Daniel, Talker Bt.
   5  *
   6  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
   7  *
   8  */
   9
  10 /* This file is part of microcontroller simulator: ucsim.
  11
  12 UCSIM is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2 of the License, or
  15 (at your option) any later version.
  16
  17 UCSIM is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with UCSIM; see the file COPYING.  If not, write to the Free
  24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  25 02111-1307, USA. */
  26 /*@1@*/
  27
  28 #include "f8cl.h"
  29
  30
  31 int
  32 cl_f8::ld8_a_i(u8_t op2)
  33 {
  34   acc8->W(op2);
  35   return resGO;
  36 }
  37
  38 int
  39 cl_f8::ld8_a_m(class cl_cell8 &m)
  40 {
  41   uint8_t v = m.R();
  42   rF&= ~(flagN|flagZ);
  43   if (v & 0x80) rF|= flagN;
  44   if (!v) rF|= flagZ;
  45   acc8->W(v);
  46   vc.rd++;
  47   return resGO;
  48 }
  49
  50 int
  51 cl_f8::ld8_m_a(class cl_cell8 &m)
  52 {
  53   m.W(acc8->get());
  54   vc.wr++;
  55   return resGO;
  56 }
  57
  58 int
  59 cl_f8::ld8_a_r(class cl_cell8 &r)
  60 {
  61   class cl_cell8 *op1, *op2;
  62   IFSWAP
  63     {
  64       op2= acc8;
  65       op1= &r;
  66     }
  67   else
  68     {
  69       op1= acc8;
  70       op2= &r;
  71     }
  72   op1->W(op2->R());
  73   return resGO;
  74 }
  75
  76 int
  77 cl_f8::ldw_a_i(u16_t op2)
  78 {
  79   acc16->W(op2);
  80   return resGO;
  81 }
  82
  83 int
  84 cl_f8::ldw_a_m(u16_t addr)
  85 {
  86   u16_t v= rom->read(addr);
  87   v+= (rom->read(addr+1))*256;
  88   rF&= ~(flagN|flagZ);
  89   if (v & 0x8000) rF|= flagN;
  90   if (!v) rF|= flagZ;
  91   acc16->W(v);
  92   vc.rd+= 2;
  93   return resGO;
  94 }
  95
  96 int
  97 cl_f8::ldw_m_a(u16_t addr)
  98 {
  99   u16_t v= acc16->get();
 100   rom->write(addr, v);
 101   rom->write(addr+1, v>>8);
 102   vc.wr+= 2;
 103   return resGO;
 104 }
 105
 106 int
 107 cl_f8::ldw_m_r(u16_t addr, u16_t r)
 108 {
 109   rom->write(addr, r);
 110   rom->write(addr+1, r>>8);
 111   vc.wr+= 2;
 112   return resGO;
 113 }
 114
 115 int
 116 cl_f8::ldw_a_r(u16_t r)
 117 {
 118   acc16->W(r);
 119   return resGO;
 120 }
 121
 122 int
 123 cl_f8::LDW_A_SP(t_mem code)
 124 {
 125   IFSWAP
 126     cSP.W(acc16->get());
 127   else
 128     acc16->W(rSP);
 129   return resGO;
 130 }
 131
 132 int
 133 cl_f8::XCH_F_NSP(t_mem code)
 134 {
 135   class cl_cell8 &c= m_n_sp();
 136   u8_t t= rF;
 137   rF = c.R();
 138   vc.rd++;
 139   c.W(t);
 140   vc.wr++;
 141   return resGO;
 142 }
 143
 144 int
 145 cl_f8::LDW_DSP_A(t_mem code)
 146 {
 147   i8_t d= fetch();
 148   u16_t pa= rSP+d;
 149   u16_t a= read_addr(rom, pa);
 150   vc.rd+= 2;
 151   u16_t v= acc16->get();
 152   rom->write(a++, v);
 153   rom->write(a, v>>8);
 154   vc.wr+= 2;
 155   return resGO;
 156 }
 157
 158
 159 int
 160 cl_f8::PUSH_M(t_mem code)
 161 {
 162   class cl_cell8 &c= m_mm();
 163   push1(c.R());
 164   vc.rd++;
 165   return resGO;
 166 }
 167
 168 int
 169 cl_f8::PUSH_NSP(t_mem code)
 170 {
 171   class cl_cell8 &c= m_n_sp();
 172   push1(c.R());
 173   vc.rd++;
 174   return resGO;
 175 }
 176
 177 int
 178 cl_f8::PUSH_A(t_mem code)
 179 {
 180   push1(acc8->get()); // TODO?
 181   return resGO;
 182 }
 183
 184 int
 185 cl_f8::PUSH_NY(t_mem code)
 186 {
 187   class cl_cell8 &c= m_n_y();
 188   push1(c.R());
 189   vc.rd++;
 190   return resGO;
 191 }
 192
 193 int
 194 cl_f8::PUSH_I(t_mem code)
 195 {
 196   push1(fetch());
 197   return resGO;
 198 }
 199
 200 int
 201 cl_f8::PUSHW_M(t_mem code)
 202 {
 203   u16_t a= a_mm();
 204   u16_t v= read_addr(rom, a);
 205   vc.rd+= 2;
 206   push2(v);
 207   return resGO;
 208 }
 209
 210 int
 211 cl_f8::PUSHW_NSP(t_mem code)
 212 {
 213   u16_t a= a_n_sp();
 214   u16_t v= read_addr(rom, a);
 215   vc.rd+= 2;
 216   push2(v);
 217   return resGO;
 218 }
 219
 220 int
 221 cl_f8::PUSHW_NNZ(t_mem code)
 222 {
 223   u16_t a= a_nn_z();
 224   u16_t v= read_addr(rom, a);
 225   vc.rd+= 2;
 226   push2(v);
 227   return resGO;
 228 }
 229
 230 int
 231 cl_f8::PUSHW_A(t_mem code)
 232 {
 233   u16_t v= acc16->get();
 234   push2(v);
 235   return resGO;
 236 }
 237
 238 int
 239 cl_f8::PUSHW_I(t_mem code)
 240 {
 241   u8_t l, h;
 242   l= fetch();
 243   h= fetch();
 244   push2(h, l);
 245   return resGO;
 246 }
 247
 248 int
 249 cl_f8::POP_A(t_mem code)
 250 {
 251   acc8->W(pop1());
 252   return resGO;
 253 }
 254
 255 int
 256 cl_f8::POPW_A(t_mem code)
 257 {
 258   acc16->W(pop2());
 259   return resGO;
 260 }
 261
 262 int
 263 cl_f8::XCH_A_NSP(t_mem code)
 264 {
 265   class cl_cell8 &c= m_n_sp();
 266   u8_t t= acc8->get();
 267   acc8->W(c.R());
 268   vc.rd++;
 269   c.W(t);
 270   vc.wr++;
 271   return resGO;
 272 }
 273
 274 int
 275 cl_f8::XCH_A_Y(t_mem code)
 276 {
 277   class cl_cell8 &c= m_y();
 278   u8_t t= acc8->get();
 279   acc8->W(c.R());
 280   vc.rd++;
 281   c.W(t);
 282   vc.wr++;
 283   return resGO;
 284 }
 285
 286 int
 287 cl_f8::XCH_A_A(t_mem code)
 288 {
 289   u16_t t= acc16->get();
 290   u8_t h, l;
 291   h= t>>8;
 292   l= t;
 293   acc16->W(l*256+h);
 294   return resGO;
 295 }
 296
 297 int
 298 cl_f8::XCHW_Y_Z(t_mem code)
 299 {
 300   u16_t t= read_addr(rom, rZ);
 301   vc.rd+= 2;
 302   rom->write(rZ  , rYL);
 303   rom->write(rZ+1, rYH);
 304   vc.wr+= 2;
 305   cY.W(t);
 306   return resGO;
 307 }
 308
 309 int
 310 cl_f8::XCHW_Z_NSP(t_mem code)
 311 {
 312   u16_t a= a_n_sp();
 313   u16_t t= read_addr(rom, a);
 314   vc.rd+= 2;
 315   rom->write(a  , rZL);
 316   rom->write(a+1, rZH);
 317   vc.wr+= 2;
 318   cZ.W(t);
 319   return resGO;
 320 }
 321
 322 int
 323 cl_f8::CAX(t_mem code)
 324 {
 325   // if ((y) == xh) (z) = xl; else xh = (y);
 326   u8_t my= rom->read(rY);
 327   vc.rd++;
 328   if (my == rXH)
 329     {
 330       rom->write(rZ, rXL);
 331       vc.wr++;
 332     }
 333   else
 334     {
 335       cXH.W(my);
 336     }
 337   return 0;
 338 }
 339
 340 int
 341 cl_f8::CAXW(t_mem code)
 342 {
 343   // if ((y) == z) (y) = x; else x = (y);
 344   u16_t my= read_addr(rom, rY);
 345   vc.rd+= 2;
 346   if (my == rZ)
 347     {
 348       rom->write(rY  , rX);
 349       rom->write(rY+1, rX>>8);
 350       vc.wr+= 2;
 351     }
 352   else
 353     {
 354       cX.W(my);
 355     }
 356   return 0;
 357 }
 358
 359 int
 360 cl_f8::CLR_M(t_mem code)
 361 {
 362   class cl_cell8 &c= m_mm();
 363   c.W(0);
 364   vc.wr++;
 365   return resGO;
 366 }
 367
 368 int
 369 cl_f8::CLR_NSP(t_mem code)
 370 {
 371   class cl_cell8 &c= m_n_sp();
 372   c.W(0);
 373   vc.wr++;
 374   return resGO;
 375 }
 376
 377 int
 378 cl_f8::CLR_A(t_mem code)
 379 {
 380   acc8->W(0);
 381   return resGO;
 382 }
 383
 384 int
 385 cl_f8::CLR_NY(t_mem code)
 386 {
 387   class cl_cell8 &c= m_n_y();
 388   c.W(0);
 389   vc.wr++;
 390   return resGO;
 391 }
 392
 393 int
 394 cl_f8::CLRW_M(t_mem code)
 395 {
 396   u16_t a= a_mm();
 397   rom->write(a  , 0);
 398   rom->write(a+1, 0);
 399   vc.wr+= 2;
 400   return resGO;
 401 }
 402
 403 int
 404 cl_f8::CLRW_NSP(t_mem code)
 405 {
 406   u16_t a= a_n_sp();
 407   rom->write(a  , 0);
 408   rom->write(a+1, 0);
 409   vc.wr+= 2;
 410   return resGO;
 411 }
 412
 413 int
 414 cl_f8::CLRW_NNZ(t_mem code)
 415 {
 416   u16_t a= a_nn_z();
 417   rom->write(a  , 0);
 418   rom->write(a+1, 0);
 419   vc.wr+= 2;
 420   return resGO;
 421 }
 422
 423 int
 424 cl_f8::CLRW_A(t_mem code)
 425 {
 426   acc16->write(0);
 427   return resGO;
 428 }
 429
 430 int
 431 cl_f8::xchb(int b)
 432 {
 433   b&= 7;
 434   u8_t mask= 1<<b;
 435   class cl_cell8 &c= m_mm();
 436   u8_t t= c.R(), a= acc8->get();
 437   u8_t mbit= t&mask;
 438   vc.rd++;
 439   t&= ~mask;
 440   if (a & 1) t|= mask;
 441   acc8->W(mbit?1:0);
 442   c.write(t);
 443   rF&= ~flagZ;
 444   if (!mbit) rF|= flagZ;
 445   cF.W(rF);
 446   vc.wr++;
 447   return resGO;
 448 }
 449
 450
 451 /* End of f8.src/imove.cc */