sdcc/sim/ucsim/stypes.h

   1 /*
   2  * Simulator of microcontrollers (stypes.h)
   3  *
   4  * Copyright (C) 1997,16 Drotos Daniel, Talker Bt.
   5  *
   6  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
   7  *
   8  */
   9
  10 /* This file is part of microcontroller simulator: ucsim.
  11
  12 UCSIM is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2 of the License, or
  15 (at your option) any later version.
  16
  17 UCSIM is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with UCSIM; see the file COPYING.  If not, write to the Free
  24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  25 02111-1307, USA. */
  26 /*@1@*/
  27
  28 #ifndef STYPES_HEADER
  29 #define STYPES_HEADER
  30
  31 #include "ddconfig.h"
  32
  33 #ifdef HAVE_INTTYPES_H
  34 #include <inttypes.h>
  35 #endif
  36 #ifdef HAVE_STDINT_H
  37 #include <stdint.h>
  38 #endif
  39
  40 //typedef int8_t TYPE_BYTE;
  41 //typedef uint8_t TYPE_UBYTE;
  42 //typedef int16_t TYPE_WORD;
  43 //typedef uint16_t TYPE_UWORD;
  44 //typedef int32_t TYPE_DWORD;
  45 //typedef uint32_t TYPE_UDWORD;
  46
  47 typedef unsigned char   uchar;
  48 typedef unsigned int    uint;
  49 typedef unsigned long   ulong;
  50
  51 typedef   signed TYPE_BYTE  i8_t;
  52 typedef unsigned TYPE_BYTE  u8_t;
  53 typedef   signed TYPE_WORD  i16_t;
  54 typedef unsigned TYPE_WORD  u16_t;
  55 typedef   signed TYPE_DWORD i32_t;
  56 typedef unsigned TYPE_DWORD u32_t;
  57 typedef   signed TYPE_QWORD i64_t;
  58 typedef unsigned TYPE_QWORD u64_t;
  59
  60 typedef /*i64_t*/u32_t          t_addr;         /* 32 bit max */
  61 typedef u32_t           t_mem;          /* 32 bit max */
  62 typedef i32_t           t_smem;         /* signed 32 bit memory */
  63
  64 #define SPECA SPEC_QWORD
  65 #define SPECM SPEC_DWORD
  66
  67 #define AI(addr)   ((int)(addr))
  68 #define AU(addr)   ((unsigned int)(addr))
  69 #define AI8(addr)  (AI((addr)&0xff))
  70 #define AU8(addr)  (AU((addr)&0xff))
  71 #define AI16(addr) (AI((addr)&0xffff))
  72 #define AU16(addr) (AU((addr)&0xffff))
  73 #define AI32(addr) (AI((addr)&0xffffffff))
  74 #define AU32(addr) (AU((addr)&0xffffffff))
  75
  76 #define MI(v)      ((int)(v))
  77 #define MU(v)      ((unsigned int)(v))
  78 #define MI8(v)     (MI((v)&0xff))
  79 #define MU8(v)     (MU((v)&0xff))
  80 #define MI32(v)    (MI((v)&0xffffffff))
  81 #define MU32(v)    (MU((v)&0xffffffff))
  82
  83 enum {
  84   max_mem_size= 0x40000000              /* 1 GB */
  85 };
  86
  87 struct id_element
  88 {
  89   int id;
  90   const char *id_string;
  91 };
  92
  93 enum error_type {
  94   err_unknown  = 0x01,
  95   err_error    = 0x02,
  96   err_warning  = 0x04
  97 };
  98
  99 // table of disassembled instructions
 100 struct dis_entry
 101 {
 102   /*uint64_t*/long long code, mask; // max 8 byte of code
 103   char  branch;
 104   i8_t length;
 105   const char *mnemonic;
 106   bool is_call;
 107   uchar ticks;
 108   void *info;
 109 };
 110
 111 // table entry of SFR and BIT names
 112 struct name_entry
 113 {
 114   int           cpu_type;
 115   t_addr        addr;
 116   const char    *name;
 117 };
 118
 119 enum cpu_type {
 120   CPU_NONE      = 0,
 121
 122   CPU_51        = 0x0001,
 123   CPU_31        = 0x0002,
 124   CPU_52        = 0x0004,
 125   CPU_32        = 0x0008,
 126   CPU_51R       = 0x0010,
 127   CPU_89C51R    = 0x0020,
 128   CPU_251       = 0x0040,
 129   CPU_DS320     = 0x0080,
 130   CPU_DS390     = 0x0100,
 131   CPU_DS390F    = 0x0200,
 132   CPU_C521      = 0x0400,
 133   CPU_517       = 0x0800,
 134   CPU_F380      = 0x1000,
 135   CPU_XC88X     = 0x2000,
 136
 137   CPU_ALL_51    = (CPU_51|CPU_31),
 138   CPU_ALL_52    = (CPU_52|CPU_32|CPU_51R|CPU_89C51R|CPU_251|
 139                    CPU_DS320|CPU_DS390|CPU_DS390F|
 140                    CPU_C521|CPU_517|CPU_XC88X|
 141                    CPU_F380),
 142   CPU_ALL_DS3X0 = (CPU_DS320|CPU_DS390|CPU_DS390F),
 143
 144   CPU_AVR       = 0x0001,
 145   CPU_ALL_AVR   = (CPU_AVR),
 146
 147   CPU_Z80       = 0x0001,
 148   CPU_Z180      = 0x0002,
 149   CPU_LR35902   = 0x0004,
 150   CPU_R2K       = 0x0008,
 151   CPU_R3KA      = 0x0010,
 152   CPU_EZ80      = 0x0020,
 153   CPU_Z80N      = 0x0040,
 154   CPU_GB80      = 0x0080,
 155   CPU_R3K       = 0x0100,
 156   CPU_R4K       = 0x0200,
 157   CPU_R5K       = 0x0400,
 158   CPU_R6K       = 0x0800,
 159   CPU_R800      = 0x1000,
 160   CPU_ALL_Z80   = (CPU_Z80|CPU_Z180|CPU_LR35902|CPU_EZ80|
 161                    CPU_Z80N|CPU_GB80|
 162                    CPU_R800),
 163   CPU_ALL_RXK   =  (CPU_R3K|CPU_R4K|CPU_R5K|CPU_R6K|CPU_R3KA|CPU_R2K),
 164
 165   CPU_XA        = 0x0001,
 166   CPU_ALL_XA    = (CPU_XA),
 167
 168   CPU_HC08      = 0x0001,
 169   CPU_HCS08     = 0x0002,
 170   CPU_ALL_HC08  = (CPU_HC08|CPU_HCS08),
 171
 172   CPU_HC11      = 0x0004,
 173   CPU_HC12      = 0x0008,
 174   CPU_ALL_HC12  = (CPU_HC11|CPU_HC12),
 175
 176   CPU_PBLAZE_3  = 0x0001,
 177   CPU_PBLAZE_6  = 0x0002,
 178   CPU_ALL_PBLAZE= (CPU_PBLAZE_3|CPU_PBLAZE_6),
 179
 180   CPU_STM8S             = 0x0001,               // S and AF family
 181   CPU_STM8AF            = 0x0001,
 182   CPU_STM8SAF           = 0x0001,
 183   // Devices of S family 0x00 00 00 XX
 184   DEV_STM8S903          = 0x00000001,
 185   DEV_STM8S003          = 0x00000002,
 186   DEV_STM8S005          = 0x00000004,
 187   DEV_STM8S007          = 0x00000008,
 188   DEV_STM8S103          = 0x00000010,
 189   DEV_STM8S105          = 0x00000020,
 190   DEV_STM8S207          = 0x00000040,
 191   DEV_STM8S208          = 0x00000080,
 192   DEV_STM8S             = (DEV_STM8S903|
 193                            DEV_STM8S003|
 194                            DEV_STM8S005|
 195                            DEV_STM8S007|
 196                            DEV_STM8S103|
 197                            DEV_STM8S105|
 198                            DEV_STM8S207|
 199                            DEV_STM8S208),
 200   // Devices of AF family 0x00 00 0X 00
 201   DEV_STM8AF52          = 0x00000100,
 202   DEV_STM8AF62_12       = 0x00000200,
 203   DEV_STM8AF62_46       = 0x00000400,
 204   DEV_STM8AF            = (DEV_STM8AF52|
 205                            DEV_STM8AF62_12|
 206                            DEV_STM8AF62_46),
 207
 208   DEV_STM8SAF           = (DEV_STM8S|DEV_STM8AF),
 209
 210   CPU_STM8L             = 0x0002,               // AL and L family
 211   // Devices of AL family 0x00 0X 00 00
 212   DEV_STM8AL3xE         = 0x00010000,
 213   DEV_STM8AL3x8         = 0x00020000,
 214   DEV_STM8AL3x346       = 0x00040000,
 215   DEV_STM8AL            = (DEV_STM8AL3xE|
 216                            DEV_STM8AL3x8|
 217                            DEV_STM8AL3x346),
 218   // Devices of L family 0xXX 00 00 00
 219   DEV_STM8L051          = 0x01000000,
 220   DEV_STM8L052C         = 0x02000000,
 221   DEV_STM8L052R         = 0x04000000,
 222   DEV_STM8L151x23       = 0x08000000,
 223   DEV_STM8L15x46        = 0x10000000,
 224   DEV_STM8L15x8         = 0x20000000,
 225   DEV_STM8L162          = 0x40000000,
 226   DEV_STM8L             = (DEV_STM8L051|
 227                            DEV_STM8L052C|
 228                            DEV_STM8L052R|
 229                            DEV_STM8L151x23|
 230                            DEV_STM8L15x46|
 231                            DEV_STM8L15x8|
 232                            DEV_STM8L162),
 233
 234   DEV_STM8ALL           = (DEV_STM8AL|DEV_STM8L),
 235
 236   CPU_STM8101           = 0x0004,               // L101 family
 237   CPU_STM8L101          = 0x0004,
 238   // Devices of L101 family 0x00 00 X0 00
 239   DEV_STM8101           = 0x00001000,
 240   DEV_STM8L101          = 0x00001000,
 241
 242   CPU_ALL_STM8  = (CPU_STM8S|CPU_STM8L|CPU_STM8101),
 243
 244   CPU_ST7       = 0x0001,
 245   CPU_ALL_ST7   = (CPU_ST7),
 246
 247   // MOS6502 and variants
 248   CPU_6502      = 0x0001,       // NMOS
 249   CPU_6502C     = 0x0002,       // 6502 + HALT pin
 250   CPU_6510      = 0x0004,       // 6502 + integrated port
 251   CPU_8500      = 0x0008,       // 6510 CMOS
 252   CPU_8502      = 0x0010,       // 8500 2 MHz
 253   CPU_7501      = 0x0020,       // 6502 HMOS-1
 254   CPU_8501      = 0x0040,       // 6502 HMOS-2
 255
 256   // 6502 based, but not 100% compatible
 257   CPU_65C02     = 0x0100,       // extended inst.set
 258   CPU_65C02S    = 0x0200,       // 65C02 variant, different inst.set
 259   CPU_65CE02    = 0x0400,       // extension of 65C02
 260
 261   // Intel 8080, 8085
 262   CPU_I8080     = 0x0001,
 263   CPU_I8085     = 0x0002,
 264
 265   CPU_PDK13     = 0x0001,
 266   CPU_PDK14     = 0x0002,
 267   CPU_PDK15     = 0x0003,
 268
 269   CPU_F8        = 0x0001,
 270
 271   CPU_P1516     = 0x0001,
 272   CPU_P2223     = 0x0002,
 273
 274   // MCS48 Intel 8048 family
 275   CPU_I8021     = 0x0001, // 1k-? "1"
 276   CPU_I8022     = 0x0002, // 2k-? "2"
 277   CPU_MCS21     = (CPU_I8021|CPU_I8022),
 278   CPU_I8035     = 0x0010, // 0k-64 "8"
 279   CPU_I8039     = 0x0020, // 0k-128 "8"
 280   CPU_I8040     = 0x0040, // 0k-256 "8"
 281   CPU_MCS30     = (CPU_I8035|CPU_I8039|CPU_I8040),
 282   CPU_I8041     = 0x0100, // "4"
 283   CPU_I8041A    = 0x0200, // "A"
 284   CPU_MCS41     = (CPU_I8041|CPU_I8041A),
 285   CPU_I8048     = 0x1000, // 1k-64 "8"
 286   CPU_I8049     = 0x2000, // 2k-128 "8"
 287   CPU_I8050     = 0x4000, // 4k-256 "8"
 288   CPU_MCS48     = (CPU_I8048|CPU_I8049|CPU_I8050),
 289
 290   // technology
 291   CPU_CMOS      = 0x0001,
 292   CPU_HMOS      = 0x0002,
 293 };
 294
 295
 296 struct cpu_entry
 297 {
 298   const char *type_str;
 299   enum cpu_type  type;
 300   int  subtype;
 301   const char *type_help;
 302   const char *sub_help;
 303 };
 304
 305 /* Classes of memories, this is index on the list */
 306 enum mem_class
 307 {
 308   MEM_ROM= 0,
 309   MEM_XRAM,
 310   MEM_IRAM,
 311   MEM_SFR,
 312   MEM_DUMMY,
 313   MEM_IXRAM,
 314   MEM_STACK,
 315   MEM_TYPES
 316 };
 317
 318 #define MEM_SFR_ID      "sfr"
 319 #define MEM_XRAM_ID     "xram"
 320 #define MEM_IXRAM_ID    "ixram"
 321 #define MEM_IRAM_ID     "iram"
 322 #define MEM_STACK_ID    "stack"
 323 #define MEM_ROM_ID      "rom"
 324
 325 // States of simulator
 326 enum sim_state {
 327   SIM_NONE      = 0,
 328   SIM_GO        = 0x01, // Processor is running
 329   SIM_QUIT      = 0x02, // Program must exit
 330   SIM_STARTEMU  = 0x04, // Start emulation mode
 331   SIM_EMU       = 0x08  // Run in emulation mode
 332 };
 333
 334 /* States of CPU */
 335 enum cpu_state {
 336   stGO          = 0,    /* Normal state */
 337   stIDLE        = 1,    /* Idle mode is active */
 338   stPD          = 2     /* Power Down mode is active */
 339 };
 340
 341 /* Result of instruction simulation */
 342 enum inst_result {
 343   resGO         = 0,    /* OK, go on */
 344   resWDTRESET   = 1,    /* Reset by WDT */
 345   resINTERRUPT  = 2,    /* Interrupt accepted */
 346   resSTOP       = 100,  /* Stop if result greater than this */
 347   resHALT       = 101,  /* Serious error, halt CPU */
 348   resINV_ADDR   = 102,  /* Invalid indirect address */
 349   resSTACK_OV   = 103,  /* Stack overflow */
 350   resBREAKPOINT = 104,  /* Fetch Breakpoint */
 351   resUSER       = 105,  /* Stopped by user */
 352   resINV_INST   = 106,  /* Invalid instruction */
 353   resINST_INV   = 106,  /* Invalid instruction */
 354   resINV        = 106,  /* Invalid instruction */
 355   resBITADDR    = 107,  /* Bit address is uninterpretable */
 356   resERROR      = 108,  /* Error happened during instruction exec */
 357   resSTEP       = 109,  /* Step command done, no more exex needed */
 358   resSIMIF      = 110,  /* Stopped by simulated prog itself through sim interface */
 359   resNOT_DONE   = 111,  /* Instruction has not simulated */
 360   resEVENTBREAK = 112,  /* Event breakpoint */
 361   resSELFJUMP   = 113,  /* Jump to itself */
 362 };
 363
 364 #define BIT_MASK(bitaddr) (1 << (bitaddr & 0x07))
 365
 366
 367 /* Type of breakpoints */
 368 enum brk_perm
 369 {
 370   brkFIX,       /* f */
 371   brkDYNAMIC    /* d */
 372 };
 373
 374 enum brk_type
 375 {
 376   brkFETCH,     /* f */
 377   brkEVENT      /* e */
 378 };
 379
 380 enum brk_event
 381 {
 382   brkNONE,
 383   brkWXRAM,     /* wx */
 384   brkRXRAM,     /* rx */
 385   brkRCODE,     /* rc */
 386   brkWIRAM,     /* wi */
 387   brkRIRAM,     /* ri */
 388   brkWSFR,      /* ws */
 389   brkRSFR,      /* rs */
 390   brkREAD,
 391   brkWRITE,
 392   brkACCESS
 393 };
 394
 395 /* Interrupt levels */
 396 enum intr_levels {
 397 //IT_NO         = -1, /* not in interrupt service */
 398   IT_LOW        = 1, /* low level interrupt service */
 399   IT_HIGH       = 2 /* service of high priority interrupt */
 400 };
 401
 402 /* cathegories of hw elements (peripherals) */
 403 enum hw_cath {
 404   HW_DUMMY      = 0x0000,
 405   HW_TIMER      = 0x0002,
 406   HW_UART       = 0x0004,
 407   HW_PORT       = 0x0008,
 408   HW_GPIO       = 0x0008,
 409   HW_PCA        = 0x0010,
 410   HW_INTERRUPT  = 0x0020,
 411   HW_WDT        = 0x0040,
 412   HW_SIMIF      = 0x0080,
 413   HW_RESET      = 0x0100,
 414   HW_CLOCK      = 0x0200,
 415   HW_CALC       = 0x0400,
 416   HW_FLASH      = 0x0800,
 417   HW_CPU        = 0x1000
 418 };
 419
 420 // Events that can happen in peripherals
 421 enum hw_event {
 422   EV_OVERFLOW,
 423   EV_PORT_CHANGED,
 424   EV_T2_MODE_CHANGED,
 425   EV_CLK_ON,
 426   EV_CLK_OFF
 427 };
 428
 429 // flags of hw units
 430 enum hw_flags {
 431   HWF_NONE      = 0,
 432   HWF_INSIDE    = 0x0001,
 433   HWF_OUTSIDE   = 0x0002,
 434   HWF_MISC      = 0x0004
 435 };
 436
 437 /* Letter cases */
 438 enum letter_case {
 439   case_upper,  /* all is upper case */
 440   case_lower,  /* all is lower case */
 441   case_case    /* first letter is upper, others are lower case */
 442 };
 443
 444
 445 #endif
 446
 447 /* End of stypes.h */