sdcc/sim/ucsim/src/core/motorola.src/glob68.cc

   1 /*
   2  * Simulator of microcontrollers (glob68.cc)
   3  *
   4  * Copyright (C) 2020 Drotos Daniel
   5  *
   6  * To contact author send email to dr.dkdb@gmail.com
   7  *
   8  */
   9
  10 /* This file is part of microcontroller simulator: ucsim.
  11
  12 UCSIM is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2 of the License, or
  15 (at your option) any later version.
  16
  17 UCSIM is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with UCSIM; see the file COPYING.  If not, write to the Free
  24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  25 02111-1307, USA. */
  26 /*@1@*/
  27
  28 #include "glob68.h"
  29
  30
  31 // code mask branch len mn call tick
  32 struct dis_entry disass_m6800[]=
  33   {
  34     { 0x01, 0xff, ' ', 1, "NOP" },
  35     { 0x06, 0xff, ' ', 1, "TAP" },
  36     { 0x07, 0xff, ' ', 1, "TAP" },
  37     { 0x08, 0xff, ' ', 1, "INX" },
  38     { 0x09, 0xff, ' ', 1, "DEX" },
  39     { 0x0a, 0xff, ' ', 1, "CLV" },
  40     { 0x0b, 0xff, ' ', 1, "SEV" },
  41     { 0x0c, 0xff, ' ', 1, "CLC" },
  42     { 0x0d, 0xff, ' ', 1, "SEC" },
  43     { 0x0e, 0xff, ' ', 1, "CLI" },
  44     { 0x0f, 0xff, ' ', 1, "SEI" },
  45
  46     { 0x10, 0xff, ' ', 1, "SBA" },
  47     { 0x11, 0xff, ' ', 1, "CBA" },
  48     { 0x16, 0xff, ' ', 1, "TAB" },
  49     { 0x17, 0xff, ' ', 1, "TBA" },
  50     { 0x19, 0xff, ' ', 1, "DAA" },
  51     { 0x1b, 0xff, ' ', 1, "ABA" },
  52
  53     { 0x20, 0xff, 'r', 2, "BRA %r" },
  54     { 0x22, 0xff, 'R', 2, "BHI %r" },
  55     { 0x23, 0xff, 'R', 2, "BLS %r" },
  56     { 0x24, 0xff, 'R', 2, "BCC %r" },
  57     { 0x25, 0xff, 'R', 2, "BCS %r" },
  58     { 0x26, 0xff, 'R', 2, "BNE %r" },
  59     { 0x27, 0xff, 'R', 2, "BEQ %r" },
  60     { 0x28, 0xff, 'R', 2, "BVC %r" },
  61     { 0x29, 0xff, 'R', 2, "BVS %r" },
  62     { 0x2a, 0xff, 'R', 2, "BPL %r" },
  63     { 0x2b, 0xff, 'R', 2, "BMI %r" },
  64     { 0x2c, 0xff, 'R', 2, "BGE %r" },
  65     { 0x2d, 0xff, 'R', 2, "BLT %r" },
  66     { 0x2e, 0xff, 'R', 2, "BGT %r" },
  67     { 0x2f, 0xff, 'R', 2, "BLE %r" },
  68
  69     { 0x30, 0xff, ' ', 1, "TSX" },
  70     { 0x31, 0xff, ' ', 1, "INS" },
  71     { 0x32, 0xff, ' ', 1, "PUL A" },
  72     { 0x33, 0xff, ' ', 1, "PUL B" },
  73     { 0x34, 0xff, ' ', 1, "DES" },
  74     { 0x35, 0xff, ' ', 1, "TXS" },
  75     { 0x36, 0xff, ' ', 1, "PSH A" },
  76     { 0x37, 0xff, ' ', 1, "PSH B" },
  77     { 0x39, 0xff, '_', 1, "RTS" },
  78
  79     { 0x3b, 0xff, '_', 1, "RTI" },
  80     { 0x3e, 0xff, ' ', 1, "WAI" },
  81     { 0x3f, 0xff, 's', 1, "SWI" },
  82
  83     { 0x40, 0xff, ' ', 1, "NEG A" },
  84     { 0x43, 0xff, ' ', 1, "COM A" },
  85     { 0x44, 0xff, ' ', 1, "LSR A" },
  86     { 0x46, 0xff, ' ', 1, "ROR A" },
  87     { 0x47, 0xff, ' ', 1, "ASR A" },
  88     { 0x48, 0xff, ' ', 1, "ASL A" },
  89     { 0x49, 0xff, ' ', 1, "ROL A" },
  90     { 0x4a, 0xff, ' ', 1, "DEC A" },
  91     { 0x4c, 0xff, ' ', 1, "INC A" },
  92     { 0x4d, 0xff, ' ', 1, "TST A" },
  93     { 0x4f, 0xff, ' ', 1, "CLR A" },
  94
  95     { 0x50, 0xff, ' ', 1, "NEG B" },
  96     { 0x53, 0xff, ' ', 1, "COM B" },
  97     { 0x54, 0xff, ' ', 1, "LSR B" },
  98     { 0x56, 0xff, ' ', 1, "ROR B" },
  99     { 0x57, 0xff, ' ', 1, "ASR B" },
 100     { 0x58, 0xff, ' ', 1, "ASL B" },
 101     { 0x59, 0xff, ' ', 1, "ROL B" },
 102     { 0x5a, 0xff, ' ', 1, "DEC B" },
 103     { 0x5c, 0xff, ' ', 1, "INC B" },
 104     { 0x5d, 0xff, ' ', 1, "TST B" },
 105     { 0x5f, 0xff, ' ', 1, "CLR B" },
 106
 107     { 0x60, 0xff, ' ', 2, "NEG %x" },
 108     { 0x63, 0xff, ' ', 2, "COM %x" },
 109     { 0x64, 0xff, ' ', 2, "LSR %x" },
 110     { 0x66, 0xff, ' ', 2, "ROR %x" },
 111     { 0x67, 0xff, ' ', 2, "ASR %x" },
 112     { 0x68, 0xff, ' ', 2, "ASL %x" },
 113     { 0x69, 0xff, ' ', 2, "ROL %x" },
 114     { 0x6a, 0xff, ' ', 2, "DEC %x" },
 115     { 0x6c, 0xff, ' ', 2, "INC %x" },
 116     { 0x6d, 0xff, ' ', 2, "TST %x" },
 117     { 0x6e, 0xff, '_', 2, "JMP %x" },
 118     { 0x6f, 0xff, ' ', 2, "CLR %x" },
 119
 120     { 0x70, 0xff, ' ', 3, "NEG %e" },
 121     { 0x73, 0xff, ' ', 3, "COM %e" },
 122     { 0x74, 0xff, ' ', 3, "LSR %e" },
 123     { 0x76, 0xff, ' ', 3, "ROR %e" },
 124     { 0x77, 0xff, ' ', 3, "ASR %e" },
 125     { 0x78, 0xff, ' ', 3, "ASL %e" },
 126     { 0x79, 0xff, ' ', 3, "ROL %e" },
 127     { 0x7a, 0xff, ' ', 3, "DEC %e" },
 128     { 0x7c, 0xff, ' ', 3, "INC %e" },
 129     { 0x7d, 0xff, ' ', 3, "TST %e" },
 130     { 0x7e, 0xff, 'e', 3, "JMP %e" },
 131     { 0x7f, 0xff, ' ', 3, "CLR %e" },
 132
 133     { 0x80, 0xff, ' ', 2, "SUB A,%b" },
 134     { 0x81, 0xff, ' ', 2, "CMP A,%b" },
 135     { 0x82, 0xff, ' ', 2, "SBC A,%b" },
 136     { 0x84, 0xff, ' ', 2, "AND A,%b" },
 137     { 0x85, 0xff, ' ', 2, "BIT A,%b" },
 138     { 0x86, 0xff, ' ', 2, "LDA A,%b" },
 139     { 0x88, 0xff, ' ', 2, "EOR A,%b" },
 140     { 0x89, 0xff, ' ', 2, "ADC A,%b" },
 141     { 0x8a, 0xff, ' ', 2, "ORA A,%b" },
 142     { 0x8b, 0xff, ' ', 2, "ADD A,%b" },
 143     { 0x8c, 0xff, ' ', 3, "CPX %B" },
 144     { 0x8d, 0xff, ' ', 2, "BSR %r" },
 145     { 0x8e, 0xff, ' ', 3, "LDS %B" },
 146
 147     { 0x90, 0xff, ' ', 2, "SUB A,%d" },
 148     { 0x91, 0xff, ' ', 2, "CMP A,%d" },
 149     { 0x92, 0xff, ' ', 2, "SBC A,%d" },
 150     { 0x94, 0xff, ' ', 2, "AND A,%d" },
 151     { 0x95, 0xff, ' ', 2, "BIT A,%d" },
 152     { 0x96, 0xff, ' ', 2, "LDA A,%d" },
 153     { 0x97, 0xff, ' ', 2, "STA A,%d" },
 154     { 0x98, 0xff, ' ', 2, "EOR A,%d" },
 155     { 0x99, 0xff, ' ', 2, "ADC A,%d" },
 156     { 0x9a, 0xff, ' ', 2, "ORA A,%d" },
 157     { 0x9b, 0xff, ' ', 2, "ADD A,%d" },
 158     { 0x9c, 0xff, ' ', 2, "CPX %D" },
 159     { 0x9e, 0xff, ' ', 2, "LDS %d" },
 160     { 0x9f, 0xff, ' ', 2, "STS %d" },
 161
 162     { 0xa0, 0xff, ' ', 2, "SUB A,%x" },
 163     { 0xa1, 0xff, ' ', 2, "CMP A,%x" },
 164     { 0xa2, 0xff, ' ', 2, "SBC A,%x" },
 165     { 0xa4, 0xff, ' ', 2, "AND A,%x" },
 166     { 0xa5, 0xff, ' ', 2, "BIT A,%x" },
 167     { 0xa6, 0xff, ' ', 2, "LDA A,%x" },
 168     { 0xa7, 0xff, ' ', 2, "STA A,%x" },
 169     { 0xa8, 0xff, ' ', 2, "EOR A,%x" },
 170     { 0xa9, 0xff, ' ', 2, "ADC A,%x" },
 171     { 0xaa, 0xff, ' ', 2, "ORA A,%x" },
 172     { 0xab, 0xff, ' ', 2, "ADD A,%x" },
 173     { 0xac, 0xff, ' ', 2, "CPX %X" },
 174     { 0xad, 0xff, '_', 2, "JSR %X" },
 175     { 0xae, 0xff, ' ', 2, "LDS %X" },
 176     { 0xaf, 0xff, ' ', 2, "STS %X" },
 177
 178     { 0xb0, 0xff, ' ', 3, "SUB A,%e" },
 179     { 0xb1, 0xff, ' ', 3, "CMP A,%e" },
 180     { 0xb2, 0xff, ' ', 3, "SBC A,%e" },
 181     { 0xb4, 0xff, ' ', 3, "AND A,%e" },
 182     { 0xb5, 0xff, ' ', 3, "BIT A,%e" },
 183     { 0xb6, 0xff, ' ', 3, "LDA A,%e" },
 184     { 0xb7, 0xff, ' ', 3, "STA A,%e" },
 185     { 0xb8, 0xff, ' ', 3, "EOR A,%e" },
 186     { 0xb9, 0xff, ' ', 3, "ADC A,%e" },
 187     { 0xba, 0xff, ' ', 3, "ORA A,%e" },
 188     { 0xbb, 0xff, ' ', 3, "ADD A,%e" },
 189     { 0xbc, 0xff, ' ', 3, "CPX %E" },
 190     { 0xbd, 0xff, 'E', 3, "JSR %e" },
 191     { 0xbe, 0xff, ' ', 3, "LDS %E" },
 192     { 0xbf, 0xff, ' ', 3, "STS %E" },
 193
 194     { 0xc0, 0xff, ' ', 2, "SUB B,%b" },
 195     { 0xc1, 0xff, ' ', 2, "CMP B,%b" },
 196     { 0xc2, 0xff, ' ', 2, "SBC B,%b" },
 197     { 0xc4, 0xff, ' ', 2, "AND B,%b" },
 198     { 0xc5, 0xff, ' ', 2, "BIT B,%b" },
 199     { 0xc6, 0xff, ' ', 2, "LDA B,%b" },
 200     { 0xc8, 0xff, ' ', 2, "EOR B,%b" },
 201     { 0xc9, 0xff, ' ', 2, "ADC B,%b" },
 202     { 0xca, 0xff, ' ', 2, "ORA B,%b" },
 203     { 0xcb, 0xff, ' ', 2, "ADD B,%b" },
 204     { 0xce, 0xff, ' ', 3, "LDX %B" },
 205
 206     { 0xd0, 0xff, ' ', 2, "SUB B,%d" },
 207     { 0xd1, 0xff, ' ', 2, "CMP B,%d" },
 208     { 0xd2, 0xff, ' ', 2, "SBC B,%d" },
 209     { 0xd4, 0xff, ' ', 2, "AND B,%d" },
 210     { 0xd5, 0xff, ' ', 2, "BIT B,%d" },
 211     { 0xd6, 0xff, ' ', 2, "LDA B,%d" },
 212     { 0xd7, 0xff, ' ', 2, "STA B,%d" },
 213     { 0xd8, 0xff, ' ', 2, "EOR B,%d" },
 214     { 0xd9, 0xff, ' ', 2, "ADC B,%d" },
 215     { 0xda, 0xff, ' ', 2, "ORA B,%d" },
 216     { 0xdb, 0xff, ' ', 2, "ADD B,%d" },
 217     { 0xde, 0xff, ' ', 2, "LDX %d" },
 218     { 0xdf, 0xff, ' ', 2, "STX %d" },
 219
 220     { 0xe0, 0xff, ' ', 2, "SUB B,%x" },
 221     { 0xe1, 0xff, ' ', 2, "CMP B,%x" },
 222     { 0xe2, 0xff, ' ', 2, "SBC B,%x" },
 223     { 0xe4, 0xff, ' ', 2, "AND B,%x" },
 224     { 0xe5, 0xff, ' ', 2, "BIT B,%x" },
 225     { 0xe6, 0xff, ' ', 2, "LDA B,%x" },
 226     { 0xe7, 0xff, ' ', 2, "STA B,%x" },
 227     { 0xe8, 0xff, ' ', 2, "EOR B,%x" },
 228     { 0xe9, 0xff, ' ', 2, "ADC B,%x" },
 229     { 0xea, 0xff, ' ', 2, "ORA B,%x" },
 230     { 0xeb, 0xff, ' ', 2, "ADD B,%x" },
 231     { 0xee, 0xff, ' ', 2, "LDX %x" },
 232     { 0xef, 0xff, ' ', 2, "STX %x" },
 233
 234     { 0xf0, 0xff, ' ', 3, "SUB B,%e" },
 235     { 0xf1, 0xff, ' ', 3, "CMP B,%e" },
 236     { 0xf2, 0xff, ' ', 3, "SBC B,%e" },
 237     { 0xf4, 0xff, ' ', 3, "AND B,%e" },
 238     { 0xf5, 0xff, ' ', 3, "BIT B,%e" },
 239     { 0xf6, 0xff, ' ', 3, "LDA B,%e" },
 240     { 0xf7, 0xff, ' ', 3, "STA B,%e" },
 241     { 0xf8, 0xff, ' ', 3, "EOR B,%e" },
 242     { 0xf9, 0xff, ' ', 3, "ADC B,%e" },
 243     { 0xfa, 0xff, ' ', 3, "ORA B,%e" },
 244     { 0xfb, 0xff, ' ', 3, "ADD B,%e" },
 245     { 0xfe, 0xff, ' ', 3, "LDX %e" },
 246     { 0xff, 0xff, ' ', 3, "STX %e" },
 247
 248     { 0, 0, 0, 0, 0, 0 }
 249   };
 250
 251 /* End of motorola.src/glob68.cc */