sdcc/sim/ucsim/src/sims/mos6502.src/glob.cc

   1 /*
   2  * Simulator of microcontrollers (glob.cc)
   3  *
   4  * Copyright (C) 2020 Drotos Daniel
   5  *
   6  * To contact author send email to dr.dkdb@gmail.com
   7  *
   8  */
   9
  10 /* This file is part of microcontroller simulator: ucsim.
  11
  12 UCSIM is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2 of the License, or
  15 (at your option) any later version.
  16
  17 UCSIM is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with UCSIM; see the file COPYING.  If not, write to the Free
  24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  25 02111-1307, USA. */
  26 /*@1@*/
  27
  28 #include "glob.h"
  29
  30
  31 instruction_wrapper_fn itab[256];
  32
  33 /*      Formats
  34         x (ind,X)
  35         y (ind),Y
  36         a abs
  37         z zpg
  38         X zpg,X
  39         Y zpg,Y
  40         i abs,X
  41         p abs.Y
  42         r rel
  43         # imm8
  44         3 (ind)
  45         4 (zind)
  46 */
  47
  48 // code mask branch len mn call tick
  49 struct dis_entry disass_mos6502[]=
  50   {
  51     { 0xea, 0xff, ' ', 1, "NOP" },
  52     { 0x00, 0xff, ' ', 1, "BRK" },
  53     { 0x40, 0xff, 'x', 1, "RTI" },
  54     { 0x58, 0xff, ' ', 1, "CLI" },
  55     { 0x78, 0xff, ' ', 1, "SEI" },
  56     { 0x08, 0xff, ' ', 1, "PHP" },
  57     { 0x18, 0xff, ' ', 1, "CLC" },
  58     { 0x28, 0xff, ' ', 1, "PLP" },
  59     { 0x38, 0xff, ' ', 1, "SEC" },
  60     { 0x48, 0xff, ' ', 1, "PHA" },
  61     { 0x68, 0xff, ' ', 1, "PLA" },
  62     { 0x88, 0xff, ' ', 1, "DEY" },
  63     { 0x98, 0xff, ' ', 1, "TYA" },
  64     { 0xa8, 0xff, ' ', 1, "TAY" },
  65     { 0xb8, 0xff, ' ', 1, "CLV" },
  66     { 0xc8, 0xff, ' ', 1, "INY" },
  67     { 0xd8, 0xff, ' ', 1, "CLD" },
  68     { 0xe8, 0xff, ' ', 1, "INX" },
  69     { 0xf8, 0xff, ' ', 1, "SED" },
  70     { 0x8a, 0xff, ' ', 1, "TXA" },
  71     { 0x9a, 0xff, ' ', 1, "TXS" },
  72     { 0xaa, 0xff, ' ', 1, "TAX" },
  73     { 0xba, 0xff, ' ', 1, "TSX" },
  74     { 0xca, 0xff, ' ', 1, "DEX" },
  75
  76     { 0x01, 0xff, ' ', 2, "ORA %x" },
  77     { 0x11, 0xff, ' ', 2, "ORA %y" },
  78     { 0x05, 0xff, ' ', 2, "ORA %z" },
  79     { 0x15, 0xff, ' ', 2, "ORA %X" },
  80     { 0x09, 0xff, ' ', 2, "ORA %#" },
  81     { 0x19, 0xff, ' ', 3, "ORA %p" },
  82     { 0x0d, 0xff, ' ', 3, "ORA %a" },
  83     { 0x1d, 0xff, ' ', 3, "ORA %i" },
  84
  85     { 0x21, 0xff, ' ', 2, "AND %x" },
  86     { 0x31, 0xff, ' ', 2, "AND %y" },
  87     { 0x25, 0xff, ' ', 2, "AND %z" },
  88     { 0x35, 0xff, ' ', 2, "AND %X" },
  89     { 0x29, 0xff, ' ', 2, "AND %#" },
  90     { 0x39, 0xff, ' ', 3, "AND %p" },
  91     { 0x2d, 0xff, ' ', 3, "AND %a" },
  92     { 0x3d, 0xff, ' ', 3, "AND %i" },
  93
  94     { 0x41, 0xff, ' ', 2, "EOR %x" },
  95     { 0x51, 0xff, ' ', 2, "EOR %y" },
  96     { 0x45, 0xff, ' ', 2, "EOR %z" },
  97     { 0x55, 0xff, ' ', 2, "EOR %X" },
  98     { 0x49, 0xff, ' ', 2, "EOR %#" },
  99     { 0x59, 0xff, ' ', 3, "EOR %p" },
 100     { 0x4d, 0xff, ' ', 3, "EOR %a" },
 101     { 0x5d, 0xff, ' ', 3, "EOR %i" },
 102
 103     { 0x61, 0xff, ' ', 2, "ADC %x" },
 104     { 0x71, 0xff, ' ', 2, "ADC %y" },
 105     { 0x65, 0xff, ' ', 2, "ADC %z" },
 106     { 0x75, 0xff, ' ', 2, "ADC %X" },
 107     { 0x69, 0xff, ' ', 2, "ADC %#" },
 108     { 0x79, 0xff, ' ', 3, "ADC %p" },
 109     { 0x6d, 0xff, ' ', 3, "ADC %a" },
 110     { 0x7d, 0xff, ' ', 3, "ADC %i" },
 111
 112     { 0x81, 0xff, ' ', 2, "STA %x" },
 113     { 0x91, 0xff, ' ', 2, "STA %y" },
 114     { 0x85, 0xff, ' ', 2, "STA %z" },
 115     { 0x95, 0xff, ' ', 2, "STA %X" },
 116     { 0x99, 0xff, ' ', 3, "STA %p" },
 117     { 0x8d, 0xff, ' ', 3, "STA %a" },
 118     { 0x9d, 0xff, ' ', 3, "STA %i" },
 119
 120     { 0xa1, 0xff, ' ', 2, "LDA %x" },
 121     { 0xb1, 0xff, ' ', 2, "LDA %y" },
 122     { 0xa5, 0xff, ' ', 2, "LDA %z" },
 123     { 0xb5, 0xff, ' ', 2, "LDA %X" },
 124     { 0xa9, 0xff, ' ', 2, "LDA %#" },
 125     { 0xb9, 0xff, ' ', 3, "LDA %p" },
 126     { 0xad, 0xff, ' ', 3, "LDA %a" },
 127     { 0xbd, 0xff, ' ', 3, "LDA %i" },
 128
 129     { 0xc1, 0xff, ' ', 2, "CMP %x" },
 130     { 0xd1, 0xff, ' ', 2, "CMP %y" },
 131     { 0xc5, 0xff, ' ', 2, "CMP %z" },
 132     { 0xd5, 0xff, ' ', 2, "CMP %X" },
 133     { 0xc9, 0xff, ' ', 2, "CMP %#" },
 134     { 0xd9, 0xff, ' ', 3, "CMP %p" },
 135     { 0xcd, 0xff, ' ', 3, "CMP %a" },
 136     { 0xdd, 0xff, ' ', 3, "CMP %i" },
 137
 138     { 0xe1, 0xff, ' ', 2, "SBC %x" },
 139     { 0xf1, 0xff, ' ', 2, "SBC %y" },
 140     { 0xe5, 0xff, ' ', 2, "SBC %z" },
 141     { 0xf5, 0xff, ' ', 2, "SBC %X" },
 142     { 0xe9, 0xff, ' ', 2, "SBC %#" },
 143     { 0xf9, 0xff, ' ', 3, "SBC %p" },
 144     { 0xed, 0xff, ' ', 3, "SBC %a" },
 145     { 0xfd, 0xff, ' ', 3, "SBC %i" },
 146
 147     { 0x84, 0xff, ' ', 2, "STY %z" },
 148     { 0x94, 0xff, ' ', 2, "STY %X" },
 149     { 0x8c, 0xff, ' ', 3, "STY %a" },
 150     { 0x86, 0xff, ' ', 2, "STX %z" },
 151     { 0x96, 0xff, ' ', 2, "STX %Y" },
 152     { 0x8e, 0xff, ' ', 3, "STX %a" },
 153
 154     { 0xa0, 0xff, ' ', 2, "LDY %#" },
 155     { 0xa4, 0xff, ' ', 2, "LDY %z" },
 156     { 0xb4, 0xff, ' ', 2, "LDY %X" },
 157     { 0xac, 0xff, ' ', 3, "LDY %a" },
 158     { 0xbc, 0xff, ' ', 3, "LDY %i" },
 159     { 0xa2, 0xff, ' ', 2, "LDX %#" },
 160     { 0xa6, 0xff, ' ', 2, "LDX %z" },
 161     { 0xb6, 0xff, ' ', 2, "LDX %Y" },
 162     { 0xae, 0xff, ' ', 3, "LDX %a" },
 163     { 0xbe, 0xff, ' ', 3, "LDX %p" },
 164
 165     { 0xc0, 0xff, ' ', 2, "CPY %#" },
 166     { 0xc4, 0xff, ' ', 2, "CPY %z" },
 167     { 0xcc, 0xff, ' ', 3, "CPY %a" },
 168     { 0xe0, 0xff, ' ', 2, "CPX %#" },
 169     { 0xe4, 0xff, ' ', 2, "CPX %z" },
 170     { 0xec, 0xff, ' ', 3, "CPX %a" },
 171
 172     { 0xe6, 0xff, ' ', 2, "INC %z" },
 173     { 0xf6, 0xff, ' ', 2, "INC %X" },
 174     { 0xee, 0xff, ' ', 3, "INC %a" },
 175     { 0xfe, 0xff, ' ', 3, "INC %i" },
 176     { 0xc6, 0xff, ' ', 2, "DEC %z" },
 177     { 0xd6, 0xff, ' ', 2, "DEC %X" },
 178     { 0xce, 0xff, ' ', 3, "DEC %a" },
 179     { 0xde, 0xff, ' ', 3, "DEC %i" },
 180
 181     { 0x06, 0xff, ' ', 2, "ASL %z" },
 182     { 0x16, 0xff, ' ', 2, "ASL %X" },
 183     { 0x0a, 0xff, ' ', 1, "ASL A" },
 184     { 0x0e, 0xff, ' ', 3, "ASL %a" },
 185     { 0x1e, 0xff, ' ', 3, "ASL %i" },
 186
 187     { 0x46, 0xff, ' ', 2, "LSR %z" },
 188     { 0x56, 0xff, ' ', 2, "LSR %X" },
 189     { 0x4a, 0xff, ' ', 1, "LSR A" },
 190     { 0x4e, 0xff, ' ', 3, "LSR %a" },
 191     { 0x5e, 0xff, ' ', 3, "LSR %i" },
 192
 193     { 0x26, 0xff, ' ', 2, "ROL %z" },
 194     { 0x36, 0xff, ' ', 2, "ROL %X" },
 195     { 0x2a, 0xff, ' ', 1, "ROL A" },
 196     { 0x2e, 0xff, ' ', 3, "ROL %a" },
 197     { 0x3e, 0xff, ' ', 3, "ROL %i" },
 198
 199     { 0x66, 0xff, ' ', 2, "ROR %z" },
 200     { 0x76, 0xff, ' ', 2, "ROR %X" },
 201     { 0x6a, 0xff, ' ', 1, "ROR A" },
 202     { 0x6e, 0xff, ' ', 3, "ROR %a" },
 203     { 0x7e, 0xff, ' ', 3, "ROR %i" },
 204
 205     { 0x24, 0xff, ' ', 2, "BIT %z" },
 206     { 0x2c, 0xff, ' ', 3, "BIT %a" },
 207
 208     { 0x4c, 0xff, 'j', 3, "JMP %j" },
 209     { 0x6c, 0xff, 'x', 3, "JMP %J" },
 210
 211     { 0x20, 0xff, 's', 3, "JSR %j" },
 212     { 0x60, 0xff, 'x', 1, "RTS" },
 213
 214     { 0x10, 0xff, 'b', 2, "BPL %r" },
 215     { 0x30, 0xff, 'b', 2, "BMI %r" },
 216     { 0x50, 0xff, 'b', 2, "BVC %r" },
 217     { 0x70, 0xff, 'b', 2, "BVS %r" },
 218     { 0x90, 0xff, 'b', 2, "BCC %r" },
 219     { 0xb0, 0xff, 'b', 2, "BCS %r" },
 220     { 0xd0, 0xff, 'b', 2, "BNE %r" },
 221     { 0xf0, 0xff, 'b', 2, "BEQ %r" },
 222
 223     { 0, 0, 0, 0, 0, 0 }
 224   };
 225
 226 struct dis_entry disass_mos65c02[]=
 227   {
 228     { 0x80, 0xff, 'b', 2, "BRA %r" },
 229
 230     { 0x02, 0xff, ' ', 2, "NOP %#" },
 231     { 0x12, 0xff, ' ', 2, "ORA %4" },
 232     { 0x22, 0xff, ' ', 2, "NOP %#" },
 233     { 0x32, 0xff, ' ', 2, "AND %4" },
 234     { 0x42, 0xff, ' ', 2, "NOP %#" },
 235     { 0x52, 0xff, ' ', 2, "EOR %4" },
 236     { 0x62, 0xff, ' ', 2, "NOP %#" },
 237     { 0x72, 0xff, ' ', 2, "ADC %4" },
 238     { 0x82, 0xff, ' ', 2, "NOP %#" },
 239     { 0x92, 0xff, ' ', 2, "STA %4" },
 240     { 0xb2, 0xff, ' ', 2, "LDA %4" },
 241     { 0xc2, 0xff, ' ', 2, "NOP %#" },
 242     { 0xd2, 0xff, ' ', 2, "CMP %4" },
 243     { 0xe2, 0xff, ' ', 2, "NOP %#" },
 244     { 0xf2, 0xff, ' ', 2, "SBC %4" },
 245
 246     { 0x04, 0xff, ' ', 2, "TSB %z" },
 247     { 0x14, 0xff, ' ', 2, "TRB %z" },
 248     { 0x34, 0xff, ' ', 2, "BIT %X" },
 249     { 0x44, 0xff, ' ', 2, "NOP %z" },
 250     { 0x54, 0xff, ' ', 2, "NOP %X" },
 251     { 0x64, 0xff, ' ', 2, "STZ %z" },
 252     { 0x74, 0xff, ' ', 2, "STZ %X" },
 253     { 0xd4, 0xff, ' ', 2, "NOP %X" },
 254     { 0xf4, 0xff, ' ', 2, "NOP %X" },
 255
 256     { 0x89, 0xff, ' ', 2, "BIT %#" },
 257
 258     { 0x1a, 0xff, ' ', 1, "INA" },
 259     { 0x3a, 0xff, ' ', 1, "DEA" },
 260     { 0x5a, 0xff, ' ', 1, "PHY" },
 261     { 0x7a, 0xff, ' ', 1, "PLY" },
 262     { 0xda, 0xff, ' ', 1, "PHX" },
 263     { 0xfa, 0xff, ' ', 1, "PLX" },
 264
 265     { 0x0c, 0xff, ' ', 3, "TSB %a" },
 266     { 0x1c, 0xff, ' ', 3, "TRB %a" },
 267     { 0x3c, 0xff, ' ', 3, "BIT %i" },
 268     { 0x5c, 0xff, ' ', 3, "NOP %a" },
 269     { 0x7c, 0xff, 'x', 3, "JMP %I" },
 270     { 0xdc, 0xff, ' ', 3, "NOP %a" },
 271     { 0xfc, 0xff, ' ', 3, "NOP %a" },
 272     { 0x9c, 0xff, ' ', 3, "STZ %a" },
 273
 274     { 0x9e, 0xff, ' ', 3, "STZ %i" },
 275
 276     { 0x03, 0x0f, ' ', 1, "NOP" },
 277     { 0x0b, 0x0f, ' ', 1, "NOP" },
 278
 279     { 0x07, 0x8f, ' ', 1, "NOP" },
 280     { 0x87, 0x8f, ' ', 1, "NOP" },
 281     { 0x0f, 0x8f, ' ', 1, "NOP" },
 282     { 0x8f, 0x8f, ' ', 1, "NOP" },
 283
 284     { 0, 0, 0, 0, 0, 0 }
 285   };
 286
 287 struct dis_entry disass_mos65c02s[]=
 288   {
 289     { 0xcb, 0xff, ' ', 1, "WAI" },
 290     { 0xdb, 0xff, ' ', 1, "STP" },
 291
 292     { 0x07, 0x8f, ' ', 2, "RMB%B %z" },
 293     { 0x87, 0x8f, ' ', 2, "SMB%B %z" },
 294     { 0x0f, 0x8f, 'B', 3, "BBR%B %z,%R" },
 295     { 0x8f, 0x8f, 'B', 3, "BBS%B %z,%R" },
 296
 297     { 0, 0, 0, 0, 0, 0 }
 298   };
 299
 300 struct cpu_entry cpus_6502[]=
 301   {
 302     {"6502"     , CPU_6502, 0           , "MOS6502", ""},
 303     {"02"       , CPU_6502, 0           , "MOS6502", ""},
 304     {"7501"     , CPU_7501, 0           , "MOS7501", ""},
 305     {"8501"     , CPU_8501, 0           , "MOS8501", ""},
 306     {"65C02"    , CPU_65C02, 0          , "MOS65C02", ""},
 307     {"C02"      , CPU_65C02, 0          , "MOS65C02", ""},
 308     {"C"        , CPU_65C02, 0          , "MOS65C02", ""},
 309     {"6510"     , CPU_6510, 0           , "MOS6510", ""},
 310     {"10"       , CPU_6510, 0           , "MOS6510", ""},
 311     {"8500"     , CPU_8500, 0           , "MOS8500", ""},
 312     {"8502"     , CPU_8502, 0           , "MOS8502", ""},
 313     {"65CE02"   , CPU_65CE02, 0         , "MOS65CE02", ""},
 314     {"CE02"     , CPU_65CE02, 0         , "MOS65CE02", ""},
 315     {"CE"       , CPU_65CE02, 0         , "MOS65CE02", ""},
 316     {"65C02S"   , CPU_65C02S, 0         , "MOS65C02S", ""},
 317     {"C02S"     , CPU_65C02S, 0         , "MOS65C02S", ""},
 318     {"CS"       , CPU_65C02S, 0         , "MOS65C02S", ""},
 319     {"S"        , CPU_65C02S, 0         , "MOS65C02S", ""},
 320
 321     {NULL, CPU_NONE, 0, "", ""}
 322   };
 323
 324 /* End of mos6502.src/glob.cc */