sdcc/sim/ucsim/src/sims/pdk.src/pdk.cc

   1 /*
   2  * Simulator of microcontrollers (pdk.cc)
   3  *
   4  * Copyright (C) 2016 Drotos Daniel
   5  *
   6  * To contact author send email to dr.dkdb@gmail.com
   7  *
   8  */
   9
  10 /* This file is part of microcontroller simulator: ucsim.
  11
  12 UCSIM is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2 of the License, or
  15 (at your option) any later version.
  16
  17 UCSIM is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with UCSIM; see the file COPYING.  If not, write to the Free
  24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  25 02111-1307, USA. */
  26 /*@1@*/
  27
  28 //#include "ddconfig.h"
  29
  30 //#include <ctype.h>
  31 //#include <stdarg.h> /* for va_list */
  32 //#include <cassert>
  33 #include <stdio.h>
  34 #include <stdlib.h>
  35 #include <string.h>
  36 //#include "i_string.h"
  37
  38 // prj
  39 #include "globals.h"
  40 //#include "pobjcl.h"
  41
  42 // sim
  43 //#include "simcl.h"
  44 #include "dregcl.h"
  45 #include "simifcl.h"
  46
  47 // local
  48 #include "glob.h"
  49 #include "pdk16cl.h"
  50 #include "t16cl.h"
  51 #include "osccl.h"
  52 #include "wdtcl.h"
  53 //#include "portcl.h"
  54 //#include "regspdk.h"
  55
  56 /*******************************************************************/
  57
  58 cl_fpp::cl_fpp(int aid, class cl_pdk *the_puc, class cl_sim *asim):
  59   cl_uc(asim)
  60 {
  61   id= aid;
  62   puc= the_puc;
  63   PCmask= 0xfff;
  64 }
  65
  66
  67 /*
  68  * Base type of PDK controllers
  69  */
  70
  71 cl_fpp::cl_fpp(int aid, class cl_pdk *the_puc, struct cpu_entry *IType, class cl_sim *asim) : cl_uc(asim)
  72 {
  73   id= aid;
  74   puc= the_puc;
  75   type = IType;
  76 }
  77
  78 int cl_fpp::init(void) {
  79   cl_uc::init(); /* Memories now exist */
  80
  81   //set_xtal(8000000);
  82
  83   // rom = address_space(MEM_ROM_ID);
  84   // ram = mem(MEM_XRAM);
  85   // ram = rom;
  86
  87   // zero out ram(this is assumed in regression tests)
  88   // for (int i = 0x0; i < 0x8000; i++) {
  89   //   ram->set((t_addr)i, 0);
  90   // }
  91
  92   cA.init();
  93   cA.decode(&rA);
  94
  95   if (puc)
  96     {
  97       chars n, d;
  98       n.format("A%d", id);
  99       d.format("Accumulator of FPP%d", id);
 100       puc->mk_cvar(&cA, n, d);
 101       if (id == 0)
 102         puc->mk_cvar(&cA, "A", "Accumulator");
 103       n.format("PC%d", id);
 104       d.format("Program counter of FPP%d", id);
 105       puc->mk_cvar(&cPC, n, d);
 106     }
 107
 108   return (0);
 109 }
 110
 111
 112 void
 113 cl_fpp::act(void)
 114 {
 115   cSP->decode(&rSP);
 116   cF ->decode(&rF);
 117 }
 118
 119 void cl_fpp::reset(void) {
 120   cl_uc::reset();
 121   sp_most = 0x00;
 122
 123   PC = id;
 124   rA = 0;
 125   //for (t_addr i = 0; i < io_size; ++i) store_io(i, 0);
 126   rTMP= 0;
 127 }
 128
 129 void cl_fpp::mk_hw_elements(void)
 130 {
 131   // TODO: Add hardware stuff here.
 132   /*
 133   class cl_hw *h;
 134   cl_uc::mk_hw_elements();
 135   add_hw(h= new cl_dreg(this, 0, "dreg"));
 136   h->init();
 137   */
 138 }
 139
 140 void cl_fpp::make_memories(void)
 141 {
 142   class cl_address_space *as;
 143   int rom_storage= 0x2000, ram_storage= 0x200;
 144   int rom_width= 16;
 145
 146   switch (type->type)
 147     {
 148     case CPU_PDK13: rom_width= 13; break;
 149     case CPU_PDK14: rom_width= 14; break;
 150     case CPU_PDK15: rom_width= 15; break;
 151     case CPU_PDK16: rom_width= 16; break;
 152     default: rom_width= 16;
 153     }
 154
 155   if (puc != NULL)
 156     {
 157       ram= puc->ram;
 158       rom= puc->rom;
 159       sfr= puc->sfr;
 160     }
 161   else
 162     {
 163       rom = as = new cl_address_space("rom", 0, rom_storage, rom_width);
 164       as->init();
 165       address_spaces->add(as);
 166       ram = as = new cl_address_space("ram", 0, ram_storage, 8);
 167       as->init();
 168       address_spaces->add(as);
 169       sfr = as = new cl_address_space("regs8", 0, io_size, 8);
 170       as->init();
 171       address_spaces->add(as);
 172
 173       class cl_address_decoder *ad;
 174       class cl_memory_chip *chip;
 175
 176       chip = new cl_chip16("rom_chip", rom_storage, rom_width);
 177       chip->init();
 178       memchips->add(chip);
 179
 180       ad = new cl_address_decoder(as = rom, chip, 0, rom_storage-1, 0);
 181       ad->init();
 182       as->decoders->add(ad);
 183       ad->activate(0);
 184
 185       chip = new cl_chip16("ram_chip", ram_storage, 8);
 186       chip->init();
 187       memchips->add(chip);
 188
 189       ad = new cl_address_decoder(as = ram, chip, 0, ram_storage-1, 0);
 190       ad->init();
 191       as->decoders->add(ad);
 192       ad->activate(0);
 193
 194       chip = new cl_chip16("io_chip", io_size, 8);
 195       chip->init();
 196       memchips->add(chip);
 197
 198       ad = new cl_address_decoder(as = sfr, chip, 0, io_size-1, 0);
 199       ad->init();
 200       as->decoders->add(ad);
 201       ad->activate(0);
 202
 203       // extra byte of the IO memory will point to the A register just for the debugger
 204       sfr->get_cell(io_size)->decode(&(rA));
 205     }
 206
 207   cSP= sfr->get_cell(2);
 208   cF = sfr->get_cell(0);
 209   act();
 210 }
 211
 212
 213 void
 214 cl_fpp::build_cmdset(class cl_cmdset *cmdset)
 215 {
 216   if (puc == NULL)
 217     cl_uc::build_cmdset(cmdset);
 218 }
 219
 220
 221 /*
 222  * Help command interpreter
 223  */
 224 /*
 225 struct dis_entry *cl_fppa::dis_tbl(void) {
 226   switch (type->type) {
 227     case CPU_PDK13:
 228       return (disass_pdk_13);
 229   case CPU_PDK14:
 230     return (disass_pdk_14);
 231   case CPU_PDK15:
 232     return (disass_pdk_15);
 233   default:
 234     return NULL;//__builtin_unreachable();
 235   }
 236 }
 237 */
 238
 239 int cl_fpp::inst_length(t_addr /*addr*/) {
 240   return 1;
 241 }
 242
 243 int cl_fpp::inst_branch(t_addr addr) {
 244   int b;
 245
 246   get_disasm_info(addr, NULL, &b, NULL, NULL);
 247
 248   return b;
 249 }
 250
 251 bool cl_fpp::is_call(t_addr addr) {
 252   struct dis_entry *e;
 253
 254   get_disasm_info(addr, NULL, NULL, NULL, &e);
 255
 256   return e ? (e->is_call) : false;
 257 }
 258
 259 int cl_fpp::longest_inst(void) { return 1; }
 260
 261 const char *cl_fpp::get_disasm_info(t_addr addr, int *ret_len, int *ret_branch,
 262                                     int *immed_offset,
 263                                     struct dis_entry **dentry) {
 264   const char *b = NULL;
 265   int immed_n = 0;
 266   int start_addr = addr;
 267   struct dis_entry *instructions= dis_tbl();
 268   /*
 269   switch (type->type) {
 270       case CPU_PDK13:
 271         instructions = disass_pdk_13;
 272         break;
 273       case CPU_PDK14:
 274         instructions = disass_pdk_14;
 275         break;
 276       case CPU_PDK15:
 277         instructions = disass_pdk_15;
 278         break;
 279       default:
 280         return "";//__builtin_unreachable();
 281   }
 282   */
 283   uint code = rom->get(addr++);
 284   int i = 0;
 285   while ((code & instructions[i].mask) != instructions[i].code &&
 286          instructions[i].mnemonic)
 287     i++;
 288   dis_entry *dis_e = &instructions[i];
 289   b = instructions[i].mnemonic;
 290
 291   if (ret_branch) {
 292     *ret_branch = dis_e->branch;
 293   }
 294
 295   if (immed_offset) {
 296     if (immed_n > 0)
 297       *immed_offset = immed_n;
 298     else
 299       *immed_offset = (addr - start_addr);
 300   }
 301
 302   if (ret_len) *ret_len = 1;
 303
 304   if (dentry) *dentry = dis_e;
 305
 306   return b;
 307 }
 308 /*
 309 char *cl_fppa::disass(t_addr addr)
 310 {
 311   chars work, temp;
 312   const char *b;
 313   int len = 0;
 314   int immed_offset = 0;
 315   struct dis_entry *dis_e;
 316   bool first= true;
 317
 318   work= "";
 319
 320   b = get_disasm_info(addr, &len, NULL, &immed_offset, &dis_e);
 321
 322   if (b == NULL)
 323     {
 324       return (strdup("UNKNOWN/INVALID"));
 325     }
 326
 327   while (*b)
 328     {
 329       if ((*b == ' ') && first)
 330         {
 331           first= false;
 332           while (work.len() < 6) work.append(' ');
 333         }
 334       if (*b == '%')
 335         {
 336           temp= "";
 337           b++;
 338           uint code = rom->get(addr) & ~(uint)dis_e->mask;
 339           switch (*(b++))
 340             {
 341             case 'k':  // k    immediate addressing
 342               temp.format("#0x%x", code);
 343               break;
 344             case 'm':  // m    memory addressing
 345               if (*b == 'n')
 346                 {
 347                   code &= m_mask();
 348                   b++;
 349                 }
 350               temp.format("0x%x", code);
 351               break;
 352             case 'i':  // i    IO addressing
 353               // TODO: Maybe add pretty printing.
 354               if (*b == 'n')
 355                 {
 356                   code &= io_mask();
 357                   ++b;
 358                 }
 359               temp.format("[0x%x]", code);
 360               break;
 361             case 'n':  // n    N-bit addressing
 362               uint n;
 363               switch (type->type) {
 364               case CPU_PDK13:
 365                 n = (code & 0xE0) >> 5;
 366                 break;
 367               case CPU_PDK14:
 368                 n = (code & 0x1C0) >> 6;
 369                 break;
 370               case CPU_PDK15:
 371                 n = (code & 0x380) >> 7;
 372                 break;
 373               default:
 374                 n= 0;//__builtin_unreachable();
 375               }
 376               temp.format("#0x%x", n);
 377               break;
 378             default:
 379               temp= "%?";
 380               break;
 381             }
 382           work+= temp;
 383         }
 384       else
 385         work+= *(b++);
 386     }
 387
 388   return strdup(work.c_str());
 389 }
 390 */
 391
 392 struct dis_entry *
 393 cl_fpp::get_dis_entry(t_addr addr)
 394 {
 395   t_mem code;
 396   code= rom->get(addr);
 397   int i;
 398   i= 0;
 399   while ((code & dis_tbl()[i].mask) != dis_tbl()[i].code &&
 400          dis_tbl()[i].mnemonic)
 401     i++;
 402   return &dis_tbl()[i];
 403 }
 404
 405 char *
 406 cl_fpp::disassc(t_addr addr, chars *comment)
 407 {
 408   chars work= chars(), temp= chars(), fmt= chars();
 409   const char *b;
 410   t_mem code;
 411   int i;
 412   bool first;
 413   struct dis_entry *de;
 414
 415   code= rom->get(addr);
 416   de= get_dis_entry(addr);
 417   if (!de || !de->mnemonic)
 418     return strdup("-- UNKNOWN/INVALID");
 419
 420   b= de->mnemonic;
 421
 422   first= true;
 423   work= "";
 424   for (i=0; b[i]; i++)
 425     {
 426       if ((b[i] == ' ') && first)
 427         {
 428           first= false;
 429           while (work.len() < 9) work.append(' ');
 430         }
 431       if (b[i] == '\'')
 432         {
 433           fmt= "";
 434           i++;
 435           while (b[i] && (b[i]!='\''))
 436             fmt.append(b[i++]);
 437           if (!b[i]) i--;
 438           if (fmt.empty())
 439             work.append("'");
 440           if (fmt == "i5")
 441             work.appendf("0x%02x", code & 0x1f);
 442           if (fmt == "m4")
 443             work.appendf("[0x%04x]", code & 0xf);
 444           if (fmt == "m6")
 445             work.appendf("[0x%04x]", code & 0x3f);
 446           if (fmt == "m7")
 447             work.appendf("[0x%04x]", code & 0x7f);
 448           if (fmt == "m8")
 449             work.appendf("[0x%04x]", code & 0xff);
 450           if (fmt == "M5")
 451             work.appendf("[0x%04x]", code & 0x1f & ~1);
 452           if (fmt == "M7")
 453             work.appendf("[0x%04x]", code & 0x7f & ~1);
 454           if (fmt == "M8")
 455             work.appendf("[0x%04x]", code & 0xff & ~1);
 456           if (fmt == "M9")
 457             work.appendf("[0x%04x]", code & 0x1ff & ~1);
 458           if (fmt == "n5")
 459             work.appendf("%d", (code>>5)&7);
 460           if (fmt == "n6")
 461             work.appendf("%d", (code>>6)&7);
 462           if (fmt == "n7")
 463             work.appendf("%d", (code>>7)&7);
 464           if (fmt == "n9")
 465             work.appendf("%d", (code>>9)&7);
 466           if (fmt == "a8")
 467             work.appendf("0x%04x", code & 0xff);
 468           if (fmt == "a10")
 469             work.appendf("0x%04x", code & 0x3ff);
 470           if (fmt == "a11")
 471             work.appendf("0x%04x", code & 0x7ff);
 472           if (fmt == "a12")
 473             work.appendf("0x%04x", code & 0xfff);
 474           if (fmt == "a13")
 475             work.appendf("0x%04x", code & 0x1fff);
 476           if (fmt == "d4")
 477             work.appendf("%d", code & 0xf);
 478           if (fmt == "d5")
 479             work.appendf("%d", code & 0x1f);
 480           if (comment && temp.nempty())
 481             comment->append(temp);
 482           continue;
 483         }
 484       if (b[i] == '%')
 485         {
 486           i++;
 487           temp= "";
 488           switch (b[i])
 489             {
 490             case 'm':
 491               work.appendf("[0x%04x]", code & m_mask());
 492               break;
 493             case 'M':
 494               work.appendf("[0x%04x]", code & m_mask() & ~1);
 495               break;
 496             case 'k':
 497               work.appendf("#0x%02x", code & 0xff);
 498               break;
 499             case 'i':
 500               work.appendf("0x%02x", code & io_mask());
 501               break;
 502             case 'n': // == n5
 503               work.appendf("%d", (code>>5)&7);
 504               break;
 505             }
 506           if (comment && temp.nempty())
 507             comment->append(temp);
 508         }
 509       else
 510         work+= b[i];
 511     }
 512
 513   return strdup(work.c_str());
 514 }
 515
 516 void
 517 cl_fpp::print_regs(class cl_console_base *con)
 518 {
 519   act();
 520   con->dd_color("answer");
 521   con->dd_printf("A = %02x %3u\n", rA, rA);
 522   con->dd_printf("       OACZ\n");
 523   con->dd_printf("F = %02x ", rF);
 524   con->dd_printf("%d%d%d%d\n", fO, fA, fC, fZ);
 525   con->dd_printf("SP= %02x\n", rSP);
 526   print_disass(PC, con);
 527 }
 528
 529 /*
 530  * Execution
 531  */
 532
 533 int cl_fpp::exec_inst(void)
 534 {
 535   t_mem code;
 536
 537   act();
 538   instPC= PC;
 539   if (fetch(&code)) {
 540     return (resBREAKPOINT);
 541   }
 542   tick(1);
 543
 544   int status = execute(code);
 545   if (status == resINV_INST)
 546     {
 547       return (resINV_INST);
 548     }
 549   return (status);
 550 }
 551
 552
 553 void
 554 cl_fpp::push(u16_t word)
 555 {
 556   u8_t b= rSP;
 557   ram->write(rSP, word);
 558   ram->write(rSP+1, word>>8);
 559   cSP->W(rSP+2);
 560   vc.wr+= 2;
 561   stack_check_overflow(b);
 562 }
 563
 564 void
 565 cl_fpp::pushlh(u8_t low, u8_t high)
 566 {
 567   u8_t b= rSP;
 568   ram->write(rSP, low);
 569   ram->write(rSP+1, high);
 570   cSP->W(rSP+2);
 571   vc.wr+= 2;
 572   stack_check_overflow(b);
 573 }
 574
 575 void
 576 cl_fpp::stack_check_overflow(void)
 577 {
 578   if (0)
 579     {
 580       class cl_stack_op *op;
 581       op= new cl_stack_op(stack_push, instPC, rSP-2, rSP);
 582       class cl_error_stack_overflow *e=
 583         new cl_error_stack_overflow(op);
 584       e->init();
 585       error(e);
 586     }
 587 }
 588
 589 void
 590 cl_fpp::stack_check_overflow(t_addr sp_before)
 591 {
 592   if (0)
 593     {
 594       class cl_stack_op *op;
 595       op= new cl_stack_op(stack_push, instPC, sp_before, rSP);
 596       class cl_error_stack_overflow *e=
 597         new cl_error_stack_overflow(op);
 598       e->init();
 599       error(e);
 600     }
 601 }
 602
 603 /****************************************************************************/
 604
 605
 606 /* Set nr of active FPP */
 607
 608 t_mem
 609 cl_act_cell::write(t_mem val)
 610 {
 611   val= puc->set_act(val);
 612   return cl_pdk_cell::write(val);
 613 }
 614
 615 /* Set nr of FPPs */
 616
 617 t_mem
 618 cl_nuof_cell::write(t_mem val)
 619 {
 620   val= puc->set_nuof(val);
 621   return cl_pdk_cell::write(val);
 622 }
 623
 624
 625 cl_fppen_op::cl_fppen_op(class cl_pdk *the_puc, class cl_memory_cell *acell):
 626   cl_memory_operator(acell)
 627 {
 628   puc= the_puc;
 629 }
 630
 631 t_mem
 632 cl_fppen_op::write(t_mem val)
 633 {
 634   return puc->set_fppen(val);
 635 }
 636
 637
 638 t_mem
 639 cl_xtal_writer::write(t_mem val)
 640 {
 641   u32_t u= puc->osc->frsys;
 642   puc->set_xtal(u);
 643   return u;
 644 }
 645
 646
 647 cl_mulrh_op::cl_mulrh_op(class cl_pdk *the_puc, class cl_memory_cell *acell):
 648   cl_memory_operator(acell)
 649 {
 650   puc= the_puc;
 651 }
 652
 653 t_mem
 654 cl_mulrh_op::read(void)
 655 {
 656   return puc->rMULRH;
 657 }
 658
 659
 660 /*
 661  * PDK uc
 662  */
 663
 664 cl_pdk::cl_pdk(struct cpu_entry *IType, class cl_sim *asim):
 665   cl_uc(asim)
 666 {
 667   int i;
 668   type = IType;
 669   for (i= 0; i<8; i++)
 670     fpps[i]= NULL;
 671 }
 672
 673 int
 674 cl_pdk::init(void)
 675 {
 676   cl_uc::init();
 677   class cl_memory_operator *op;
 678   fpps[0]= mk_fpp(0);
 679
 680   cFPPEN= sfr->get_cell(1);
 681   cFPPEN->decode(&rFPPEN);
 682   op= new cl_fppen_op(this, cFPPEN);
 683   op->init();
 684   cFPPEN->append_operator(op);
 685
 686   op= new cl_mulrh_op(this, sfr->get_cell(9));
 687   sfr->get_cell(9)->append_operator(op);
 688
 689   mk_mvar(sfr, 0, "FLAG", "ACC Status Flag Register");
 690   mk_mvar(sfr, 0, "F", "ACC Status Flag Register");
 691   mk_mvar(sfr, 1, "FPPEN", "FPP unit Enable Register");
 692   mk_mvar(sfr, 2, "SP", "Stack Pointer Register");
 693   mk_mvar(sfr, 3, "CLKMD", "Clock Mode Register");
 694   mk_mvar(sfr, 5, "INTRQ", "Interrupt Request Register");
 695   mk_mvar(sfr, 6, "T16M", "Timer16 Mode Register");
 696   mk_mvar(sfr, 8, "MULOP", "Multplier Operand Register");
 697   mk_mvar(sfr, 8, "MISC", "MISC Register");
 698   mk_mvar(sfr, 9, "MULRH", "Multplier Result High Byte Register");
 699   mk_mvar(sfr, 0xa, "EOSCR", "External Oscillator Setting Register");
 700   mk_mvar(sfr, 0xc, "INTEGS", "Interrupt Edge Select Register");
 701
 702   cact= new cl_act_cell(this);
 703   reg_cell_var(cact, &act, "fpp", "ID of actual FPPA");
 704   nuof_fpp= 1;
 705   cnuof_fpp= new cl_nuof_cell(this);
 706   reg_cell_var(cnuof_fpp, &nuof_fpp, "nuof_fpp", "Number of FPPs");
 707
 708   if (type->type == CPU_PDKX)
 709     {
 710       fpps[1]= mk_fpp(1);
 711       fpps[2]= mk_fpp(2);
 712       fpps[3]= mk_fpp(3);
 713       fpps[4]= mk_fpp(4);
 714       fpps[5]= mk_fpp(5);
 715       fpps[6]= mk_fpp(6);
 716       fpps[7]= mk_fpp(7);
 717       nuof_fpp= 8;
 718     }
 719
 720   act= 0;
 721   rFPPEN= 1;
 722   single= true;
 723   cPC.decode(&(fpps[0]->PC));
 724
 725   return 0;
 726 }
 727
 728 const char *
 729 cl_pdk::id_string(void)
 730 {
 731   switch (type->type)
 732     {
 733     case CPU_PDK13:
 734       return("pdk13");
 735     case CPU_PDK14:
 736       return("pdk14");
 737     case CPU_PDK15:
 738       return("pdk15");
 739     case CPU_PDK16:
 740       return("pdk16");
 741     default:
 742       return("pdk");
 743   }
 744 }
 745
 746 void
 747 cl_pdk::make_memories(void)
 748 {
 749   class cl_address_space *as;
 750   class cl_address_decoder *ad;
 751   class cl_memory_chip *chip;
 752   int rom_size= 0x2000, ram_size=0x200;
 753
 754   rom = as = new cl_address_space("rom", 0, rom_size, 16);
 755   as->init();
 756   address_spaces->add(as);
 757   ram = as = new cl_address_space("ram", 0, ram_size, 8);
 758   as->init();
 759   address_spaces->add(as);
 760   sfr = as = new cl_address_space("regs8", 0, io_size, 8);
 761   as->init();
 762   address_spaces->add(as);
 763
 764   chip = new cl_chip16("rom_chip", rom_size, 16);
 765   chip->init();
 766   memchips->add(chip);
 767
 768   ad = new cl_address_decoder(as = rom, chip, 0, rom_size-1, 0);
 769   ad->init();
 770   as->decoders->add(ad);
 771   ad->activate(0);
 772
 773   chip = new cl_chip16("ram_chip", ram_size, 8);
 774   chip->init();
 775   memchips->add(chip);
 776
 777   ad = new cl_address_decoder(as = ram, chip, 0, ram_size-1, 0);
 778   ad->init();
 779   as->decoders->add(ad);
 780   ad->activate(0);
 781
 782   chip = new cl_chip16("io_chip", io_size, 8);
 783   chip->init();
 784   memchips->add(chip);
 785
 786   ad = new cl_address_decoder(as = sfr, chip, 0, io_size-1, 0);
 787   ad->init();
 788   as->decoders->add(ad);
 789   ad->activate(0);
 790 }
 791
 792 void
 793 cl_pdk::mk_hw_elements(void)
 794 {
 795   //class cl_hw *h;
 796   cl_uc::mk_hw_elements();
 797
 798   add_hw(osc= new cl_osc(this, "osc"));
 799   osc->init();
 800
 801   add_hw(t16= new cl_t16(this, "t16"));
 802   t16->init();
 803
 804   add_hw(wdt= new cl_wdt(this, "wdt"));
 805   wdt->init();
 806
 807   class cl_memory_cell *c;
 808   class cl_hw *simif= get_hw("simif", 0);
 809   if (simif)
 810     {
 811       c= simif->cfg_cell(simif_xtal);
 812       c->prepend_operator(new cl_xtal_writer(this, c));
 813     }
 814 }
 815
 816 class cl_fpp *
 817 cl_pdk::mk_fpp(int id)
 818 {
 819   class cl_fpp *fppa;
 820   switch (type->type)
 821     {
 822     case CPU_PDK13: fppa= new cl_fpp13(id, this, sim); break;
 823     case CPU_PDK14: fppa= new cl_fpp14(id, this, sim); break;
 824     case CPU_PDK15: fppa= new cl_fpp15(id, this, sim); break;
 825     case CPU_PDK16: fppa= new cl_fpp16(id, this, sim); break;
 826     case CPU_PDKX:  fppa= new cl_fpp15(id, this, sim); break;
 827     default: fppa= new cl_fpp14(id, this, sim); break;
 828     }
 829   fppa->init();
 830   return fppa;
 831 }
 832
 833 void
 834 cl_pdk::reset(void)
 835 {
 836   int i;
 837   mode= pm_run;
 838   for (i=0; i<nuof_fpp; i++)
 839     fpps[i]->reset();
 840
 841   instPC= PC= 0;
 842   state = stGO;
 843   ticks->set(0, 0);
 844   isr_ticks->set(0, 0);
 845   idle_ticks->set(0, 0);
 846   halt_ticks->set(0, 0);
 847   vc.inst= vc.fetch= vc.rd= vc.wr= 0;
 848
 849   stack_ops->free_all();
 850
 851   for (i= 0; i < hws->count; i++)
 852     {
 853       class cl_hw *hw= (class cl_hw *)(hws->at(i));
 854       hw->reset();
 855     }
 856 }
 857
 858 u8_t
 859 cl_pdk::set_fppen(u8_t val)
 860 {
 861   int i, n;
 862   u8_t m;
 863   if (val == 0)
 864     val= 1;
 865   for (i=0, m=1, n=0; i<8; i++, m<<=1)
 866     {
 867       if (fpps[i] == NULL)
 868         val&= ~m;
 869       else
 870         n++;
 871     }
 872   single= n==1;
 873   return val;
 874 }
 875
 876 u8_t
 877 cl_pdk::set_act(u8_t val)
 878 {
 879   u8_t r= 0;
 880   if (val < nuof_fpp)
 881     r= val;
 882   cPC.decode(&(fpps[act]->PC));
 883   PC= fpps[act]->PC;
 884   return r;
 885 }
 886
 887 u8_t
 888 cl_pdk::set_nuof(u8_t val)
 889 {
 890   int i;
 891   if (val > 8)
 892     val= 8;
 893   if (val<1)
 894     val= 1;
 895   for (i=0; i<8; i++)
 896     {
 897       if (i<val)
 898         {
 899           if (fpps[i] == NULL)
 900             fpps[i]= mk_fpp(i);
 901           else
 902             fpps[i]->reset();
 903         }
 904       else
 905         {
 906           if (fpps[i] != NULL)
 907             {
 908               delete fpps[i];
 909               fpps[i]= NULL;
 910             }
 911         }
 912     }
 913   if (rFPPEN == 0)
 914     set_fppen(1);
 915   else
 916     set_fppen(rFPPEN);
 917   return val;
 918 }
 919
 920 t_addr
 921 cl_pdk::get_pc(int id)
 922 {
 923   if (id >= nuof_fpp)
 924     return 0;
 925   return fpps[id]->PC;
 926 }
 927
 928 void
 929 cl_pdk::set_pc(int id, t_addr new_pc)
 930 {
 931   if (id >= nuof_fpp)
 932     return;
 933   fpps[id]->cPC.W(new_pc);
 934 }
 935
 936
 937 int
 938 cl_pdk::exec_inst(void)
 939 {
 940   int it, ret= resHALT;
 941   if (mode == pm_pd)
 942     return resHALT;
 943   while (!(rFPPEN & (1<<act)))
 944     act= (act+1)%nuof_fpp;
 945   inst_ticks= 0;
 946   if (mode == pm_run)
 947     {
 948       fpps[act]->pre_inst();
 949       ret= fpps[act]->exec_inst();
 950       fpps[act]->post_inst();
 951       it= inst_ticks= fpps[act]->inst_ticks;
 952       tick(it);
 953       inst_ticks= it;
 954       int i;
 955       vc.inst= vc.fetch= vc.rd= vc.wr= 0;
 956       for (i= 0; i<nuof_fpp; i++)
 957         {
 958           vc.inst+= fpps[i]->vc.inst;
 959           vc.fetch+= fpps[i]->vc.fetch;
 960           vc.rd+= fpps[i]->vc.rd;
 961           vc.wr+= fpps[i]->vc.wr;
 962         }
 963       if (rFPPEN != 1)
 964         {
 965           do
 966             act= (act+1)%nuof_fpp;
 967           while (!(rFPPEN & (1<<act)));
 968           cPC.decode(&(fpps[act]->PC));
 969         }
 970     }
 971   PC= fpps[act]->PC;
 972   return ret;
 973 }
 974
 975
 976 char *
 977 cl_pdk::disassc(t_addr addr, chars *comment)
 978 {
 979   return fpps[0]->disassc(addr, comment);
 980 }
 981
 982
 983 void
 984 cl_pdk::print_regs(class cl_console_base *con)
 985 {
 986   int i;
 987
 988   for (i= 0; i<nuof_fpp; i++)
 989     {
 990       //con->dd_color((i==act)?"result":"answer");
 991       if (rFPPEN & (1<<i))
 992         con->dd_cprintf("ui_run", "FPP%d:EN   ", i);
 993       else
 994         con->dd_cprintf("ui_stop", "FPP%d:DIS  ", i);
 995     }
 996   con->dd_printf("\n");
 997   for (i= 0; i<nuof_fpp; i++)
 998     {
 999       con->dd_color((i==act)?"result":"answer");
1000       con->dd_printf("A=%02x %3u  ", fpps[i]->rA, fpps[i]->rA);
1001     }
1002   con->dd_printf("\n");
1003   for (i= 0; i<nuof_fpp; i++)
1004     {
1005       con->dd_color((i==act)?"result":"answer");
1006       con->dd_printf("  OACZ    ");
1007     }
1008   con->dd_printf("\n");
1009   for (i= 0; i<nuof_fpp; i++)
1010     {
1011       con->dd_color((i==act)?"result":"answer");
1012       con->dd_printf("F=", fpps[i]->rF);
1013       con->dd_printf("%d%d%d%d    ",
1014                      ((fpps[i]->rF&BIT_OV)>>BITPOS_OV),
1015                      ((fpps[i]->rF&BIT_AC)>>BITPOS_AC),
1016                      ((fpps[i]->rF&BIT_C )>>BITPOS_C ),
1017                      ((fpps[i]->rF&BIT_Z )>>BITPOS_Z ));
1018     }
1019   con->dd_printf("\n");
1020   for (i= 0; i<nuof_fpp; i++)
1021     {
1022       con->dd_color((i==act)?"result":"answer");
1023       con->dd_printf("SP=%02x     ", fpps[i]->rSP);
1024     }
1025   con->dd_printf("\n");
1026
1027   for (i=0; i<nuof_fpp; i++)
1028     {
1029       con->dd_color((i==act)?"result":"answer");
1030       con->dd_printf("%cFPP%d%c: ", (rFPPEN&(1<<act))?'+':'-', i, (act==i)?'*':' ');
1031       fpps[0]->print_disass(fpps[i]->PC, con);
1032     }
1033 }
1034
1035
1036 /* End of pdk.src/pdk.cc */