sdcc/sim/ucsim/src/sims/rxk.src/ibranch.cc

   1 /*
   2  * Simulator of microcontrollers (ibranch.cc)
   3  *
   4  * Copyright (C) 2020 Drotos Daniel
   5  *
   6  * To contact author send email to dr.dkdb@gmail.com
   7  *
   8  */
   9
  10 /* This file is part of microcontroller simulator: ucsim.
  11
  12 UCSIM is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2 of the License, or
  15 (at your option) any later version.
  16
  17 UCSIM is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with UCSIM; see the file COPYING.  If not, write to the Free
  24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  25 02111-1307, USA. */
  26
  27 #include "appcl.h"
  28
  29 #include "rxkcl.h"
  30 #include "r3kacl.h"
  31 #include "r4kcl.h"
  32
  33
  34 int
  35 cl_rxk::DJNZ(t_mem code)
  36 {
  37   u8_t v= rB - 1;
  38   i8_t r= fetch();
  39   destB().W(v);
  40   if (v)
  41     PC= (PC + r) & 0xffff;
  42   tick5p1(4);
  43   return resGO;
  44 }
  45
  46 int
  47 cl_rxk::JR(t_mem code)
  48 {
  49   i8_t r= fetch();
  50   PC= (PC + r) & 0xffff;
  51   tick5p1(4);
  52   return resGO;
  53 }
  54
  55 int
  56 cl_rxk::LJP(t_mem code)
  57 {
  58   u8_t x, h, l;
  59   l= fetch();
  60   h= fetch();
  61   x= fetch();
  62   cXPC.W(x);
  63   PC= h*256+l;
  64   tick(9);
  65   return resGO;
  66 }
  67
  68 int
  69 cl_rxk::CALL_mn(t_mem code)
  70 {
  71   u8_t h, l;
  72   l= fetch();
  73   h= fetch();
  74   rom->write(--rSP, PC>>8);
  75   rom->write(--rSP, PC);
  76   PC= h*256+l;
  77   cSP.W(rSP);
  78   tick5p1(11);
  79   vc.wr+= 2;
  80   return resGO;
  81 }
  82
  83 int
  84 cl_rxk::LCALL_lmn(t_mem code)
  85 {
  86   u8_t h, l, x;
  87   l= fetch();
  88   h= fetch();
  89   x= fetch();
  90   cSP.W(rSP-1);
  91   rom->write(rSP, rXPC);
  92   cSP.W(rSP-1);
  93   rom->write(rSP, PC>>8);
  94   cSP.W(rSP-1);
  95   rom->write(rSP, PC);
  96   PC= h*256+l;
  97   cXPC.W(x);
  98   tick5p1(18);
  99   vc.wr+= 3;
 100   return resGO;
 101 }
 102
 103 int
 104 cl_rxk::rst_v(t_mem code)
 105 {
 106   if ((jaj || (juj&1)) && (code == 0xef)) return resGO;
 107   u8_t l= (code&0x38) << 1;
 108   cSP.W(rSP-1);
 109   rom->write(rSP, PC>>8);
 110   cSP.W(rSP-1);
 111   rom->write(rSP, PC);
 112   PC= rIIR * 256 + l;
 113   vc.wr+= 2;
 114   tick5p3(7);
 115   return resGO;
 116 }
 117
 118
 119 int
 120 cl_rxk::jr_cc(bool cond)
 121 {
 122   i8_t r= fetch();
 123   if (cond)
 124     PC= (PC + r) & 0xffff;
 125   tick5p1(4);
 126   return resGO;
 127 }
 128
 129 int
 130 cl_rxk::ret_f(bool f)
 131 {
 132   if (f)
 133     {
 134       u8_t l, h;
 135       l= mem->read(rSP);
 136       cSP.W(++rSP);
 137       h= mem->read(rSP);
 138       cSP.W(++rSP);
 139       vc.rd+= 2;
 140       PC= h*256 + l;
 141     }
 142   tick(7);
 143   return resGO;
 144 }
 145
 146 int
 147 cl_rxk::jp_f_mn(bool f)
 148 {
 149   u8_t l, h;
 150   l= fetch();
 151   h= fetch();
 152   if (f)
 153     {
 154       PC= h*256+l;
 155     }
 156   tick(6);
 157   return resGO;
 158 }
 159
 160 int
 161 cl_rxk::LRET(t_mem code)
 162 {
 163   u8_t l, h, x;
 164   l= mem->read(rSP);
 165   cSP.W(++rSP);
 166   h= mem->read(rSP);
 167   cSP.W(++rSP);
 168   PC= h*256+l;
 169   x= mem->read(rSP);
 170   cSP.W(++rSP);
 171   cXPC.W(x);
 172   tick(12);
 173   return resGO;
 174 }
 175
 176 int
 177 cl_rxk::RETI(t_mem code)
 178 {
 179   u8_t l, h, x;
 180   x= mem->read(rSP);
 181   cSP.W(++rSP);
 182   l= mem->read(rSP);
 183   cSP.W(++rSP);
 184   h= mem->read(rSP);
 185   cSP.W(++rSP);
 186   PC= h*256+l;
 187   cIP.W(x);
 188   tick(11);
 189   return resGO;
 190 }
 191
 192
 193 /*
 194  *                                                    R3000A,R4000,R5000
 195  */
 196
 197 int
 198 cl_r3ka::SYSCALL(t_mem code)
 199 {
 200   cSP.W(rSP-1);
 201   rom->write(rSP, PC>>8);
 202   cSP.W(rSP-1);
 203   rom->write(rSP, PC);
 204   PC= rIIR * 256 + 0x60;
 205   vc.wr+= 2;
 206   tick5p3(9);
 207   return resGO;
 208 }
 209
 210 int
 211 cl_r4k::DWJNZ(t_mem code)
 212 {
 213   i8_t e= fetch();
 214   u16_t v= rBC-1;
 215   destBC().W(v);
 216   if (v)
 217     PC= (PC + e) & 0xffff;
 218   tick5p1(6);
 219   return resGO;
 220 }
 221
 222 int
 223 cl_r4k::lljp_cx(t_mem code)
 224 {
 225   u8_t cx= (code>>3) & 0x3;
 226   bool cond= false, z, s, v, c, sxv;
 227   s= rF & flagS;
 228   v= rF & flagV;
 229   z= rF & flagZ;
 230   c= rF & flagC;
 231   sxv= (!s && v) || (s && !v);
 232   switch (cx)
 233     {
 234     case 0: // GT: (Z or (S xor V))=0
 235       cond= !(z || (sxv));
 236       break;
 237     case 1: // GTU: ((C=0) and (Z=0))=1
 238       cond= !c && !z;
 239       break;
 240     case 2: // LT: (S xor V)=1
 241       cond= sxv;
 242       break;
 243     case 3: // V: V=1
 244       cond= rF & flagV;
 245       break;
 246     }
 247   u16_t mn, lxpc;
 248   mn= fetch();
 249   mn+= fetch() * 256;
 250   lxpc= fetch();
 251   lxpc+= fetch() * 256;
 252   lxpc&= 0xfff;
 253   if (cond)
 254     {
 255       PC= mn;
 256       LXPC->W(lxpc);
 257     }
 258   tick(13);
 259   return resGO;
 260 }
 261
 262 int
 263 cl_r4k::lljp_cc(t_mem code)
 264 {
 265   u8_t cc= (code>>3) & 0x3;
 266   bool cond= false, z, c;
 267   z= rF & flagZ;
 268   c= rF & flagC;
 269   switch (cc)
 270     {
 271     case 0: // NZ
 272       cond= !z;
 273       break;
 274     case 1: // Z
 275       cond= z;
 276       break;
 277     case 2: // NC
 278       cond= !c;
 279       break;
 280     case 3: // C
 281       cond= c;
 282       break;
 283     }
 284   u16_t mn, lxpc;
 285   mn= fetch();
 286   mn+= fetch() * 256;
 287   lxpc= fetch();
 288   lxpc+= fetch() * 256;
 289   lxpc&= 0xfff;
 290   if (cond)
 291     {
 292       PC= mn;
 293       LXPC->W(lxpc);
 294     }
 295   tick(13);
 296   return resGO;
 297 }
 298
 299 int
 300 cl_r4k::jre_cx_cc(bool cond)
 301 {
 302   u8_t el, eh;
 303   el= fetch();
 304   eh= fetch();
 305   i16_t ee= eh*256+el;
 306   if (cond)
 307     PC= (PC + ee) & 0xffff;
 308   tick5p1(8);
 309   return resGO;
 310 }
 311
 312 int
 313 cl_r4k::CALL_iIR(t_mem code)
 314 {
 315   u16_t a= rSP;
 316   rom->write(--a, PC>>8);
 317   rom->write(--a, PC);
 318   vc.wr+= 2;
 319   cSP.W(a);
 320   PC= cIR->get();
 321   tick5p1(11);
 322   return resGO;
 323 }
 324
 325 int
 326 cl_r4k::CALL_iHL(t_mem code)
 327 {
 328   u16_t a= rSP;
 329   rom->write(--a, PC>>8);
 330   rom->write(--a, PC);
 331   vc.wr+= 2;
 332   cSP.W(a);
 333   PC= rHL;
 334   tick5p1(11);
 335   return resGO;
 336 }
 337
 338 int
 339 cl_r4k::LLRET(t_mem code)
 340 {
 341   u16_t h= 0, l= 0;
 342   u16_t a= rSP;
 343   l= rom->read(a++);
 344   l+= rom->read(a++)*256;
 345   h= rom->read(a++);
 346   h+= rom->read(a++)*256;
 347   vc.rd+= 4;
 348   cSP.W(a);
 349   PC= l;
 350   LXPC->write(h);
 351   tick(13);
 352   return resGO;
 353 }
 354
 355 int
 356 cl_r4k::FSYSCALL(t_mem code)
 357 {
 358   u16_t a= rSP;
 359   rom->write(--a, PC>>8);
 360   rom->write(--a, PC);
 361   rom->write(--a, rSU);
 362   cSP.W(a);
 363   vc.wr+= 3;
 364   PC= rIIR*256+0x60;
 365   cSU.W(rSU<<2);
 366   tick5p1(14);
 367   destF().W(rF|flagC);
 368   return resGO;
 369 }
 370
 371 int
 372 cl_r4k::SYSRET(t_mem code)
 373 {
 374   u16_t a= rSP, v;
 375   cSU.W(rom->read(a++));
 376   v= rom->read(a++);
 377   v+= rom->read(a++)*256;
 378   vc.rd+= 3;
 379   cSP.W(a);
 380   tick(11);
 381   PC= v;
 382   return resGO;
 383 }
 384
 385 int
 386 cl_r4k::LLCALL_iJKHL(t_mem code)
 387 {
 388   u16_t a= rSP, x= LXPC->get();
 389   rom->write(--a, x>>8);
 390   rom->write(--a, x);
 391   rom->write(--a, PC>>8);
 392   rom->write(--a, PC);
 393   PC= rHL;
 394   LXPC->W(rJK);
 395   cSP.W(a);
 396   tick5p1(18);
 397   return resGO;
 398 }
 399
 400 int
 401 cl_r4k::LLJP_lxpcmn(t_mem code)
 402 {
 403   u16_t mn, lxpc;
 404   mn= fetch();
 405   mn+= fetch()*256;
 406   lxpc= fetch();
 407   lxpc+= fetch()*256;
 408   LXPC->W(lxpc);
 409   PC= mn;
 410   tick(11);
 411   return resGO;
 412 }
 413
 414 int
 415 cl_r4k::LLCALL_lxpcmn(t_mem code)
 416 {
 417   u16_t mn, lxpc;
 418   u16_t a= rSP;
 419
 420   lxpc= rXPC;
 421   rom->write(--a, lxpc>>8);
 422   rom->write(--a, lxpc);
 423   mn= PC;
 424   rom->write(--a, mn>>8);
 425   rom->write(--a, mn);
 426   cSP.W(a);
 427   vc.wr+= 4;
 428
 429   mn= fetch();
 430   mn+= fetch()*256;
 431   lxpc= fetch();
 432   lxpc+= fetch()*256;
 433
 434   LXPC->W(lxpc);
 435   PC= mn;
 436   tick(11);
 437   return resGO;
 438 }
 439
 440 int
 441 cl_r4k::JRE_ee(t_mem code)
 442 {
 443   u16_t ee;
 444   ee= fetch();
 445   ee+= fetch()*256;
 446   i16_t offset= ee;
 447   PC+= offset;
 448   PC&= 0xffff;
 449   tick5p1(6);
 450   return resGO;
 451 }
 452
 453 int
 454 cl_r4k::jr_cx_e(bool cond)
 455 {
 456   i8_t e= fetch();
 457   if (cond)
 458     PC= (PC + e) & 0xffff;
 459   tick5p1(4);
 460   return resGO;
 461 }
 462
 463 int
 464 cl_r4k::jp_cx_mn(bool cond)
 465 {
 466   u16_t mn= fetch();
 467   mn+= fetch()*256;
 468   if (cond)
 469     PC= mn;
 470   tick(6);
 471   return resGO;
 472 }
 473
 474
 475 /* End of rxk.src/ibranch.cc */