sdcc/sim/ucsim/src/sims/s51.src/interrupt.cc

   1 /*
   2  * Simulator of microcontrollers (interrupt.cc)
   3  *
   4  * Copyright (C) 1999 Drotos Daniel
   5  *
   6  * To contact author send email to dr.dkdb@gmail.com
   7  *
   8  */
   9
  10 /* This file is part of microcontroller simulator: ucsim.
  11
  12 UCSIM is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2 of the License, or
  15 (at your option) any later version.
  16
  17 UCSIM is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with UCSIM; see the file COPYING.  If not, write to the Free
  24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  25 02111-1307, USA. */
  26 /*@1@*/
  27
  28 //#include <stdarg.h>
  29
  30 // prj
  31 #include "utils.h"
  32
  33 // sim
  34 #include "itsrccl.h"
  35
  36 // local
  37 #include "interruptcl.h"
  38 #include "regs51.h"
  39 //#include "uc51cl.h"
  40 #include "types51.h"
  41
  42
  43 cl_interrupt::cl_interrupt(class cl_uc *auc):
  44   cl_hw(auc, HW_INTERRUPT, 0, "irq")
  45 {
  46   was_reti= false;
  47 }
  48
  49 int
  50 cl_interrupt::init(void)
  51 {
  52   cl_hw::init();
  53   sfr= uc->address_space(MEM_SFR_ID);
  54   if (sfr)
  55     {
  56       register_cell(sfr, IE);
  57       cell_tcon= register_cell(sfr, TCON);
  58       bit_INT0= sfr->read(P3) & bm_INT0;
  59       bit_INT1= sfr->read(P3) & bm_INT1;
  60       cl_address_space *bas= uc->address_space("bits");
  61       cell_it0= register_cell(bas, 0x88);
  62       cell_it1= register_cell(bas, 0x8a);
  63     }
  64   return(0);
  65 }
  66
  67 void
  68 cl_interrupt::added_to_uc(void)
  69 {
  70   class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
  71   class cl_it_src *is;
  72
  73   uc->it_sources->add(is= new cl_it_src(uc, bmEX0,
  74                                         sfr->get_cell(IE), bmEX0,
  75                                         sfr->get_cell(TCON), bmIE0,
  76                                         0x0003, true, false,
  77                                         "external #0", 1));
  78   is->init();
  79   uc->it_sources->add(is= new cl_it_src(uc, bmEX1,
  80                                         sfr->get_cell(IE), bmEX1,
  81                                         sfr->get_cell(TCON), bmIE1,
  82                                         0x0013, true, false,
  83                                         "external #1", 3));
  84   is->init();
  85 }
  86
  87 void
  88 cl_interrupt::write(class cl_memory_cell *cell, t_mem *val)
  89 {
  90   if (cell == cell_it0)
  91     bit_IT0= *val;
  92   else if (cell == cell_it1)
  93     bit_IT1= *val;
  94   else if (cell == cell_tcon)
  95     {
  96       bit_IT0= *val & bmIT0;
  97       bit_IT1= *val & bmIT1;
  98     }
  99   else
 100     // IE register
 101     was_reti= true;
 102 }
 103
 104 /*void
 105 cl_interrupt::mem_cell_changed(class cl_m *mem, t_addr addr)
 106 {
 107 }*/
 108
 109 int
 110 cl_interrupt::tick(int cycles)
 111 {
 112   if (!bit_IT0 && !bit_INT0)
 113     cell_tcon->set(cell_tcon->get() | bmIE0);
 114   if (!bit_IT1 && !bit_INT1)
 115     cell_tcon->set(cell_tcon->get() | bmIE1);
 116   return(resGO);
 117 }
 118
 119 void
 120 cl_interrupt::reset(void)
 121 {
 122   was_reti= false;
 123 }
 124
 125 void
 126 cl_interrupt::happen(class cl_hw *where, enum hw_event he, void *params)
 127 {
 128   struct ev_port_changed *ep= (struct ev_port_changed *)params;
 129
 130   if (where->category == HW_PORT &&
 131       he == EV_PORT_CHANGED &&
 132       ep->id == 3)
 133     {
 134       t_mem p3n= ep->new_pins & ep->new_value;
 135       t_mem p3o= ep->pins & ep->prev_value;
 136       if (bit_IT0 &&
 137           !(p3n & bm_INT0) &&
 138           (p3o & bm_INT0))
 139         cell_tcon->set(cell_tcon->get() | bmIE0);
 140       if (bit_IT1 &&
 141           !(p3n & bm_INT1) &&
 142           (p3o & bm_INT1))
 143         cell_tcon->set(cell_tcon->get() | bmIE1);
 144       bit_INT0= p3n & bm_INT0;
 145       bit_INT1= p3n & bm_INT1;
 146     }
 147 }
 148
 149
 150 void
 151 cl_interrupt::print_info(class cl_console_base *con)
 152 {
 153   //int ie= sfr->get(IE);
 154   int i;
 155
 156   con->dd_printf("Interrupts are %s. Interrupt sources:\n",
 157                  (uc->it_enabled())?"enabled":"disabled");
 158   con->dd_printf("  Handler  En  Pr Req Act Name\n");
 159   for (i= 0; i < uc->it_sources->count; i++)
 160     {
 161       class cl_it_src *is= (class cl_it_src *)(uc->it_sources->at(i));
 162       con->dd_printf("  0x%06x", AU(is->addr));
 163       con->dd_printf(" %-3s", (is->enabled())?"en":"dis");
 164       con->dd_printf(" %2d", uc->priority_of(is->ie_mask));
 165       con->dd_printf(" %-3s", (is->pending())?"YES":"no");
 166       con->dd_printf(" %-3s", (is->active)?"act":"no");
 167       con->dd_printf(" %s", object_name(is));
 168       con->dd_printf("\n");
 169     }
 170   con->dd_printf("Active interrupt service(s):\n");
 171   con->dd_printf("  Pr Handler  PC       Source\n");
 172   for (i= 0; i < uc->it_levels->count; i++)
 173     {
 174       class it_level *il= (class it_level *)(uc->it_levels->at(i));
 175       if (il->level >= 0)
 176         {
 177           con->dd_printf("  %2d", il->level);
 178           con->dd_printf(" 0x%06x", AU(il->addr));
 179           con->dd_printf(" 0x%06x", AU(il->PC));
 180           con->dd_printf(" %s", (il->source)?(object_name(il->source)):
 181                          "nothing");
 182           con->dd_printf("\n");
 183         }
 184     }
 185   //print_cfg_info(con);
 186 }
 187
 188
 189 /* End of s51.src/interrupt.cc */