sdcc/sim/ucsim/src/sims/stm8.src/flash.cc

   1 /*
   2  * Simulator of microcontrollers (flash.cc)
   3  *
   4  * Copyright (C) 2017 Drotos Daniel
   5  *
   6  * To contact author send email to dr.dkdb@gmail.com
   7  *
   8  */
   9
  10 /* This file is part of microcontroller simulator: ucsim.
  11
  12 UCSIM is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2 of the License, or
  15 (at your option) any later version.
  16
  17 UCSIM is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with UCSIM; see the file COPYING.  If not, write to the Free
  24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  25 02111-1307, USA. */
  26 /*@1@*/
  27
  28 #include <stdlib.h>
  29 #include <string.h>
  30
  31 #include "globals.h"
  32
  33 #include "stm8cl.h"
  34
  35 #include "flashcl.h"
  36
  37
  38 /* Address space/cell which can contain flash memory */
  39
  40 t_mem
  41 cl_flash_cell::write(t_mem val)
  42 {
  43   if (flags & CELL_READ_ONLY)
  44     {
  45       class cl_stm8 *uc= (cl_stm8 *)(application->get_uc());
  46       if (uc)
  47         {
  48           t_addr a;
  49           if (uc->rom->is_owned(this, &a) &&
  50               uc->flash_ctrl)
  51             {
  52               uc->flash_ctrl->flash_write(a, val);
  53               return d();
  54             }
  55         }
  56     }
  57   return cl_cell8::write(val);
  58 }
  59
  60 cl_flash_as::cl_flash_as(const char *id, t_addr astart, t_addr asize):
  61   cl_address_space(id, astart, asize, 8)
  62 {
  63   class cl_flash_cell c8(8);
  64   class cl_memory_cell *cell= &c8;
  65   start_address= astart;
  66   decoders= new cl_decoder_list(2, 2, false);
  67   cella= (class cl_memory_cell *)malloc(size * sizeof(class cl_memory_cell));
  68   int s1= sizeof(class cl_memory_cell);
  69   int s2= sizeof(class cl_flash_cell);
  70   printf("s1=%d s2=%d\n", s1, s2);
  71   //cell->init();
  72   t_addr i;
  73   for (i= 0; i < size; i++)
  74     {
  75       void *p= &(cella[i]);
  76       memcpy(p, (void*)cell, sizeof(class cl_memory_cell));
  77       cella[i].init();
  78     }
  79   dummy= new cl_dummy_cell(8);
  80   dummy->init();
  81 }
  82
  83 int
  84 cl_flash_as::init(void)
  85 {
  86   return cl_memory::init();
  87 }
  88
  89
  90 cl_iapsr_op::cl_iapsr_op(class cl_memory_cell *acell):
  91   cl_memory_operator(acell)
  92 {
  93   set_name("EOP_clearer");
  94 }
  95
  96 // read clears EOP and WR_PG_DIS bits
  97 t_mem
  98 cl_iapsr_op::read(void)
  99 {
 100   t_mem v= cell->get();
 101   cell->set(v&0x05);
 102   return v;
 103 }
 104
 105
 106 /* Flash controller */
 107
 108 cl_flash::cl_flash(class cl_uc *auc, t_addr abase, const char *aname):
 109         cl_hw(auc, HW_FLASH, 0, aname)
 110 {
 111   base= abase;
 112   set_name(aname);
 113   wbuf_started= false;
 114   wbuf_start= 0;
 115   rww= true;
 116 }
 117
 118 int
 119 cl_flash::init(void)
 120 {
 121   cl_hw::init();
 122   registration();
 123   return 0;
 124 }
 125
 126 void
 127 cl_flash::reset(void)
 128 {
 129   uc->sim->app->debug("FLASH reset\n");
 130   puk1st= false;
 131   duk1st= false;
 132   p_unlocked= false;
 133   d_unlocked= false;
 134   p_failed= false;
 135   d_failed= false;
 136
 137   state= fs_wait_mode;
 138   mode= fm_unknown;
 139
 140   cr1r->set/*write*/(0);
 141   iapsr->set/*write*/(0x40);
 142   cr2r->set/*write*/(0);
 143   if (ncr2r)
 144     ncr2r->set/*write*/(0xff);
 145 }
 146
 147
 148 const char *
 149 cl_flash::cfg_help(t_addr addr)
 150 {
 151   switch (addr)
 152     {
 153     case stm8_flash_on: return "Turn ticking of flash on/off (bool, RW)";
 154     }
 155   return "Not used";
 156 }
 157
 158
 159 int
 160 cl_flash::tick(int cycles)
 161 {
 162   if (state & fs_busy)
 163     {
 164       double now= uc->ticks->get_rtime();
 165       double elapsed= (now - start_time) * 10e6;
 166
 167       if ((state == fs_pre_erase) &&
 168           (elapsed > tprog/2.0))
 169         {
 170           int i;
 171           uc->sim->app->debug("FLASH zeroing %06lx .. %d\n", wbuf_start, wbuf_size);
 172           for (i= 0; i < wbuf_size; i++)
 173             {
 174               class cl_memory_cell *c= uc->rom->get_cell(wbuf_start + i);
 175               c->download(0);
 176             }
 177           if (mode == fm_erase)
 178             {
 179               uc->sim->app->debug("FLASH end of erase, finish\n");
 180               finish_program(true);
 181             }
 182           else
 183             {
 184               uc->sim->app->debug("FLASH end of erase, cont program\n");
 185               state= fs_program;
 186             }
 187         }
 188       else if (elapsed > tprog)
 189         {
 190           int i;
 191           uc->sim->app->debug("FLASH dl-ing %06lx .. %06l\n", wbuf_start, wbuf_start+wbuf_size);
 192           for (i= 0; i < wbuf_size; i++)
 193             {
 194               class cl_memory_cell *c= uc->rom->get_cell(wbuf_start + i);
 195               t_mem org= c->get(), n;
 196               n= org | wbuf[i];
 197               c->download(n);
 198               uc->sim->app->debug("FLASH dl [%06lx]= %x (org=%x)\n",
 199                                   wbuf_start+i, n, org);
 200             }
 201           uc->sim->app->debug("FLASH end of program\n");
 202           finish_program(true);
 203         }
 204     }
 205   return 0;
 206 }
 207
 208 void
 209 cl_flash::finish_program(bool ok)
 210 {
 211   if (ok)
 212     iapsr->set(iapsr->get() | 0x04);
 213   else
 214     iapsr->set(iapsr->get() | 0x01);
 215   uc->sim->app->debug("FLASH prg finish, OK=%d iapsr=%02x\n", ok, iapsr->get());
 216   state= fs_wait_mode;
 217 }
 218
 219 t_mem
 220 cl_flash::read(class cl_memory_cell *cell)
 221 {
 222   t_mem v;
 223
 224   if (conf(cell, NULL))
 225     return cell->get();
 226
 227   v= cell->get();
 228   if (cell == pukr)
 229     v= 0;
 230   else if (cell == dukr)
 231     v= 0;
 232   else if (cell == iapsr)
 233     {
 234       v&= ~0x0a;
 235       if (p_unlocked)
 236         v|= 0x02;
 237       if (d_unlocked)
 238         v|= 0x08;
 239       if (v & 0x05)
 240         {
 241           uc->sim->app->debug("FLASH read iapsr5 %02x\n",v);
 242           //uc->sim->stop(0);
 243         }
 244       // clear of EOP and WR_PG_DIS bits will be done by cl_iapsr_op
 245       cell->set(v);
 246     }
 247   return v;
 248 }
 249
 250 void
 251 cl_flash::write(class cl_memory_cell *cell, t_mem *val)
 252 {
 253   if (conf(cell, val))
 254     return;
 255
 256   if (cell == pukr)
 257     {
 258       uc->sim->app->debug("FLASH write-pukr %02x\n",*val);
 259       if (p_failed)
 260         ;
 261       else if (!puk1st)
 262         {
 263           if (*val == PMASS1)
 264             puk1st= true;
 265           else
 266             p_failed= true;
 267         }
 268       else
 269         {
 270           if (*val == PMASS2)
 271             puk1st= false, p_unlocked= true;
 272           else
 273             puk1st= false, p_failed= true;
 274         }
 275       *val= 0;
 276     }
 277   else if (cell == dukr)
 278     {
 279       uc->sim->app->debug("FLASH write-dukr %02x\n",*val);
 280       if (d_failed)
 281         ;
 282       else if (!duk1st)
 283         {
 284           if (*val == DMASS1)
 285             duk1st= true;
 286           else
 287             d_failed= true;
 288         }
 289       else
 290         {
 291           if (*val == DMASS2)
 292             duk1st= false, d_unlocked= true;
 293           else
 294             duk1st= false, d_failed= true;
 295         }
 296       *val= 0;
 297     }
 298   else if (cell == iapsr)
 299     {
 300       uc->sim->app->debug("FLASH write-iapsr %02x\n",*val);
 301       t_mem org= iapsr->get();
 302       // PUL, DUL
 303       if (!(*val & 0x02))
 304         p_unlocked= puk1st= false;
 305       if (!(*val & 0x08))
 306         d_unlocked= duk1st= false;
 307       *val&= ~0x0a;
 308       if (p_unlocked)
 309         *val|= 0x02;
 310       if (d_unlocked)
 311         *val|= 0x08;
 312       // HVOFF
 313       *val&= ~0x40;
 314       // EOP
 315       *val&= 0x40;
 316       if (org & 0x40)
 317         *val|= 0x40;
 318     }
 319   else if (cell == cr2r)
 320     {
 321       uc->sim->app->debug("FLASH write-cr2r %02x\n",*val);
 322       *val&= ~0x0e;
 323       if (state & fs_busy)
 324         {
 325           *val&= ~0x30;
 326           *val|= (cr2r->get() & 0x30);
 327         }
 328       if ((ncr2r == NULL) ||
 329           (ncr2r->get() == ((~(*val))&0xff)))
 330         set_flash_mode(*val);
 331     }
 332   else if ((ncr2r != NULL) &&
 333            (cell == ncr2r))
 334     {
 335       uc->sim->app->debug("FLASH write-ncr2r %02x\n",*val);
 336       *val|= 0x0e;
 337       if (state & fs_busy)
 338         {
 339           *val&= ~0x30;
 340           *val|= (ncr2r->get() & 0x30);
 341         }
 342       if (cr2r->get() == ((~(*val))&0xff))
 343         set_flash_mode((~(*val))&0xff);
 344     }
 345 }
 346
 347
 348 t_mem
 349 cl_flash::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
 350 {
 351   switch ((enum stm8_flash_cfg)addr)
 352     {
 353     case stm8_flash_on:
 354       if (val)
 355         {
 356           if (*val)
 357             on= true;
 358           else
 359             on= false;
 360         }
 361       else
 362         cell->set(on?1:0);
 363       break;
 364     case stm8_flash_nuof_cfg:
 365       break;
 366     }
 367   return cell->get();
 368 }
 369
 370
 371 void
 372 cl_flash::flash_write(t_addr a, t_mem val)
 373 {
 374   uc->sim->app->debug("FLASH wr(%06lx,%02x)\n",a,val);
 375   if (!uc)
 376     {
 377       uc->sim->app->debug("  no uc\n");
 378       return;
 379     }
 380   if (uc->rom == NULL)
 381     {
 382       uc->sim->app->debug("  no rom\n");
 383       return;
 384     }
 385   if ((a >= 0x8000) &&
 386       !p_unlocked)
 387     {
 388       uc->sim->app->debug("  plocked\n");
 389       return;
 390     }
 391   if ((a < 0x8000) &&
 392       !d_unlocked)
 393     {
 394       uc->sim->app->debug("  dlocked\n");
 395       return;
 396     }
 397   if (state & fs_busy)
 398     {
 399       uc->sim->app->debug("  busy %d\n",state);
 400       return;
 401     }
 402
 403   uc->sim->app->debug("  wbuf_start=%06lx\n",wbuf_start);
 404   if (wbuf_start == 0)
 405     {
 406       uc->sim->app->debug("  calling start_wbuf(%06lx)\n",a);
 407       start_wbuf(a);
 408     }
 409
 410   int offset= a - wbuf_start;
 411   uc->sim->app->debug("  offset=%d\n",offset);
 412   if (mode == fm_byte)
 413     {
 414       // fixup tprog
 415       wbuf[0]= uc->rom->get(wbuf_start + 0);
 416       wbuf[1]= uc->rom->get(wbuf_start + 1);
 417       wbuf[2]= uc->rom->get(wbuf_start + 2);
 418       wbuf[3]= uc->rom->get(wbuf_start + 3);
 419       if (tprog < 6000)
 420         {
 421           if (wbuf[0] ||
 422               wbuf[1] ||
 423               wbuf[2] ||
 424               wbuf[3])
 425             tprog= 6000;
 426         }
 427       wbuf[offset]= val;
 428       if (tprog < 6000)
 429         start_program(fs_program);
 430     }
 431   else if (mode == fm_erase)
 432     {
 433       uc->sim->app->debug("  romwrite in erase mode\n");
 434       wbuf[offset]= val;
 435       wbuf_writes++;
 436       if ((wbuf_writes == 4) &&
 437           (((a+1) % 4) == 0))
 438         {
 439           u8_t v= 0;
 440           v|= wbuf[0];
 441           v|= wbuf[1];
 442           v|= wbuf[2];
 443           v|= wbuf[3];
 444           if (v == 0)
 445             {
 446               uc->sim->app->debug("  starting erase\n");
 447               start_program(fs_pre_erase);
 448             }
 449         }
 450     }
 451   else
 452     {
 453       wbuf[offset]= val;
 454       wbuf_started= true;
 455       wbuf_writes++;
 456       if ((wbuf_writes == wbuf_size) ||
 457           (offset == wbuf_size-1))
 458         {
 459           if ((mode == fm_fast_word) ||
 460               (mode == fm_fast_block))
 461             start_program(fs_program);
 462           else
 463             start_program(fs_pre_erase);
 464         }
 465     }
 466 }
 467
 468 // normal program: 6 ms
 469 // fast program: 3 ms
 470 // erase: 3 ms
 471
 472 void
 473 cl_flash::set_flash_mode(t_mem cr2val)
 474 {
 475   bool fix= cr1r->get() & 0x01; /* FIX */
 476
 477   uc->sim->app->debug("FLASH set_mode %02x\n", cr2val);
 478   if (cr2val & 0x40 /* WPRG */ )
 479     {
 480       mode= fm_word;
 481       tprog= 6000; /* normal mode */
 482       wbuf_size= 4;
 483     }
 484   else if (cr2val & 0x20 /* ERASE */ )
 485     {
 486       mode= fm_erase;
 487       tprog= 3000;
 488       wbuf_size= 128;
 489     }
 490   else if (cr2val & 0x10 /* FPRG */ )
 491     {
 492       mode= fm_fast_block;
 493       tprog= 3000;
 494       wbuf_size= 128;
 495     }
 496   else if (cr2val & 0x01 /* PRG */ )
 497     {
 498       mode= fm_block;
 499       tprog= 6000;
 500       wbuf_size= 128;
 501     }
 502   else
 503     {
 504       mode= fm_byte;
 505       tprog= fix?6000:3000;
 506       wbuf_size= 4;
 507     }
 508   state= fs_wait_data;
 509   uc->sim->app->debug("FLASH state=wait_data\n");
 510   wbuf_started= false;
 511   wbuf_start= 0;
 512 }
 513
 514 void
 515 cl_flash::start_wbuf(t_addr addr)
 516 {
 517   int i;
 518   wbuf_start= addr - (addr % wbuf_size);
 519   wbuf_writes= 0;
 520   for (i= 0; i < 256; i++)
 521     wbuf[i]= 0;
 522   uc->sim->app->debug("FLASH start_wbuf %06lx (wbuf_start=%06lx,size=%d)\n", addr, wbuf_start, wbuf_size);
 523 }
 524
 525 void
 526 cl_flash::start_program(enum stm8_flash_state start_state)
 527 {
 528   uc->sim->app->debug("FLASH start prg state=0x%x wbuf=%02x,%02x,%02x,%02x\n",
 529                       start_state,
 530                       wbuf[0], wbuf[1], wbuf[2], wbuf[3]);
 531   state= start_state;
 532   start_time= uc->ticks->get_rtime();
 533 }
 534
 535 const char *
 536 cl_flash::state_name(enum stm8_flash_state s)
 537 {
 538   switch (s)
 539     {
 540     case fs_wait_mode: return "wait_mode";
 541     case fs_wait_data: return "wait_data";
 542     case fs_pre_erase: return "erase";
 543     case fs_program: return "program";
 544     case fs_busy: return "busy";
 545     }
 546   return "unknown";
 547 }
 548
 549 void
 550 cl_flash::print_info(class cl_console_base *con)
 551 {
 552   con->dd_printf(chars("", "Flash at %s\n", uc->rom->addr_format), base);
 553   con->dd_printf("PUK: ");
 554   if (p_failed)
 555     con->dd_printf("fail");
 556   else if (p_unlocked)
 557     con->dd_printf("unlocked");
 558   else if (puk1st)
 559     con->dd_printf("MASS1");
 560   else
 561     con->dd_printf("locked");
 562   con->dd_printf("\n");
 563
 564   con->dd_printf("DUK: ");
 565   if (d_failed)
 566     con->dd_printf("fail");
 567   else if (d_unlocked)
 568     con->dd_printf("unlocked");
 569   else if (duk1st)
 570     con->dd_printf("MASS1");
 571   else
 572     con->dd_printf("locked");
 573   con->dd_printf("\n");
 574
 575   con->dd_printf("State: %s\n", state_name(state));
 576   //print_cfg_info(con);
 577 }
 578
 579
 580 /* SAF */
 581
 582 cl_saf_flash::cl_saf_flash(class cl_uc *auc, t_addr abase):
 583         cl_flash(auc, abase, "flash")
 584 {
 585 }
 586
 587 void
 588 cl_saf_flash::registration(void)
 589 {
 590   class cl_it_src *is;
 591
 592   cr1r= register_cell(uc->rom, base+0);
 593   cr2r= register_cell(uc->rom, base+1);
 594   ncr2r= register_cell(uc->rom, base+2);
 595   iapsr= register_cell(uc->rom, base+5);
 596   pukr= register_cell(uc->rom, base+8);
 597   dukr= register_cell(uc->rom, base+10);
 598
 599   uc->it_sources->add(is= new cl_it_src(uc, 24,
 600                                         cr1r,0x02,
 601                                         iapsr,0x04,
 602                                         0x8008+24*4, false, false,
 603                                         "FLASH_EOP", 20*20+0));
 604   uc->it_sources->add(is= new cl_it_src(uc, 24,
 605                                         cr1r,0x02,
 606                                         iapsr,0x01,
 607                                         0x8008+24*4, false, false,
 608                                         "FLASH_RO", 20*20+1));
 609   is->init();
 610
 611   class cl_iapsr_op *o= new cl_iapsr_op(iapsr);
 612   iapsr->append_operator(o);
 613 }
 614
 615
 616 /* L,L101 */
 617
 618 cl_l_flash::cl_l_flash(class cl_uc *auc, t_addr abase):
 619         cl_flash(auc, abase, "flash")
 620 {
 621 }
 622
 623 void
 624 cl_l_flash::registration(void)
 625 {
 626   class cl_it_src *is;
 627
 628   cr1r= register_cell(uc->rom, base+0);
 629   cr2r= register_cell(uc->rom, base+1);
 630   pukr= register_cell(uc->rom, base+2);
 631   dukr= register_cell(uc->rom, base+3);
 632   iapsr= register_cell(uc->rom, base+4);
 633   ncr2r= NULL;
 634
 635   uc->it_sources->add(is= new cl_it_src(uc, 1,
 636                                         cr1r,0x02,
 637                                         iapsr,0x04,
 638                                         0x8008+1*4, false, false,
 639                                         "FLASH_EOP", 20*20+0));
 640   uc->it_sources->add(is= new cl_it_src(uc, 1,
 641                                         cr1r,0x02,
 642                                         iapsr,0x01,
 643                                         0x8008+1*4, false, false,
 644                                         "FLASH_RO", 20*20+1));
 645   is->init();
 646 }
 647
 648
 649 /* End of stm8.src/flash.cc */