Hackfix and re-enable strtoull and wcstoull, see bug #3798.
[sdcc.git] / sdcc-extra / emu / rrz80 / cpu / z80_op3.c
blobdd0d43ad02961ac690f3e514edca637716125b6d
1 /*
2 * Copyright (C) 1996-1998 Szeredi Miklos
3 * Email: mszeredi@inf.bme.hu
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version. See the file COPYING.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #ifndef NO_OPDEF
22 #include "z80_def.h"
23 #include "z80_op3.h"
24 #include "z80_ari.h"
25 #endif
27 #define ARIR(arin, func, an, rn, r, n) \
28 OPDEF(arin ## _ ## rn, 0x80+an*8+n) \
29 { \
30 func(r); \
31 ENTIME(4); \
34 #define ARIIHL(arin, func, an) \
35 OPDEF(arin ## _ihl, 0x86+an*8) \
36 { \
37 func(*HLP); \
38 ENTIME(7); \
41 #define ARIID(arin, func, an, ixyn, ixy) \
42 OPDEF(arin ## _i ## ixyn ## d, 0x86+an*8)\
43 { \
44 register dbyte addr; \
45 register byte val; \
46 IXDGET(ixy, addr); \
47 val = READ(addr); \
48 func(val); \
49 ENTIME(15); \
53 #define ADD_A_R(rn, r, n) ARIR(add_a, ADD, 0, rn, r, n)
54 #define ADC_A_R(rn, r, n) ARIR(adc_a, ADC, 1, rn, r, n)
55 #define SUB_R(rn, r, n) ARIR(sub, SUB, 2, rn, r, n)
56 #define SBC_A_R(rn, r, n) ARIR(sbc_a, SBC, 3, rn, r, n)
57 #define AND_R(rn, r, n) ARIR(and, AND, 4, rn, r, n)
58 #define XOR_R(rn, r, n) ARIR(xor, XOR, 5, rn, r, n)
59 #define OR_R(rn, r, n) ARIR(or, OR, 6, rn, r, n)
60 #define CP_R(rn, r, n) ARIR(cp, CP, 7, rn, r, n)
62 ADD_A_R(b, RB, 0)
63 ADD_A_R(c, RC, 1)
64 ADD_A_R(d, RD, 2)
65 ADD_A_R(e, RE, 3)
66 ADD_A_R(h, RH, 4)
67 ADD_A_R(l, RL, 5)
68 ADD_A_R(a, RA, 7)
70 ADC_A_R(b, RB, 0)
71 ADC_A_R(c, RC, 1)
72 ADC_A_R(d, RD, 2)
73 ADC_A_R(e, RE, 3)
74 ADC_A_R(h, RH, 4)
75 ADC_A_R(l, RL, 5)
76 ADC_A_R(a, RA, 7)
78 SUB_R(b, RB, 0)
79 SUB_R(c, RC, 1)
80 SUB_R(d, RD, 2)
81 SUB_R(e, RE, 3)
82 SUB_R(h, RH, 4)
83 SUB_R(l, RL, 5)
84 SUB_R(a, RA, 7)
86 SBC_A_R(b, RB, 0)
87 SBC_A_R(c, RC, 1)
88 SBC_A_R(d, RD, 2)
89 SBC_A_R(e, RE, 3)
90 SBC_A_R(h, RH, 4)
91 SBC_A_R(l, RL, 5)
92 SBC_A_R(a, RA, 7)
94 AND_R(b, RB, 0)
95 AND_R(c, RC, 1)
96 AND_R(d, RD, 2)
97 AND_R(e, RE, 3)
98 AND_R(h, RH, 4)
99 AND_R(l, RL, 5)
100 AND_R(a, RA, 7)
102 XOR_R(b, RB, 0)
103 XOR_R(c, RC, 1)
104 XOR_R(d, RD, 2)
105 XOR_R(e, RE, 3)
106 XOR_R(h, RH, 4)
107 XOR_R(l, RL, 5)
108 /* XOR_R(a, RA, 7) */
110 OPDEF(xor_a, 0xAF)
112 RA = 0;
113 RF = (RF & ~(ALLF)) | (ZF | PVF);
114 ENTIME(4);
117 OR_R(b, RB, 0)
118 OR_R(c, RC, 1)
119 OR_R(d, RD, 2)
120 OR_R(e, RE, 3)
121 OR_R(h, RH, 4)
122 OR_R(l, RL, 5)
123 OR_R(a, RA, 7)
125 CP_R(b, RB, 0)
126 CP_R(c, RC, 1)
127 CP_R(d, RD, 2)
128 CP_R(e, RE, 3)
129 CP_R(h, RH, 4)
130 CP_R(l, RL, 5)
131 CP_R(a, RA, 7)
133 ARIIHL(add_a, ADD, 0)
134 ARIIHL(adc_a, ADC, 1)
135 ARIIHL(sub, SUB, 2)
136 ARIIHL(sbc_a, SBC, 3)
137 ARIIHL(and, AND, 4)
138 ARIIHL(xor, XOR, 5)
139 ARIIHL(or, OR, 6)
140 ARIIHL(cp, CP, 7)
142 #include "z80_op3x.c"