sdcc-extra/emu/rrz80/cpu/z80_op6.c

   1 /*
   2  * Copyright (C) 1996-1998 Szeredi Miklos
   3  * Email: mszeredi@inf.bme.hu
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version. See the file COPYING.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  */
  20
  21 #ifndef NO_OPDEF
  22 #include "z80_def.h"
  23 #include "z80_op6.h"
  24 #endif
  25
  26 #define GHL DANM(cbaddr)
  27
  28 #define B7(r) (((r) & 0x80) >> 7)
  29 #define B0(r) ((r) & 0x01)
  30
  31 #define SHIFTROTL(r, mod) \
  32 {                                  \
  33   register int carry;              \
  34   carry = B7(r);                   \
  35   r = mod;                         \
  36   RF = (RF & ~(AALLF)) | carry |    \
  37        TAB(orf_tbl)[(byte) r];     \
  38 }
  39
  40
  41 #define SHIFTROTR(r, mod) \
  42 {                                  \
  43   register int carry;              \
  44   carry = B0(r);                   \
  45   r = mod;                         \
  46   RF = (RF & ~(AALLF)) | carry |    \
  47        TAB(orf_tbl)[(byte) r];     \
  48 }
  49
  50
  51 #define RLC(r) SHIFTROTL(r, (r << 1) | carry)
  52 #define RRC(r) SHIFTROTR(r, (r >> 1) | (carry << 7))
  53 #define RLN(r) SHIFTROTL(r, (r << 1) | (RF & CF))
  54 #define RRN(r) SHIFTROTR(r, (r >> 1) | ((RF & CF) << 7))
  55 #define SLA(r) SHIFTROTL(r, r << 1)
  56 #define SRA(r) SHIFTROTR(r, (byte) ((sbyte) r >> 1))
  57 #define SLL(r) SHIFTROTL(r, (r << 1) | 0x01)
  58 #define SRL(r) SHIFTROTR(r, r >> 1)
  59
  60
  61 #define SHRR(shrn, func, an, rn, r, n) \
  62 OPDEF(shrn ## _ ## rn, 0x00+an*8+n)      \
  63 {                                        \
  64   func(r);                               \
  65   ENTIME(8);                             \
  66 }
  67
  68 #define SHRIHL(shrn, func, an) \
  69 OPDEF(shrn ## _ihl, 0x06+an*8)           \
  70 {                                        \
  71   register byte btmp;                    \
  72   btmp = READ(GHL);                      \
  73   func(btmp);                            \
  74   WRITE(GHL, btmp);                      \
  75   ENTIME(15);                            \
  76 }
  77
  78 #define RLC_R(rn, r, n) SHRR(rlc, RLC, 0, rn, r, n)
  79 #define RRC_R(rn, r, n) SHRR(rrc, RRC, 1, rn, r, n)
  80 #define RL_R(rn, r, n)  SHRR(rl,  RLN,  2, rn, r, n)
  81 #define RR_R(rn, r, n)  SHRR(rr,  RRN,  3, rn, r, n)
  82 #define SLA_R(rn, r, n) SHRR(sla, SLA, 4, rn, r, n)
  83 #define SRA_R(rn, r, n) SHRR(sra, SRA, 5, rn, r, n)
  84 #define SLL_R(rn, r, n) SHRR(sll, SLL, 6, rn, r, n)
  85 #define SRL_R(rn, r, n) SHRR(srl, SRL, 7, rn, r, n)
  86
  87 RLC_R(b, RB, 0)
  88 RLC_R(c, RC, 1)
  89 RLC_R(d, RD, 2)
  90 RLC_R(e, RE, 3)
  91 RLC_R(h, RH, 4)
  92 RLC_R(l, RL, 5)
  93 RLC_R(a, RA, 7)
  94
  95 RRC_R(b, RB, 0)
  96 RRC_R(c, RC, 1)
  97 RRC_R(d, RD, 2)
  98 RRC_R(e, RE, 3)
  99 RRC_R(h, RH, 4)
 100 RRC_R(l, RL, 5)
 101 RRC_R(a, RA, 7)
 102
 103 RL_R(b, RB, 0)
 104 RL_R(c, RC, 1)
 105 RL_R(d, RD, 2)
 106 RL_R(e, RE, 3)
 107 RL_R(h, RH, 4)
 108 RL_R(l, RL, 5)
 109 RL_R(a, RA, 7)
 110
 111 RR_R(b, RB, 0)
 112 RR_R(c, RC, 1)
 113 RR_R(d, RD, 2)
 114 RR_R(e, RE, 3)
 115 RR_R(h, RH, 4)
 116 RR_R(l, RL, 5)
 117 RR_R(a, RA, 7)
 118
 119 SLA_R(b, RB, 0)
 120 SLA_R(c, RC, 1)
 121 SLA_R(d, RD, 2)
 122 SLA_R(e, RE, 3)
 123 SLA_R(h, RH, 4)
 124 SLA_R(l, RL, 5)
 125 SLA_R(a, RA, 7)
 126
 127 SRA_R(b, RB, 0)
 128 SRA_R(c, RC, 1)
 129 SRA_R(d, RD, 2)
 130 SRA_R(e, RE, 3)
 131 SRA_R(h, RH, 4)
 132 SRA_R(l, RL, 5)
 133 SRA_R(a, RA, 7)
 134
 135 SLL_R(b, RB, 0)
 136 SLL_R(c, RC, 1)
 137 SLL_R(d, RD, 2)
 138 SLL_R(e, RE, 3)
 139 SLL_R(h, RH, 4)
 140 SLL_R(l, RL, 5)
 141 SLL_R(a, RA, 7)
 142
 143 SRL_R(b, RB, 0)
 144 SRL_R(c, RC, 1)
 145 SRL_R(d, RD, 2)
 146 SRL_R(e, RE, 3)
 147 SRL_R(h, RH, 4)
 148 SRL_R(l, RL, 5)
 149 SRL_R(a, RA, 7)
 150
 151 SHRIHL(rlc, RLC, 0)
 152 SHRIHL(rrc, RRC, 1)
 153 SHRIHL(rl,  RLN, 2)
 154 SHRIHL(rr,  RRN, 3)
 155 SHRIHL(sla, SLA, 4)
 156 SHRIHL(sra, SRA, 5)
 157 SHRIHL(sll, SLL, 6)
 158 SHRIHL(srl, SRL, 7)
 159
 160 #define BIT(r, n) \
 161   RF = (RF & ~(SF | ZF | NF)) | (r & SF) | (((~r >> n) & 0x01) << 6)
 162
 163 #define BIT_N_R(bn, rn, r, n) \
 164 OPDEF(bit_ ## bn ## _ ## rn, 0x40+bn*8+n) \
 165 {                                         \
 166   BIT(r, bn);                             \
 167   ENTIME(8);                              \
 168 }
 169
 170 #define BIT_N_IHL(bn) \
 171 OPDEF(bit_ ## bn ## _ihl, 0x46+bn*8) \
 172 {                                         \
 173   register byte btmp;                     \
 174   btmp = READ(GHL);                       \
 175   BIT(btmp, bn);                          \
 176   ENTIME(12);                             \
 177 }
 178
 179 BIT_N_R(0, b, RB, 0)
 180 BIT_N_R(0, c, RC, 1)
 181 BIT_N_R(0, d, RD, 2)
 182 BIT_N_R(0, e, RE, 3)
 183 BIT_N_R(0, h, RH, 4)
 184 BIT_N_R(0, l, RL, 5)
 185 BIT_N_R(0, a, RA, 7)
 186
 187 BIT_N_R(1, b, RB, 0)
 188 BIT_N_R(1, c, RC, 1)
 189 BIT_N_R(1, d, RD, 2)
 190 BIT_N_R(1, e, RE, 3)
 191 BIT_N_R(1, h, RH, 4)
 192 BIT_N_R(1, l, RL, 5)
 193 BIT_N_R(1, a, RA, 7)
 194
 195 BIT_N_R(2, b, RB, 0)
 196 BIT_N_R(2, c, RC, 1)
 197 BIT_N_R(2, d, RD, 2)
 198 BIT_N_R(2, e, RE, 3)
 199 BIT_N_R(2, h, RH, 4)
 200 BIT_N_R(2, l, RL, 5)
 201 BIT_N_R(2, a, RA, 7)
 202
 203 BIT_N_R(3, b, RB, 0)
 204 BIT_N_R(3, c, RC, 1)
 205 BIT_N_R(3, d, RD, 2)
 206 BIT_N_R(3, e, RE, 3)
 207 BIT_N_R(3, h, RH, 4)
 208 BIT_N_R(3, l, RL, 5)
 209 BIT_N_R(3, a, RA, 7)
 210
 211 BIT_N_R(4, b, RB, 0)
 212 BIT_N_R(4, c, RC, 1)
 213 BIT_N_R(4, d, RD, 2)
 214 BIT_N_R(4, e, RE, 3)
 215 BIT_N_R(4, h, RH, 4)
 216 BIT_N_R(4, l, RL, 5)
 217 BIT_N_R(4, a, RA, 7)
 218
 219 BIT_N_R(5, b, RB, 0)
 220 BIT_N_R(5, c, RC, 1)
 221 BIT_N_R(5, d, RD, 2)
 222 BIT_N_R(5, e, RE, 3)
 223 BIT_N_R(5, h, RH, 4)
 224 BIT_N_R(5, l, RL, 5)
 225 BIT_N_R(5, a, RA, 7)
 226
 227 BIT_N_R(6, b, RB, 0)
 228 BIT_N_R(6, c, RC, 1)
 229 BIT_N_R(6, d, RD, 2)
 230 BIT_N_R(6, e, RE, 3)
 231 BIT_N_R(6, h, RH, 4)
 232 BIT_N_R(6, l, RL, 5)
 233 BIT_N_R(6, a, RA, 7)
 234
 235 BIT_N_R(7, b, RB, 0)
 236 BIT_N_R(7, c, RC, 1)
 237 BIT_N_R(7, d, RD, 2)
 238 BIT_N_R(7, e, RE, 3)
 239 BIT_N_R(7, h, RH, 4)
 240 BIT_N_R(7, l, RL, 5)
 241 BIT_N_R(7, a, RA, 7)
 242
 243 BIT_N_IHL(0)
 244 BIT_N_IHL(1)
 245 BIT_N_IHL(2)
 246 BIT_N_IHL(3)
 247 BIT_N_IHL(4)
 248 BIT_N_IHL(5)
 249 BIT_N_IHL(6)
 250 BIT_N_IHL(7)
 251
 252 #define RES(r, n) r &= ~(1 << n)
 253
 254 #define RES_N_R(bn, rn, r, n) \
 255 OPDEF(res_ ## bn ## _ ## rn, 0x80+bn*8+n) \
 256 {                                         \
 257   RES(r, bn);                             \
 258   ENTIME(8);                              \
 259 }
 260
 261 #define RES_N_IHL(bn) \
 262 OPDEF(res_ ## bn ## _ihl, 0x86+bn*8) \
 263 {                                         \
 264   register byte btmp;                     \
 265   btmp = READ(GHL);                       \
 266   RES(btmp, bn);                          \
 267   WRITE(GHL, btmp);                       \
 268   ENTIME(15);                             \
 269 }
 270
 271
 272 RES_N_R(0, b, RB, 0)
 273 RES_N_R(0, c, RC, 1)
 274 RES_N_R(0, d, RD, 2)
 275 RES_N_R(0, e, RE, 3)
 276 RES_N_R(0, h, RH, 4)
 277 RES_N_R(0, l, RL, 5)
 278 RES_N_R(0, a, RA, 7)
 279
 280 RES_N_R(1, b, RB, 0)
 281 RES_N_R(1, c, RC, 1)
 282 RES_N_R(1, d, RD, 2)
 283 RES_N_R(1, e, RE, 3)
 284 RES_N_R(1, h, RH, 4)
 285 RES_N_R(1, l, RL, 5)
 286 RES_N_R(1, a, RA, 7)
 287
 288 RES_N_R(2, b, RB, 0)
 289 RES_N_R(2, c, RC, 1)
 290 RES_N_R(2, d, RD, 2)
 291 RES_N_R(2, e, RE, 3)
 292 RES_N_R(2, h, RH, 4)
 293 RES_N_R(2, l, RL, 5)
 294 RES_N_R(2, a, RA, 7)
 295
 296 RES_N_R(3, b, RB, 0)
 297 RES_N_R(3, c, RC, 1)
 298 RES_N_R(3, d, RD, 2)
 299 RES_N_R(3, e, RE, 3)
 300 RES_N_R(3, h, RH, 4)
 301 RES_N_R(3, l, RL, 5)
 302 RES_N_R(3, a, RA, 7)
 303
 304 RES_N_R(4, b, RB, 0)
 305 RES_N_R(4, c, RC, 1)
 306 RES_N_R(4, d, RD, 2)
 307 RES_N_R(4, e, RE, 3)
 308 RES_N_R(4, h, RH, 4)
 309 RES_N_R(4, l, RL, 5)
 310 RES_N_R(4, a, RA, 7)
 311
 312 RES_N_R(5, b, RB, 0)
 313 RES_N_R(5, c, RC, 1)
 314 RES_N_R(5, d, RD, 2)
 315 RES_N_R(5, e, RE, 3)
 316 RES_N_R(5, h, RH, 4)
 317 RES_N_R(5, l, RL, 5)
 318 RES_N_R(5, a, RA, 7)
 319
 320 RES_N_R(6, b, RB, 0)
 321 RES_N_R(6, c, RC, 1)
 322 RES_N_R(6, d, RD, 2)
 323 RES_N_R(6, e, RE, 3)
 324 RES_N_R(6, h, RH, 4)
 325 RES_N_R(6, l, RL, 5)
 326 RES_N_R(6, a, RA, 7)
 327
 328 RES_N_R(7, b, RB, 0)
 329 RES_N_R(7, c, RC, 1)
 330 RES_N_R(7, d, RD, 2)
 331 RES_N_R(7, e, RE, 3)
 332 RES_N_R(7, h, RH, 4)
 333 RES_N_R(7, l, RL, 5)
 334 RES_N_R(7, a, RA, 7)
 335
 336 RES_N_IHL(0)
 337 RES_N_IHL(1)
 338 RES_N_IHL(2)
 339 RES_N_IHL(3)
 340 RES_N_IHL(4)
 341 RES_N_IHL(5)
 342 RES_N_IHL(6)
 343 RES_N_IHL(7)
 344
 345
 346 #define SET(r, n) r |= (1 << n)
 347
 348 #define SET_N_R(bn, rn, r, n) \
 349 OPDEF(set_ ## bn ## _ ## rn, 0xC0+bn*8+n) \
 350 {                                         \
 351   SET(r, bn);                             \
 352   ENTIME(8);                              \
 353 }
 354
 355 #define SET_N_IHL(bn) \
 356 OPDEF(set_ ## bn ## _ihl, 0x86+bn*8) \
 357 {                                         \
 358   register byte btmp;                     \
 359   btmp = READ(GHL);                       \
 360   SET(btmp, bn);                          \
 361   WRITE(GHL, btmp);                       \
 362   ENTIME(15);                             \
 363 }
 364
 365
 366 SET_N_R(0, b, RB, 0)
 367 SET_N_R(0, c, RC, 1)
 368 SET_N_R(0, d, RD, 2)
 369 SET_N_R(0, e, RE, 3)
 370 SET_N_R(0, h, RH, 4)
 371 SET_N_R(0, l, RL, 5)
 372 SET_N_R(0, a, RA, 7)
 373
 374 SET_N_R(1, b, RB, 0)
 375 SET_N_R(1, c, RC, 1)
 376 SET_N_R(1, d, RD, 2)
 377 SET_N_R(1, e, RE, 3)
 378 SET_N_R(1, h, RH, 4)
 379 SET_N_R(1, l, RL, 5)
 380 SET_N_R(1, a, RA, 7)
 381
 382 SET_N_R(2, b, RB, 0)
 383 SET_N_R(2, c, RC, 1)
 384 SET_N_R(2, d, RD, 2)
 385 SET_N_R(2, e, RE, 3)
 386 SET_N_R(2, h, RH, 4)
 387 SET_N_R(2, l, RL, 5)
 388 SET_N_R(2, a, RA, 7)
 389
 390 SET_N_R(3, b, RB, 0)
 391 SET_N_R(3, c, RC, 1)
 392 SET_N_R(3, d, RD, 2)
 393 SET_N_R(3, e, RE, 3)
 394 SET_N_R(3, h, RH, 4)
 395 SET_N_R(3, l, RL, 5)
 396 SET_N_R(3, a, RA, 7)
 397
 398 SET_N_R(4, b, RB, 0)
 399 SET_N_R(4, c, RC, 1)
 400 SET_N_R(4, d, RD, 2)
 401 SET_N_R(4, e, RE, 3)
 402 SET_N_R(4, h, RH, 4)
 403 SET_N_R(4, l, RL, 5)
 404 SET_N_R(4, a, RA, 7)
 405
 406 SET_N_R(5, b, RB, 0)
 407 SET_N_R(5, c, RC, 1)
 408 SET_N_R(5, d, RD, 2)
 409 SET_N_R(5, e, RE, 3)
 410 SET_N_R(5, h, RH, 4)
 411 SET_N_R(5, l, RL, 5)
 412 SET_N_R(5, a, RA, 7)
 413
 414 SET_N_R(6, b, RB, 0)
 415 SET_N_R(6, c, RC, 1)
 416 SET_N_R(6, d, RD, 2)
 417 SET_N_R(6, e, RE, 3)
 418 SET_N_R(6, h, RH, 4)
 419 SET_N_R(6, l, RL, 5)
 420 SET_N_R(6, a, RA, 7)
 421
 422 SET_N_R(7, b, RB, 0)
 423 SET_N_R(7, c, RC, 1)
 424 SET_N_R(7, d, RD, 2)
 425 SET_N_R(7, e, RE, 3)
 426 SET_N_R(7, h, RH, 4)
 427 SET_N_R(7, l, RL, 5)
 428 SET_N_R(7, a, RA, 7)
 429
 430 SET_N_IHL(0)
 431 SET_N_IHL(1)
 432 SET_N_IHL(2)
 433 SET_N_IHL(3)
 434 SET_N_IHL(4)
 435 SET_N_IHL(5)
 436 SET_N_IHL(6)
 437 SET_N_IHL(7)