1 /* A portme.c for SDCC targeting the RCM3319 board
3 (c) 2021 Philipp Klaus Krause
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of the GNU General Public License as published by the
7 Free Software Foundation; either version 2, or (at your option) any
12 #include "stdcbench.h"
14 #define REG(addr, reg) __sfr __at(addr) reg
16 REG(0x00, GCSR); // global control / status register
17 REG(0x01, RTCCR); // Real Time Clock Control Register
18 REG(0x02, RTC0R); // Real Time Clock Data Register 0
19 REG(0x03, RTC1R); // Real Time Clock Data Register 1
20 REG(0x04, RTC2R); // Real Time Clock Data Register 2
21 REG(0x05, RTC3R); // Real Time Clock Data Register 3
22 REG(0x06, RTC4R); // Real Time Clock Data Register 4
23 REG(0x07, RTC5R); // Real Time Clock Data Register 5
24 REG(0x08, WDTCR); // watch-dog timer control register
25 REG(0x09, WDTTR); // watch-dog timer test register
26 REG(0x0F, GCDR); // global clock double register
27 REG(0x14, MB0CR); // Memory Bank 0 Control Register
28 REG(0x16, MB2CR); // Memory Bank 2 Control Register
29 REG(0x55, PCFR); // Port C Function Register
30 REG(0xA0, TACSR); // Timer A Control/Status Register
31 REG(0xA9, TAT4R); // Timer A Time Constant 4 Register
32 REG(0xC0, SADR); // Serial Port A Data Register
33 REG(0xC3, SASR); // Serial Port A Status Register
34 REG(0xC4, SACR); // Serial Port A Control Register
36 void stdcbench_error(const char *message)
38 printf("ERROR: %s\n", message);
44 #if __STDC_VERSION__ < 201112L
48 #if __SDCC_REVISION >= 13762
49 unsigned char __sdcc_external_startup(void)
51 unsigned char _sdcc_external_startup(void)
58 // normal oscillator, processor and peripheral from main clock, no periodic interrupt
61 GCDR = 0x07; // Double clock to get more speed
63 // Configure memory wait states
64 MB0CR = 0x88; // Flash - 1 wait state (for 45 ns Flash @ 44.2 MHz) with write-protection
65 MB2CR = 0x85; // RAM - 1 wait states (for 55 ns RAM @ 44.2 MHz)
72 PCFR = 0x40; // Use pin PC6 as TXA
73 TAT4R = 36 - 1; // Use divider for 38400 baud - value in register is one less than the divider used (e.g. a value of 0 will result in clock division by 1).
74 TACSR = 0x01; // Enable timer A
75 SACR = 0x00; // No interrupts, 8-bit async mode
78 stdcbench_clock_t stdcbench_clock(void)
80 stdcbench_clock_t clock0, clock1;
84 clock0 = ((stdcbench_clock_t)(RTC0R) << 0) | ((stdcbench_clock_t)(RTC1R) << 8) | ((stdcbench_clock_t)(RTC2R) << 16) | ((stdcbench_clock_t)(RTC3R) << 24);
85 clock1 = ((stdcbench_clock_t)(RTC0R) << 0) | ((stdcbench_clock_t)(RTC1R) << 8) | ((stdcbench_clock_t)(RTC2R) << 16) | ((stdcbench_clock_t)(RTC3R) << 24);
86 } while (clock0 != clock1);
90 #if defined(__SDCC) && __SDCC_REVISION < 9624 // Old SDCC weirdness
93 while (SASR & 0x04); // Wait for empty transmitter data register
99 while (SASR & 0x04); // Wait for empty transmitter data register
105 _Noreturn void main(void)
111 printf("\n%s\n", stdcbench_name_version_string);
116 printf("stdcbench c90base score: %lu\n", c90base_score);
119 printf("stdcbench c90lib score: %lu\n", c90lib_score);
121 printf("stdcbench final score: %lu\n", score);