sdcc/device/include/ds80c390.h

   1 /*-------------------------------------------------------------------------
   2    ds80c390.h - Register Declarations for the DALLAS DS80C390 Processor
   3                  far from complete, e.g. no CAN
   4
   5    Copyright (C) 2000, Johan Knol <johan.knol AT iduna.nl>
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef DS80C390_H
  31 #define DS80C390_H
  32
  33 __sfr __at (0x80) P4;           /* ce3..ce0, a19..a16 */
  34 __sfr __at (0x81) SP;           /* stack pointer */
  35 __sfr __at (0x82) DPL;          /* data pointer 0 lsb */
  36 __sfr __at (0x83) DPH;          /* data pointer 0 msb */
  37 __sfr __at (0x84) DPL1;         /* data pointer 1 lsb */
  38 __sfr __at (0x85) DPH1;         /* data pointer 1 msb */
  39 __sfr __at (0x86) DPS;          /* data pointer select */
  40 __sfr __at (0x87) PCON;         /* power control */
  41 __sfr __at (0x88) TCON;         /* timer/counter control */
  42   __sbit __at (0x88) IT0;
  43   __sbit __at (0x89) IE0;
  44   __sbit __at (0x8a) IT1;
  45   __sbit __at (0x8b) IE1;
  46   __sbit __at (0x8c) TR0;
  47   __sbit __at (0x8d) TF0;
  48   __sbit __at (0x8e) TR1;
  49   __sbit __at (0x8f) TF1;
  50 __sfr __at (0x89) TMOD;         /* timer mode control */
  51 __sfr __at (0x8a) TL0;          /* timer 0 lsb */
  52 __sfr __at (0x8b) TL1;          /* timer 1 msb */
  53 __sfr __at (0x8c) TH0;          /* timer 0 msb */
  54 __sfr __at (0x8d) TH1;          /* timer 1 msb */
  55 __sfr __at (0x8e) CKCON;        /* clock control */
  56 __sfr __at (0x90) P1;
  57   __sbit __at (0x90) T2;
  58   __sbit __at (0x91) T2EX;
  59   __sbit __at (0x92) RXD1;
  60   __sbit __at (0x93) TXD1;
  61   __sbit __at (0x94) INT2;
  62   __sbit __at (0x95) INT3;
  63   __sbit __at (0x96) INT4;
  64   __sbit __at (0x97) INT5;
  65 __sfr __at (0x91) EXIF;         /* external interrupt flag */
  66 __sfr __at (0x92) P4CNT;
  67 __sfr __at (0x93) DPX;          /* extended datapointer 0 */
  68 __sfr __at (0x95) DPX1;         /* extended datapointer 1 */
  69 __sfr __at (0x98) SCON0;        /* serial 0 control */
  70   __sbit __at (0x98) RI_0;
  71   __sbit __at (0x99) TI_0;
  72   __sbit __at (0x9a) RB8_0;
  73   __sbit __at (0x9b) TB8_0;
  74   __sbit __at (0x9c) REN_0;
  75   __sbit __at (0x9d) SM2_0;
  76   __sbit __at (0x9e) SM1_0;
  77   __sbit __at (0x9f) SM0_0;
  78   __sbit __at (0x9f) FE_0;      /* depending on SMOD0 */
  79 __sfr __at (0x99) SBUF0;        /* serial 0 data buffer */
  80 __sfr __at (0x9b) ESP;          /* extended stack pointer */
  81 __sfr __at (0x9c) AP;           /* address page */
  82 __sfr __at (0x9d) ACON;         /* address control */
  83 __sfr __at (0xa0) P2;           /* never mind the sbits */
  84 __sfr __at (0xa1) P5;
  85 __sfr __at (0xa2) P5CNT;
  86 __sfr __at (0xa8) IE;           /* interrupt enable */
  87   __sbit __at (0xa8) EX0;
  88   __sbit __at (0xa9) ET0;
  89   __sbit __at (0xaa) EX1;
  90   __sbit __at (0xab) ET1;
  91   __sbit __at (0xac) ES0;
  92   __sbit __at (0xad) ET2;
  93   __sbit __at (0xae) ES1;
  94   __sbit __at (0xaf) EA;
  95 __sfr __at (0xb0) P3;
  96   __sbit __at (0xb0) RXD0;
  97   __sbit __at (0xb1) TXD0;
  98   __sbit __at (0xb2) INT0;
  99   __sbit __at (0xb3) INT1;
 100   __sbit __at (0xb4) T0;
 101   __sbit __at (0xb5) T1;
 102   __sbit __at (0xb6) WR;
 103   __sbit __at (0xb7) RD;
 104 __sfr __at (0xb8) IP;           /* interupt priority */
 105   __sbit __at (0xb8) PX0;       /* external 0 */
 106   __sbit __at (0xb9) PT0;       /* timer 0 */
 107   __sbit __at (0xba) PX1;       /* external 1 */
 108   __sbit __at (0xbb) PT1;       /* timer 1 */
 109   __sbit __at (0xbc) PS0;       /* serial port 0 */
 110   __sbit __at (0xbd) PT2;       /* timer 2 */
 111   __sbit __at (0xbe) PS1;       /* serial port 1 */
 112 __sfr __at (0xc0) SCON1;        /* serial 1 control */
 113   __sbit __at (0xc0) RI_1;
 114   __sbit __at (0xc1) TI_1;
 115   __sbit __at (0xc2) RB8_1;
 116   __sbit __at (0xc3) TB8_1;
 117   __sbit __at (0xc4) REN_1;
 118   __sbit __at (0xc5) SM2_1;
 119   __sbit __at (0xc6) SM1_1;
 120   __sbit __at (0xc7) SM0_1;
 121   __sbit __at (0xc7) FE_1;      /* depending on SMOD0 */
 122 __sfr __at (0xc1) SBUF1;        /* serial 1 data buffer */
 123 __sfr __at (0xc4) PMR;          /* power managment */
 124 __sfr __at (0xc6) MCON;         /* memory control register */
 125 __sfr __at (0xc7) TA;           /* timed access register */
 126 __sfr __at (0xc8) T2CON;        /* timer 2 control */
 127   __sbit __at (0xc8) CP_RL;     /* capture/reload */
 128   __sbit __at (0xc9) C_T;       /* count/timer */
 129   __sbit __at (0xca) TR2;       /* stop/run */
 130   __sbit __at (0xcb) EXEN2;
 131   __sbit __at (0xcc) TCLK;
 132   __sbit __at (0xcd) RCLK;
 133   __sbit __at (0xce) EXF2;
 134   __sbit __at (0xcf) TF2;       /* overflow flag */
 135 __sfr __at (0xc9) T2MOD;        /* timer 2 mode */
 136 __sfr __at (0xca) RCAP2L;       /* timer 2 capture/reload */
 137 __sfr __at (0xca) RTL2;         /* depends on CP_RL */
 138 __sfr __at (0xcb) RCAP2H;
 139 __sfr __at (0xcb) RTH2;
 140 __sfr __at (0xcc) TL2;          /* timer 2 lsb */
 141 __sfr __at (0xcd) TH2;          /* timer 2 msb */
 142 __sfr __at (0xd0) PSW;          /* program status word (byte actually) */
 143   __sbit __at (0xd0) P;         /* parity */
 144   __sbit __at (0xd1) F1;        /* user flag 1 */
 145   __sbit __at (0xd2) OV;        /* overflow flag */
 146   __sbit __at (0xd3) RS0;       /* register select l */
 147   __sbit __at (0xd4) RS1;       /* register select h */
 148   __sbit __at (0xd5) F0;        /* user flag 0 */
 149   __sbit __at (0xd6) AC;        /* auxiliary carry flag */
 150   __sbit __at (0xd7) CY;        /* carry flag */
 151 __sfr __at (0xd1) MCNT0;        /* arithmetic accellerator */
 152 __sfr __at (0xd2) MCNT1;
 153 __sfr __at (0xd3) MA;
 154 __sfr __at (0xd4) MB;
 155 __sfr __at (0xd5) MC;
 156 __sfr __at (0xd8) WDCON;        /* watch dog */
 157   __sbit __at (0xd8) RWT;
 158   __sbit __at (0xd9) EWT;
 159   __sbit __at (0xda) WDRF;
 160   __sbit __at (0xdb) WDIF;
 161   __sbit __at (0xdc) PFI;
 162   __sbit __at (0xdd) EPFI;
 163   __sbit __at (0xde) POR;
 164   __sbit __at (0xdf) SMOD_1;
 165 __sfr __at (0xe0) ACC;          /* accumulator */
 166 __sfr __at (0xe8) EIE;          /* extended interrupt enable */
 167   __sbit __at (0xe8) EX2;
 168   __sbit __at (0xe9) EX3;
 169   __sbit __at (0xea) EX4;
 170   __sbit __at (0xeb) EX5;
 171   __sbit __at (0xec) EWDI;
 172   __sbit __at (0xed) C1IE;
 173   __sbit __at (0xee) C0IE;
 174   __sbit __at (0xef) CANBIE;
 175 __sfr __at (0xea) MXAX;         /* extended address register */
 176 __sfr __at (0xf0) B;            /* aux accumulator */
 177 __sfr __at (0xf8) EIP;          /* extended interrupt priority */
 178   __sbit __at (0xf8) PX2;
 179   __sbit __at (0xf9) PX3;
 180   __sbit __at (0xfa) PX4;
 181   __sbit __at (0xfb) PX5;
 182   __sbit __at (0xfc) PWDI;
 183   __sbit __at (0xfd) C1IP;
 184   __sbit __at (0xfe) C0IP;
 185   __sbit __at (0xff) CANBIP;
 186
 187 /*  WORD/DWORD Registers  */
 188
 189 __sfr16 __at (0x8C8A) TMR0;  /* TIMER 0 COUNTER                                 */
 190 __sfr16 __at (0x8D8B) TMR1;  /* TIMER 1 COUNTER                 */
 191 __sfr16 __at (0xCDCC) TMR2;  /* TIMER 2 COUNTER                 */
 192 __sfr16 __at (0xCBCA) RCAP2; /* TIMER 2 CAPTURE REGISTER WORD   */
 193
 194 #endif /* DS80C390_H */