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Hackfix and re-enable strtoull and wcstoull, see bug #3798.
[sdcc.git] / sdcc / device / include / mcs51 / C8051F200.h
blob5eb67da04d0f2b1c0c3949b0a2e323b54d93bbcb
1 /*---------------------------------------------------------------------------
2 C8051F200.h - Register Declarations for the Cygnal/SiLabs C8051F2xx
3 Processor Range
4
5 Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30 #ifndef C8051F200_H
31 #define C8051F200_H
32
33
34 /* BYTE Registers */
35 __sfr __at (0x80) P0 ; /* PORT 0 */
36 __sfr __at (0x81) SP ; /* STACK POINTER */
37 __sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
38 __sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
39 __sfr __at (0x87) PCON ; /* POWER Control */
40 __sfr __at (0x88) TCON ; /* TIMER Control */
41 __sfr __at (0x89) TMOD ; /* TIMER MODE */
42 __sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
43 __sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
44 __sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
45 __sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
46 __sfr __at (0x8E) CKCON ; /* CLOCK Control */
47 __sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W Control */
48 __sfr __at (0x90) P1 ; /* PORT 1 */
49 __sfr __at (0x98) SCON ; /* SERIAL PORT Control */
50 __sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
51 __sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 Configuration */
52 __sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
53 __sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE Control */
54 __sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 Control */
55 __sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 Control */
56 __sfr __at (0xA0) P2 ; /* PORT 2 */
57 __sfr __at (0xA4) PRT0CF ; /* PORT 0 OUTPUT MODE Configuration */
58 __sfr __at (0xA5) PRT1CF ; /* PORT 1 OUTPUT MODE Configuration */
59 __sfr __at (0xA6) PRT2CF ; /* PORT 2 OUTPUT MODE Configuration */
60 __sfr __at (0xA7) PRT3CF ; /* PORT 3 OUTPUT MODE Configuration */
61 __sfr __at (0xA8) IE ; /* Interrupt Enable */
62 __sfr __at (0xAD) SWCINT ; /* SOFTWARE-Controlled Interrupt FLAGS */
63 __sfr __at (0xAD) PRT1IF ; /* SOFTWARE-Controlled Interrupt FLAGS (LEGACY NAME) */
64 __sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE Control (F206/F226/F236)*/
65 __sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */
66 __sfr __at (0xB0) P3 ; /* PORT 3 */
67 __sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR Control */
68 __sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR Control */
69 __sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
70 __sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
71 __sfr __at (0xB8) IP ; /* Interrupt Priority */
72 __sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION (Not on F230/1/6) */
73 __sfr __at (0xBC) ADC0CF ; /* ADC 0 Configuration (Not on F230/1/6) */
74 __sfr __at (0xBE) ADC0L ; /* ADC 0 Data LOW ( F206 only ) */
75 __sfr __at (0xBF) ADC0H ; /* ADC 0 Data High */
76 __sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN Register LOW( F206 only ) */
77 __sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN Register (Not on F230/1/6) */
78 __sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN Register LOW ( F206 only ) */
79 __sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN Register (Not on F230/1/6) */
80 __sfr __at (0xC8) T2CON ; /* TIMER 2 Control */
81 __sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE Register - LOW BYTE */
82 __sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE Register - HIGH BYTE */
83 __sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
84 __sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
85 __sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
86 __sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 Control */
87 __sfr __at (0xE0) ACC ; /* ACCUMULATOR */
88 __sfr __at (0xE1) PRT0MX ; /* PORT MUX Configuration Register 0 */
89 __sfr __at (0xE2) PRT1MX ; /* PORT MUX Configuration Register 1 */
90 __sfr __at (0xE3) PRT2MX ; /* PORT MUX Configuration Register 2 */
91 __sfr __at (0xE6) EIE1 ; /* EXTERNAL Interrupt Enable 1 */
92 __sfr __at (0xE7) EIE2 ; /* EXTERNAL Interrupt Enable 2 */
93 __sfr __at (0xE8) ADC0CN ; /* ADC 0 Control (Not on F230/1/6) */
94 __sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
95 __sfr __at (0xF0) B ; /* B Register */
96 __sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE Configuration */
97 __sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE Configuration */
98 __sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE Configuration */
99 __sfr __at (0xF4) P3MODE ; /* PORT 3 INPUT MODE Configuration (Not on F221/F231)*/
100 __sfr __at (0xF6) EIP1 ; /* EXTERNAL Interrupt Priority Register 1 */
101 __sfr __at (0xF7) EIP2 ; /* EXTERNAL Interrupt Priority Register 2 */
102 __sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 Control */
103 __sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER Control */
104
105
106 /* WORD/DWORD Registers */
107
108 __sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
109 __sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
110 __sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
111 __sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
112 __sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
113 __sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
114 __sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
115
116
117 /* BIT Registers */
118
119 /* P0 0x80 */
120 __sbit __at (0x80) P0_0 ;
121 __sbit __at (0x81) P0_1 ;
122 __sbit __at (0x82) P0_2 ;
123 __sbit __at (0x83) P0_3 ;
124 __sbit __at (0x84) P0_4 ; /* Port0 I/O Bits */
125 __sbit __at (0x85) P0_5 ;
126 __sbit __at (0x86) P0_6 ;
127 __sbit __at (0x87) P0_7 ;
128
129 /* TCON 0x88 */
130 __sbit __at (0x88) IT0 ; /* EXT. Interrupt 0 TYPE */
131 __sbit __at (0x89) IE0 ; /* EXT. Interrupt 0 EDGE FLAG */
132 __sbit __at (0x8A) IT1 ; /* EXT. Interrupt 1 TYPE */
133 __sbit __at (0x8B) IE1 ; /* EXT. Interrupt 1 EDGE FLAG */
134 __sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF Control */
135 __sbit __at (0x8D) TF0 ; /* TIMER 0 Overflow FLAG */
136 __sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF Control */
137 __sbit __at (0x8F) TF1 ; /* TIMER 1 Overflow FLAG */
138
139 /* P1 0x90 */
140 __sbit __at (0x90) P1_0 ;
141 __sbit __at (0x91) P1_1 ;
142 __sbit __at (0x92) P1_2 ;
143 __sbit __at (0x93) P1_3 ;
144 __sbit __at (0x94) P1_4 ; /* Port1 I/O Bits */
145 __sbit __at (0x95) P1_5 ;
146 __sbit __at (0x96) P1_6 ;
147 __sbit __at (0x97) P1_7 ;
148
149 /* SCON 0x98 */
150 __sbit __at (0x98) RI ; /* RECEIVE Interrupt FLAG */
151 __sbit __at (0x99) TI ; /* TRANSMIT Interrupt FLAG */
152 __sbit __at (0x9A) RB8 ; /* RECEIVE BIT 8 */
153 __sbit __at (0x9B) TB8 ; /* TRANSMIT BIT 8 */
154 __sbit __at (0x9C) REN ; /* RECEIVE Enable */
155 __sbit __at (0x9D) SM2 ; /* MULTIPROCESSOR COMMUNICATION Enable */
156 __sbit __at (0x9E) SM1 ; /* SERIAL MODE Control BIT 1 */
157 __sbit __at (0x9F) SM0 ; /* SERIAL MODE Control BIT 0 */
158
159 /* P2 0xA0 */
160 __sbit __at (0xA0) P2_0 ;
161 __sbit __at (0xA1) P2_1 ;
162 __sbit __at (0xA2) P2_2 ;
163 __sbit __at (0xA3) P2_3 ;
164 __sbit __at (0xA4) P2_4 ; /* Port2 I/O Bits */
165 __sbit __at (0xA5) P2_5 ;
166 __sbit __at (0xA6) P2_6 ;
167 __sbit __at (0xA7) P2_7 ;
168
169 /* IE 0xA8 */
170 __sbit __at (0xA8) EX0 ; /* EXTERNAL Interrupt 0 Enable */
171 __sbit __at (0xA9) ET0 ; /* TIMER 0 Interrupt Enable */
172 __sbit __at (0xAA) EX1 ; /* EXTERNAL Interrupt 1 Enable */
173 __sbit __at (0xAB) ET1 ; /* TIMER 1 Interrupt Enable */
174 __sbit __at (0xAC) ES ; /* SERIAL PORT Interrupt Enable */
175 __sbit __at (0xAD) ET2 ; /* TIMER 2 Interrupt Enable */
176 //------------- /* Bit 6 not used */
177 __sbit __at (0xAF) EA ; /* GLOBAL Interrupt Enable */
178
179 /* P2 0xB0 */
180 __sbit __at (0xB0) P3_0 ;
181 __sbit __at (0xB1) P3_1 ;
182 __sbit __at (0xB2) P3_2 ;
183 __sbit __at (0xB3) P3_3 ;
184 __sbit __at (0xB4) P3_4 ; /* Port3 I/O Bits */
185 __sbit __at (0xB5) P3_5 ;
186 __sbit __at (0xB6) P3_6 ;
187 __sbit __at (0xB7) P3_7 ;
188
189 /* IP 0xB8 */
190 __sbit __at (0xB8) PX0 ; /* EXTERNAL Interrupt 0 Priority */
191 __sbit __at (0xB9) PT0 ; /* TIMER 0 Priority */
192 __sbit __at (0xBA) PX1 ; /* EXTERNAL Interrupt 1 Priority */
193 __sbit __at (0xBB) PT1 ; /* TIMER 1 Priority */
194 __sbit __at (0xBC) PS ; /* SERIAL PORT Priority */
195 __sbit __at (0xBD) PT2 ; /* TIMER 2 Priority */
196 //------------- /* Bit 6 not used */
197 //------------- /* Bit 7 not used */
198
199 /* T2CON 0xC8 */
200 __sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
201 __sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
202 __sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF Control */
203 __sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL Enable FLAG */
204 __sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
205 __sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
206 __sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
207 __sbit __at (0xCF) TF2 ; /* TIMER 2 Overflow FLAG */
208
209 /* PSW 0xD0 */
210 __sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
211 __sbit __at (0xD1) F1 ; /* USER FLAG 1 */
212 __sbit __at (0xD2) OV ; /* Overflow FLAG */
213 __sbit __at (0xD3) RS0 ; /* Register BANK SELECT 0 */
214 __sbit __at (0xD4) RS1 ; /* Register BANK SELECT 1 */
215 __sbit __at (0xD5) F0 ; /* USER FLAG 0 */
216 __sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
217 __sbit __at (0xD7) CY ; /* CARRY FLAG */
218
219 /* ADC0CN 0xE8 */
220 __sbit __at (0xE8) ADLJST ; /* Left Justify Data (F206 only) */
221 __sbit __at (0xE9) ADWINT ; /* WINDOW COMPARE Interrupt FLAG */
222 __sbit __at (0xEA) ADSTM0 ; /* START OF CONVERSION MODE BIT 0 */
223 __sbit __at (0xEB) ADSTM1 ; /* START OF CONVERSION MODE BIT 1 */
224 __sbit __at (0xEC) ADBUSY ; /* BUSY FLAG */
225 __sbit __at (0xED) ADCINT ; /* CONVERISION COMPLETE Interrupt FLAG */
226 __sbit __at (0xEE) ADCTM ; /* TRACK MODE */
227 __sbit __at (0xEF) ADCEN ; /* Enable */
228
229 /* SPI0CN 0xF8 */
230 __sbit __at (0xF8) SPIEN ; /* SPI Enable */
231 __sbit __at (0xF9) MSTEN ; /* MASTER Enable */
232 __sbit __at (0xFA) SLVSEL ; /* SLAVE SELECT */
233 __sbit __at (0xFB) TXBSY ; /* TX BUSY FLAG */
234 __sbit __at (0xFC) RXOVRN ; /* RX OVERRUN FLAG */
235 __sbit __at (0xFD) MODF ; /* MODE FAULT FLAG */
236 __sbit __at (0xFE) WCOL ; /* WRITE COLLISION FLAG */
237 __sbit __at (0xFF) SPIF ; /* Interrupt FLAG */
238
239 #endif
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