sdcc/device/include/mcs51/C8051F360.h

   1 /*-------------------------------------------------------------------------
   2    C8051F360.h - Register Declarations for the SiLabs C8051F36x
   3    Processor Range
   4
   5    Copyright (C) 2007, Maarten Brock, sourceforge.brock@dse.nl
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef C8051F360_H
  31 #define C8051F360_H
  32
  33 #include <compiler.h>
  34
  35 /*  All Pages */
  36
  37 SFR(P0,         0x80);      // Port 0
  38    SBIT(P0_0,     0x80, 0); // Port 0 bit 0
  39    SBIT(P0_1,     0x80, 1); // Port 0 bit 1
  40    SBIT(P0_2,     0x80, 2); // Port 0 bit 2
  41    SBIT(P0_3,     0x80, 3); // Port 0 bit 3
  42    SBIT(P0_4,     0x80, 4); // Port 0 bit 4
  43    SBIT(P0_5,     0x80, 5); // Port 0 bit 5
  44    SBIT(P0_6,     0x80, 6); // Port 0 bit 6
  45    SBIT(P0_7,     0x80, 7); // Port 0 bit 7
  46 SFR(SP,         0x81);      // Stack Pointer
  47 SFR(DPL,        0x82);      // Data Pointer Low Byte
  48 SFR(DPH,        0x83);      // Data Pointer High Byte
  49 SFR(SFRNEXT,    0x85);      // SFR Stack Next Page
  50 SFR(SFRLAST,    0x86);      // SFR Stack Last Page
  51 SFR(PCON,       0x87);      // Power Mode Control
  52 SFR(TCON,       0x88);      // Timer Control
  53    SBIT(IT0,      0x88, 0); // Ext. Interrupt 0 Type Select
  54    SBIT(IE0,      0x88, 1); // Ext. Interrupt 0 Flag
  55    SBIT(IT1,      0x88, 2); // Ext. Interrupt 1 Type Select
  56    SBIT(IE1,      0x88, 3); // Ext. Interrupt 1 Flag
  57    SBIT(TR0,      0x88, 4); // Timer 0 Run Control
  58    SBIT(TF0,      0x88, 5); // Timer 0 Overflow Flag
  59    SBIT(TR1,      0x88, 6); // Timer 1 Run Control
  60    SBIT(TF1,      0x88, 7); // Timer 1 Overflow Flag
  61 SFR(TMOD,       0x89);      // Timer Mode
  62 SFR16E(TMR0,    0x8C8A);    // Timer/Counter 0 Word
  63    SFR(TL0,       0x8A);    // Timer/Counter 0 Low Byte
  64    SFR(TH0,       0x8C);    // Timer/Counter 0 High Byte
  65 SFR16E(TMR1,    0x8D8B);    // Timer/Counter 1 Word
  66    SFR(TL1,       0x8B);    // Timer/Counter 1 Low Byte
  67    SFR(TH1,       0x8D);    // Timer/Counter 1 High Byte
  68 SFR(CKCON,      0x8E);      // Clock Control
  69 SFR(P1,         0x90);      // Port 1
  70    SBIT(P1_0,     0x90, 0); // Port 1 bit 0
  71    SBIT(P1_1,     0x90, 1); // Port 1 bit 1
  72    SBIT(P1_2,     0x90, 2); // Port 1 bit 2
  73    SBIT(P1_3,     0x90, 3); // Port 1 bit 3
  74    SBIT(P1_4,     0x90, 4); // Port 1 bit 4
  75    SBIT(P1_5,     0x90, 5); // Port 1 bit 5
  76    SBIT(P1_6,     0x90, 6); // Port 1 bit 6
  77    SBIT(P1_7,     0x90, 7); // Port 1 bit 7
  78 SFR(TMR3CN,     0x91);      // Timer 3 Control
  79 SFR16(TMR3RL,   0x92);      // Timer 3 Reload Register Word
  80    SFR(TMR3RLL,    0x92);   // Timer 3 Reload Register Low Byte
  81    SFR(TMR3RLH,    0x93);   // Timer 3 Reload Register High Byte
  82 SFR16(TMR3,     0x94);      // Timer 3 Word
  83    SFR(TMR3L,      0x94);   // Timer 3 Low Byte
  84    SFR(TMR3H,      0x95);   // Timer 3 High Byte
  85 SFR16(IDA0,     0x96);      // IDAC 0 Word
  86    SFR(IDA0L,      0x96);   // IDAC 0 Low Byte
  87    SFR(IDA0H,      0x97);   // IDAC 0 High Byte
  88 SFR(SCON0,      0x98);      // Serial Port 0 Control
  89    SBIT(RI0,      0x98, 0); // Receive Interrupt Flag
  90    SBIT(TI0,      0x98, 1); // Transmit Interrupt Flag
  91    SBIT(RB80,     0x98, 2); // Ninth Receive Bit
  92    SBIT(TB80,     0x98, 3); // Ninth Transmission Bit
  93    SBIT(REN0,     0x98, 4); // Receive Enable
  94    SBIT(MCE0,     0x98, 5); // Multiprocessor Communication Enable
  95    SBIT(S0MODE,   0x98, 7); // Serial Port 0 Operation Mode
  96 SFR(SBUF0,      0x99);      // Serial Port 0 Data Buffer
  97 SFR(CPT1CN,     0x9A);      // Comparator 1 Control
  98 SFR(CPT0CN,     0x9B);      // Comparator 0 Control
  99 SFR(CPT1MD,     0x9C);      // Comparator 1 Mode Selection
 100 SFR(CPT0MD,     0x9D);      // Comparator 0 Mode Selection
 101 SFR(CPT1MX,     0x9E);      // Comparator 1 MUX Selection
 102 SFR(CPT0MX,     0x9F);      // Comparator 0 MUX Selection
 103 SFR(P2,         0xA0);      // Port 2
 104    SBIT(P2_0,     0xA0, 0); // Port 2 bit 0
 105    SBIT(P2_1,     0xA0, 1); // Port 2 bit 1
 106    SBIT(P2_2,     0xA0, 2); // Port 2 bit 2
 107    SBIT(P2_3,     0xA0, 3); // Port 2 bit 3
 108    SBIT(P2_4,     0xA0, 4); // Port 2 bit 4
 109    SBIT(P2_5,     0xA0, 5); // Port 2 bit 5
 110    SBIT(P2_6,     0xA0, 6); // Port 2 bit 6
 111    SBIT(P2_7,     0xA0, 7); // Port 2 bit 7
 112 SFR(SPI0CFG,    0xA1);      // SPI Configuration
 113 SFR(SPI0CKR,    0xA2);      // SPI Clock Rate Control
 114 SFR(SPI0DAT,    0xA3);      // SPI Data
 115 SFR(SFRPAGE,    0xA7);      // SFR Page Select
 116 SFR(IE,         0xA8);      // Interrupt Enable
 117    SBIT(EX0,      0xA8, 0); // Enable External Interrupt 0
 118    SBIT(ET0,      0xA8, 1); // Enable Timer 0 Interrupt
 119    SBIT(EX1,      0xA8, 2); // Enable External Interrupt 1
 120    SBIT(ET1,      0xA8, 3); // Enable Timer 1 Interrupt
 121    SBIT(ES0,      0xA8, 4); // Enable Serial Port Interrupt
 122    SBIT(ET2,      0xA8, 5); // Enable Timer 2 Interrupt
 123    SBIT(ESPI0,    0xA8, 6); // Enable SPI0 Interrupt
 124    SBIT(EA,       0xA8, 7); // Global Interrupt Enable
 125 SFR(EMI0CN,     0xAA);      // EMIF Control
 126 SFR(_XPAGE,     0xAA);      // SDCC: XDATA/PDATA Page
 127 SFR(P3,         0xB0);      // Port 3
 128    SBIT(P3_0,     0xB0, 0); // Port 3 bit 0
 129    SBIT(P3_1,     0xB0, 1); // Port 3 bit 1
 130    SBIT(P3_2,     0xB0, 2); // Port 3 bit 2
 131    SBIT(P3_3,     0xB0, 3); // Port 3 bit 3
 132    SBIT(P3_4,     0xB0, 4); // Port 3 bit 4
 133    SBIT(P3_5,     0xB0, 5); // Port 3 bit 5
 134    SBIT(P3_6,     0xB0, 6); // Port 3 bit 6
 135    SBIT(P3_7,     0xB0, 7); // Port 3 bit 7
 136 SFR(P4,         0xB5);      // Port 4
 137 SFR(IP,         0xB8);      // Interrupt Priority
 138    SBIT(PX0,      0xB8, 0); // External Interrupt 0 Priority
 139    SBIT(PT0,      0xB8, 1); // Timer 0 Interrupt Priority
 140    SBIT(PX1,      0xB8, 2); // External Interrupt 1 Priority
 141    SBIT(PT1,      0xB8, 3); // Timer 1 Interrupt Priority
 142    SBIT(PS0,      0xB8, 4); // Serial Port Interrupt Priority
 143    SBIT(PT2,      0xB8, 5); // Timer 2 Interrupt Priority
 144    SBIT(PSPI0,    0xB8, 6); // SPI0 Interrupt Priority
 145 SFR(IDA0CN,     0xB9);      // IDAC 0 Control
 146 SFR(AMX0N,      0xBA);      // AMUX 0 Negative Channel Select
 147 SFR(AMX0P,      0xBB);      // AMUX 0 Positive Channel Select
 148 SFR(ADC0CF,     0xBC);      // ADC0 Configuration
 149 SFR16(ADC0,     0xBD);      // ADC0 Word
 150    SFR(ADC0L,     0xBD);    // ADC0 Low Byte
 151    SFR(ADC0H,     0xBE);    // ADC0 High Byte
 152 SFR(SMB0CN,     0xC0);      // SMBus Control
 153    SBIT(SI,       0xC0, 0); // SMBus Interrupt Flag
 154    SBIT(ACK,      0xC0, 1); // SMBus Acknowledge Flag
 155    SBIT(ARBLOST,  0xC0, 2); // SMBus Arbitration Lost Indicator
 156    SBIT(ACKRQ,    0xC0, 3); // SMBus Acknowledge Request
 157    SBIT(STO,      0xC0, 4); // SMBus Stop Flag
 158    SBIT(STA,      0xC0, 5); // SMBus Start Flag
 159    SBIT(TXMODE,   0xC0, 6); // SMBus Transmit Mode Indicator
 160    SBIT(MASTER,   0xC0, 7); // SMBus Master/Slave Indicator
 161 SFR(SMB0CF,     0xC1);      // SMBus Configuration
 162 SFR(SMB0DAT,    0xC2);      // SMBus Data
 163 SFR16(ADC0GT,   0xC3);      // ADC0 Greater-Than Data Word
 164    SFR(ADC0GTL,   0xC3);    // ADC0 Greater-Than Data Low Byte
 165    SFR(ADC0GTH,   0xC4);    // ADC0 Greater-Than Data High Byte
 166 SFR16(ADC0LT,   0xC5);      // ADC0 Less-Than Data Word
 167    SFR(ADC0LTL,   0xC5);    // ADC0 Less-Than Data Low Byte
 168    SFR(ADC0LTH,   0xC6);    // ADC0 Less-Than Data High Byte
 169 SFR(TMR2CN,     0xC8);      // Timer/Counter 2 Control
 170    SBIT(T2XCLK,   0xC8, 0); // Timer 2 External Clock Select
 171    SBIT(TR2,      0xC8, 2); // Timer 2 Run Control
 172    SBIT(T2SPLIT,  0xC8, 3); // Timer 2 Split Mode Enable
 173    SBIT(TF2CEN,   0xC8, 4); // Timer 2 Low-Frequency Oscillator Capture Enable
 174    SBIT(TF2LEN,   0xC8, 5); // Timer 2 Low Byte Interrupt Enable
 175    SBIT(TF2L,     0xC8, 6); // Timer 2 Low Byte Overflow Flag
 176    SBIT(TF2H,     0xC8, 7); // Timer 2 High Byte Overflow Flag
 177 SFR16(TMR2RL,   0xCA);      // Timer/Counter 2 Reload Word
 178    SFR(TMR2RLL,   0xCA);    // Timer/Counter 2 Reload Low Byte
 179    SFR(TMR2RLH,   0xCB);    // Timer/Counter 2 Reload High Byte
 180 SFR16(TMR2,     0xCC);      // Timer/Counter 2 Word
 181    SFR(TMR2L,     0xCC);    // Timer/Counter 2 Low Byte
 182    SFR(TMR2H,     0xCD);    // Timer/Counter 2 High Byte
 183 SFR(PSW,        0xD0);      // Program Status Word
 184    SBIT(P,        0xD0, 0); // Parity Flag
 185    SBIT(F1,       0xD0, 1); // User-Defined Flag
 186    SBIT(OV,       0xD0, 2); // Overflow Flag
 187    SBIT(RS0,      0xD0, 3); // Register Bank Select 0
 188    SBIT(RS1,      0xD0, 4); // Register Bank Select 1
 189    SBIT(F0,       0xD0, 5); // User-Defined Flag
 190    SBIT(AC,       0xD0, 6); // Auxiliary Carry Flag
 191    SBIT(CY,       0xD0, 7); // Carry Flag
 192 SFR(REF0CN,     0xD1);      // Voltage Reference Control
 193 SFR(PCA0CN,     0xD8);      // PCA Control
 194    SBIT(CCF0,     0xD8, 0); // PCA Module 0 Capture/Compare Flag
 195    SBIT(CCF1,     0xD8, 1); // PCA Module 1 Capture/Compare Flag
 196    SBIT(CCF2,     0xD8, 2); // PCA Module 2 Capture/Compare Flag
 197    SBIT(CCF3,     0xD8, 3); // PCA Module 3 Capture/Compare Flag
 198    SBIT(CCF4,     0xD8, 4); // PCA Module 4 Capture/Compare Flag
 199    SBIT(CCF5,     0xD8, 5); // PCA Module 5 Capture/Compare Flag
 200    SBIT(CR,       0xD8, 6); // PCA Counter/Timer Run Control
 201    SBIT(CF,       0xD8, 7); // PCA Counter/Timer Overflow Flag
 202 SFR(PCA0MD,     0xD9);      // PCA Mode
 203 SFR(PCA0CPM0,   0xDA);      // PCA Module 0 Mode
 204 SFR(PCA0CPM1,   0xDB);      // PCA Module 1 Mode
 205 SFR(PCA0CPM2,   0xDC);      // PCA Module 2 Mode
 206 SFR(PCA0CPM3,   0xDD);      // PCA Module 3 Mode
 207 SFR(PCA0CPM4,   0xDE);      // PCA Module 4 Mode
 208 SFR(PCA0CPM5,   0xDF);      // PCA Module 5 Mode
 209 SFR(ACC,        0xE0);      // Accumulator
 210 SFR(IT01CF,     0xE4);      // INT0/INT1 Configuration
 211 SFR(EIE1,       0xE6);      // Extended Interrupt Enable 1
 212 SFR(EIE2,       0xE7);      // Extended Interrupt Enable 2
 213 SFR(ADC0CN,     0xE8);      // ADC0 Control
 214    SBIT(AD0CM0,   0xE8, 0); // ADC0 Conversion Start Mode Select Bit 0
 215    SBIT(AD0CM1,   0xE8, 1); // ADC0 Conversion Start Mode Select Bit 1
 216    SBIT(AD0CM2,   0xE8, 2); // ADC0 Conversion Start Mode Select Bit 2
 217    SBIT(AD0WINT,  0xE8, 3); // ADC0 Window Compare Interrupt Flag
 218    SBIT(AD0BUSY,  0xE8, 4); // ADC0 Busy Bit
 219    SBIT(AD0INT,   0xE8, 5); // ADC0 Conversion Complete Interrupt Flag
 220    SBIT(AD0TM,    0xE8, 6); // ADC0 Track Mode Bit
 221    SBIT(AD0EN,    0xE8, 7); // ADC0 Enable Bit
 222 SFR16(PCA0CP1,  0xE9);      // PCA Capture 1 Word
 223    SFR(PCA0CPL1,  0xE9);    // PCA Capture 1 Low Byte
 224    SFR(PCA0CPH1,  0xEA);    // PCA Capture 1 High Byte
 225 SFR16(PCA0CP2,  0xEB);      // PCA Capture 2 Word
 226    SFR(PCA0CPL2,  0xEB);    // PCA Capture 2 Low Byte
 227    SFR(PCA0CPH2,  0xEC);    // PCA Capture 2 High Byte
 228 SFR16(PCA0CP3,  0xED);      // PCA Capture 3 Word
 229    SFR(PCA0CPL3,  0xED);    // PCA Capture 3 Low Byte
 230    SFR(PCA0CPH3,  0xEE);    // PCA Capture 3 High Byte
 231 SFR(RSTSRC,     0xEF);      // Reset Source Configuration/Status
 232 SFR(B,          0xF0);      // B Register
 233 SFR16(PCA0CP5,  0xF5);      // PCA Capture 5 Word
 234    SFR(PCA0CPL5,  0xF5);    // PCA Capture 5 Low Byte
 235    SFR(PCA0CPH5,  0xF6);    // PCA Capture 5 High Byte
 236 SFR(SPI0CN,     0xF8);      // SPI0 Control
 237    SBIT(SPIEN,    0xF8, 0); // SPI0 Enable
 238    SBIT(TXBMT,    0xF8, 1); // SPI0 Transmit Buffer Empty
 239    SBIT(NSSMD0,   0xF8, 2); // SPI0 Slave Select Mode Bit 0
 240    SBIT(NSSMD1,   0xF8, 3); // SPI0 Slave Select Mode Bit 1
 241    SBIT(RXOVRN,   0xF8, 4); // SPI0 Receive Overrun Flag
 242    SBIT(MODF,     0xF8, 5); // SPI0 Mode Fault Flag
 243    SBIT(WCOL,     0xF8, 6); // SPI0 Write Collision Flag
 244    SBIT(SPIF,     0xF8, 7); // SPI0 Interrupt Flag
 245 SFR16(PCA0,     0xF9);      // PCA Counter Word
 246    SFR(PCA0L,     0xF9);    // PCA Counter Low Byte
 247    SFR(PCA0H,     0xFA);    // PCA Counter High Byte
 248 SFR16(PCA0CP0,  0xFB);      // PCA Capture 0 Word
 249    SFR(PCA0CPL0,  0xFB);    // PCA Capture 0 Low Byte
 250    SFR(PCA0CPH0,  0xFC);    // PCA Capture 0 High Byte
 251 SFR16(PCA0CP4,  0xFD);      // PCA Capture 4 Word
 252    SFR(PCA0CPL4,  0xFD);    // PCA Capture 4 Low Byte
 253    SFR(PCA0CPH4,  0xFE);    // PCA Capture 4 High Byte
 254 SFR(VDM0CN,     0xFF);      // VDD Monitor Control
 255
 256 /*  Page 0x00 */
 257
 258 SFR(PSCTL,      0x8F);      // Program Store R/W Control
 259 SFR16(MAC0A,    0xA4);      // MAC0 A Register Word
 260    SFR(MAC0AL,    0xA4);    // MAC0 A Register Low Byte
 261    SFR(MAC0AH,    0xA5);    // MAC0 A Register High Byte
 262 SFR16(MAC0RND,  0xAE);      // MAC0 Rounding Register Word
 263    SFR(MAC0RNDL,  0xAE);    // MAC0 Rounding Register Low Byte
 264    SFR(MAC0RNDH,  0xAF);    // MAC0 Rounding Register High Byte
 265 SFR(P2MAT,      0xB1);      // Port 2 Match
 266 SFR(P2MASK,     0xB2);      // Port 2 Mask
 267 SFR(FLSCL,      0xB6);      // Flash Scale
 268 SFR(FLKEY,      0xB7);      // Flash Lock and Key
 269 SFR(MAC0STA,    0xCF);      // MAC0 Status Register
 270 SFR32(MAC0ACC,  0xD2);      // MAC0 Accumulator Long Word
 271    SFR(MAC0ACC0,  0xD2);    // MAC0 Accumulator Byte 0 (LSB)
 272    SFR(MAC0ACC1,  0xD3);    // MAC0 Accumulator Byte 1
 273    SFR(MAC0ACC2,  0xD4);    // MAC0 Accumulator Byte 2
 274    SFR(MAC0ACC3,  0xD5);    // MAC0 Accumulator Byte 3 (MSB)
 275 SFR(MAC0OVR,    0xD6);      // MAC0 Accumulator Overflow
 276 SFR(MAC0CF,     0xD7);      // MAC0 Configuration
 277 SFR(P1MAT,      0xE1);      // Port 1 Match
 278 SFR(P1MASK,     0xE2);      // Port 1 Mask
 279 // No sfr16 definition for MAC0B because MAC0BL must be written last
 280    SFR(MAC0BL,    0xF1);    // MAC0 B Register Low Byte
 281    SFR(MAC0BH,    0xF2);    // MAC0 B Register High Byte
 282 SFR(P0MAT,      0xF3);      // Port 0 Match
 283 SFR(P0MASK,     0xF4);      // Port 0 Mask
 284
 285 /*  Page 0x0F */
 286
 287 SFR(CCH0CN,     0x84);      // Cache Control
 288 SFR(CLKSEL,     0x8F);      // Clock Select
 289 SFR(P0MDOUT,    0xA4);      // Port 0 Output Mode Configuration
 290 SFR(P1MDOUT,    0xA5);      // Port 1 Output Mode Configuration
 291 SFR(P2MDOUT,    0xA6);      // Port 2 Output Mode Configuration
 292 SFR(PLL0DIV,    0xA9);      // PLL Divider
 293 SFR(FLSTAT,     0xAC);      // Flash Status
 294 SFR(OSCLCN,     0xAD);      // Internal Low-Frequency Oscillator Control
 295 SFR(P4MDOUT,    0xAE);      // Port 4 Output Mode Configuration
 296 SFR(P3MDOUT,    0xAF);      // Port 3 Output Mode Configuration
 297 SFR(PLL0MUL,    0xB1);      // PLL Multiplier
 298 SFR(PLL0FLT,    0xB2);      // PLL Filter
 299 SFR(PLL0CN,     0xB3);      // PLL Control
 300 SFR(OSCXCN,     0xB6);      // External Oscillator Control
 301 SFR(OSCICN,     0xB7);      // Internal Oscillator Control
 302 SFR(OSCICL,     0xBF);      // Internal Oscillator Calibration
 303 SFR(EMI0CF,     0xC7);      // EMIF Configuration
 304 SFR(CCH0TN,     0xC9);      // Cache Tuning
 305 SFR(EIP1,       0xCE);      // Extended Interrupt Priority 1
 306 SFR(EIP2,       0xCF);      // Extended Interrupt Priority 2
 307 SFR(CCH0LC,     0xD2);      // Cache Lock
 308 SFR(CCH0MA,     0xD3);      // Cache Miss Accumulator
 309 SFR(P0SKIP,     0xD4);      // Port 0 Skip
 310 SFR(P1SKIP,     0xD5);      // Port 1 Skip
 311 SFR(P2SKIP,     0xD6);      // Port 2 Skip
 312 SFR(P3SKIP,     0xD7);      // Port 3 Skip
 313 SFR(XBR0,       0xE1);      // Port I/O Crossbar Control 0
 314 SFR(XBR1,       0xE2);      // Port I/O Crossbar Control 1
 315 SFR(SFR0CN,     0xE5);      // SFR Page Control
 316 SFR(P0MDIN,     0xF1);      // Port 0 Input Mode Configuration
 317 SFR(P1MDIN,     0xF2);      // Port 1 Input Mode Configuration
 318 SFR(P2MDIN,     0xF3);      // Port 2 Input Mode Configuration
 319 SFR(P3MDIN,     0xF4);      // Port 3 Input Mode Configuration
 320 SFR(EMI0TC,     0xF7);      // EMIF Timing Control
 321
 322 /* Predefined SFR Bit Masks */
 323
 324 #define PCON_IDLE         0x01    /* PCON                                */
 325 #define PCON_STOP         0x02    /* PCON                                */
 326 #define T1M               0x08    /* CKCON                               */
 327 #define PSWE              0x01    /* PSCTL                               */
 328 #define PSEE              0x02    /* PSCTL                               */
 329 #define PORSF             0x02    /* RSTSRC                              */
 330 #define SWRSF             0x10    /* RSTSRC                              */
 331 #define ECCF              0x01    /* PCA0CPMn                            */
 332 #define PWM               0x02    /* PCA0CPMn                            */
 333 #define TOG               0x04    /* PCA0CPMn                            */
 334 #define MAT               0x08    /* PCA0CPMn                            */
 335 #define CAPN              0x10    /* PCA0CPMn                            */
 336 #define CAPP              0x20    /* PCA0CPMn                            */
 337 #define ECOM              0x40    /* PCA0CPMn                            */
 338 #define PWM16             0x80    /* PCA0CPMn                            */
 339 #define CP0E              0x10    /* XBR0                                */
 340 #define CP0AE             0x20    /* XBR0                                */
 341
 342 /* Interrupts */
 343
 344 #define INT_EXT0          0       // External Interrupt 0
 345 #define INT_TIMER0        1       // Timer0 Overflow
 346 #define INT_EXT1          2       // External Interrupt 1
 347 #define INT_TIMER1        3       // Timer1 Overflow
 348 #define INT_UART0         4       // Serial Port 0
 349 #define INT_TIMER2        5       // Timer2 Overflow
 350 #define INT_SPI0          6       // Serial Peripheral Interface 0
 351 #define INT_SMBUS0        7       // SMBus0 Interface
 352 //                        8          Reserved
 353 #define INT_ADC0_WINDOW   9       // ADC0 Window Comparison
 354 #define INT_ADC0_EOC      10      // ADC0 End Of Conversion
 355 #define INT_PCA0          11      // PCA0 Peripheral
 356 #define INT_COMPARATOR0   12      // Comparator0
 357 #define INT_COMPARATOR1   13      // Comparator1
 358 #define INT_TIMER3        14      // Timer3 Overflow
 359 //                        15         Reserved
 360 #define INT_PORT_MATCH    16      // Port Match
 361
 362 #endif