sdcc/device/include/mcs51/at89s53.h

   1 /*-------------------------------------------------------------------------
   2    at89s53.h - Register Declarations for the Atmel AT89S53 Processor
   3
   4    Copyright (C) 2005, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
   5
   6    This library is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published by the
   8    Free Software Foundation; either version 2, or (at your option) any
   9    later version.
  10
  11    This library is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this library; see the file COPYING. If not, write to the
  18    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  19    MA 02110-1301, USA.
  20
  21    As a special exception, if you link this library with other files,
  22    some of which are compiled with SDCC, to produce an executable,
  23    this library does not by itself cause the resulting executable to
  24    be covered by the GNU General Public License. This exception does
  25    not however invalidate any other reasons why the executable file
  26    might be covered by the GNU General Public License.
  27 -------------------------------------------------------------------------*/
  28
  29 #ifndef REG_AT89S53_H
  30 #define REG_AT89S53_H
  31
  32 #include <8052.h>     /* load difinitions for the 8052 core */
  33
  34 #ifdef REG8052_H
  35 #undef REG8052_H
  36 #endif
  37
  38 /* define AT89S53 specific registers only */
  39 __sfr __at (0x84) DP1L;     /* Data Pointer 1 Low Byte */
  40 __sfr __at (0x85) DP1H;     /* Data Pointer 1 High Byte */
  41 __sfr __at (0x86) SPDR;     /* SPI Data Register */
  42 __sfr __at (0xAA) SPSR;     /* SPI Status Register */
  43 __sfr __at (0x96) WMCON;    /* Watchdog and Memory Control Register */
  44 __sfr __at (0xD5) SPCR;     /* SPI Control Register */
  45
  46 /*------------------------------------------------
  47 SPSR (0xAA) Bit Values - Reset Value = 0000.0000
  48 ------------------------------------------------*/
  49 #define WCOL_   0x40    /* SPI Write Collision Flag: 1=Collision */
  50 #define SPIF_   0x80    /* SPI Interrupt Flag */
  51
  52 /*------------------------------------------------
  53 WMCON (0x96) Bit Values
  54 ------------------------------------------------*/
  55 #define WDTEN_   0x01
  56
  57 #define WDTRST_  0x02   /* Watchdog Timer Reset and EEPROM Ready,/Busy Flag*/
  58 #define EERDY_   0x02   /* Watchdog Timer Reset and EEPROM Ready,/Busy Flag */
  59
  60 #define DPS_     0x04   /* Data Pointer Select: 0=DP0, 1=DP1 */
  61 #define EEMEN_   0x08   /* Internal EEPROM Access Enable: 1=Enabled */
  62 #define EEMWE_   0x10   /* Internal EEPROM Write Enable: 1=Enabled */
  63 #define PS0_     0x20   /* Prescaler bit 0 for the Watchdog Timer */
  64 #define PS1_     0x40   /* Prescaler bit 1 for the Watchdog Timer */
  65 #define PS2_     0x80   /* Prescaler bit 2 for the Watchdog Timer */
  66                         /* 000 =   16ms Timeout */
  67                         /* 001 =   32ms Timeout */
  68                         /* 010 =   64ms Timeout */
  69                         /* 011 =  128ms Timeout */
  70                         /* 100 =  256ms Timeout */
  71                         /* 101 =  512ms Timeout */
  72                         /* 110 = 1024ms Timeout */
  73                         /* 111 = 2048ms Timeout */
  74
  75 /*------------------------------------------------
  76 SPCR (0xD5) Bit Values - Reset Value = 0000.01XX
  77 ------------------------------------------------*/
  78 #define SPR0_   0x01    /* SPI Clock Rate Select bit 0 */
  79 #define SPR1_   0x02    /* SPI Clock Rate Select bit 1 */
  80                         /* 00 = Fosc / 4   */
  81                         /* 01 = Fosc / 16  */
  82                         /* 10 = Fosc / 64  */
  83                         /* 11 = Fosc / 128 */
  84
  85 #define CPHA_   0x04    /* SPI Clock Phase */
  86 #define CPOL_   0x08    /* SPI Clock Polarity */
  87 #define MSTR_   0x10    /* SPI Master/Slave Select: 0=Slave, 1=Master */
  88 #define DORD_   0x20    /* SPI Data Order: 0=MSB First, 1=LSB First */
  89 #define SPE_    0x40    /* SPI Enable: 0=Disabled, 1=Enabled */
  90 #define SPIE_   0x80    /* SPI Interrupt Enable: 0=Disabled, 1=Enabled */
  91
  92 #endif /*REG_AT89S53_H*/