sdcc/device/include/mcs51/at89x52.h

   1 /*-------------------------------------------------------------------------
   2    at89x52.h - register declarations for ATMEL 89x52 processors
   3
   4    Copyright (C) 1999, Bernd Bartmann <bernd.bartmann AT gmail.com>
   5
   6    Based on reg51.h by Sandeep Dutta sandeep.dutta AT usa.net
   7    KEIL C compatible definitions are included
   8
   9    This library is free software; you can redistribute it and/or modify it
  10    under the terms of the GNU General Public License as published by the
  11    Free Software Foundation; either version 2, or (at your option) any
  12    later version.
  13
  14    This library is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this library; see the file COPYING. If not, write to the
  21    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  22    MA 02110-1301, USA.
  23
  24    As a special exception, if you link this library with other files,
  25    some of which are compiled with SDCC, to produce an executable,
  26    this library does not by itself cause the resulting executable to
  27    be covered by the GNU General Public License. This exception does
  28    not however invalidate any other reasons why the executable file
  29    might be covered by the GNU General Public License.
  30 -------------------------------------------------------------------------*/
  31
  32 #ifndef AT89x52_H
  33 #define AT89x52_H
  34
  35 #include <compiler.h>
  36
  37 /* BYTE addressable registers */
  38 SFR(P0,         0x80);
  39 SFR(SP,         0x81);
  40 SFR(DPL,        0x82);
  41 SFR(DPH,        0x83);
  42 SFR(PCON,       0x87);
  43 SFR(TCON,       0x88);
  44 SFR(TMOD,       0x89);
  45 SFR(TL0,        0x8A);
  46 SFR(TL1,        0x8B);
  47 SFR(TH0,        0x8C);
  48 SFR(TH1,        0x8D);
  49 SFR(P1,         0x90);
  50 SFR(SCON,       0x98);
  51 SFR(SBUF,       0x99);
  52 SFR(P2,         0xA0);
  53 SFR(IE,         0xA8);
  54 SFR(P3,         0xB0);
  55 SFR(IP,         0xB8);
  56 SFR(T2CON,      0xC8);
  57 SFR(T2MOD,      0xC9);
  58 SFR(RCAP2L,     0xCA);
  59 SFR(RCAP2H,     0xCB);
  60 SFR(TL2,        0xCC);
  61 SFR(TH2,        0xCD);
  62 SFR(PSW,        0xD0);
  63 SFR(ACC,        0xE0);
  64 SFR(A,          0xE0);
  65 SFR(B,          0xF0);
  66
  67
  68 /* BIT addressable registers */
  69 /* P0 */
  70 SBIT(P0_0,              0x80,   0);
  71 SBIT(P0_1,              0x80,   1);
  72 SBIT(P0_2,              0x80,   2);
  73 SBIT(P0_3,              0x80,   3);
  74 SBIT(P0_4,              0x80,   4);
  75 SBIT(P0_5,              0x80,   5);
  76 SBIT(P0_6,              0x80,   6);
  77 SBIT(P0_7,              0x80,   7);
  78
  79 /* TCON */
  80 SBIT(IT0,               0x88,   0);
  81 SBIT(IE0,               0x88,   1);
  82 SBIT(IT1,               0x88,   2);
  83 SBIT(IE1,               0x88,   3);
  84 SBIT(TR0,               0x88,   4);
  85 SBIT(TF0,               0x88,   5);
  86 SBIT(TR1,               0x88,   6);
  87 SBIT(TF1,               0x88,   7);
  88
  89 /* P1 */
  90 SBIT(P1_0,              0x90,   0);
  91 SBIT(P1_1,              0x90,   1);
  92 SBIT(P1_2,              0x90,   2);
  93 SBIT(P1_3,              0x90,   3);
  94 SBIT(P1_4,              0x90,   4);
  95 SBIT(P1_5,              0x90,   5);
  96 SBIT(P1_6,              0x90,   6);
  97 SBIT(P1_7,              0x90,   7);
  98
  99 SBIT(T2,                0x90,   0);
 100 SBIT(T2EX,              0x90,   1);
 101
 102 /* SCON */
 103 SBIT(RI,                0x98,   0);
 104 SBIT(TI,                0x98,   1);
 105 SBIT(RB8,               0x98,   2);
 106 SBIT(TB8,               0x98,   3);
 107 SBIT(REN,               0x98,   4);
 108 SBIT(SM2,               0x98,   5);
 109 SBIT(SM1,               0x98,   6);
 110 SBIT(SM0,               0x98,   7);
 111
 112 /* P2 */
 113 SBIT(P2_0,              0xA0,   0);
 114 SBIT(P2_1,              0xA0,   1);
 115 SBIT(P2_2,              0xA0,   2);
 116 SBIT(P2_3,              0xA0,   3);
 117 SBIT(P2_4,              0xA0,   4);
 118 SBIT(P2_5,              0xA0,   5);
 119 SBIT(P2_6,              0xA0,   6);
 120 SBIT(P2_7,              0xA0,   7);
 121
 122 /* IE */
 123 SBIT(EX0,               0xA8,   0);
 124 SBIT(ET0,               0xA8,   1);
 125 SBIT(EX1,               0xA8,   2);
 126 SBIT(ET1,               0xA8,   3);
 127 SBIT(ES,                0xA8,   4);
 128 SBIT(ET2,               0xA8,   5);
 129 SBIT(EA,                0xA8,   7);
 130
 131 /* P3 */
 132 SBIT(P3_0,              0xB0,   0);
 133 SBIT(P3_1,              0xB0,   1);
 134 SBIT(P3_2,              0xB0,   2);
 135 SBIT(P3_3,              0xB0,   3);
 136 SBIT(P3_4,              0xB0,   4);
 137 SBIT(P3_5,              0xB0,   5);
 138 SBIT(P3_6,              0xB0,   6);
 139 SBIT(P3_7,              0xB0,   7);
 140
 141 SBIT(RXD,               0xB0,   0);
 142 SBIT(TXD,               0xB0,   1);
 143 SBIT(INT0,              0xB0,   2);
 144 SBIT(INT1,              0xB0,   3);
 145 SBIT(T0,                0xB0,   4);
 146 SBIT(T1,                0xB0,   5);
 147 SBIT(WR,                0xB0,   6);
 148 SBIT(RD,                0xB0,   7);
 149
 150 /* IP */
 151 SBIT(PX0,               0xB8,   0);
 152 SBIT(PT0,               0xB8,   1);
 153 SBIT(PX1,               0xB8,   2);
 154 SBIT(PT1,               0xB8,   3);
 155 SBIT(PS,                0xB8,   4);
 156 SBIT(PT2,               0xB8,   5);
 157
 158 /* T2CON */
 159 SBIT(T2CON_0,   0xC8,   0);
 160 SBIT(T2CON_1,   0xC8,   1);
 161 SBIT(T2CON_2,   0xC8,   2);
 162 SBIT(T2CON_3,   0xC8,   3);
 163 SBIT(T2CON_4,   0xC8,   4);
 164 SBIT(T2CON_5,   0xC8,   5);
 165 SBIT(T2CON_6,   0xC8,   6);
 166 SBIT(T2CON_7,   0xC8,   7);
 167
 168 SBIT(CP_RL2,    0xC8,   0);
 169 SBIT(C_T2,              0xC8,   1);
 170 SBIT(TR2,               0xC8,   2);
 171 SBIT(EXEN2,             0xC8,   3);
 172 SBIT(TCLK,              0xC8,   4);
 173 SBIT(RCLK,              0xC8,   5);
 174 SBIT(EXF2,              0xC8,   6);
 175 SBIT(TF2,               0xC8,   7);
 176
 177 /* PSW */
 178 SBIT(P,                 0xD0,   0);
 179 SBIT(FL,                0xD0,   1);
 180 SBIT(OV,                0xD0,   2);
 181 SBIT(RS0,               0xD0,   3);
 182 SBIT(RS1,               0xD0,   4);
 183 SBIT(F0,                0xD0,   5);
 184 SBIT(AC,                0xD0,   6);
 185 SBIT(CY,                0xD0,   7);
 186
 187
 188 /* BIT definitions for bits that are not directly accessible */
 189 /* PCON bits */
 190 #define IDL             0x01
 191 #define PD              0x02
 192 #define GF0             0x04
 193 #define GF1             0x08
 194 #define SMOD            0x80
 195
 196 #define IDL_            0x01
 197 #define PD_             0x02
 198 #define GF0_            0x04
 199 #define GF1_            0x08
 200 #define SMOD_           0x80
 201
 202 /* TMOD bits */
 203 #define M0_0            0x01
 204 #define M1_0            0x02
 205 #define C_T0            0x04
 206 #define GATE0           0x08
 207 #define M0_1            0x10
 208 #define M1_1            0x20
 209 #define C_T1            0x40
 210 #define GATE1           0x80
 211
 212 #define M0_0_           0x01
 213 #define M1_0_           0x02
 214 #define C_T0_           0x04
 215 #define GATE0_          0x08
 216 #define M0_1_           0x10
 217 #define M1_1_           0x20
 218 #define C_T1_           0x40
 219 #define GATE1_          0x80
 220
 221 #define T0_M0           0x01
 222 #define T0_M1           0x02
 223 #define T0_CT           0x04
 224 #define T0_GATE         0x08
 225 #define T1_M0           0x10
 226 #define T1_M1           0x20
 227 #define T1_CT           0x40
 228 #define T1_GATE         0x80
 229
 230 #define T0_M0_          0x01
 231 #define T0_M1_          0x02
 232 #define T0_CT_          0x04
 233 #define T0_GATE_        0x08
 234 #define T1_M0_          0x10
 235 #define T1_M1_          0x20
 236 #define T1_CT_          0x40
 237 #define T1_GATE_        0x80
 238
 239 #define T0_MASK         0x0F
 240 #define T1_MASK         0xF0
 241
 242 #define T0_MASK_        0x0F
 243 #define T1_MASK_        0xF0
 244
 245 /* T2MOD bits */
 246 #define DCEN            0x01
 247 #define T2OE            0x02
 248
 249 #define DCEN_           0x01
 250 #define T2OE_           0x02
 251
 252
 253 /* Interrupt numbers: address = (number * 8) + 3 */
 254 #define IE0_VECTOR      0       /* 0x03 external interrupt 0 */
 255 #define TF0_VECTOR      1       /* 0x0b timer 0 */
 256 #define IE1_VECTOR      2       /* 0x13 external interrupt 1 */
 257 #define TF1_VECTOR      3       /* 0x1b timer 1 */
 258 #define SI0_VECTOR      4       /* 0x23 serial port 0 */
 259 #define TF2_VECTOR      5       /* 0x2B timer 2 */
 260 #define EX2_VECTOR      5       /* 0x2B external interrupt 2 */
 261
 262 #endif