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Hackfix and re-enable strtoull and wcstoull, see bug #3798.
[sdcc.git] / sdcc / device / include / mcs51 / msc1210.h
blob0e555c69798ed58532766989b5d615f787a1196c
1 /*-------------------------------------------------------------------------
2 msc1210.h - register declarations for Texas Intruments MSC12xx MCU family
3
4 Copyright (C) 2006, Philippe Latu <philippe.latu AT linux-france.org>
5
6 This library is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
9 later version.
10
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this library; see the file COPYING. If not, write to the
18 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
19 MA 02110-1301, USA.
20
21 As a special exception, if you link this library with other files,
22 some of which are compiled with SDCC, to produce an executable,
23 this library does not by itself cause the resulting executable to
24 be covered by the GNU General Public License. This exception does
25 not however invalidate any other reasons why the executable file
26 might be covered by the GNU General Public License.
27 -------------------------------------------------------------------------*/
28
29 #ifndef __MSC1210_H__
30 #define __MSC1210_H__
31
32 /* BYTE Registers with bit definitions */
33
34 __sfr __at (0x80) P0; /* Port 0 */
35 __sfr __at (0x81) SP; /* Stack Pointer */
36 __sfr __at (0x82) DPL; /* Data Pointer 0: low byte */
37 __sfr __at (0x82) DPL0; /* Data Pointer 0: low byte */
38 __sfr __at (0x83) DPH; /* Data Pointer 0: high byte */
39 __sfr __at (0x83) DPH0; /* Data Pointer 0: high byte */
40 __sfr __at (0x84) DPL1; /* Data Pointer 1: low byte */
41 __sfr __at (0x85) DPH1; /* Data Pointer 1: high byte */
42 __sfr __at (0x86) DPS; /* Data Pointer Select */
43 __sfr __at (0x87) PCON; /* Power Control */
44 __sfr __at (0x88) TCON; /* Timer Control */
45 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
46 /* |TF1|TR1|TF0|TR0|IE1|IT1|IE0|IT0| */
47 __sbit __at (0x88) IT0; /* External Interrupt 0 Type */
48 __sbit __at (0x89) IE0; /* External Interrupt 0 Edge Flag */
49 __sbit __at (0x8a) IT1; /* External Interrupt 1 Type */
50 __sbit __at (0x8b) IE1; /* External Interrupt 1 Edge Flag */
51 __sbit __at (0x8c) TR0; /* Timer 0 On/Off Control */
52 __sbit __at (0x8d) TF0; /* Timer 0 Overflow Flag */
53 __sbit __at (0x8e) TR1; /* Timer 1 On/Off Control */
54 __sbit __at (0x8f) TF1; /* Timer 1 Overflow Flag */
55 __sfr __at (0x89) TMOD; /* Timer Mode */
56 __sfr __at (0x8a) TL0; /* Timer 0: low byte */
57 __sfr __at (0x8b) TL1; /* Timer 1: low byte */
58 __sfr __at (0x8c) TH0; /* Timer 0: high byte */
59 __sfr __at (0x8d) TH1; /* Timer 1: high byte */
60 __sfr __at (0x8e) CKCON; /* Clock Control */
61 __sfr __at (0x8f) MWS; /* Memory Write Select */
62 __sfr __at (0x90) P1; /* Port 1 */
63 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
64 /* | | | | | | |T2EX|T2 | */
65 __sbit __at (0x90) T2; /* Timer 2 External Input */
66 __sbit __at (0x91) T2EX; /* Timer 2 Capture/Reload */
67 __sfr __at (0x91) EXIF; /* External Interrupt Flag */
68 __sfr __at (0x92) MPAGE; /* Memory Page */
69 __sfr __at (0x92) _XPAGE; /* XDATA/PDATA PAGE */
70 __sfr __at (0x93) CADDR; /* Configuration Address Register */
71 __sfr __at (0x94) CDATA; /* Configuration Data Register */
72 __sfr __at (0x95) MCON; /* Memory Configuration */
73 __sfr __at (0x98) SCON; /* Serial Control 0 */
74 __sfr __at (0x98) SCON0; /* Serial Control 0 */
75 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
76 /* |SM0|SM1|SM2|REN|TB8|RB8|TI |RI | */
77 __sbit __at (0x98) RI; /* Receive Interrupt Flag */
78 __sbit __at (0x98) RI0; /* Receive Interrupt Flag */
79 __sbit __at (0x98) RI_0; /* Receive Interrupt Flag */
80 __sbit __at (0x99) TI; /* Transmit Interrupt Flag */
81 __sbit __at (0x99) TI0; /* Transmit Interrupt Flag */
82 __sbit __at (0x99) TI_0; /* Transmit Interrupt Flag */
83 __sbit __at (0x9a) RB8; /* Receive Bit 8 */
84 __sbit __at (0x9a) RB8_0; /* Receive Bit 8 */
85 __sbit __at (0x9b) TB8; /* Transmit Bit 8 */
86 __sbit __at (0x9b) TB8_0; /* Transmit Bit 8 */
87 __sbit __at (0x9c) REN; /* Receive Enable */
88 __sbit __at (0x9c) REN_0; /* Receive Enable */
89 __sbit __at (0x9d) SM2; /* Multiprocessor Communication Enable*/
90 __sbit __at (0x9d) SM2_0; /* Multiprocessor Communication Enable*/
91 __sbit __at (0x9e) SM1; /* Serial Port Select Mode 1 */
92 __sbit __at (0x9e) SM1_0; /* Serial Port Select Mode 1 */
93 __sbit __at (0x9f) SM0; /* Serial Port Select Mode 0 */
94 __sbit __at (0x9f) SM0_0; /* Serial Port Select Mode 0 */
95 __sfr __at (0x99) SBUF; /* Serial Buffer 0 */
96 __sfr __at (0x99) SBUF0; /* Serial Buffer 0 */
97 __sfr __at (0x9a) SPICON; /* SPI Control */
98 __sfr __at (0x9a) I2CCON; /* I2C Control */
99 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
100 /* |SCLK2|SCLK1|SCLK0|FIFO|ORDER|MSTR|CPHA|CPOL| */
101 __sbit __at (0x9a) CPOL; /* Serial Clock Polarity */
102 __sbit __at (0x9b) CPHA; /* Serial Clock Phase Control */
103 __sbit __at (0x9c) MSTR; /* Set Master Mode */
104 __sbit __at (0x9d) ORDER; /* Set Bit Order Transmit/Receive */
105 __sbit __at (0x9e) FIFO; /* Enable Fifo Buffer */
106 __sbit __at (0x9f) SCLK0; /* Clock Divider Select 0 */
107 __sbit __at (0xa0) SCLK1; /* Clock Divider Select 1 */
108 __sbit __at (0xa1) SCLK2; /* Clock Divider Select 2 */
109 __sfr __at (0x9b) SPIDATA; /* SPI Data */
110 __sfr __at (0x9b) I2CDATA; /* I2C Data */
111 __sfr __at (0x9c) SPIRCON; /* SPI Receive Control */
112 __sfr __at (0x9c) I2CGM; /* I2C GM Register */
113 __sfr __at (0x9d) SPITCON; /* SPI Transmit Control */
114 __sfr __at (0x9d) I2CSTAT; /* I2C Status */
115 __sfr __at (0x9e) SPISTART; /* SPI Buffer Start Address */
116 __sfr __at (0x9e) I2CSTART; /* I2C Start */
117 __sfr __at (0x9f) SPIEND; /* SPI Buffer End Address */
118 __sfr __at (0xa0) P2; /* Port 2 */
119 __sfr __at (0xa1) PWMCON; /* PWM Control */
120 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
121 /* | | |PPOL|PWMSEL|SPDSEL|TPCNTL2|TPCNTL1|TPCNTL0| */
122 __sbit __at (0xa1) TPCNTL0; /* Generator Control */
123 __sbit __at (0xa2) TPCNTL1; /* Generator Control */
124 __sbit __at (0xa3) TPCNTL2; /* Generator Control */
125 __sbit __at (0xa4) SPDSEL; /* Speed Selection */
126 __sbit __at (0xa5) PWMSEL; /* PWM Register Select */
127 __sbit __at (0xa6) PPOL; /* Period Polarity */
128 __sfr __at (0xa2) PWMLOW; /* PWM low byte */
129 __sfr __at (0xa2) TONELOW; /* Tone low byte */
130 __sfr __at (0xa3) PWMHI; /* PWM high byte */
131 __sfr __at (0xa3) TONEHI; /* Tone high byte */
132 __sfr __at (0xa4) AIPOL; /* Auxiliary Interrupt Poll */
133 __sfr __at (0xa5) PAI; /* Pending Auxiliary Interrupt */
134 __sfr __at (0xa6) AIE; /* Auxiliary Interrupt Enable */
135 __sfr __at (0xa7) AISTAT; /* Auxiliary Interrupt Status */
136 __sfr __at (0xa8) IE; /* Interrupt Enable */
137 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
138 /* |EA |ES1|ET2|ES0|ET1|EX1|ET0|EX0| */
139 __sbit __at (0xa8) EX0; /* Enable External Interrupt 0 */
140 __sbit __at (0xa9) ET0; /* Enable Timer 0 Interrupt */
141 __sbit __at (0xaa) EX1; /* Enable External Interrupt 1 */
142 __sbit __at (0xab) ET1; /* Enable Timer 1 Interrupt */
143 __sbit __at (0xac) ES0; /* Enable Serial Port 0 Interrupt */
144 __sbit __at (0xad) ET2; /* Enable Timer 2 Interrupt */
145 __sbit __at (0xae) ES1; /* Enable Serial Port 1 Interrupt */
146 __sbit __at (0xaf) EA; /* Global Interrupt Enable */
147 __sfr __at (0xa9) BPCON; /* Breakpoint Control */
148 __sfr __at (0xaa) BPL; /* Breakpoint Address Low */
149 __sfr __at (0xab) BPH; /* Breakpoint Address High */
150 __sfr __at (0xac) P0DDRL; /* Port 0 Data Direction Low */
151 __sfr __at (0xad) P0DDRH; /* Port 0 Data Direction High */
152 __sfr __at (0xae) P1DDRL; /* Port 1 Data Direction Low */
153 __sfr __at (0xaf) P1DDRH; /* Port 1 Data Direction High */
154 __sfr __at (0xb0) P3; /* Port 3 */
155 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
156 /* |RD |WR |T1 |T0 |INT1|INT0|TXD|RXD| */
157 __sbit __at (0xb0) RXD; /* Serial Port 0 Receive */
158 __sbit __at (0xb0) RXD0; /* Serial Port 0 Receive */
159 __sbit __at (0xb1) TXD; /* Serial Port 0 Transmit */
160 __sbit __at (0xb1) TXD0; /* Serial Port 0 Transmit */
161 __sbit __at (0xb2) INT0; /* External Interrupt 0 */
162 __sbit __at (0xb3) INT1; /* External Interrupt 1 */
163 __sbit __at (0xb4) T0; /* Timer 0 External Input */
164 __sbit __at (0xb5) T1; /* Timer 1 External Input */
165 __sbit __at (0xb6) WR; /* External Memory Write Strobe */
166 __sbit __at (0xb7) RD; /* External Memory Read Strobe */
167 __sfr __at (0xb1) P2DDRL; /* Port 2 Data Direction Low */
168 __sfr __at (0xb2) P2DDRH; /* Port 2 Data Direction High */
169 __sfr __at (0xb3) P3DDRL; /* Port 3 Data Direction Low */
170 __sfr __at (0xb4) P3DDRH; /* Port 3 Data Direction High */
171 __sfr __at (0xb5) DACL; /* Digital-to-Analog Converter Low */
172 __sfr __at (0xb6) DACH; /* Digital-to-Analog Converter High */
173 __sfr __at (0xb7) DACSEL; /* Digital-to-Analog Converter Select */
174 __sfr __at (0xb8) IP; /* Interrupt Priority */
175 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
176 /* | | |PT2|PS |PT1|PX1|PT0|PX0| */
177 __sbit __at (0xb8) PX0; /* External Interrupt 0 */
178 __sbit __at (0xb9) PT0; /* Timer 0 */
179 __sbit __at (0xba) PX1; /* External Interrupt 1 */
180 __sbit __at (0xbb) PT1; /* Timer 1 */
181 __sbit __at (0xbc) PS; /* Serial Port */
182 __sbit __at (0xbd) PT2; /* Timer 2 */
183 __sfr __at (0xc0) SCON1; /* Serial Control 1 */
184 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
185 /* |SM0|SM1|SM2|REN|TB8|RB8|TI |RI | */
186 __sbit __at (0xc0) RI1; /* Receive Interrupt Flag */
187 __sbit __at (0xc0) RI_1; /* Receive Interrupt Flag */
188 __sbit __at (0xc1) TI1; /* Transmit Interrupt Flag */
189 __sbit __at (0xc1) TI_1; /* Transmit Interrupt Flag */
190 __sbit __at (0xc2) RB8_1; /* Receive Bit 8 */
191 __sbit __at (0xc3) TB8_1; /* Transmit Bit 8 */
192 __sbit __at (0xc4) REN_1; /* Receive Enable */
193 __sbit __at (0xc5) SM2_1; /* Multiprocessor Communication Enable*/
194 __sbit __at (0xc6) SM1_1; /* Serial Port Select Mode 1 */
195 __sbit __at (0xc7) SM0_1; /* Serial Port Select Mode 0 */
196 __sfr __at (0xc1) SBUF1; /* Serial Buffer 1 */
197 __sfr __at (0xc6) EWU; /* Enable Wake Up */
198 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
199 /* | | | | | |EWUEX1|EWUEX0|EWUWDT| */
200 __sbit __at (0xc6) EWUWDT; /* Enable Watchdog Interrupt */
201 __sbit __at (0xc7) EWUEX0; /* Enable External Interrupt 0 */
202 __sbit __at (0xc8) EWUEX1; /* Enable External Interrupt 1 */
203 __sfr __at (0xc7) SYSCLK; /* System Clock Divider */
204 __sfr __at (0xc8) T2CON; /* Timer 2 Control */
205 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
206 /* |TF2|EXF2|RCLK|TCLK|EXEN2|TR2|C_T2|CP_RL2 | */
207 __sbit __at (0xc8) CP_RL2; /* Capture/Reload Flag */
208 __sbit __at (0xc9) C_T2; /* Overflow Flag */
209 __sbit __at (0xca) TR2; /* Timer Run */
210 __sbit __at (0xcb) EXEN2; /* Timer External Enable */
211 __sbit __at (0xcc) TCLK; /* Transmit Clock Flag */
212 __sbit __at (0xcd) RCLK; /* Receive Clock Flag */
213 __sbit __at (0xce) EXF2; /* External Flag */
214 __sbit __at (0xcf) TF2; /* Overflow Flag */
215 __sfr __at (0xca) RCAP2L; /* Timer 2 Capture Low */
216 __sfr __at (0xcb) RCAP2H; /* Timer 2 Capture High */
217 __sfr __at (0xcc) TL2; /* Timer 2 Low byte */
218 __sfr __at (0xcd) TH2; /* Timer 2 High byte */
219 __sfr __at (0xd0) PSW; /* Program Status Word */
220 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
221 /* |CY |AC |F0 |RS1|RS0|OV |F1 |P | */
222 __sbit __at (0xd0) P; /* Parity Flag */
223 __sbit __at (0xd1) F1; /* General Purpose User Flag 1 */
224 __sbit __at (0xd2) OV; /* Overflow Flag */
225 __sbit __at (0xd3) RS0; /* Register Bank Select 0 Flag */
226 __sbit __at (0xd4) RS1; /* Register Bank Select 1 Flag */
227 __sbit __at (0xd5) F0; /* General Purpose User Flag 0 */
228 __sbit __at (0xd6) AC; /* Auxiliary Carry Flag */
229 __sbit __at (0xd7) CY; /* Carry Flag */
230 __sfr __at (0xd1) OCL; /* (ADC) Offset Calibration Low byte */
231 __sfr __at (0xd2) OCM; /* (ADC) Offset Calibration Middle byte */
232 __sfr __at (0xd3) OCH; /* (ADC) Offset Calibration High byte */
233 __sfr __at (0xd4) GCL; /* (ADC) Gain Low byte */
234 __sfr __at (0xd5) GCM; /* (ADC) Gain Middle byte */
235 __sfr __at (0xd6) GCH; /* (ADC) Gain High byte */
236 __sfr __at (0xd7) ADMUX; /* ADC Multiplexer Register */
237 __sfr __at (0xd8) EICON; /* Enable Interrupt Control */
238 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
239 /* |SMOD1| |EAI|AI |WDTI| | | | */
240 __sbit __at (0xdb) WDTI; /* Watchdog Timer Interrupt Flag */
241 __sbit __at (0xdc) AI; /* Auxiliary Interrupt Flag */
242 __sbit __at (0xdd) EAI; /* Enable Auxiliary Interrupt */
243 __sbit __at (0xdf) SMOD1; /* Serial Port 1 Mode */
244 __sfr __at (0xd9) ADRESL; /* ADC Conversion Result Low byte */
245 __sfr __at (0xda) ADRESM; /* ADC Conversion Result Middle byte */
246 __sfr __at (0xdb) ADRESH; /* ADC Conversion Result High byte */
247 __sfr __at (0xdc) ADCON0; /* ADC Control 0 */
248 __sfr __at (0xdd) ADCON1; /* ADC Control 1 */
249 __sfr __at (0xde) ADCON2; /* ADC Control 2 */
250 __sfr __at (0xdf) ADCON3; /* ADC Control 3 */
251 __sfr __at (0xe0) ACC; /* Accumulator */
252 __sfr __at (0xe1) SSCON; /* Summation and Shift Control */
253 __sfr __at (0xe2) SUMR0; /* Summation Register 0 (LSB) */
254 __sfr __at (0xe3) SUMR1; /* Summation Register 1 */
255 __sfr __at (0xe4) SUMR2; /* Summation Register 2 */
256 __sfr __at (0xe5) SUMR3; /* Summation Register 3 (MSB) */
257 __sfr __at (0xe6) ODAC; /* (ADC) Offset DAC Register */
258 __sfr __at (0xe7) LVDCON; /* Low Voltage Detection Control */
259 __sfr __at (0xe8) EIE; /* Extended Interrupt Enable */
260 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
261 /* | | | |EWDI|EX5|EX4|EX3|EX2| */
262 __sbit __at (0xe8) EX2; /* Enable External Interrupt 2 */
263 __sbit __at (0xe9) EX3; /* Enable External Interrupt 3 */
264 __sbit __at (0xea) EX4; /* Enable External Interrupt 4 */
265 __sbit __at (0xeb) EX5; /* Enable External Interrupt 5 */
266 __sbit __at (0xec) EWDI; /* Enable Watchdog Interrupt */
267 __sfr __at (0xe9) HWPC0; /* Hardware Product Code 0 */
268 __sfr __at (0xea) HWPC1; /* Hardware Product Code 1 */
269 __sfr __at (0xeb) HWVER; /* Hardware Version number */
270 __sfr __at (0xee) FMCON; /* Flash Memory Control */
271 __sfr __at (0xef) FTCON; /* Flash Memory Timing Control */
272 __sfr __at (0xf0) B; /* B Register */
273 __sfr __at (0xf1) PDCON; /* Power Down Control */
274 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
275 /* | | | |PDPWM|PDAD|PDWDT|PDST|PDSPI| */
276 __sbit __at (0xf1) PDSPI; /* SPI System Control */
277 __sbit __at (0xf2) PDST; /* System Timer Control */
278 __sbit __at (0xf3) PDWDT; /* Watchdog Timer Control */
279 __sbit __at (0xf4) PDAD; /* A/D Control */
280 __sbit __at (0xf5) PDPWM; /* PWM Control */
281 __sfr __at (0xf2) PASEL; /* /PSEN|ALE Select */
282 __sfr __at (0xf6) ACLK; /* Analog Clock */
283 __sfr __at (0xf7) SRST; /* System Reset Register */
284 __sfr __at (0xf8) EIP; /* Extended Interrupt Priority */
285 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
286 /* | | | |PWDI|PX5|PX4|PX3|PX2| */
287 __sbit __at (0xf8) PX2; /* External Interrupt 2 Priority */
288 __sbit __at (0xf9) PX3; /* External Interrupt 3 Priority */
289 __sbit __at (0xfa) PX4; /* External Interrupt 4 Priority */
290 __sbit __at (0xfb) PX5; /* External Interrupt 5 Priority */
291 __sbit __at (0xfc) PWDI; /* Watchdog Interrupt Priority */
292 __sfr __at (0xf9) SECINT; /* Seconds Timer Interrupt */
293 __sfr __at (0xfa) MSINT; /* Milliseconds Interrupt */
294 __sfr __at (0xfb) USEC; /* Microsecond Register */
295 __sfr __at (0xfc) MSECL; /* Millisecond Low byte */
296 __sfr __at (0xfd) MSECH; /* Millisecond High byte */
297 __sfr __at (0xfe) HMSEC; /* Hundred Millisecond Clock */
298 __sfr __at (0xff) WDTCON; /* Watchdog Control */
299
300 /* Word Registers */
301 __sfr16 __at (0x8c8a) TMR0;
302 __sfr16 __at (0x8d8b) TMR1;
303 __sfr16 __at (0xa3a2) PWM;
304 __sfr16 __at (0xa3a2) TONE;
305 __sfr16 __at (0xabaa) BP;
306 __sfr16 __at (0xabaa) BREAKPT;
307 __sfr16 __at (0xadac) P0DDR;
308 __sfr16 __at (0xafae) P1DDR;
309 __sfr16 __at (0xb2b1) P2DDR;
310 __sfr16 __at (0xb4b3) P3DDR;
311 __sfr16 __at (0xcbca) RCAP2;
312 __sfr16 __at (0xcdcc) TMR2;
313 __sfr16 __at (0xdfde) DECIMATION;
314 __sfr16 __at (0xfdfc) ONEMS;
315 __sfr16 __at (0xfdfc) MSEC;
316
317 /* Double Word Registers */
318 __sfr32 __at (0xe5e4e3e2) SUMR;
319
320 #endif
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