sdcc/device/include/mcs51/p89c66x.h

   1 /*-------------------------------------------------------------------------
   2    p89c66x.h - This header allows to use the microcontroler Philips P89c66x
   3    with the compiler SDCC.
   4
   5    Copyright (C), 2007 Gudjon I. Gudjonsson <gudjon AT gudjon.org>
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 /*-------------------------------------------------------------------------
  31  The registered are ordered in the same way as in the NXP data sheet
  32  P89C660_662_664_3.PDF, see http://www.nxp.com
  33 -------------------------------------------------------------------------*/
  34
  35 #ifndef __P89c66x_H__
  36 #define __P89c66x_H__
  37 #include <compiler.h>
  38
  39 /*BYTE Registers*/
  40 SFR(ACC, 0xE0); // Accumulator
  41         SBIT(ACC_7, 0xE0, 7);
  42         SBIT(ACC_6, 0xE0, 6);
  43         SBIT(ACC_5, 0xE0, 5);
  44         SBIT(ACC_4, 0xE0, 4);
  45         SBIT(ACC_3, 0xE0, 3);
  46         SBIT(ACC_2, 0xE0, 2);
  47         SBIT(ACC_1, 0xE0, 1);
  48         SBIT(ACC_0, 0xE0, 0);
  49 SFR(AUXR, 0x8E); // Auxiliary
  50         #define EXTRAM 0x02
  51         #define AO     0x01
  52 SFR(AUXR1, 0xA2); // Auxiliary 1
  53         #define ENBOOT 0x20
  54         #define GF2    0x08
  55         // Bit 2 must be 0
  56         #define DPS    0x01
  57 SFR(B, 0xF0); // B register
  58         SBIT(B7, 0xF0, 7);
  59         SBIT(B6, 0xF0, 6);
  60         SBIT(B5, 0xF0, 5);
  61         SBIT(B4, 0xF0, 4);
  62         SBIT(B3, 0xF0, 3);
  63         SBIT(B2, 0xF0, 2);
  64         SBIT(B1, 0xF0, 1);
  65         SBIT(B0, 0xF0, 0);
  66 SFR(CCAP0H, 0xFA); // Module 0 Capture High
  67 SFR(CCAP1H, 0xFB); // Module 1 Capture High
  68 SFR(CCAP2H, 0xFC); // Module 2 Capture High
  69 SFR(CCAP3H, 0xFD); // Module 3 Capture High
  70 SFR(CCAP4H, 0xFE); // Module 4 Capture High
  71 SFR(CCAP0L, 0xEA); // Module 0 Capture Low
  72 SFR(CCAP1L, 0xEB); // Module 1 Capture Low
  73 SFR(CCAP2L, 0xEC); // Module 2 Capture Low
  74 SFR(CCAP3L, 0xED); // Module 3 Capture Low
  75 SFR(CCAP4L, 0xEE); // Module 4 Capture Low
  76 SFR(CCAPM0, 0xC2); // Module 0 Mode
  77 SFR(CCAPM1, 0xC3); // Module 1 Mode
  78 SFR(CCAPM2, 0xC4); // Module 2 Mode
  79 SFR(CCAPM3, 0xC5); // Module 3 Mode
  80 SFR(CCAPM4, 0xC6); // Module 4 Mode
  81         #define ECOM   0x40
  82         #define CAPP   0x20
  83         #define CAPN   0x10
  84         #define MAT    0x08
  85         #define TOG    0x04
  86         #define PWM    0x02
  87         #define ECCF   0x01
  88 SFR(CCON,   0xC0); // PCA Counter Control
  89         SBIT(CF,   0xC0, 7);
  90         SBIT(CR,   0xC0, 6);
  91         SBIT(CCF4, 0xC0, 4);
  92         SBIT(CCF3, 0xC0, 3);
  93         SBIT(CCF2, 0xC0, 2);
  94         SBIT(CCF1, 0xC0, 1);
  95         SBIT(CCF0, 0xC0, 0);
  96 SFR(CH,   0xF9); // PCA Counter High
  97 SFR(CL,   0xE9); // PCA Counter Low
  98 SFR(CMOD, 0xC1); // PCA Counter Mode
  99         #define CIDL 0x80
 100         #define WDTE 0x40
 101         #define CPS1 0x04
 102         #define CPS0 0x02
 103         #define ECF  0x01
 104 SFR(DPH,  0x83); // Data Pointer High
 105 SFR(DPL,  0x82); // Data Pointer Low
 106 SFR(IEN0, 0xA8); // Interrupt Enable 0
 107         SBIT(EA,  0xA8, 7);
 108         SBIT(EC,  0xA8, 6);
 109         SBIT(ES1, 0xA8, 5);
 110         SBIT(ES0, 0xA8, 4);
 111         SBIT(ET1, 0xA8, 3);
 112         SBIT(EX1, 0xA8, 2);
 113         SBIT(ET0, 0xA8, 1);
 114         SBIT(EX0, 0xA8, 0);
 115 SFR(IEN1, 0xE8); // Interrupt Enable 1
 116         SBIT(ET2, 0xE8, 0);
 117 SFR(IP, 0xB8); // Interrupt Priority
 118         SBIT(PT2, 0xB8, 7);
 119         SBIT(PPC, 0xB8, 6);
 120         SBIT(PS1, 0xB8, 5);
 121         SBIT(PS0, 0xB8, 4);
 122         SBIT(PT1, 0xB8, 3);
 123         SBIT(PX1, 0xB8, 2);
 124         SBIT(PT0, 0xB8, 1);
 125         SBIT(PX0, 0xB8, 0);
 126 SFR(IPH, 0xB7); // Interrupt Priority High
 127         #define PT2H  0x80
 128         #define PPCH  0x40
 129         #define PS1H  0x20
 130         #define PS0H  0x10
 131         #define PT1H  0x08
 132         #define PX1H  0x04
 133         #define PT0H  0x02
 134         #define PX0H  0x01
 135 SFR(P0, 0x80); // Port 0
 136         SBIT(AD7,  0x80, 7);
 137         SBIT(P0_7, 0x80, 7);
 138         SBIT(AD6,  0x80, 6);
 139         SBIT(P0_6, 0x80, 6);
 140         SBIT(AD5,  0x80, 5);
 141         SBIT(P0_5, 0x80, 5);
 142         SBIT(AD4,  0x80, 4);
 143         SBIT(P0_4, 0x80, 4);
 144         SBIT(AD3,  0x80, 3);
 145         SBIT(P0_3, 0x80, 3);
 146         SBIT(AD2,  0x80, 2);
 147         SBIT(P0_2, 0x80, 2);
 148         SBIT(AD1,  0x80, 1);
 149         SBIT(P0_1, 0x80, 1);
 150         SBIT(AD0,  0x80, 0);
 151         SBIT(P0_0, 0x80, 0);
 152 SFR(P1, 0x90); // Port 1
 153         SBIT(T1_CEX4, 0x90, 7);
 154         SBIT(P1_7,    0x90, 7);
 155         SBIT(T0_CEX3, 0x90, 6);
 156         SBIT(P1_6,    0x90, 6);
 157         SBIT(CEX2,    0x90, 5);
 158         SBIT(P1_5,    0x90, 5);
 159         SBIT(CEX1,    0x90, 4);
 160         SBIT(P1_4,    0x90, 4);
 161         SBIT(CEX0,    0x90, 3);
 162         SBIT(P1_3,    0x90, 3);
 163         SBIT(ECI,     0x90, 2);
 164         SBIT(P1_2,    0x90, 2);
 165         SBIT(T2EX,    0x90, 1);
 166         SBIT(P1_1,    0x90, 1);
 167         SBIT(T2,      0x90, 0);
 168         SBIT(P1_0,    0x90, 0);
 169 SFR(P2, 0xA0); // Port 2
 170         SBIT(AD15, 0xA0, 7);
 171         SBIT(P2_7, 0xA0, 7);
 172         SBIT(AD14, 0xA0, 6);
 173         SBIT(P2_6, 0xA0, 6);
 174         SBIT(AD13, 0xA0, 5);
 175         SBIT(P2_5, 0xA0, 5);
 176         SBIT(AD12, 0xA0, 4);
 177         SBIT(P2_4, 0xA0, 4);
 178         SBIT(AD11, 0xA0, 3);
 179         SBIT(P2_3, 0xA0, 3);
 180         SBIT(AD10, 0xA0, 2);
 181         SBIT(P2_2, 0xA0, 2);
 182         SBIT(AD9,  0xA0, 1);
 183         SBIT(P2_1, 0xA0, 1);
 184         SBIT(AD8,  0xA0, 0);
 185         SBIT(P2_0, 0xA0, 0);
 186 SFR(P3, 0xB0); // Port 3
 187         SBIT(RD,   0xB0, 7);
 188         SBIT(P3_7, 0xB0, 7);
 189         SBIT(WR,   0xB0, 6);
 190         SBIT(P3_6, 0xB0, 6);
 191         SBIT(T1,   0xB0, 5);
 192         SBIT(P3_5, 0xB0, 5);
 193         SBIT(T0,   0xB0, 4);
 194         SBIT(P3_4, 0xB0, 4);
 195         SBIT(INT1, 0xB0, 3);
 196         SBIT(P3_3, 0xB0, 3);
 197         SBIT(INT0, 0xB0, 2);
 198         SBIT(P3_2, 0xB0, 2);
 199         SBIT(TXD,  0xB0, 1);
 200         SBIT(P3_1, 0xB0, 1);
 201         SBIT(RXD,  0xB0, 0);
 202         SBIT(P3_0, 0xB0, 0);
 203 SFR(PCON, 0x87); // Power Control
 204         #define SMOD1 0x80
 205         #define SMOD0 0x40
 206         #define POF   0x10
 207         #define GF1   0x80
 208         #define GF0   0x40
 209         #define PD    0x20
 210         #define IDL   0x10
 211 SFR(PSW, 0xD0); // Program Status Word
 212         SBIT(CY,  0xD0, 7);
 213         SBIT(AC,  0xD0, 6);
 214         SBIT(F0,  0xD0, 5);
 215         SBIT(RS1, 0xD0, 4);
 216         SBIT(RS0, 0xD0, 3);
 217         SBIT(OV,  0xD0, 2);
 218         SBIT(F1,  0xD0, 1);
 219         SBIT(P,   0xD0, 0);
 220 SFR(RCAP2H, 0xCB); // Timer 2 Capture High
 221 SFR(RCAP2L, 0xCA); // Timer 2 Capture Low
 222 SFR(SADDR,  0xA9); // I2C Slave Address
 223 SFR(SADEN,  0xB9); // I2C Slave Address Mask
 224 SFR(S0BUF,  0x99); // Serial Data Buffer
 225 SFR(S0CON,  0x98); // Serial Control
 226         SBIT(SM0_FE, 0x98, 7);
 227         SBIT(SM1,    0x98, 6);
 228         SBIT(SM2,    0x98, 5);
 229         SBIT(REN,    0x98, 4);
 230         SBIT(TB8,    0x98, 3);
 231         SBIT(RB8,    0x98, 2);
 232         SBIT(TI,     0x98, 1);
 233         SBIT(RI,     0x98, 0);
 234 SFR(SP,    0x81); // Stack Pointer
 235 SFR(S1DAT, 0xDA); // I2C Serial 1 Data
 236 SFR(S1IST, 0xDC); // I2C Serial 1 Internal Status
 237 SFR(S1ADR, 0xDB); // I2C Serial 1 Address
 238         #define GC  0x01
 239 SFR(S1STA, 0xD9); // I2C Serial 1 Status
 240         #define SC4 0x80
 241         #define SC3 0x40
 242         #define SC2 0x20
 243         #define SC1 0x10
 244         #define SC0 0x08
 245 SFR(S1CON, 0xD8); // I2C Serial 1 Control
 246         SBIT(CR2,  0xD8, 7);
 247         SBIT(ENS1, 0xD8, 6);
 248         SBIT(STA,  0xD8, 5);
 249         SBIT(STO,  0xD8, 4);
 250         SBIT(SI,   0xD8, 3);
 251         SBIT(AA,   0xD8, 2);
 252         SBIT(CR1,  0xD8, 1);
 253         SBIT(CR0,  0xD8, 0);
 254 SFR(TCON, 0x88); // Timer Control
 255         SBIT(TF1, 0x88, 7);
 256         SBIT(TR1, 0x88, 6);
 257         SBIT(TF0, 0x88, 5);
 258         SBIT(TR0, 0x88, 4);
 259         SBIT(IE1, 0x88, 3);
 260         SBIT(IT1, 0x88, 2);
 261         SBIT(IE0, 0x88, 1);
 262         SBIT(IT0, 0x88, 0);
 263 SFR(T2CON, 0xC8); // Timer 2 Control
 264         SBIT(TF2,    0xC8, 7);
 265         SBIT(EXF2,   0xC8, 6);
 266         SBIT(RCLK,   0xC8, 5);
 267         SBIT(TCLK,   0xC8, 4);
 268         SBIT(EXEN2,  0xC8, 3);
 269         SBIT(TR2,    0xC8, 2);
 270         SBIT(C_T2,   0xC8, 1);
 271         SBIT(CP_RL2, 0xC8, 0);
 272 SFR(T2MOD,  0xC9); // Timer 2 Mode Control
 273         #define T2OE 0x02
 274         #define DCEN 0x01
 275 SFR(TH0 ,   0x8C); // Timer High 0
 276 SFR(TH1,    0x8D); // Timer High 1
 277 SFR(TH2,    0xCD); // Timer High 2
 278 SFR(TL0,    0x8A); // Timer Low 0
 279 SFR(TL1,    0x8B); // Timer Low 1
 280 SFR(TL2,    0xCC); // Timer Low 2
 281 SFR(TMOD,   0x89); // Timer Mode
 282         #define GATE_1 0x80
 283         #define C_T_1  0x40
 284         #define M1_1   0x20
 285         #define M0_1   0x10
 286         #define GATE_0 0x08
 287         #define C_T_0  0x04
 288         #define M1_0   0x02
 289         #define M0_0   0x01
 290 SFR(WDTRST, 0xA6); // Watchdog Timer Reset
 291
 292 #endif