sdcc/device/include/mcs51/p89lpc933_4.h

   1 /*-------------------------------------------------------------------------
   2    p89lpc933_4.h - This header allows to use the microcontrolers NXP
   3    (formerly Philips) p89lpc933, 934.
   4
   5    Copyright (C) 2008, Gudjon I. Gudjonsson <gudjon AT gudjon.org>
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 /*-------------------------------------------------------------------------
  31  The registered are ordered in the same way as in the NXP data sheet:
  32  http://www.standardics.nxp.com/products/lpc900/datasheet/p89lpc933.p89lpc934.p89lpc935.p89lpc936.pdf
  33 -------------------------------------------------------------------------*/
  34
  35 #ifndef __P89LPC933_4_H__
  36 #define __P89LPC933_4_H__
  37 #include <compiler.h>
  38
  39 /*BYTE Registers*/
  40 SFR(ACC, 0xE0); // Accumulator
  41         SBIT(ACC_7, 0xE0, 7);
  42         SBIT(ACC_6, 0xE0, 6);
  43         SBIT(ACC_5, 0xE0, 5);
  44         SBIT(ACC_4, 0xE0, 4);
  45         SBIT(ACC_3, 0xE0, 3);
  46         SBIT(ACC_2, 0xE0, 2);
  47         SBIT(ACC_1, 0xE0, 1);
  48         SBIT(ACC_0, 0xE0, 0);
  49 SFR(ADCON0, 0x8E); // A/D control register 0
  50         #define  ENADC0   0x04
  51 SFR(ADCON1, 0x97); // A/D control register 1
  52         #define  ENBI1    0x80
  53         #define  ENADCI1  0x40
  54         #define  TMM1     0x20
  55         #define  EDGE1    0x10
  56         #define  ADCI1    0x08
  57         #define  ENADC1   0x04
  58         #define  ADCS11   0x02
  59         #define  ADCS10   0x01
  60 SFR(ADINS, 0xA3); // A/D input select
  61         #define  ADI13    0x80
  62         #define  ADI12    0x40
  63         #define  ADI11    0x20
  64         #define  ADI10    0x10
  65 SFR(ADMODA, 0xC0); // A/D mode register A
  66         SBIT(BNDI1,  0xC0, 7);
  67         SBIT(BURST1, 0xC0, 6);
  68         SBIT(SCC1,   0xC0, 5);
  69         SBIT(SCAN1,  0xC0, 4);
  70 SFR(ADMODB, 0xA1); // A/D mode register B
  71         #define  CLK2     0x80
  72         #define  CLK1     0x40
  73         #define  CLK0     0x20
  74         #define  ENDAC1   0x08
  75         #define  ENDAC0   0x04
  76         #define  BSA1     0x02
  77 SFR(AD0DAT3, 0xF4); // A/D_0 data register 3
  78 SFR(AD1BH,   0xC4); // A/D_1 boundary high register
  79 SFR(AD1BL,   0xBC); // A/D_1 boundary low register
  80 SFR(AD1DAT0, 0xD5); // A/D_1 data register 0
  81 SFR(AD1DAT1, 0xD6); // A/D_1 data register 1
  82 SFR(AD1DAT2, 0xD7); // A/D_1 data register 2
  83 SFR(AD1DAT3, 0xF5); // A/D_1 data register 3
  84 SFR(AUXR1,   0xA2); // Auxilary function register
  85         #define  CLKLP    0x80
  86         #define  EBRR     0x40
  87         #define  ENT1     0x20
  88         #define  ENT0     0x10
  89         #define  SRST     0x08  // Bit 2 is always 0
  90         #define  DPS      0x01
  91 SFR(B, 0xF0); // B register
  92         SBIT(B7, 0xF0, 7);
  93         SBIT(B6, 0xF0, 6);
  94         SBIT(B5, 0xF0, 5);
  95         SBIT(B4, 0xF0, 4);
  96         SBIT(B3, 0xF0, 3);
  97         SBIT(B2, 0xF0, 2);
  98         SBIT(B1, 0xF0, 1);
  99         SBIT(B0, 0xF0, 0);
 100 SFR(BRGR0,  0xBE); // Baud rate generator rate low
 101 SFR(BRGR1,  0xBF); // Baud rate generator rate high
 102 SFR(BRGCON, 0xBD); // Baud rate generator control
 103         #define  SBRGS    0x02
 104         #define  BRGEN    0x01
 105 SFR(CMP1,   0xAC); // Comparator 1 control register
 106         #define  CE1      0x20
 107         #define  CP1      0x10
 108         #define  CN1      0x08
 109         #define  OE1      0x04
 110         #define  CO1      0x02
 111         #define  CMF1     0x01
 112 SFR(CMP2,   0xAD); // Comparator 2 control register
 113         #define  CE2      0x20
 114         #define  CP2      0x10
 115         #define  CN2      0x08
 116         #define  OE2      0x04
 117         #define  CO2      0x02
 118         #define  CMF2     0x01
 119 SFR(DIVM,   0x95); // CPU clock divide-by-M control
 120 SFR(DPH,  0x83); // Data Pointer High
 121 SFR(DPL,  0x82); // Data Pointer Low
 122 SFR(FMADRH, 0xE7); // Program flash address high
 123 SFR(FMADRL, 0xE6); // Program flash address low
 124 SFR(FMCON,  0xE4);
 125         // Program flash control (Read)
 126         #define  BUSY     0x80
 127         #define  HVA      0x08
 128         #define  HVE      0x04
 129         #define  SV       0x02
 130         #define  OI       0x01
 131         // Program flash control (Write)
 132         #define  FMCMD_7  0x80
 133         #define  FMCMD_6  0x40
 134         #define  FMCMD_5  0x20
 135         #define  FMCMD_4  0x10
 136         #define  FMCMD_3  0x08
 137         #define  FMCMD_2  0x04
 138         #define  FMCMD_1  0x02
 139         #define  FMCMD_0  0x01
 140 SFR(FMDATA,  0xE5); // Program flash data
 141 SFR(I2ADR,   0xDB); // I2C slave address register
 142         #define I2ADR_6  0x80
 143         #define I2ADR_5  0x40
 144         #define I2ADR_4  0x20
 145         #define I2ADR_3  0x10
 146         #define I2ADR_2  0x08
 147         #define I2ADR_1  0x04
 148         #define I2ADR_0  0x02
 149         #define GC       0x01
 150 SFR(I2CON,  0xD8); // I2C control register
 151         SBIT(I2EN,  0xD8, 6);
 152         SBIT(STA,   0xD8, 5);
 153         SBIT(STO,   0xD8, 4);
 154         SBIT(SI,    0xD8, 3);
 155         SBIT(AA,    0xD8, 2);
 156         SBIT(CRSEL, 0xD8, 0);
 157 SFR(I2DAT,  0xDA); // I2C data register
 158 SFR(I2SCLH, 0xDD); // I2C serial clock generator/SCL duty cycle register high
 159 SFR(I2SCLL, 0xDC); // I2C serial clock generator/SCL duty cycle register low
 160 SFR(I2STAT, 0xD9); // I2C status register
 161         #define STA_4   0x80
 162         #define STA_3   0x40
 163         #define STA_2   0x20
 164         #define STA_1   0x10
 165         #define STA_0   0x08    // Only write 0 to the lowest three bits
 166 SFR(ICRAH,  0xAB); // Input capture A register high
 167 SFR(ICRAL,  0xAA); // Input capture A register low
 168 SFR(ICRBH,  0xAF); // Input capture B register high
 169 SFR(ICRBL,  0xAE); // Input capture B register low
 170 SFR(IEN0,   0xA8); // Interrupt Enable 0
 171         SBIT(EA,     0xA8, 7);
 172         SBIT(EWDRT,  0xA8, 6);
 173         SBIT(EBO,    0xA8, 5);
 174         SBIT(ES_ESR, 0xA8, 4);
 175         SBIT(ET1,    0xA8, 3);
 176         SBIT(EX1,    0xA8, 2);
 177         SBIT(ET0,    0xA8, 1);
 178         SBIT(EX0,    0xA8, 0);
 179 SFR(IEN1,  0xE8); // Interrupt Enable 1
 180         SBIT(EAD,    0xE8, 7);
 181         SBIT(EST,    0xE8, 6);
 182         SBIT(ESPI,   0xE8, 3);
 183         SBIT(EC,     0xE8, 2);
 184         SBIT(EKBI,   0xE8, 1);
 185         SBIT(EI2C,   0xE8, 0);
 186 SFR(IP0, 0xB8); // Interrupt Priority 0
 187         SBIT(PWDRT,  0xB8, 6);
 188         SBIT(PBO,    0xB8, 5);
 189         SBIT(PS_PSR, 0xB8, 4);
 190         SBIT(PT1,    0xB8, 3);
 191         SBIT(PX1,    0xB8, 2);
 192         SBIT(PT0,    0xB8, 1);
 193         SBIT(PX0,    0xB8, 0);
 194 SFR(IP0H, 0xB7); // Interrupt Priority 0 high
 195         #define PWDRTH    0x40
 196         #define PBOH      0x20
 197         #define PSH_PSRH  0x10
 198         #define PT1H      0x08
 199         #define PX1H      0x04
 200         #define PT0H      0x02
 201         #define PX0H      0x01
 202 SFR(IP1,  0xF8); // Interrupt Priority 1
 203         SBIT(PAD,   0xF8, 7);
 204         SBIT(PST,   0xF8, 6);
 205         SBIT(PSPI,  0xF8, 3);
 206         SBIT(PC,    0xF8, 2);
 207         SBIT(PKBI,  0xF8, 1);
 208         SBIT(PI2C,  0xF8, 0);
 209 SFR(IP1H, 0xF7); // Interrupt Priority 1 High
 210         #define PADH   0x80
 211         #define PSTH   0x40
 212         #define PSPIH  0x08
 213         #define PCH    0x04
 214         #define PKBIH  0x02
 215         #define PI2CH  0x01
 216 SFR(KBCON, 0x94); // Keypad control register
 217         #define PATN_SEL 0x02
 218         #define KBIF     0x01
 219 SFR(KBMASK, 0x86); // Keypad interrupt mask register
 220 SFR(KBPATN, 0x93); // Keypad pattern register
 221 SFR(P0, 0x80); // Port 0
 222         SBIT(P0_7,  0x80, 7);
 223         SBIT(T1,    0x80, 7);
 224         SBIT(KB7,   0x80, 7);
 225         SBIT(P0_6,  0x80, 6);
 226         SBIT(CMP_1, 0x80, 6); // Renamed, not to conflict with the CMP1 register
 227         SBIT(KB6,   0x80, 6);
 228         SBIT(P0_5,  0x80, 5);
 229         SBIT(CMPREF,0x80, 5);
 230         SBIT(KB5,   0x80, 5);
 231         SBIT(P0_4,  0x80, 4);
 232         SBIT(CIN1A, 0x80, 4);
 233         SBIT(KB4,   0x80, 4);
 234         SBIT(P0_3,  0x80, 3);
 235         SBIT(CIN1B, 0x80, 3);
 236         SBIT(KB3,   0x80, 3);
 237         SBIT(P0_2,  0x80, 2);
 238         SBIT(CIN2A, 0x80, 2);
 239         SBIT(KB2,   0x80, 2);
 240         SBIT(P0_1,  0x80, 1);
 241         SBIT(CIN2B, 0x80, 1);
 242         SBIT(KB1,   0x80, 1);
 243         SBIT(P0_0,  0x80, 0);
 244         SBIT(CMP_2, 0x80, 0); // Renamed, not to conflict with the CMP2 register
 245         SBIT(KB0,   0x80, 0);
 246 SFR(P1, 0x90); // Port 1
 247         SBIT(P1_7,    0x90, 7);
 248         SBIT(P1_6,    0x90, 6);
 249         SBIT(P1_5,    0x90, 5);
 250         SBIT(RST,     0x90, 5);
 251         SBIT(P1_4,    0x90, 4);
 252         SBIT(INT1,    0x90, 4);
 253         SBIT(P1_3,    0x90, 3);
 254         SBIT(INT0,    0x90, 3);
 255         SBIT(SDA,     0x90, 3);
 256         SBIT(P1_2,    0x90, 2);
 257         SBIT(T0,      0x90, 2);
 258         SBIT(SCL,     0x90, 2);
 259         SBIT(P1_1,    0x90, 1);
 260         SBIT(RXD,     0x90, 1);
 261         SBIT(P1_0,    0x90, 0);
 262         SBIT(TXD,     0x90, 0);
 263 SFR(P2, 0xA0); // Port 2
 264         SBIT(P2_7,   0xA0, 7);
 265         SBIT(P2_6,   0xA0, 6);
 266         SBIT(P2_5,   0xA0, 5);
 267         SBIT(SPICLK, 0xA0, 5);
 268         SBIT(P2_4,   0xA0, 4);
 269         SBIT(SS,     0xA0, 4);
 270         SBIT(P2_3,   0xA0, 3);
 271         SBIT(MISO,   0xA0, 3);
 272         SBIT(P2_2,   0xA0, 2);
 273         SBIT(MOSI,   0xA0, 2);
 274         SBIT(P2_1,   0xA0, 1);
 275         SBIT(P2_0,   0xA0, 0);
 276 SFR(P3, 0xB0); // Port 3
 277         SBIT(P3_7, 0xB0, 7);
 278         SBIT(P3_6, 0xB0, 6);
 279         SBIT(P3_5, 0xB0, 5);
 280         SBIT(P3_4, 0xB0, 4);
 281         SBIT(P3_3, 0xB0, 3);
 282         SBIT(P3_2, 0xB0, 2);
 283         SBIT(P3_1, 0xB0, 1);
 284         SBIT(XTAL1,0xB0, 1);
 285         SBIT(P3_0, 0xB0, 0);
 286         SBIT(XTAL2,0xB0, 0);
 287 SFR(P0M1, 0x84); // Port 0 output mode 1
 288         #define P0M1_7  0x80
 289         #define P0M1_6  0x40
 290         #define P0M1_5  0x20
 291         #define P0M1_4  0x10
 292         #define P0M1_3  0x08
 293         #define P0M1_2  0x04
 294         #define P0M1_1  0x02
 295         #define P0M1_0  0x01
 296 SFR(P0M2, 0x85); // Port 0 output mode 2
 297         #define P0M2_7  0x80
 298         #define P0M2_6  0x40
 299         #define P0M2_5  0x20
 300         #define P0M2_4  0x10
 301         #define P0M2_3  0x08
 302         #define P0M2_2  0x04
 303         #define P0M2_1  0x02
 304         #define P0M2_0  0x01
 305 SFR(P1M1, 0x91); // Port 1 output mode 1
 306         #define P1M1_7  0x80
 307         #define P1M1_6  0x40
 308         #define P1M1_4  0x10
 309         #define P1M1_3  0x08
 310         #define P1M1_2  0x04
 311         #define P1M1_1  0x02
 312         #define P1M1_0  0x01
 313 SFR(P1M2, 0x92); // Port 1 output mode 2
 314         #define P1M2_7  0x80
 315         #define P1M2_6  0x40
 316         #define P1M2_4  0x10
 317         #define P1M2_3  0x08
 318         #define P1M2_2  0x04
 319         #define P1M2_1  0x02
 320         #define P1M2_0  0x01
 321 SFR(P2M1, 0xA4); // Port 2 output mode 1
 322         #define P2M1_7  0x80
 323         #define P2M1_6  0x40
 324         #define P2M1_5  0x20
 325         #define P2M1_4  0x10
 326         #define P2M1_3  0x08
 327         #define P2M1_2  0x04
 328         #define P2M1_1  0x02
 329         #define P2M1_0  0x01
 330 SFR(P2M2, 0xA5); // Port 2 output mode 2
 331         #define P2M2_7  0x80
 332         #define P2M2_6  0x40
 333         #define P2M2_5  0x20
 334         #define P2M2_4  0x10
 335         #define P2M2_3  0x08
 336         #define P2M2_2  0x04
 337         #define P2M2_1  0x02
 338         #define P2M2_0  0x01
 339 SFR(P3M1, 0xB1); // Port 3 output mode 1
 340         #define P3M1_1  0x02
 341         #define P3M1_0  0x01
 342 SFR(P3M2, 0xB2); // Port 3 output mode 2
 343         #define P3M2_1  0x02
 344         #define P3M2_0  0x01
 345 SFR(PCON,  0x87); // Power control register
 346         #define SMOD1   0x80
 347         #define SMOD0   0x40
 348         #define BOPD    0x20
 349         #define BOI     0x10
 350         #define GF1     0x08
 351         #define GF0     0x04
 352         #define PMOD1   0x02
 353         #define PMOD0   0x01
 354 SFR(PCONA, 0xB5); // Power control register A
 355         #define RTCPD   0x80
 356         #define VCPD    0x20
 357         #define ADPD    0x10
 358         #define I2PD    0x08
 359         #define SPPD    0x04
 360         #define SPD     0x02
 361 SFR(PSW, 0xD0); // Program Status Word
 362         SBIT(CY,  0xD0, 7);
 363         SBIT(AC,  0xD0, 6);
 364         SBIT(F0,  0xD0, 5);
 365         SBIT(RS1, 0xD0, 4);
 366         SBIT(RS0, 0xD0, 3);
 367         SBIT(OV,  0xD0, 2);
 368         SBIT(F1,  0xD0, 1);
 369         SBIT(P,   0xD0, 0);
 370 SFR(PT0AD, 0xF6); // Port 0 digital input disable
 371         #define PT0AD_5   0x20
 372         #define PT0AD_4   0x10
 373         #define PT0AD_3   0x08
 374         #define PT0AD_2   0x04
 375         #define PT0AD_1   0x02
 376 SFR(RSTSRC, 0xDF); // Reset source register
 377         #define BOF    0x20
 378         #define POF    0x10
 379         #define R_BK   0x08
 380         #define R_WD   0x04
 381         #define R_SF   0x02
 382         #define R_EX   0x01
 383 SFR(RTCCON, 0xD1); // Real-time clock control
 384         #define RTCF   0x80
 385         #define RTCS1  0x40
 386         #define RTCS0  0x20
 387         #define ERTC   0x02
 388         #define RTCEN  0x01
 389 SFR(RTCH,  0xD2); // Real-time clock register high
 390 SFR(RTCL,  0xD3); // Real-time clock register low
 391 SFR(SADDR, 0xA9); // Serial port address register
 392 SFR(SADEN, 0xB9); // Serial port address enable
 393 SFR(SBUF,  0x99); // Serial port data buffer register
 394 SFR(SCON,  0x98); // Serial port control
 395         SBIT(SM0_FE, 0x98, 7);
 396         SBIT(SM1,    0x98, 6);
 397         SBIT(SM2,    0x98, 5);
 398         SBIT(REN,    0x98, 4);
 399         SBIT(TB8,    0x98, 3);
 400         SBIT(RB8,    0x98, 2);
 401         SBIT(TI,     0x98, 1);
 402         SBIT(RI,     0x98, 0);
 403 SFR(SSTAT, 0xBA); // Serial port extended status register
 404         #define DBMOD  0x80
 405         #define INTLO  0x40
 406         #define CIDIS  0x20
 407         #define DBISEL 0x10
 408         #define FE     0x08
 409         #define BR     0x04
 410         #define OE     0x02
 411         #define STINT  0x01
 412 SFR(SP,     0x81); // Stack Pointer
 413 SFR(SPCTL,  0xE2); // SPI control register
 414         #define SSIG  0x80
 415         #define SPEN  0x40
 416         #define DORD  0x20
 417         #define MSTR  0x10
 418         #define CPOL  0x08
 419         #define CPHA  0x04
 420         #define SPR1  0x02
 421         #define SPR0  0x01
 422 SFR(SPSTAT, 0xE1); // SPI status register
 423         #define SPIF  0x80
 424         #define WCOL  0x40
 425 SFR(SPDAT,  0xE3); // SPI data register
 426 SFR(TAMOD,  0x8F); // Timer 0 and 1 auxiliary mode
 427         #define T1M2  0x10
 428         #define T0M2  0x01
 429 SFR(TCON,   0x88); // Timer 0 and 1 control
 430         SBIT(TF1, 0x88, 7);
 431         SBIT(TR1, 0x88, 6);
 432         SBIT(TF0, 0x88, 5);
 433         SBIT(TR0, 0x88, 4);
 434         SBIT(IE1, 0x88, 3);
 435         SBIT(IT1, 0x88, 2);
 436         SBIT(IE0, 0x88, 1);
 437         SBIT(IT0, 0x88, 0);
 438 SFR(TH0,  0x8C); // Timer 0 high
 439 SFR(TH1,  0x8D); // Timer 1 high
 440 SFR(TL0,  0x8A); // Timer 0 low
 441 SFR(TL1,  0x8B); // Timer 1 low
 442 SFR(TMOD, 0x89); // Timer 0 and 1 mode
 443         #define T1GATE  0x80
 444         #define T1C_T   0x40
 445         #define T1M1    0x20
 446         #define T1M0    0x10
 447         #define T0GATE  0x08
 448         #define T0C_T   0x04
 449         #define T0M1    0x02
 450         #define T0M0    0x01
 451 SFR(TRIM, 0x96); // Internal oscillator trim register
 452         #define RCCLK   0x80
 453         #define ENCLK   0x40
 454         #define TRIM_5  0x20
 455         #define TRIM_4  0x10
 456         #define TRIM_3  0x08
 457         #define TRIM_2  0x04
 458         #define TRIM_1  0x02
 459         #define TRIM_0  0x01
 460 SFR(WDCON, 0xA7); // Watchdog control register
 461         #define PRE2    0x80
 462         #define PRE1    0x40
 463         #define PRE0    0x20
 464         #define WDRUN   0x04
 465         #define WDTOF   0x02
 466         #define WDCLK   0x01
 467 SFR(WDL,    0xC1); // Watchdog load
 468 SFR(WFEED1, 0xC2); // Watchdog feed 1
 469 SFR(WFEED2, 0xC3); // Watchdog feed 2
 470 #endif // __P89LPC933_4_H__