sdcc/device/include/mcs51/p89lpc938.h

   1 /*-------------------------------------------------------------------------
   2    p89lpc938.h - This header defines register addresses for the Philips
   3    P89LPC938 microcontroller for use with the SDCC compiler.
   4
   5    Copyright (C) 2007, Kyle Guinn <elyk03@gmail.com>
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef P89LPC938_H
  31 #define P89LPC938_H
  32
  33 /* SFR byte addresses */
  34 __sfr __at (0x80) P0;      /* Port 0                               */
  35 __sfr __at (0x81) SP;      /* Stack pointer                        */
  36 __sfr __at (0x82) DPL;     /* Data pointer low                     */
  37 __sfr __at (0x83) DPH;     /* Data pointer high                    */
  38 __sfr __at (0x84) P0M1;    /* Port 0 output mode 1                 */
  39 __sfr __at (0x85) P0M2;    /* Port 0 output mode 2                 */
  40 __sfr __at (0x86) KBMASK;  /* Keypad interrupt mask register       */
  41 __sfr __at (0x87) PCON;    /* Power control register               */
  42 __sfr __at (0x88) TCON;    /* Timer 0 and 1 control                */
  43 __sfr __at (0x89) TMOD;    /* Timer 0 and 1 mode                   */
  44 __sfr __at (0x8A) TL0;     /* Timer 0 low                          */
  45 __sfr __at (0x8B) TL1;     /* Timer 1 low                          */
  46 __sfr __at (0x8C) TH0;     /* Timer 0 high                         */
  47 __sfr __at (0x8D) TH1;     /* Timer 1 high                         */
  48 __sfr __at (0x8F) TAMOD;   /* Timer 0 and 1 auxiliary mode         */
  49 __sfr __at (0x90) P1;      /* Port 1                               */
  50 __sfr __at (0x91) P1M1;    /* Port 1 output mode 1                 */
  51 __sfr __at (0x92) P1M2;    /* Port 1 output mode 2                 */
  52 __sfr __at (0x93) KBPATN;  /* Keypad pattern register              */
  53 __sfr __at (0x94) KBCON;   /* Keypad control register              */
  54 __sfr __at (0x95) DIVM;    /* CPU clock divide-by-M control        */
  55 __sfr __at (0x96) TRIM;    /* Internal oscillator trim register    */
  56 __sfr __at (0x97) AD0CON;  /* ADC0 control register                */
  57 __sfr __at (0x98) SCON;    /* Serial port control                  */
  58 __sfr __at (0x99) SBUF;    /* Serial port data buffer register     */
  59 __sfr __at (0xA0) P2;      /* Port 2                               */
  60 __sfr __at (0xA1) AD0MODB; /* ADC0 mode register B                 */
  61 __sfr __at (0xA2) AUXR1;   /* Auxiliary function register          */
  62 __sfr __at (0xA3) AD0INS;  /* ADC0 input select                    */
  63 __sfr __at (0xA4) P2M1;    /* Port 2 output mode 1                 */
  64 __sfr __at (0xA5) P2M2;    /* Port 2 output mode 2                 */
  65 __sfr __at (0xA7) WDCON;   /* Watchdog control register            */
  66 __sfr __at (0xA8) IEN0;    /* Interrupt enable 0                   */
  67 __sfr __at (0xA9) SADDR;   /* Serial port address register         */
  68 __sfr __at (0xAA) ICRAL;   /* Input capture A register low         */
  69 __sfr __at (0xAB) ICRAH;   /* Input capture A register high        */
  70 __sfr __at (0xAC) CMP1;    /* Comparator 1 control register        */
  71 __sfr __at (0xAD) CMP2;    /* Comparator 2 control register        */
  72 __sfr __at (0xAE) ICRBL;   /* Input capture B register low         */
  73 __sfr __at (0xAF) ICRBH;   /* Input capture B register high        */
  74 __sfr __at (0xB0) P3;      /* Port 3                               */
  75 __sfr __at (0xB1) P3M1;    /* Port 3 output mode 1                 */
  76 __sfr __at (0xB2) P3M2;    /* Port 3 output mode 2                 */
  77 __sfr __at (0xB5) PCONA;   /* Power control register A             */
  78 __sfr __at (0xB7) IP0H;    /* Interrupt priority 0 high            */
  79 __sfr __at (0xB8) IP0;     /* Interrupt priority 0                 */
  80 __sfr __at (0xB9) SADEN;   /* Serial port address enable           */
  81 __sfr __at (0xBA) SSTAT;   /* Serial port extended status register */
  82 __sfr __at (0xBD) BRGCON;  /* Baud rate generator control          */
  83 __sfr __at (0xBE) BRGR0;   /* Baud rate generator rate low         */
  84 __sfr __at (0xBF) BRGR1;   /* Baud rate generator rate high        */
  85 __sfr __at (0xC0) AD0MODA; /* ADC0 mode register A                 */
  86 __sfr __at (0xC1) WDL;     /* Watchdog load                        */
  87 __sfr __at (0xC2) WFEED1;  /* Watchdog feed 1                      */
  88 __sfr __at (0xC3) WFEED2;  /* Watchdog feed 2                      */
  89 __sfr __at (0xC8) TCR20;   /* CCU control register 0               */
  90 __sfr __at (0xC9) TICR2;   /* CCU interrupt control register       */
  91 __sfr __at (0xCA) TPCR2L;  /* Prescaler control register low       */
  92 __sfr __at (0xCB) TPCR2H;  /* Prescaler control register high      */
  93 __sfr __at (0xCC) TL2;     /* CCU timer low                        */
  94 __sfr __at (0xCD) TH2;     /* CCU timer high                       */
  95 __sfr __at (0xCE) TOR2L;   /* CCU reload register low              */
  96 __sfr __at (0xCF) TOR2H;   /* CCU reload register high             */
  97 __sfr __at (0xD0) PSW;     /* Program status word                  */
  98 __sfr __at (0xD1) RTCCON;  /* RTC control                          */
  99 __sfr __at (0xD2) RTCH;    /* RTC register high                    */
 100 __sfr __at (0xD3) RTCL;    /* RTC register low                     */
 101 __sfr __at (0xD5) IEN2;    /* Interrupt enable 2                   */
 102 __sfr __at (0xD6) IP2;     /* Interrupt priority 2                 */
 103 __sfr __at (0xD7) IP2H;    /* Interrupt priority 2 high            */
 104 __sfr __at (0xD8) I2CON;   /* I²C control register                 */
 105 __sfr __at (0xD9) I2STAT;  /* I²C status register                  */
 106 __sfr __at (0xDA) I2DAT;   /* I²C data register                    */
 107 __sfr __at (0xDB) I2ADR;   /* I²C slave address register           */
 108 __sfr __at (0xDC) I2SCLL;  /* Serial clock generator low/
 109                             * SCL duty cycle register low          */
 110 __sfr __at (0xDD) I2SCLH;  /* Serial clock generator high/
 111                             * SCL duty cycle register high         */
 112 __sfr __at (0xDE) TISE2;   /* CCU interrupt status encode register */
 113 __sfr __at (0xDF) RSTSRC;  /* Reset source register                */
 114 __sfr __at (0xE0) ACC;     /* Accumulator                          */
 115 __sfr __at (0xE1) SPSTAT;  /* SPI status register                  */
 116 __sfr __at (0xE2) SPCTL;   /* SPI control register                 */
 117 __sfr __at (0xE3) SPDAT;   /* SPI data register                    */
 118 __sfr __at (0xE4) FMCON;   /* Program Flash control (Read)/
 119                             * Program Flash control (Write)        */
 120 __sfr __at (0xE5) FMDATA;  /* Program Flash data                   */
 121 __sfr __at (0xE6) FMADRL;  /* Program Flash address low            */
 122 __sfr __at (0xE7) FMADRH;  /* Program Flash address high           */
 123 __sfr __at (0xE8) IEN1;    /* Interrupt enable 1                   */
 124 __sfr __at (0xE9) TIFR2;   /* CCU interrupt flag register          */
 125 __sfr __at (0xEA) CCCRA;   /* Capture compare A control register   */
 126 __sfr __at (0xEB) CCCRB;   /* Capture compare B control register   */
 127 __sfr __at (0xEC) CCCRC;   /* Capture compare C control register   */
 128 __sfr __at (0xED) CCCRD;   /* Capture compare D control register   */
 129 __sfr __at (0xEE) OCRAL;   /* Output compare A register low        */
 130 __sfr __at (0xEF) OCRAH;   /* Output compare A register high       */
 131 __sfr __at (0xF0) B;       /* B register                           */
 132 __sfr __at (0xF1) DEECON;  /* Data EEPROM control register         */
 133 __sfr __at (0xF2) DEEDAT;  /* Data EEPROM data register            */
 134 __sfr __at (0xF3) DEEADR;  /* Data EEPROM address register         */
 135 __sfr __at (0xF6) PT0AD;   /* Port 0 digital input disable         */
 136 __sfr __at (0xF7) IP1H;    /* Interrupt priority 1 high            */
 137 __sfr __at (0xF8) IP1;     /* Interrupt priority 1                 */
 138 __sfr __at (0xF9) TCR21;   /* CCU control register 1               */
 139 __sfr __at (0xFA) OCRBL;   /* Output compare B register low        */
 140 __sfr __at (0xFB) OCRBH;   /* Output compare B register high       */
 141 __sfr __at (0xFC) OCRCL;   /* Output compare C register low        */
 142 __sfr __at (0xFD) OCRCH;   /* Output compare C register high       */
 143 __sfr __at (0xFE) OCRDL;   /* Output compare D register low        */
 144 __sfr __at (0xFF) OCRDH;   /* Output compare D register high       */
 145
 146 /* 16-bit SFRs (duplicates of above) */
 147 __sfr16 __at (0x8382) DPTR;  /* Data pointer               */
 148 __sfr16 __at (0x8C8A) TMR0;  /* Timer 0 count              */
 149 __sfr16 __at (0x8D8B) TMR1;  /* Timer 1 count              */
 150 __sfr16 __at (0xABAA) ICRA;  /* Input capture A register   */
 151 __sfr16 __at (0xAFAE) ICRB;  /* Input capture B register   */
 152 __sfr16 __at (0xBFBE) BRGR;  /* Baud rate generator        */
 153 __sfr16 __at (0xCBCA) TPCR2; /* Prescaler control register */
 154 __sfr16 __at (0xCDCC) TMR2;  /* Timer 2 count              */
 155 __sfr16 __at (0xCFCE) TOR2;  /* CCU reload register        */
 156 __sfr16 __at (0xD2D3) RTC;   /* RTC register               */
 157 __sfr16 __at (0xDDDC) I2SCL; /* Serial clock generator/
 158                               * SCL duty cycle register    */
 159 __sfr16 __at (0xE7E6) FMADR; /* Program Flash address      */
 160 __sfr16 __at (0xEFEE) OCRA;  /* Output compare A register  */
 161 __sfr16 __at (0xFBFA) OCRB;  /* Output compare B register  */
 162 __sfr16 __at (0xFDFC) OCRC;  /* Output compare C register  */
 163 __sfr16 __at (0xFFFE) OCRD;  /* Output compare D register  */
 164
 165 /* "Extended SFRs" (logically in __xdata memory space) */
 166 #define BNDSTA0  (*(__xdata volatile unsigned char*)0xFFED) /* ADC0 boundary status register           */
 167 #define ADC0LBND (*(__xdata volatile unsigned char*)0xFFEE) /* ADC0 low_boundary register (MSB)        */
 168 #define ADC0HBND (*(__xdata volatile unsigned char*)0xFFEF) /* ADC0 high_boundary register, left (MSB) */
 169 #define AD0DAT7R (*(__xdata volatile unsigned char*)0xFFF0) /* ADC0 data register 7, right (LSB)       */
 170 #define AD0DAT7L (*(__xdata volatile unsigned char*)0xFFF1) /* ADC0 data register 7, left (MSB)        */
 171 #define AD0DAT6R (*(__xdata volatile unsigned char*)0xFFF2) /* ADC0 data register 6, right (LSB)       */
 172 #define AD0DAT6L (*(__xdata volatile unsigned char*)0xFFF3) /* ADC0 data register 6, left (MSB)        */
 173 #define AD0DAT5R (*(__xdata volatile unsigned char*)0xFFF4) /* ADC0 data register 5, right (LSB)       */
 174 #define AD0DAT5L (*(__xdata volatile unsigned char*)0xFFF5) /* ADC0 data register 5, left (MSB)        */
 175 #define AD0DAT4R (*(__xdata volatile unsigned char*)0xFFF6) /* ADC0 data register 4, right (LSB)       */
 176 #define AD0DAT4L (*(__xdata volatile unsigned char*)0xFFF7) /* ADC0 data register 4, left (MSB)        */
 177 #define AD0DAT3R (*(__xdata volatile unsigned char*)0xFFF8) /* ADC0 data register 3, right (LSB)       */
 178 #define AD0DAT3L (*(__xdata volatile unsigned char*)0xFFF9) /* ADC0 data register 3, left (MSB)        */
 179 #define AD0DAT2R (*(__xdata volatile unsigned char*)0xFFFA) /* ADC0 data register 2, right (LSB)       */
 180 #define AD0DAT2L (*(__xdata volatile unsigned char*)0xFFFB) /* ADC0 data register 2, left (MSB)        */
 181 #define AD0DAT1R (*(__xdata volatile unsigned char*)0xFFFC) /* ADC0 data register 1, right (LSB)       */
 182 #define AD0DAT1L (*(__xdata volatile unsigned char*)0xFFFD) /* ADC0 data register 1, left (MSB)        */
 183 #define AD0DAT0R (*(__xdata volatile unsigned char*)0xFFFE) /* ADC0 data register 0, right (LSB)       */
 184 #define AD0DAT0L (*(__xdata volatile unsigned char*)0xFFFF) /* ADC0 data register 0, left (MSB)        */
 185
 186 /* Special Function Bits */
 187 /* P0 (0x80) */
 188 __sbit __at (0x80) P0_0;
 189 __sbit __at (0x81) P0_1;
 190 __sbit __at (0x82) P0_2;
 191 __sbit __at (0x83) P0_3;
 192 __sbit __at (0x84) P0_4;
 193 __sbit __at (0x85) P0_5;
 194 __sbit __at (0x86) P0_6;
 195 __sbit __at (0x87) P0_7;
 196 #define CMP_2  P0_0 /* Renamed:  Name conflicts with SFR 0xAD */
 197 #define KB0    P0_0
 198 #define CIN2B  P0_1
 199 #define KB1    P0_1
 200 #define CIN2A  P0_2
 201 #define KB2    P0_2
 202 #define CIN1B  P0_3
 203 #define KB3    P0_3
 204 #define CIN1A  P0_4
 205 #define KB4    P0_4
 206 #define CMPREF P0_5
 207 #define KB5    P0_5
 208 #define CMP_1  P0_6 /* Renamed:  Name conflicts with SFR 0xAC */
 209 #define KB6    P0_6
 210 #define T1     P0_7
 211 #define KB7    P0_7
 212
 213 /* TCON (0x88) */
 214 __sbit __at (0x88) TCON_0;
 215 __sbit __at (0x89) TCON_1;
 216 __sbit __at (0x8A) TCON_2;
 217 __sbit __at (0x8B) TCON_3;
 218 __sbit __at (0x8C) TCON_4;
 219 __sbit __at (0x8D) TCON_5;
 220 __sbit __at (0x8E) TCON_6;
 221 __sbit __at (0x8F) TCON_7;
 222 #define IT0 TCON_0
 223 #define IE0 TCON_1
 224 #define IT1 TCON_2
 225 #define IE1 TCON_3
 226 #define TR0 TCON_4
 227 #define TF0 TCON_5
 228 #define TR1 TCON_6
 229 #define TF1 TCON_7
 230
 231 /* P1 (0x90) */
 232 __sbit __at (0x90) P1_0;
 233 __sbit __at (0x91) P1_1;
 234 __sbit __at (0x92) P1_2;
 235 __sbit __at (0x93) P1_3;
 236 __sbit __at (0x94) P1_4;
 237 __sbit __at (0x95) P1_5;
 238 __sbit __at (0x96) P1_6;
 239 __sbit __at (0x97) P1_7;
 240 #define TXD  P1_0
 241 #define RXD  P1_1
 242 #define T0   P1_2
 243 #define SCL  P1_2
 244 #define INT0 P1_3
 245 #define SDA  P1_3
 246 #define INT1 P1_4
 247 #define RST  P1_5
 248 #define OCB  P1_6
 249 #define OCC  P1_7
 250
 251 /* SCON (0x98) */
 252 __sbit __at (0x98) SCON_0;
 253 __sbit __at (0x99) SCON_1;
 254 __sbit __at (0x9A) SCON_2;
 255 __sbit __at (0x9B) SCON_3;
 256 __sbit __at (0x9C) SCON_4;
 257 __sbit __at (0x9D) SCON_5;
 258 __sbit __at (0x9E) SCON_6;
 259 __sbit __at (0x9F) SCON_7;
 260 #define RI  SCON_0
 261 #define TI  SCON_1
 262 #define RB8 SCON_2
 263 #define TB8 SCON_3
 264 #define REN SCON_4
 265 #define SM2 SCON_5
 266 #define SM1 SCON_6
 267 #define SM0 SCON_7
 268 #define FE  SCON_7
 269
 270 /* P2 (0xA0) */
 271 __sbit __at (0xA0) P2_0;
 272 __sbit __at (0xA1) P2_1;
 273 __sbit __at (0xA2) P2_2;
 274 __sbit __at (0xA3) P2_3;
 275 __sbit __at (0xA4) P2_4;
 276 __sbit __at (0xA5) P2_5;
 277 __sbit __at (0xA6) P2_6;
 278 __sbit __at (0xA7) P2_7;
 279 #define ICB    P2_0
 280 #define OCD    P2_1
 281 #define MOSI   P2_2
 282 #define MISO   P2_3
 283 #define SS     P2_4
 284 #define SPICLK P2_5
 285 #define OCA    P2_6
 286 #define ICA    P2_7
 287
 288 /* IEN0 (0xA8) */
 289 __sbit __at (0xA8) IEN0_0;
 290 __sbit __at (0xA9) IEN0_1;
 291 __sbit __at (0xAA) IEN0_2;
 292 __sbit __at (0xAB) IEN0_3;
 293 __sbit __at (0xAC) IEN0_4;
 294 __sbit __at (0xAD) IEN0_5;
 295 __sbit __at (0xAE) IEN0_6;
 296 __sbit __at (0xAF) IEN0_7;
 297 #define EX0   IEN0_0
 298 #define ET0   IEN0_1
 299 #define EX1   IEN0_2
 300 #define ET1   IEN0_3
 301 #define ES    IEN0_4
 302 #define ESR   IEN0_4
 303 #define EBO   IEN0_5
 304 #define EWDRT IEN0_6
 305 #define EA    IEN0_7
 306
 307 /* P3 (0xB0) */
 308 __sbit __at (0xB0) P3_0;
 309 __sbit __at (0xB1) P3_1;
 310 __sbit __at (0xB2) P3_2;
 311 __sbit __at (0xB3) P3_3;
 312 __sbit __at (0xB4) P3_4;
 313 __sbit __at (0xB5) P3_5;
 314 __sbit __at (0xB6) P3_6;
 315 __sbit __at (0xB7) P3_7;
 316 #define XTAL2 P3_0
 317 #define XTAL1 P3_1
 318
 319 /* IP0 (0xB8) */
 320 __sbit __at (0xB8) IP0_0;
 321 __sbit __at (0xB9) IP0_1;
 322 __sbit __at (0xBA) IP0_2;
 323 __sbit __at (0xBB) IP0_3;
 324 __sbit __at (0xBC) IP0_4;
 325 __sbit __at (0xBD) IP0_5;
 326 __sbit __at (0xBE) IP0_6;
 327 __sbit __at (0xBF) IP0_7;
 328 #define PX0   IP0_0
 329 #define PT0   IP0_1
 330 #define PX1   IP0_2
 331 #define PT1   IP0_3
 332 #define PS    IP0_4
 333 #define PSR   IP0_4
 334 #define PBO   IP0_5
 335 #define PWDRT IP0_6
 336
 337 /* AD0MODA (0xC0) */
 338 __sbit __at (0xC0) AD0MODA_0;
 339 __sbit __at (0xC1) AD0MODA_1;
 340 __sbit __at (0xC2) AD0MODA_2;
 341 __sbit __at (0xC3) AD0MODA_3;
 342 __sbit __at (0xC4) AD0MODA_4;
 343 __sbit __at (0xC5) AD0MODA_5;
 344 __sbit __at (0xC6) AD0MODA_6;
 345 __sbit __at (0xC7) AD0MODA_7;
 346 #define SCAN0  AD0MODA_4
 347 #define SCC0   AD0MODA_5
 348 #define BURST0 AD0MODA_6
 349 #define BNDI0  AD0MODA_7
 350
 351 /* TCR20 (0xC8) */
 352 __sbit __at (0xC8) TCR20_0;
 353 __sbit __at (0xC9) TCR20_1;
 354 __sbit __at (0xCA) TCR20_2;
 355 __sbit __at (0xCB) TCR20_3;
 356 __sbit __at (0xCC) TCR20_4;
 357 __sbit __at (0xCD) TCR20_5;
 358 __sbit __at (0xCE) TCR20_6;
 359 __sbit __at (0xCF) TCR20_7;
 360 #define TMOD20 TCR20_0
 361 #define TMOD21 TCR20_1
 362 #define TDIR2  TCR20_2
 363 #define ALTAB  TCR20_3
 364 #define ALTCD  TCR20_4
 365 #define HLTEN  TCR20_5
 366 #define HLTRN  TCR20_6
 367 #define PLEEN  TCR20_7
 368
 369 /* PSW (0xD0) */
 370 __sbit __at (0xD0) PSW_0;
 371 __sbit __at (0xD1) PSW_1;
 372 __sbit __at (0xD2) PSW_2;
 373 __sbit __at (0xD3) PSW_3;
 374 __sbit __at (0xD4) PSW_4;
 375 __sbit __at (0xD5) PSW_5;
 376 __sbit __at (0xD6) PSW_6;
 377 __sbit __at (0xD7) PSW_7;
 378 #define P   PSW_0
 379 #define F1  PSW_1
 380 #define OV  PSW_2
 381 #define RS0 PSW_3
 382 #define RS1 PSW_4
 383 #define F0  PSW_5
 384 #define AC  PSW_6
 385 #define CY  PSW_7
 386
 387 /* I2CON (0xD8) */
 388 __sbit __at (0xD8) I2CON_0;
 389 __sbit __at (0xD9) I2CON_1;
 390 __sbit __at (0xDA) I2CON_2;
 391 __sbit __at (0xDB) I2CON_3;
 392 __sbit __at (0xDC) I2CON_4;
 393 __sbit __at (0xDD) I2CON_5;
 394 __sbit __at (0xDE) I2CON_6;
 395 __sbit __at (0xDF) I2CON_7;
 396 #define CRSEL I2CON_0
 397 #define AA    I2CON_2
 398 #define SI    I2CON_3
 399 #define STO   I2CON_4
 400 #define STA   I2CON_5
 401 #define I2EN  I2CON_6
 402
 403 /* ACC (0xE0) */
 404 __sbit __at (0xE0) ACC_0;
 405 __sbit __at (0xE1) ACC_1;
 406 __sbit __at (0xE2) ACC_2;
 407 __sbit __at (0xE3) ACC_3;
 408 __sbit __at (0xE4) ACC_4;
 409 __sbit __at (0xE5) ACC_5;
 410 __sbit __at (0xE6) ACC_6;
 411 __sbit __at (0xE7) ACC_7;
 412
 413 /* IEN1 (0xE8) */
 414 __sbit __at (0xE8) IEN1_0;
 415 __sbit __at (0xE9) IEN1_1;
 416 __sbit __at (0xEA) IEN1_2;
 417 __sbit __at (0xEB) IEN1_3;
 418 __sbit __at (0xEC) IEN1_4;
 419 __sbit __at (0xED) IEN1_5;
 420 __sbit __at (0xEE) IEN1_6;
 421 __sbit __at (0xEF) IEN1_7;
 422 #define EI2C IEN1_0
 423 #define EKBI IEN1_1
 424 #define EC   IEN1_2
 425 #define ESPI IEN1_3
 426 #define ECCU IEN1_4
 427 #define EST  IEN1_6
 428 #define EIEE IEN1_7
 429
 430 /* B (0xF0) */
 431 __sbit __at (0xF0) B_0;
 432 __sbit __at (0xF1) B_1;
 433 __sbit __at (0xF2) B_2;
 434 __sbit __at (0xF3) B_3;
 435 __sbit __at (0xF4) B_4;
 436 __sbit __at (0xF5) B_5;
 437 __sbit __at (0xF6) B_6;
 438 __sbit __at (0xF7) B_7;
 439
 440 /* IP1 (0xF8) */
 441 __sbit __at (0xF8) IP1_0;
 442 __sbit __at (0xF9) IP1_1;
 443 __sbit __at (0xFA) IP1_2;
 444 __sbit __at (0xFB) IP1_3;
 445 __sbit __at (0xFC) IP1_4;
 446 __sbit __at (0xFD) IP1_5;
 447 __sbit __at (0xFE) IP1_6;
 448 __sbit __at (0xFF) IP1_7;
 449 #define PI2C  IP1_0
 450 #define PKBI  IP1_1
 451 #define PC    IP1_2
 452 #define PSPI  IP1_3
 453 #define PCCU  IP1_4
 454 #define PST   IP1_6
 455 #define PADEE IP1_7
 456
 457 #endif /* P89LPC938_H */