sdcc/device/include/mcs51/sab80515.h

   1 /*-------------------------------------------------------------------------
   2    sab80515.h - Register Declarations for SIEMENS/INFINEON SAB 80515 Processor
   3    based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
   4    KEIL C compatible definitions are included
   5
   6    Copyright (C) 2005, Bela Torok / bela.torok@kssg.ch
   7
   8    This library is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published by the
  10    Free Software Foundation; either version 2, or (at your option) any
  11    later version.
  12
  13    This library is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this library; see the file COPYING. If not, write to the
  20    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  21    MA 02110-1301, USA.
  22
  23    As a special exception, if you link this library with other files,
  24    some of which are compiled with SDCC, to produce an executable,
  25    this library does not by itself cause the resulting executable to
  26    be covered by the GNU General Public License. This exception does
  27    not however invalidate any other reasons why the executable file
  28    might be covered by the GNU General Public License.
  29 -------------------------------------------------------------------------*/
  30
  31 #ifndef SAB80515_H
  32 #define SAB80515_H
  33
  34 #include <compiler.h>
  35
  36 /* BYTE addressable registers */
  37 SFR(P0,         0x80);
  38 SFR(SP,         0x81);
  39 SFR(DPL,        0x82);
  40 SFR(DPH,        0x83);
  41 SFR(PCON,       0x87);
  42 SFR(TCON,       0x88);
  43 SFR(TMOD,       0x89);
  44 SFR(TL0,        0x8A);
  45 SFR(TL1,        0x8B);
  46 SFR(TH0,        0x8C);
  47 SFR(TH1,        0x8D);
  48 SFR(P1,         0x90);
  49 SFR(SCON,       0x98);
  50 SFR(SBUF,       0x99);
  51 SFR(P2,         0xA0);
  52 SFR(IE,         0xA8);
  53 SFR(IEN0,       0xA8); /* as called by Siemens */
  54 SFR(IP0,        0xA9); /* interrupt priority register - SAB80515 specific */
  55 SFR(P3,         0xB0);
  56 SFR(IEN1,       0xB8); /* interrupt enable register - SAB80515 specific */
  57 SFR(IP1,        0xB9); /* interrupt priority register as called by Siemens */
  58 SFR(IRCON,      0xC0); /* interrupt control register - SAB80515 specific */
  59 SFR(CCEN,       0xC1); /* compare/capture enable register */
  60 SFR(CCL1,       0xC2); /* compare/capture register 1, low byte */
  61 SFR(CCH1,       0xC3); /* compare/capture register 1, high byte */
  62 SFR(CCL2,       0xC4); /* compare/capture register 2, low byte */
  63 SFR(CCH2,       0xC5); /* compare/capture register 2, high byte */
  64 SFR(CCL3,       0xC6); /* compare/capture register 3, low byte */
  65 SFR(CCH3,       0xC7); /* compare/capture register 3, high byte */
  66 SFR(T2CON,      0xC8);
  67 SFR(CRCL,       0xCA); /* compare/reload/capture register, low byte */
  68 SFR(CRCH,       0xCB); /* compare/reload/capture register, high byte */
  69 SFR(TL2,        0xCC);
  70 SFR(TH2,        0xCD);
  71 SFR(PSW,        0xD0);
  72 SFR(ADCON,      0xD8); /* A/D-converter control register */
  73 SFR(ADDAT,      0xD9); /* A/D-converter data register */
  74 SFR(DAPR,       0xDA); /* D/A-converter program register */
  75 SFR(P6,         0xDB); /* Port 6 - SAB80515 specific */
  76 SFR(ACC,        0xE0);
  77 SFR(A,          0xE0);
  78 SFR(P4,         0xE8); /* Port 4 - SAB80515 specific */
  79 SFR(B,          0xF0);
  80 SFR(P5,         0xF8); /* Port 5 - SAB80515 specific */
  81
  82
  83 /* BIT addressable registers */
  84 /* P0 */
  85 SBIT(P0_0,              0x80,   0);
  86 SBIT(P0_1,              0x80,   1);
  87 SBIT(P0_2,              0x80,   2);
  88 SBIT(P0_3,              0x80,   3);
  89 SBIT(P0_4,              0x80,   4);
  90 SBIT(P0_5,              0x80,   5);
  91 SBIT(P0_6,              0x80,   6);
  92 SBIT(P0_7,              0x80,   7);
  93
  94 /* TCON */
  95 SBIT(IT0,               0x88,   0);
  96 SBIT(IE0,               0x88,   1);
  97 SBIT(IT1,               0x88,   2);
  98 SBIT(IE1,               0x88,   3);
  99 SBIT(TR0,               0x88,   4);
 100 SBIT(TF0,               0x88,   5);
 101 SBIT(TR1,               0x88,   6);
 102 SBIT(TF1,               0x88,   7);
 103
 104 /* P1 */
 105 SBIT(P1_0,              0x90,   0);
 106 SBIT(P1_1,              0x90,   1);
 107 SBIT(P1_2,              0x90,   2);
 108 SBIT(P1_3,              0x90,   3);
 109 SBIT(P1_4,              0x90,   4);
 110 SBIT(P1_5,              0x90,   5);
 111 SBIT(P1_6,              0x90,   6);
 112 SBIT(P1_7,              0x90,   7);
 113
 114 SBIT(INT3_CC0,  0x90,   0); /* P1 alternate functions - SAB80515 specific */
 115 SBIT(INT4_CC1,  0x90,   1);
 116 SBIT(INT5_CC2,  0x90,   2);
 117 SBIT(INT6_CC3,  0x90,   3);
 118 SBIT(INT2,              0x90,   4);
 119 SBIT(T2EX,              0x90,   5);
 120 SBIT(CLKOUT,    0x90,   6);
 121 SBIT(T2,                0x90,   7);
 122
 123 /* SCON */
 124 SBIT(RI,                0x98,   0);
 125 SBIT(TI,                0x98,   1);
 126 SBIT(RB8,               0x98,   2);
 127 SBIT(TB8,               0x98,   3);
 128 SBIT(REN,               0x98,   4);
 129 SBIT(SM2,               0x98,   5);
 130 SBIT(SM1,               0x98,   6);
 131 SBIT(SM0,               0x98,   7);
 132
 133 /* P2 */
 134 SBIT(P2_0,              0xA0,   0);
 135 SBIT(P2_1,              0xA0,   1);
 136 SBIT(P2_2,              0xA0,   2);
 137 SBIT(P2_3,              0xA0,   3);
 138 SBIT(P2_4,              0xA0,   4);
 139 SBIT(P2_5,              0xA0,   5);
 140 SBIT(P2_6,              0xA0,   6);
 141 SBIT(P2_7,              0xA0,   7);
 142
 143 /* IEN0 */
 144 SBIT(EX0,               0xA8,   0);
 145 SBIT(ET0,               0xA8,   1);
 146 SBIT(EX1,               0xA8,   2);
 147 SBIT(ET1,               0xA8,   3);
 148 SBIT(ES,                0xA8,   4);
 149 SBIT(ET2,               0xA8,   5);
 150 SBIT(WDT,               0xA8,   6); /* watchdog timer reset - SAB80515 specific */
 151 SBIT(EA,                0xA8,   7);
 152
 153 SBIT(EAL,               0xA8,   7); /* EA as called by Siemens */
 154
 155 /* P3 */
 156 SBIT(P3_0,              0xB0,   0);
 157 SBIT(P3_1,              0xB0,   1);
 158 SBIT(P3_2,              0xB0,   2);
 159 SBIT(P3_3,              0xB0,   3);
 160 SBIT(P3_4,              0xB0,   4);
 161 SBIT(P3_5,              0xB0,   5);
 162 SBIT(P3_6,              0xB0,   6);
 163 SBIT(P3_7,              0xB0,   7);
 164
 165 SBIT(RXD,               0xB0,   0);
 166 SBIT(TXD,               0xB0,   1);
 167 SBIT(INT0,              0xB0,   2);
 168 SBIT(INT1,              0xB0,   3);
 169 SBIT(T0,                0xB0,   4);
 170 SBIT(T1,                0xB0,   5);
 171 SBIT(WR,                0xB0,   6);
 172 SBIT(RD,                0xB0,   7);
 173
 174 /* IEN1 */
 175 SBIT(EADC,              0xB8,   0); /* A/D converter interrupt enable */
 176 SBIT(EX2,               0xB8,   1);
 177 SBIT(EX3,               0xB8,   2);
 178 SBIT(EX4,               0xB8,   3);
 179 SBIT(EX5,               0xB8,   4);
 180 SBIT(EX6,               0xB8,   5);
 181 SBIT(SWDT,              0xB8,   6); /* watchdog timer start/reset */
 182 SBIT(EXEN2,             0xB8,   7); /* timer2 external reload interrupt enable */
 183
 184 /* IRCON */
 185 SBIT(IADC,              0xC0,   0); /* A/D converter irq flag */
 186 SBIT(IEX2,              0xC0,   1); /* external interrupt edge detect flag */
 187 SBIT(IEX3,              0xC0,   2);
 188 SBIT(IEX4,              0xC0,   3);
 189 SBIT(IEX5,              0xC0,   4);
 190 SBIT(IEX6,              0xC0,   5);
 191 SBIT(TF2,               0xC0,   6); /* timer 2 owerflow flag  */
 192 SBIT(EXF2,              0xC0,   7); /* timer2 reload flag */
 193
 194 /* T2CON */
 195 SBIT(T2CON_0,   0xC8,   0);
 196 SBIT(T2CON_1,   0xC8,   1);
 197 SBIT(T2CON_2,   0xC8,   2);
 198 SBIT(T2CON_3,   0xC8,   3);
 199 SBIT(T2CON_4,   0xC8,   4);
 200 SBIT(T2CON_5,   0xC8,   5);
 201 SBIT(T2CON_6,   0xC8,   6);
 202 SBIT(T2CON_7,   0xC8,   7);
 203
 204 SBIT(T2I0,              0xC8,   0);
 205 SBIT(T2I1,              0xC8,   1);
 206 SBIT(T2CM,              0xC8,   2);
 207 SBIT(T2R0,              0xC8,   3);
 208 SBIT(T2R1,              0xC8,   4);
 209 SBIT(I2FR,              0xC8,   5);
 210 SBIT(I3FR,              0xC8,   6);
 211 SBIT(T2PS,              0xC8,   7);
 212
 213
 214 /* PSW */
 215 SBIT(P,                 0xD0,   0);
 216 SBIT(FL,                0xD0,   1);
 217 SBIT(OV,                0xD0,   2);
 218 SBIT(RS0,               0xD0,   3);
 219 SBIT(RS1,               0xD0,   4);
 220 SBIT(F0,                0xD0,   5);
 221 SBIT(AC,                0xD0,   6);
 222 SBIT(CY,                0xD0,   7);
 223
 224 SBIT(F1,                0xD0,   1);
 225
 226 /* ADCON */
 227 SBIT(MX0,               0xD8,   0);
 228 SBIT(MX1,               0xD8,   1);
 229 SBIT(MX2,               0xD8,   2);
 230 SBIT(ADM,               0xD8,   3);
 231 SBIT(BSY,               0xD8,   4);
 232
 233 SBIT(CLK,               0xD8,   6);
 234 SBIT(BD,                0xD8,   7);
 235
 236 /* A */
 237 SBIT(AREG_F0,   0xA0,   0);
 238 SBIT(AREG_F1,   0xA0,   1);
 239 SBIT(AREG_F2,   0xA0,   2);
 240 SBIT(AREG_F3,   0xA0,   3);
 241 SBIT(AREG_F4,   0xA0,   4);
 242 SBIT(AREG_F5,   0xA0,   5);
 243 SBIT(AREG_F6,   0xA0,   6);
 244 SBIT(AREG_F7,   0xA0,   7);
 245
 246 /* P4 */
 247 SBIT(P4_0,              0xE8,   0);
 248 SBIT(P4_1,              0xE8,   1);
 249 SBIT(P4_2,              0xE8,   2);
 250 SBIT(P4_3,              0xE8,   3);
 251 SBIT(P4_4,              0xE8,   4);
 252 SBIT(P4_5,              0xE8,   5);
 253 SBIT(P4_6,              0xE8,   6);
 254 SBIT(P4_7,              0xE8,   7);
 255
 256 /* B */
 257 SBIT(BREG_F0,   0xF0,   0);
 258 SBIT(BREG_F1,   0xF0,   1);
 259 SBIT(BREG_F2,   0xF0,   2);
 260 SBIT(BREG_F3,   0xF0,   3);
 261 SBIT(BREG_F4,   0xF0,   4);
 262 SBIT(BREG_F5,   0xF0,   5);
 263 SBIT(BREG_F6,   0xF0,   6);
 264 SBIT(BREG_F7,   0xF0,   7);
 265
 266 /* P5 */
 267 SBIT(P5_0,              0xF8,   0);
 268 SBIT(P5_1,              0xF8,   1);
 269 SBIT(P5_2,              0xF8,   2);
 270 SBIT(P5_3,              0xF8,   3);
 271 SBIT(P5_4,              0xF8,   4);
 272 SBIT(P5_5,              0xF8,   5);
 273 SBIT(P5_6,              0xF8,   6);
 274 SBIT(P5_7,              0xF8,   7);
 275
 276 /* BIT definitions for bits that are not directly accessible */
 277 /* PCON bits */
 278 #define IDL             0x01
 279 #define PD              0x02
 280 #define GF0             0x04
 281 #define GF1             0x08
 282 #define SMOD            0x80
 283
 284 #define IDL_            0x01
 285 #define PD_             0x02
 286 #define GF0_            0x04
 287 #define GF1_            0x08
 288 #define SMOD_           0x80
 289
 290 /* TMOD bits */
 291 #define M0_0            0x01
 292 #define M1_0            0x02
 293 #define C_T0            0x04
 294 #define GATE0           0x08
 295 #define M0_1            0x10
 296 #define M1_1            0x20
 297 #define C_T1            0x40
 298 #define GATE1           0x80
 299
 300 #define M0_0_           0x01
 301 #define M1_0_           0x02
 302 #define C_T0_           0x04
 303 #define GATE0_          0x08
 304 #define M0_1_           0x10
 305 #define M1_1_           0x20
 306 #define C_T1_           0x40
 307 #define GATE1_          0x80
 308
 309 #define T0_M0           0x01
 310 #define T0_M1           0x02
 311 #define T0_CT           0x04
 312 #define T0_GATE         0x08
 313 #define T1_M0           0x10
 314 #define T1_M1           0x20
 315 #define T1_CT           0x40
 316 #define T1_GATE         0x80
 317
 318 #define T0_M0_          0x01
 319 #define T0_M1_          0x02
 320 #define T0_CT_          0x04
 321 #define T0_GATE_        0x08
 322 #define T1_M0_          0x10
 323 #define T1_M1_          0x20
 324 #define T1_CT_          0x40
 325 #define T1_GATE_        0x80
 326
 327 #define T0_MASK         0x0F
 328 #define T1_MASK         0xF0
 329
 330 #define T0_MASK_        0x0F
 331 #define T1_MASK_        0xF0
 332
 333 /* T2MOD bits */
 334 #define DCEN            0x01
 335 #define T2OE            0x02
 336
 337 #define DCEN_           0x01
 338 #define T2OE_           0x02
 339
 340 /* WMCON bits */
 341 #define WMCON_WDTEN     0x01
 342 #define WMCON_WDTRST    0x02
 343 #define WMCON_DPS       0x04
 344 #define WMCON_EEMEN     0x08
 345 #define WMCON_EEMWE     0x10
 346 #define WMCON_PS0       0x20
 347 #define WMCON_PS1       0x40
 348 #define WMCON_PS2       0x80
 349
 350 /* SPCR-SPI bits */
 351 #define SPCR_SPR0       0x01
 352 #define SPCR_SPR1       0x02
 353 #define SPCR_CPHA       0x04
 354 #define SPCR_CPOL       0x08
 355 #define SPCR_MSTR       0x10
 356 #define SPCR_DORD       0x20
 357 #define SPCR_SPE        0x40
 358 #define SPCR_SPIE       0x80
 359
 360 /* SPSR-SPI bits */
 361 #define SPSR_WCOL       0x40
 362 #define SPSR_SPIF       0x80
 363
 364 /* SPDR-SPI bits */
 365 #define SPDR_SPD0       0x10
 366 #define SPDR_SPD1       0x20
 367 #define SPDR_SPD2       0x40
 368 #define SPDR_SPD3       0x80
 369 #define SPDR_SPD4       0x10
 370 #define SPDR_SPD5       0x20
 371 #define SPDR_SPD6       0x40
 372 #define SPDR_SPD7       0x80
 373
 374 /* Interrupt numbers: address = (number * 8) + 3 */
 375 #define IE0_VECTOR      0       /* 0x03 external interrupt 0 */
 376 #define TF0_VECTOR      1       /* 0x0b timer 0 */
 377 #define IE1_VECTOR      2       /* 0x13 external interrupt 1 */
 378 #define TF1_VECTOR      3       /* 0x1b timer 1 */
 379 #define SI0_VECTOR      4       /* 0x23 serial port 0 */
 380 #define TF2_VECTOR      5       /* 0x2B timer 2 */
 381 #define EX2_VECTOR      5       /* 0x2B external interrupt 2 */
 382
 383 #define IADC_VECTOR     8       /* 0x43 A/D converter interrupt */
 384 #define IEX2_VECTOR     9       /* 0x4B external interrupt 2 */
 385 #define IEX3_VECTOR    10       /* 0x53 external interrupt 3 */
 386 #define IEX4_VECTOR    11       /* 0x5B external interrupt 4 */
 387 #define IEX5_VECTOR    12       /* 0x63 external interrupt 5 */
 388 #define IEX6_VECTOR    13       /* 0x6B external interrupt 6 */
 389
 390 #endif
 391