sdcc/device/include/mcs51/stc12.h

   1 /*-------------------------------------------------------------------------
   2    stc12.h - Register Declarations for STC10/11/12 Series
   3    Based on 8051.h and compiler.h
   4
   5    Copyright (c) 2012, intron@intron.ac
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 /*
  31    Brief:
  32
  33        STC10/11/12 series are 8051-compatible MCU's. The "official" website
  34    is http://www.stcmcu.com/ (In Chinese Han only), and datasheets in Chinese
  35    Han and English can be downloaded there.
  36
  37    Reference:
  38
  39    1. The "official" C header file (written for another C51 compiler):
  40         http://www.stcmcu.com/datasheet/stc/STC-AD-PDF/STC_NEW_8051.H
  41    2. Datasheets for STC12(C/LE)5Axx(S2/AD) series:
  42       Chinese Han:
  43         http://www.stcmcu.com/datasheet/stc/STC-AD-PDF/STC12C5A60S2.pdf
  44       English:
  45         http://www.stcmcu.com/datasheet/stc/STC-AD-PDF/STC12C5A60S2-english.pdf
  46    3. Datasheets for STC12(C/LE)52xxAD series:
  47       Chinese Han:
  48         http://www.stcmcu.com/datasheet/stc/STC-AD-PDF/STC12C5201AD.pdf
  49       English:
  50         http://www.stcmcu.com/datasheet/stc/STC-AD-PDF/STC12C5201AD-english.pdf
  51    4. Datasheets for STC11/10 series:
  52       Chinese Han:
  53         http://www.stcmcu.com/datasheet/stc/STC-AD-PDF/STC11F-10Fxx.pdf
  54       English:
  55         http://www.stcmcu.com/datasheet/stc/STC-AD-PDF/STC11F-10Fxx-english.pdf
  56  */
  57
  58 #ifndef _STC12_H_
  59 #define _STC12_H_
  60
  61 #include <8051.h>
  62 #include <compiler.h>
  63
  64 #ifdef REG8051_H
  65 #undef REG8051_H
  66 #endif
  67
  68 /*
  69  * Auxiliary Register
  70  *   Bit Mapping: T0x12 T1x12 UART_M0x6 BRTR S2SMOD BRTx12 EXTRAM S1BRS
  71  *   Reset Value: 0000,0000
  72  */
  73 SFR(AUXR, 0x8E);
  74
  75 /*
  76  * Auxiliary Register 1
  77  *   Bit Mapping: - PCA_P4 SPI_P4 S2_P4 GF2 ADRJ - DPS
  78  *   Reset Value: x000,00x0
  79  */
  80 SFR(AUXR1, 0xA2);
  81
  82 /*
  83  * Control Register for Clock Output and Power Down Wake-up
  84  *   Bit Mapping: PCAWAKEUP RXD_PIN_IE T1_PIN_IE T0_PIN_IE
  85  *                LVD_WAKE BRTCLKO T1CLKO T0CLKO
  86  *                (Here "O" is the letter meaning "output", not the digit.)
  87  *   Reset Value: 0000,0000
  88  */
  89 SFR(WAKE_CLKO, 0x8F);
  90
  91 /*
  92  * Clock Devider Register
  93  *   Bit Mapping: - - - - - CLKS2 CLKS1 CLKS0
  94  *   Reset Value: xxxx,x000
  95  */
  96 SFR(CLK_DIV, 0x97);
  97
  98 /*
  99  * Stretch register
 100  *   Bit Mapping: - - ALES1 ALES0 - RWS2 RWS1 RWS0
 101  *   Reset Value: xx10,x011
 102  */
 103 SFR(BUS_SPEED, 0xA1);
 104
 105 /* Two extended bits in IE */
 106 SBIT(ELVD, 0xA8, 6); /* Enable Low Voltage Detection Interrupt */
 107 SBIT(EADC, 0xA8, 5); /* Enable ADC Interrupt */
 108
 109 /*
 110  * Auxiliary Interrupt Register
 111  *   Bit Mapping: - - - - - - ESPI ES2
 112  *   Reset Value: xxxx,xx00
 113  */
 114 SFR(IE2, 0xAF);
 115
 116 /* Three extended bits in IP */
 117 SBIT(PPCA, 0xB8, 7); /* Interrupt Priority for PCA */
 118 SBIT(PLVD, 0xB8, 6); /* Interrupt Priority for Low Voltage Detection */
 119 SBIT(PADC, 0xB8, 5); /* Interrupt Priority for ADC */
 120
 121 /*
 122  * Higher bits for Interrupt Priority
 123  *   Bit Mapping: PPCAH PLVDH PADCH PSH PT1H PX1H PT0H PX0H
 124  *   Reset Value: 0000,0000
 125  */
 126 SFR(IPH, 0xB7);
 127
 128 /*
 129  * The 2nd Interrupt Priority Register, Lower bits
 130  *   Bit Mapping: - - - - - - PSPI PS2
 131  *   Reset Value: xxxx,xx00
 132  */
 133 SFR(IP2, 0xB5);
 134
 135 /*
 136  * The 2nd Interrupt Priority Register, Higher bits
 137  *   Bit Mapping: - - - - - - PSPIH PS2H
 138  *   Reset Value: xxxx,xx00
 139  */
 140 SFR(IP2H, 0xB6);
 141
 142 /*
 143  * Two Extended GPIO Ports: P4 and P5
 144  * - For DIP-40 and QFN-40 packages, only higher 4 bits of P4 are available.
 145  * - For PLCC-44 and LQFP-44 packages, only all 8 bits of P4 are available.
 146  * - For LQFP-48 package, all 8 bits of P4 and lower 4 bits of P5 are
 147  *   available.
 148  */
 149 SFR(P4, 0xC0);
 150     SBIT(P4_0, 0xC0, 0);
 151     SBIT(P4_1, 0xC0, 1);
 152     SBIT(P4_2, 0xC0, 2);
 153     SBIT(P4_3, 0xC0, 3);
 154     SBIT(P4_4, 0xC0, 4);
 155     SBIT(P4_5, 0xC0, 5);
 156     SBIT(P4_6, 0xC0, 6);
 157     SBIT(P4_7, 0xC0, 7);
 158 SFR(P5, 0xC8); /* Only lower 4 bits */
 159     SBIT(P5_0, 0xC8, 0);
 160     SBIT(P5_1, 0xC8, 1);
 161     SBIT(P5_2, 0xC8, 2);
 162     SBIT(P5_3, 0xC8, 3);
 163
 164 /* Working Mode Registers for P0, P1, P2, P3, P4 and P5 */
 165 SFR(P0M0, 0x94);
 166 SFR(P0M1, 0x93);
 167 SFR(P1M0, 0x92);
 168 SFR(P1M1, 0x91);
 169 SFR(P2M0, 0x96);
 170 SFR(P2M1, 0x95);
 171 SFR(P3M0, 0xB2);
 172 SFR(P3M1, 0xB1);
 173 SFR(P4M0, 0xB4);
 174 SFR(P4M1, 0xB3);
 175 SFR(P4SW, 0xBB); /* - LVD_P4.6 ALE_P4.5 NA_P4.4 - - - -   Reset: x000,xxxx */
 176 SFR(P5M0, 0xCA);
 177 SFR(P5M1, 0xC9);
 178
 179 /* Slave Address Mask for Serial Communication */
 180 SFR(SADEN, 0xB9);
 181
 182 /* Slave Address for Serial Communication */
 183 SFR(SADDR, 0xA9);
 184
 185 /*
 186  * The Control Register for the 2nd Serial Communication Port
 187  *   Bit Mapping: S2SM0 S2SM1 S2SM2 S2REN S2TB8 S2RB8 S2TI S2RI
 188  *   Reset Value: 0000,0000
 189  */
 190 SFR(S2CON, 0x9A);
 191
 192 /* Data Buffer Register for the 2nd Serial Communication Port */
 193 SFR(S2BUF, 0x9B);
 194
 195 /*
 196  * Reload Value Register for the Specific Baud Rate Generator
 197  * (Independent from the 8051 Timer)
 198  */
 199 SFR(BRT, 0x9C);
 200
 201 /*
 202  * Watchdog Timer Control Register
 203  *   Bit Mapping: WDT_FLAG - EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0
 204  *   Reset Value: 0x00,0000
 205  */
 206 SFR(WDT_CONTR, 0xC1);
 207
 208 /*
 209  * PCA Control Register
 210  *   Bit Mapping: CF CR - - - - CCF1 CCF0
 211  *   Reset Value: 00xx,xx00
 212  */
 213 SFR(CCON, 0xD8);
 214     SBIT(CF, 0xD8, 7);
 215     SBIT(CR, 0xD8, 6);
 216     SBIT(CCF1, 0xD8, 1);
 217     SBIT(CCF0, 0xD8, 0);
 218
 219 /*
 220  * PCA Mode Register
 221  *   Bit Mapping: CIDL - - - CPS2 CPS1 CPS0 ECF
 222  *   Reset Value: 0xxx,x000
 223  */
 224 SFR(CMOD, 0xD9);
 225
 226 /* PCA Counter Registers */
 227 SFR(CL, 0xE9); /* Lower 8 bits */
 228 SFR(CH, 0xF9); /* Higher 8 bits */
 229
 230 /*
 231  * PCA Module 0 PWM Register
 232  *   Bit Mapping: - ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0
 233  *   Reset Value: x000,0000
 234  */
 235 SFR(CCAPM0, 0xDA);
 236
 237 /*
 238  * PCA Module 1 PWM Register
 239  *   Bit Mapping: - ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1
 240  *   Reset Value: x000,0000
 241  */
 242 SFR(CCAPM1, 0xDB);
 243
 244 /* PCA Module 0/1 Capture/Comparison Registers */
 245 SFR(CCAP0L, 0xEA);
 246 SFR(CCAP0H, 0xFA);
 247 SFR(CCAP1L, 0xEB);
 248 SFR(CCAP1H, 0xFB);
 249
 250 /*
 251  * PCA Module 0 PWM Auxiliary Register
 252  *   Bit Mapping: - - - - - - EPC0H EPC0L
 253  *   Reset Value: xxxx,xx00
 254  */
 255 SFR(PCA_PWM0, 0xF2);
 256
 257 /*
 258  * PCA Module 1 PWM Auxiliary Register
 259  *   Bit Mapping: - - - - - - EPC1H EPC1L
 260  *   Reset Value: xxxx,xx00
 261  */
 262 SFR(PCA_PWM1, 0xF3);
 263
 264 /* Switch P1 pins between ADC inputs and GPIO Port pins */
 265 SFR(P1ASF, 0x9D);
 266
 267 /*
 268  * ADC Control Register
 269  *   Bit Mapping: ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0
 270  *   Reset Value: 0000,0000
 271  */
 272 SFR(ADC_CONTR, 0xBC);
 273
 274 /* ADC Converting Result Registers */
 275 SFR(ADC_RES, 0xBD); /* Higher Bits */
 276 SFR(ADC_RESL, 0xBE); /* Lower Bits */
 277
 278 /*
 279  * SPI Control Register
 280  *   Bit Mapping: SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0
 281  *   Reset Value: 0000,0100
 282  */
 283 SFR(SPCTL, 0xCE);
 284
 285 /*
 286  * SPI Status Register
 287  *   Bit Mapping: SPIF WCOL - - - - - -
 288  *   Reset Value: 00xx,xxxx
 289  */
 290 SFR(SPSTAT, 0xCD);
 291
 292 /* SPI Data Register */
 293 SFR(SPDAT, 0xCF);
 294
 295 /* In-Application-Programming Data Register */
 296 SFR(IAP_DATA, 0xC2);
 297
 298 /* In-Application-Programming Address Registers */
 299 SFR(IAP_ADDRH, 0xC3); /* Higher 8 bits */
 300 SFR(IAP_ADDRL, 0xC4); /* Lower 8 bits */
 301
 302 /*
 303  * In-Application-Programming Address Registers
 304  *   Bit Mapping: - - - - - - MS1 MS0
 305  *   Reset Value: xxxx,xx00
 306  */
 307 SFR(IAP_CMD, 0xC5);
 308
 309 /* In-Application-Programming Trigger Registers */
 310 SFR(IAP_TRIG, 0xC6);
 311
 312 /*
 313  * In-Application-Programming Control Register
 314  *   Bit Mapping: IAPEN SWBS SWRST CFAIL - WT2 WT1 WT0
 315  *   Reset Value: 0000,x000
 316  */
 317 SFR(IAP_CONTR, 0xC7);
 318
 319 #endif /* _STC12_H_ */
 320