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Hackfix and re-enable strtoull and wcstoull, see bug #3798.
[sdcc.git] / sdcc / device / non-free / include / pic14 / pic12f609.h
blob1a164594dbe2d1137fa010af629751afff1bd95d
1 /*
2 * This declarations of the PIC12F609 MCU.
3 *
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
6 *
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:03 UTC.
8 *
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
12 *
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
21 *
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
23 */
24
25 #ifndef __PIC12F609_H__
26 #define __PIC12F609_H__
27
28 //==============================================================================
29 //
30 // Register Addresses
31 //
32 //==============================================================================
33
34 #ifndef NO_ADDR_DEFINES
35
36 #define INDF_ADDR 0x0000
37 #define TMR0_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR_ADDR 0x0004
41 #define GPIO_ADDR 0x0005
42 #define PORTA_ADDR 0x0005
43 #define PCLATH_ADDR 0x000A
44 #define INTCON_ADDR 0x000B
45 #define PIR1_ADDR 0x000C
46 #define TMR1_ADDR 0x000E
47 #define TMR1L_ADDR 0x000E
48 #define TMR1H_ADDR 0x000F
49 #define T1CON_ADDR 0x0010
50 #define VRCON_ADDR 0x0019
51 #define CMCON0_ADDR 0x001A
52 #define CMCON1_ADDR 0x001C
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISIO_ADDR 0x0085
56 #define PIE1_ADDR 0x008C
57 #define PCON_ADDR 0x008E
58 #define OSCTUNE_ADDR 0x0090
59 #define WPU_ADDR 0x0095
60 #define WPUA_ADDR 0x0095
61 #define IOC_ADDR 0x0096
62 #define IOCA_ADDR 0x0096
63 #define ANSEL_ADDR 0x009F
64
65 #endif // #ifndef NO_ADDR_DEFINES
66
67 //==============================================================================
68 //
69 // Register Definitions
70 //
71 //==============================================================================
72
73 extern __at(0x0000) __sfr INDF;
74 extern __at(0x0001) __sfr TMR0;
75 extern __at(0x0002) __sfr PCL;
76
77 //==============================================================================
78 // STATUS Bits
79
80 extern __at(0x0003) __sfr STATUS;
81
82 typedef union
83 {
84 struct
85 {
86 unsigned C : 1;
87 unsigned DC : 1;
88 unsigned Z : 1;
89 unsigned NOT_PD : 1;
90 unsigned NOT_TO : 1;
91 unsigned RP0 : 1;
92 unsigned RP1 : 1;
93 unsigned IRP : 1;
94 };
95
96 struct
97 {
98 unsigned : 5;
99 unsigned RP : 2;
100 unsigned : 1;
101 };
102 } __STATUSbits_t;
103
104 extern __at(0x0003) volatile __STATUSbits_t STATUSbits;
105
106 #define _C 0x01
107 #define _DC 0x02
108 #define _Z 0x04
109 #define _NOT_PD 0x08
110 #define _NOT_TO 0x10
111 #define _RP0 0x20
112 #define _RP1 0x40
113 #define _IRP 0x80
114
115 //==============================================================================
116
117 extern __at(0x0004) __sfr FSR;
118
119 //==============================================================================
120 // GPIO Bits
121
122 extern __at(0x0005) __sfr GPIO;
123
124 typedef union
125 {
126 struct
127 {
128 unsigned GP0 : 1;
129 unsigned GP1 : 1;
130 unsigned GP2 : 1;
131 unsigned GP3 : 1;
132 unsigned GP4 : 1;
133 unsigned GP5 : 1;
134 unsigned : 1;
135 unsigned : 1;
136 };
137
138 struct
139 {
140 unsigned GPIO0 : 1;
141 unsigned GPIO1 : 1;
142 unsigned GPIO2 : 1;
143 unsigned GPIO3 : 1;
144 unsigned GPIO4 : 1;
145 unsigned GPIO5 : 1;
146 unsigned : 1;
147 unsigned : 1;
148 };
149
150 struct
151 {
152 unsigned RA0 : 1;
153 unsigned RA1 : 1;
154 unsigned RA2 : 1;
155 unsigned RA3 : 1;
156 unsigned RA4 : 1;
157 unsigned RA5 : 1;
158 unsigned : 1;
159 unsigned : 1;
160 };
161
162 struct
163 {
164 unsigned GP : 6;
165 unsigned : 2;
166 };
167
168 struct
169 {
170 unsigned GPIO : 6;
171 unsigned : 2;
172 };
173
174 struct
175 {
176 unsigned RA : 6;
177 unsigned : 2;
178 };
179 } __GPIObits_t;
180
181 extern __at(0x0005) volatile __GPIObits_t GPIObits;
182
183 #define _GP0 0x01
184 #define _GPIO0 0x01
185 #define _RA0 0x01
186 #define _GP1 0x02
187 #define _GPIO1 0x02
188 #define _RA1 0x02
189 #define _GP2 0x04
190 #define _GPIO2 0x04
191 #define _RA2 0x04
192 #define _GP3 0x08
193 #define _GPIO3 0x08
194 #define _RA3 0x08
195 #define _GP4 0x10
196 #define _GPIO4 0x10
197 #define _RA4 0x10
198 #define _GP5 0x20
199 #define _GPIO5 0x20
200 #define _RA5 0x20
201
202 //==============================================================================
203
204
205 //==============================================================================
206 // PORTA Bits
207
208 extern __at(0x0005) __sfr PORTA;
209
210 typedef union
211 {
212 struct
213 {
214 unsigned GP0 : 1;
215 unsigned GP1 : 1;
216 unsigned GP2 : 1;
217 unsigned GP3 : 1;
218 unsigned GP4 : 1;
219 unsigned GP5 : 1;
220 unsigned : 1;
221 unsigned : 1;
222 };
223
224 struct
225 {
226 unsigned GPIO0 : 1;
227 unsigned GPIO1 : 1;
228 unsigned GPIO2 : 1;
229 unsigned GPIO3 : 1;
230 unsigned GPIO4 : 1;
231 unsigned GPIO5 : 1;
232 unsigned : 1;
233 unsigned : 1;
234 };
235
236 struct
237 {
238 unsigned RA0 : 1;
239 unsigned RA1 : 1;
240 unsigned RA2 : 1;
241 unsigned RA3 : 1;
242 unsigned RA4 : 1;
243 unsigned RA5 : 1;
244 unsigned : 1;
245 unsigned : 1;
246 };
247
248 struct
249 {
250 unsigned GP : 6;
251 unsigned : 2;
252 };
253
254 struct
255 {
256 unsigned GPIO : 6;
257 unsigned : 2;
258 };
259
260 struct
261 {
262 unsigned RA : 6;
263 unsigned : 2;
264 };
265 } __PORTAbits_t;
266
267 extern __at(0x0005) volatile __PORTAbits_t PORTAbits;
268
269 #define _PORTA_GP0 0x01
270 #define _PORTA_GPIO0 0x01
271 #define _PORTA_RA0 0x01
272 #define _PORTA_GP1 0x02
273 #define _PORTA_GPIO1 0x02
274 #define _PORTA_RA1 0x02
275 #define _PORTA_GP2 0x04
276 #define _PORTA_GPIO2 0x04
277 #define _PORTA_RA2 0x04
278 #define _PORTA_GP3 0x08
279 #define _PORTA_GPIO3 0x08
280 #define _PORTA_RA3 0x08
281 #define _PORTA_GP4 0x10
282 #define _PORTA_GPIO4 0x10
283 #define _PORTA_RA4 0x10
284 #define _PORTA_GP5 0x20
285 #define _PORTA_GPIO5 0x20
286 #define _PORTA_RA5 0x20
287
288 //==============================================================================
289
290 extern __at(0x000A) __sfr PCLATH;
291
292 //==============================================================================
293 // INTCON Bits
294
295 extern __at(0x000B) __sfr INTCON;
296
297 typedef union
298 {
299 struct
300 {
301 unsigned GPIF : 1;
302 unsigned INTF : 1;
303 unsigned TMR0IF : 1;
304 unsigned GPIE : 1;
305 unsigned INTE : 1;
306 unsigned TMR0IE : 1;
307 unsigned PEIE : 1;
308 unsigned GIE : 1;
309 };
310
311 struct
312 {
313 unsigned : 1;
314 unsigned : 1;
315 unsigned T0IF : 1;
316 unsigned : 1;
317 unsigned : 1;
318 unsigned T0IE : 1;
319 unsigned : 1;
320 unsigned : 1;
321 };
322 } __INTCONbits_t;
323
324 extern __at(0x000B) volatile __INTCONbits_t INTCONbits;
325
326 #define _GPIF 0x01
327 #define _INTF 0x02
328 #define _TMR0IF 0x04
329 #define _T0IF 0x04
330 #define _GPIE 0x08
331 #define _INTE 0x10
332 #define _TMR0IE 0x20
333 #define _T0IE 0x20
334 #define _PEIE 0x40
335 #define _GIE 0x80
336
337 //==============================================================================
338
339
340 //==============================================================================
341 // PIR1 Bits
342
343 extern __at(0x000C) __sfr PIR1;
344
345 typedef union
346 {
347 struct
348 {
349 unsigned TMR1IF : 1;
350 unsigned : 1;
351 unsigned : 1;
352 unsigned C1IF : 1;
353 unsigned : 1;
354 unsigned : 1;
355 unsigned : 1;
356 unsigned : 1;
357 };
358
359 struct
360 {
361 unsigned T1IF : 1;
362 unsigned : 1;
363 unsigned : 1;
364 unsigned CMIF : 1;
365 unsigned : 1;
366 unsigned : 1;
367 unsigned : 1;
368 unsigned : 1;
369 };
370 } __PIR1bits_t;
371
372 extern __at(0x000C) volatile __PIR1bits_t PIR1bits;
373
374 #define _TMR1IF 0x01
375 #define _T1IF 0x01
376 #define _C1IF 0x08
377 #define _CMIF 0x08
378
379 //==============================================================================
380
381 extern __at(0x000E) __sfr TMR1;
382 extern __at(0x000E) __sfr TMR1L;
383 extern __at(0x000F) __sfr TMR1H;
384
385 //==============================================================================
386 // T1CON Bits
387
388 extern __at(0x0010) __sfr T1CON;
389
390 typedef union
391 {
392 struct
393 {
394 unsigned TMR1ON : 1;
395 unsigned TMR1CS : 1;
396 unsigned NOT_T1SYNC : 1;
397 unsigned T1OSCEN : 1;
398 unsigned T1CKPS0 : 1;
399 unsigned T1CKPS1 : 1;
400 unsigned TMR1GE : 1;
401 unsigned T1GINV : 1;
402 };
403
404 struct
405 {
406 unsigned : 4;
407 unsigned T1CKPS : 2;
408 unsigned : 2;
409 };
410 } __T1CONbits_t;
411
412 extern __at(0x0010) volatile __T1CONbits_t T1CONbits;
413
414 #define _TMR1ON 0x01
415 #define _TMR1CS 0x02
416 #define _NOT_T1SYNC 0x04
417 #define _T1OSCEN 0x08
418 #define _T1CKPS0 0x10
419 #define _T1CKPS1 0x20
420 #define _TMR1GE 0x40
421 #define _T1GINV 0x80
422
423 //==============================================================================
424
425
426 //==============================================================================
427 // VRCON Bits
428
429 extern __at(0x0019) __sfr VRCON;
430
431 typedef union
432 {
433 struct
434 {
435 unsigned VR0 : 1;
436 unsigned VR1 : 1;
437 unsigned VR2 : 1;
438 unsigned VR3 : 1;
439 unsigned FBREN : 1;
440 unsigned VRR : 1;
441 unsigned : 1;
442 unsigned C1VREN : 1;
443 };
444
445 struct
446 {
447 unsigned : 1;
448 unsigned : 1;
449 unsigned : 1;
450 unsigned : 1;
451 unsigned FVREN : 1;
452 unsigned : 1;
453 unsigned : 1;
454 unsigned CMVREN : 1;
455 };
456
457 struct
458 {
459 unsigned : 1;
460 unsigned : 1;
461 unsigned : 1;
462 unsigned : 1;
463 unsigned VP6EN : 1;
464 unsigned : 1;
465 unsigned : 1;
466 unsigned : 1;
467 };
468
469 struct
470 {
471 unsigned VR : 4;
472 unsigned : 4;
473 };
474 } __VRCONbits_t;
475
476 extern __at(0x0019) volatile __VRCONbits_t VRCONbits;
477
478 #define _VR0 0x01
479 #define _VR1 0x02
480 #define _VR2 0x04
481 #define _VR3 0x08
482 #define _FBREN 0x10
483 #define _FVREN 0x10
484 #define _VP6EN 0x10
485 #define _VRR 0x20
486 #define _C1VREN 0x80
487 #define _CMVREN 0x80
488
489 //==============================================================================
490
491
492 //==============================================================================
493 // CMCON0 Bits
494
495 extern __at(0x001A) __sfr CMCON0;
496
497 typedef union
498 {
499 struct
500 {
501 unsigned C1CH : 1;
502 unsigned : 1;
503 unsigned C1R : 1;
504 unsigned : 1;
505 unsigned C1POL : 1;
506 unsigned C1OE : 1;
507 unsigned C1OUT : 1;
508 unsigned C1ON : 1;
509 };
510
511 struct
512 {
513 unsigned C1CH0 : 1;
514 unsigned : 1;
515 unsigned CMR : 1;
516 unsigned : 1;
517 unsigned CMPOL : 1;
518 unsigned CMOE : 1;
519 unsigned COUT : 1;
520 unsigned CMON : 1;
521 };
522
523 struct
524 {
525 unsigned CMCH : 1;
526 unsigned : 1;
527 unsigned : 1;
528 unsigned : 1;
529 unsigned : 1;
530 unsigned : 1;
531 unsigned : 1;
532 unsigned : 1;
533 };
534 } __CMCON0bits_t;
535
536 extern __at(0x001A) volatile __CMCON0bits_t CMCON0bits;
537
538 #define _C1CH 0x01
539 #define _C1CH0 0x01
540 #define _CMCH 0x01
541 #define _C1R 0x04
542 #define _CMR 0x04
543 #define _C1POL 0x10
544 #define _CMPOL 0x10
545 #define _C1OE 0x20
546 #define _CMOE 0x20
547 #define _C1OUT 0x40
548 #define _COUT 0x40
549 #define _C1ON 0x80
550 #define _CMON 0x80
551
552 //==============================================================================
553
554
555 //==============================================================================
556 // CMCON1 Bits
557
558 extern __at(0x001C) __sfr CMCON1;
559
560 typedef union
561 {
562 struct
563 {
564 unsigned C1SYNC : 1;
565 unsigned T1GSS : 1;
566 unsigned : 1;
567 unsigned C1HYS : 1;
568 unsigned T1ACS : 1;
569 unsigned : 1;
570 unsigned : 1;
571 unsigned : 1;
572 };
573
574 struct
575 {
576 unsigned CMSYNC : 1;
577 unsigned : 1;
578 unsigned : 1;
579 unsigned CMHYS : 1;
580 unsigned : 1;
581 unsigned : 1;
582 unsigned : 1;
583 unsigned : 1;
584 };
585 } __CMCON1bits_t;
586
587 extern __at(0x001C) volatile __CMCON1bits_t CMCON1bits;
588
589 #define _C1SYNC 0x01
590 #define _CMSYNC 0x01
591 #define _T1GSS 0x02
592 #define _C1HYS 0x08
593 #define _CMHYS 0x08
594 #define _T1ACS 0x10
595
596 //==============================================================================
597
598
599 //==============================================================================
600 // OPTION_REG Bits
601
602 extern __at(0x0081) __sfr OPTION_REG;
603
604 typedef union
605 {
606 struct
607 {
608 unsigned PS0 : 1;
609 unsigned PS1 : 1;
610 unsigned PS2 : 1;
611 unsigned PSA : 1;
612 unsigned T0SE : 1;
613 unsigned T0CS : 1;
614 unsigned INTEDG : 1;
615 unsigned NOT_GPPU : 1;
616 };
617
618 struct
619 {
620 unsigned PS : 3;
621 unsigned : 5;
622 };
623 } __OPTION_REGbits_t;
624
625 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits;
626
627 #define _PS0 0x01
628 #define _PS1 0x02
629 #define _PS2 0x04
630 #define _PSA 0x08
631 #define _T0SE 0x10
632 #define _T0CS 0x20
633 #define _INTEDG 0x40
634 #define _NOT_GPPU 0x80
635
636 //==============================================================================
637
638
639 //==============================================================================
640 // TRISA Bits
641
642 extern __at(0x0085) __sfr TRISA;
643
644 typedef union
645 {
646 struct
647 {
648 unsigned TRISIO0 : 1;
649 unsigned TRISIO1 : 1;
650 unsigned TRISIO2 : 1;
651 unsigned TRISIO3 : 1;
652 unsigned TRISIO4 : 1;
653 unsigned TRISIO5 : 1;
654 unsigned : 1;
655 unsigned : 1;
656 };
657
658 struct
659 {
660 unsigned TRISA0 : 1;
661 unsigned TRISA1 : 1;
662 unsigned TRISA2 : 1;
663 unsigned TRISA3 : 1;
664 unsigned TRISA4 : 1;
665 unsigned TRISA5 : 1;
666 unsigned : 1;
667 unsigned : 1;
668 };
669
670 struct
671 {
672 unsigned TRISIO : 6;
673 unsigned : 2;
674 };
675
676 struct
677 {
678 unsigned TRISA : 6;
679 unsigned : 2;
680 };
681 } __TRISAbits_t;
682
683 extern __at(0x0085) volatile __TRISAbits_t TRISAbits;
684
685 #define _TRISIO0 0x01
686 #define _TRISA0 0x01
687 #define _TRISIO1 0x02
688 #define _TRISA1 0x02
689 #define _TRISIO2 0x04
690 #define _TRISA2 0x04
691 #define _TRISIO3 0x08
692 #define _TRISA3 0x08
693 #define _TRISIO4 0x10
694 #define _TRISA4 0x10
695 #define _TRISIO5 0x20
696 #define _TRISA5 0x20
697
698 //==============================================================================
699
700
701 //==============================================================================
702 // TRISIO Bits
703
704 extern __at(0x0085) __sfr TRISIO;
705
706 typedef union
707 {
708 struct
709 {
710 unsigned TRISIO0 : 1;
711 unsigned TRISIO1 : 1;
712 unsigned TRISIO2 : 1;
713 unsigned TRISIO3 : 1;
714 unsigned TRISIO4 : 1;
715 unsigned TRISIO5 : 1;
716 unsigned : 1;
717 unsigned : 1;
718 };
719
720 struct
721 {
722 unsigned TRISA0 : 1;
723 unsigned TRISA1 : 1;
724 unsigned TRISA2 : 1;
725 unsigned TRISA3 : 1;
726 unsigned TRISA4 : 1;
727 unsigned TRISA5 : 1;
728 unsigned : 1;
729 unsigned : 1;
730 };
731
732 struct
733 {
734 unsigned TRISIO : 6;
735 unsigned : 2;
736 };
737
738 struct
739 {
740 unsigned TRISA : 6;
741 unsigned : 2;
742 };
743 } __TRISIObits_t;
744
745 extern __at(0x0085) volatile __TRISIObits_t TRISIObits;
746
747 #define _TRISIO_TRISIO0 0x01
748 #define _TRISIO_TRISA0 0x01
749 #define _TRISIO_TRISIO1 0x02
750 #define _TRISIO_TRISA1 0x02
751 #define _TRISIO_TRISIO2 0x04
752 #define _TRISIO_TRISA2 0x04
753 #define _TRISIO_TRISIO3 0x08
754 #define _TRISIO_TRISA3 0x08
755 #define _TRISIO_TRISIO4 0x10
756 #define _TRISIO_TRISA4 0x10
757 #define _TRISIO_TRISIO5 0x20
758 #define _TRISIO_TRISA5 0x20
759
760 //==============================================================================
761
762
763 //==============================================================================
764 // PIE1 Bits
765
766 extern __at(0x008C) __sfr PIE1;
767
768 typedef union
769 {
770 struct
771 {
772 unsigned TMR1IE : 1;
773 unsigned : 1;
774 unsigned : 1;
775 unsigned C1IE : 1;
776 unsigned : 1;
777 unsigned : 1;
778 unsigned : 1;
779 unsigned : 1;
780 };
781
782 struct
783 {
784 unsigned T1IE : 1;
785 unsigned : 1;
786 unsigned : 1;
787 unsigned CMIE : 1;
788 unsigned : 1;
789 unsigned : 1;
790 unsigned : 1;
791 unsigned : 1;
792 };
793 } __PIE1bits_t;
794
795 extern __at(0x008C) volatile __PIE1bits_t PIE1bits;
796
797 #define _TMR1IE 0x01
798 #define _T1IE 0x01
799 #define _C1IE 0x08
800 #define _CMIE 0x08
801
802 //==============================================================================
803
804
805 //==============================================================================
806 // PCON Bits
807
808 extern __at(0x008E) __sfr PCON;
809
810 typedef union
811 {
812 struct
813 {
814 unsigned NOT_BOR : 1;
815 unsigned NOT_POR : 1;
816 unsigned : 1;
817 unsigned : 1;
818 unsigned : 1;
819 unsigned : 1;
820 unsigned : 1;
821 unsigned : 1;
822 };
823
824 struct
825 {
826 unsigned NOT_BOD : 1;
827 unsigned : 1;
828 unsigned : 1;
829 unsigned : 1;
830 unsigned : 1;
831 unsigned : 1;
832 unsigned : 1;
833 unsigned : 1;
834 };
835 } __PCONbits_t;
836
837 extern __at(0x008E) volatile __PCONbits_t PCONbits;
838
839 #define _NOT_BOR 0x01
840 #define _NOT_BOD 0x01
841 #define _NOT_POR 0x02
842
843 //==============================================================================
844
845
846 //==============================================================================
847 // OSCTUNE Bits
848
849 extern __at(0x0090) __sfr OSCTUNE;
850
851 typedef union
852 {
853 struct
854 {
855 unsigned TUN0 : 1;
856 unsigned TUN1 : 1;
857 unsigned TUN2 : 1;
858 unsigned TUN3 : 1;
859 unsigned TUN4 : 1;
860 unsigned : 1;
861 unsigned : 1;
862 unsigned : 1;
863 };
864
865 struct
866 {
867 unsigned TUN : 5;
868 unsigned : 3;
869 };
870 } __OSCTUNEbits_t;
871
872 extern __at(0x0090) volatile __OSCTUNEbits_t OSCTUNEbits;
873
874 #define _TUN0 0x01
875 #define _TUN1 0x02
876 #define _TUN2 0x04
877 #define _TUN3 0x08
878 #define _TUN4 0x10
879
880 //==============================================================================
881
882
883 //==============================================================================
884 // WPU Bits
885
886 extern __at(0x0095) __sfr WPU;
887
888 typedef union
889 {
890 struct
891 {
892 unsigned WPUA0 : 1;
893 unsigned WPUA1 : 1;
894 unsigned WPUA2 : 1;
895 unsigned : 1;
896 unsigned WPUA4 : 1;
897 unsigned WPUA5 : 1;
898 unsigned : 1;
899 unsigned : 1;
900 };
901
902 struct
903 {
904 unsigned WPU0 : 1;
905 unsigned WPU1 : 1;
906 unsigned WPU2 : 1;
907 unsigned : 1;
908 unsigned WPU4 : 1;
909 unsigned WPU5 : 1;
910 unsigned : 1;
911 unsigned : 1;
912 };
913 } __WPUbits_t;
914
915 extern __at(0x0095) volatile __WPUbits_t WPUbits;
916
917 #define _WPUA0 0x01
918 #define _WPU0 0x01
919 #define _WPUA1 0x02
920 #define _WPU1 0x02
921 #define _WPUA2 0x04
922 #define _WPU2 0x04
923 #define _WPUA4 0x10
924 #define _WPU4 0x10
925 #define _WPUA5 0x20
926 #define _WPU5 0x20
927
928 //==============================================================================
929
930
931 //==============================================================================
932 // WPUA Bits
933
934 extern __at(0x0095) __sfr WPUA;
935
936 typedef union
937 {
938 struct
939 {
940 unsigned WPUA0 : 1;
941 unsigned WPUA1 : 1;
942 unsigned WPUA2 : 1;
943 unsigned : 1;
944 unsigned WPUA4 : 1;
945 unsigned WPUA5 : 1;
946 unsigned : 1;
947 unsigned : 1;
948 };
949
950 struct
951 {
952 unsigned WPU0 : 1;
953 unsigned WPU1 : 1;
954 unsigned WPU2 : 1;
955 unsigned : 1;
956 unsigned WPU4 : 1;
957 unsigned WPU5 : 1;
958 unsigned : 1;
959 unsigned : 1;
960 };
961 } __WPUAbits_t;
962
963 extern __at(0x0095) volatile __WPUAbits_t WPUAbits;
964
965 #define _WPUA_WPUA0 0x01
966 #define _WPUA_WPU0 0x01
967 #define _WPUA_WPUA1 0x02
968 #define _WPUA_WPU1 0x02
969 #define _WPUA_WPUA2 0x04
970 #define _WPUA_WPU2 0x04
971 #define _WPUA_WPUA4 0x10
972 #define _WPUA_WPU4 0x10
973 #define _WPUA_WPUA5 0x20
974 #define _WPUA_WPU5 0x20
975
976 //==============================================================================
977
978
979 //==============================================================================
980 // IOC Bits
981
982 extern __at(0x0096) __sfr IOC;
983
984 typedef union
985 {
986 struct
987 {
988 unsigned IOC0 : 1;
989 unsigned IOC1 : 1;
990 unsigned IOC2 : 1;
991 unsigned IOC3 : 1;
992 unsigned IOC4 : 1;
993 unsigned IOC5 : 1;
994 unsigned : 1;
995 unsigned : 1;
996 };
997
998 struct
999 {
1000 unsigned IOCA0 : 1;
1001 unsigned IOCA1 : 1;
1002 unsigned IOCA2 : 1;
1003 unsigned IOCA3 : 1;
1004 unsigned IOCA4 : 1;
1005 unsigned IOCA5 : 1;
1006 unsigned : 1;
1007 unsigned : 1;
1008 };
1009
1010 struct
1011 {
1012 unsigned IOCA : 6;
1013 unsigned : 2;
1014 };
1015
1016 struct
1017 {
1018 unsigned IOC : 6;
1019 unsigned : 2;
1020 };
1021 } __IOCbits_t;
1022
1023 extern __at(0x0096) volatile __IOCbits_t IOCbits;
1024
1025 #define _IOC0 0x01
1026 #define _IOCA0 0x01
1027 #define _IOC1 0x02
1028 #define _IOCA1 0x02
1029 #define _IOC2 0x04
1030 #define _IOCA2 0x04
1031 #define _IOC3 0x08
1032 #define _IOCA3 0x08
1033 #define _IOC4 0x10
1034 #define _IOCA4 0x10
1035 #define _IOC5 0x20
1036 #define _IOCA5 0x20
1037
1038 //==============================================================================
1039
1040
1041 //==============================================================================
1042 // IOCA Bits
1043
1044 extern __at(0x0096) __sfr IOCA;
1045
1046 typedef union
1047 {
1048 struct
1049 {
1050 unsigned IOC0 : 1;
1051 unsigned IOC1 : 1;
1052 unsigned IOC2 : 1;
1053 unsigned IOC3 : 1;
1054 unsigned IOC4 : 1;
1055 unsigned IOC5 : 1;
1056 unsigned : 1;
1057 unsigned : 1;
1058 };
1059
1060 struct
1061 {
1062 unsigned IOCA0 : 1;
1063 unsigned IOCA1 : 1;
1064 unsigned IOCA2 : 1;
1065 unsigned IOCA3 : 1;
1066 unsigned IOCA4 : 1;
1067 unsigned IOCA5 : 1;
1068 unsigned : 1;
1069 unsigned : 1;
1070 };
1071
1072 struct
1073 {
1074 unsigned IOCA : 6;
1075 unsigned : 2;
1076 };
1077
1078 struct
1079 {
1080 unsigned IOC : 6;
1081 unsigned : 2;
1082 };
1083 } __IOCAbits_t;
1084
1085 extern __at(0x0096) volatile __IOCAbits_t IOCAbits;
1086
1087 #define _IOCA_IOC0 0x01
1088 #define _IOCA_IOCA0 0x01
1089 #define _IOCA_IOC1 0x02
1090 #define _IOCA_IOCA1 0x02
1091 #define _IOCA_IOC2 0x04
1092 #define _IOCA_IOCA2 0x04
1093 #define _IOCA_IOC3 0x08
1094 #define _IOCA_IOCA3 0x08
1095 #define _IOCA_IOC4 0x10
1096 #define _IOCA_IOCA4 0x10
1097 #define _IOCA_IOC5 0x20
1098 #define _IOCA_IOCA5 0x20
1099
1100 //==============================================================================
1101
1102
1103 //==============================================================================
1104 // ANSEL Bits
1105
1106 extern __at(0x009F) __sfr ANSEL;
1107
1108 typedef struct
1109 {
1110 unsigned ANS0 : 1;
1111 unsigned ANS1 : 1;
1112 unsigned : 1;
1113 unsigned ANS3 : 1;
1114 unsigned : 1;
1115 unsigned : 1;
1116 unsigned : 1;
1117 unsigned : 1;
1118 } __ANSELbits_t;
1119
1120 extern __at(0x009F) volatile __ANSELbits_t ANSELbits;
1121
1122 #define _ANS0 0x01
1123 #define _ANS1 0x02
1124 #define _ANS3 0x08
1125
1126 //==============================================================================
1127
1128
1129 //==============================================================================
1130 //
1131 // Configuration Bits
1132 //
1133 //==============================================================================
1134
1135 #define _CONFIG 0x2007
1136
1137 //----------------------------- CONFIG Options -------------------------------
1138
1139 #define _FOSC_LP 0x3FF8 // LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
1140 #define _LP_OSC 0x3FF8 // LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
1141 #define _FOSC_XT 0x3FF9 // XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
1142 #define _XT_OSC 0x3FF9 // XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
1143 #define _FOSC_HS 0x3FFA // HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
1144 #define _HS_OSC 0x3FFA // HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
1145 #define _FOSC_EC 0x3FFB // EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN.
1146 #define _EC_OSC 0x3FFB // EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN.
1147 #define _FOSC_INTOSCIO 0x3FFC // INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN.
1148 #define _INTRC_OSC_NOCLKOUT 0x3FFC // INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN.
1149 #define _INTOSCIO 0x3FFC // INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN.
1150 #define _FOSC_INTOSCCLK 0x3FFD // INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN.
1151 #define _INTRC_OSC_CLKOUT 0x3FFD // INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN.
1152 #define _INTOSC 0x3FFD // INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN.
1153 #define _FOSC_EXTRCIO 0x3FFE // RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN.
1154 #define _EXTRC_OSC_NOCLKOUT 0x3FFE // RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN.
1155 #define _EXTRCIO 0x3FFE // RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN.
1156 #define _FOSC_EXTRCCLK 0x3FFF // RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN.
1157 #define _EXTRC_OSC_CLKOUT 0x3FFF // RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN.
1158 #define _EXTRC 0x3FFF // RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN.
1159 #define _WDTE_OFF 0x3FF7 // WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
1160 #define _WDT_OFF 0x3FF7 // WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
1161 #define _WDTE_ON 0x3FFF // WDT enabled.
1162 #define _WDT_ON 0x3FFF // WDT enabled.
1163 #define _PWRTE_ON 0x3FEF // PWRT enabled.
1164 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
1165 #define _MCLRE_OFF 0x3FDF // MCLR pin function is digital input, MCLR internally tied to VDD.
1166 #define _MCLRE_ON 0x3FFF // MCLR pin function is MCLR.
1167 #define _CP_ON 0x3FBF // Program memory code protection is enabled.
1168 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
1169 #define _IOSCFS_4MHZ 0x3F7F // 4 MHz.
1170 #define _IOSCFS4 0x3F7F // 4 MHz.
1171 #define _IOSCFS_8MHZ 0x3FFF // 8 MHz.
1172 #define _IOSCFS8 0x3FFF // 8 MHz.
1173 #define _BOREN_OFF 0x3CFF // BOR disabled.
1174 #define _BOR_OFF 0x3CFF // BOR disabled.
1175 #define _BOD_OFF 0x3CFF // BOR disabled.
1176 #define _BOREN_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1177 #define _BOR_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1178 #define _BOD_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1179 #define _BOREN_ON 0x3FFF // BOR enabled.
1180 #define _BOR_ON 0x3FFF // BOR enabled.
1181 #define _BOD_ON 0x3FFF // BOR enabled.
1182
1183 //==============================================================================
1184
1185 #define _DEVID1 0x2006
1186
1187 #define _IDLOC0 0x2000
1188 #define _IDLOC1 0x2001
1189 #define _IDLOC2 0x2002
1190 #define _IDLOC3 0x2003
1191
1192 //==============================================================================
1193
1194 #ifndef NO_BIT_DEFINES
1195
1196 #define ANS0 ANSELbits.ANS0 // bit 0
1197 #define ANS1 ANSELbits.ANS1 // bit 1
1198 #define ANS3 ANSELbits.ANS3 // bit 3
1199
1200 #define C1CH CMCON0bits.C1CH // bit 0, shadows bit in CMCON0bits
1201 #define C1CH0 CMCON0bits.C1CH0 // bit 0, shadows bit in CMCON0bits
1202 #define CMCH CMCON0bits.CMCH // bit 0, shadows bit in CMCON0bits
1203 #define C1R CMCON0bits.C1R // bit 2, shadows bit in CMCON0bits
1204 #define CMR CMCON0bits.CMR // bit 2, shadows bit in CMCON0bits
1205 #define C1POL CMCON0bits.C1POL // bit 4, shadows bit in CMCON0bits
1206 #define CMPOL CMCON0bits.CMPOL // bit 4, shadows bit in CMCON0bits
1207 #define C1OE CMCON0bits.C1OE // bit 5, shadows bit in CMCON0bits
1208 #define CMOE CMCON0bits.CMOE // bit 5, shadows bit in CMCON0bits
1209 #define C1OUT CMCON0bits.C1OUT // bit 6, shadows bit in CMCON0bits
1210 #define COUT CMCON0bits.COUT // bit 6, shadows bit in CMCON0bits
1211 #define C1ON CMCON0bits.C1ON // bit 7, shadows bit in CMCON0bits
1212 #define CMON CMCON0bits.CMON // bit 7, shadows bit in CMCON0bits
1213
1214 #define C1SYNC CMCON1bits.C1SYNC // bit 0, shadows bit in CMCON1bits
1215 #define CMSYNC CMCON1bits.CMSYNC // bit 0, shadows bit in CMCON1bits
1216 #define T1GSS CMCON1bits.T1GSS // bit 1
1217 #define C1HYS CMCON1bits.C1HYS // bit 3, shadows bit in CMCON1bits
1218 #define CMHYS CMCON1bits.CMHYS // bit 3, shadows bit in CMCON1bits
1219 #define T1ACS CMCON1bits.T1ACS // bit 4
1220
1221 #define GP0 GPIObits.GP0 // bit 0, shadows bit in GPIObits
1222 #define GPIO0 GPIObits.GPIO0 // bit 0, shadows bit in GPIObits
1223 #define RA0 GPIObits.RA0 // bit 0, shadows bit in GPIObits
1224 #define GP1 GPIObits.GP1 // bit 1, shadows bit in GPIObits
1225 #define GPIO1 GPIObits.GPIO1 // bit 1, shadows bit in GPIObits
1226 #define RA1 GPIObits.RA1 // bit 1, shadows bit in GPIObits
1227 #define GP2 GPIObits.GP2 // bit 2, shadows bit in GPIObits
1228 #define GPIO2 GPIObits.GPIO2 // bit 2, shadows bit in GPIObits
1229 #define RA2 GPIObits.RA2 // bit 2, shadows bit in GPIObits
1230 #define GP3 GPIObits.GP3 // bit 3, shadows bit in GPIObits
1231 #define GPIO3 GPIObits.GPIO3 // bit 3, shadows bit in GPIObits
1232 #define RA3 GPIObits.RA3 // bit 3, shadows bit in GPIObits
1233 #define GP4 GPIObits.GP4 // bit 4, shadows bit in GPIObits
1234 #define GPIO4 GPIObits.GPIO4 // bit 4, shadows bit in GPIObits
1235 #define RA4 GPIObits.RA4 // bit 4, shadows bit in GPIObits
1236 #define GP5 GPIObits.GP5 // bit 5, shadows bit in GPIObits
1237 #define GPIO5 GPIObits.GPIO5 // bit 5, shadows bit in GPIObits
1238 #define RA5 GPIObits.RA5 // bit 5, shadows bit in GPIObits
1239
1240 #define GPIF INTCONbits.GPIF // bit 0
1241 #define INTF INTCONbits.INTF // bit 1
1242 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
1243 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
1244 #define GPIE INTCONbits.GPIE // bit 3
1245 #define INTE INTCONbits.INTE // bit 4
1246 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
1247 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
1248 #define PEIE INTCONbits.PEIE // bit 6
1249 #define GIE INTCONbits.GIE // bit 7
1250
1251 #define IOC0 IOCbits.IOC0 // bit 0, shadows bit in IOCbits
1252 #define IOCA0 IOCbits.IOCA0 // bit 0, shadows bit in IOCbits
1253 #define IOC1 IOCbits.IOC1 // bit 1, shadows bit in IOCbits
1254 #define IOCA1 IOCbits.IOCA1 // bit 1, shadows bit in IOCbits
1255 #define IOC2 IOCbits.IOC2 // bit 2, shadows bit in IOCbits
1256 #define IOCA2 IOCbits.IOCA2 // bit 2, shadows bit in IOCbits
1257 #define IOC3 IOCbits.IOC3 // bit 3, shadows bit in IOCbits
1258 #define IOCA3 IOCbits.IOCA3 // bit 3, shadows bit in IOCbits
1259 #define IOC4 IOCbits.IOC4 // bit 4, shadows bit in IOCbits
1260 #define IOCA4 IOCbits.IOCA4 // bit 4, shadows bit in IOCbits
1261 #define IOC5 IOCbits.IOC5 // bit 5, shadows bit in IOCbits
1262 #define IOCA5 IOCbits.IOCA5 // bit 5, shadows bit in IOCbits
1263
1264 #define PS0 OPTION_REGbits.PS0 // bit 0
1265 #define PS1 OPTION_REGbits.PS1 // bit 1
1266 #define PS2 OPTION_REGbits.PS2 // bit 2
1267 #define PSA OPTION_REGbits.PSA // bit 3
1268 #define T0SE OPTION_REGbits.T0SE // bit 4
1269 #define T0CS OPTION_REGbits.T0CS // bit 5
1270 #define INTEDG OPTION_REGbits.INTEDG // bit 6
1271 #define NOT_GPPU OPTION_REGbits.NOT_GPPU // bit 7
1272
1273 #define TUN0 OSCTUNEbits.TUN0 // bit 0
1274 #define TUN1 OSCTUNEbits.TUN1 // bit 1
1275 #define TUN2 OSCTUNEbits.TUN2 // bit 2
1276 #define TUN3 OSCTUNEbits.TUN3 // bit 3
1277 #define TUN4 OSCTUNEbits.TUN4 // bit 4
1278
1279 #define NOT_BOR PCONbits.NOT_BOR // bit 0, shadows bit in PCONbits
1280 #define NOT_BOD PCONbits.NOT_BOD // bit 0, shadows bit in PCONbits
1281 #define NOT_POR PCONbits.NOT_POR // bit 1
1282
1283 #define TMR1IE PIE1bits.TMR1IE // bit 0, shadows bit in PIE1bits
1284 #define T1IE PIE1bits.T1IE // bit 0, shadows bit in PIE1bits
1285 #define C1IE PIE1bits.C1IE // bit 3, shadows bit in PIE1bits
1286 #define CMIE PIE1bits.CMIE // bit 3, shadows bit in PIE1bits
1287
1288 #define TMR1IF PIR1bits.TMR1IF // bit 0, shadows bit in PIR1bits
1289 #define T1IF PIR1bits.T1IF // bit 0, shadows bit in PIR1bits
1290 #define C1IF PIR1bits.C1IF // bit 3, shadows bit in PIR1bits
1291 #define CMIF PIR1bits.CMIF // bit 3, shadows bit in PIR1bits
1292
1293 #define C STATUSbits.C // bit 0
1294 #define DC STATUSbits.DC // bit 1
1295 #define Z STATUSbits.Z // bit 2
1296 #define NOT_PD STATUSbits.NOT_PD // bit 3
1297 #define NOT_TO STATUSbits.NOT_TO // bit 4
1298 #define RP0 STATUSbits.RP0 // bit 5
1299 #define RP1 STATUSbits.RP1 // bit 6
1300 #define IRP STATUSbits.IRP // bit 7
1301
1302 #define TMR1ON T1CONbits.TMR1ON // bit 0
1303 #define TMR1CS T1CONbits.TMR1CS // bit 1
1304 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
1305 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
1306 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
1307 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
1308 #define TMR1GE T1CONbits.TMR1GE // bit 6
1309 #define T1GINV T1CONbits.T1GINV // bit 7
1310
1311 #define TRISIO0 TRISAbits.TRISIO0 // bit 0, shadows bit in TRISAbits
1312 #define TRISA0 TRISAbits.TRISA0 // bit 0, shadows bit in TRISAbits
1313 #define TRISIO1 TRISAbits.TRISIO1 // bit 1, shadows bit in TRISAbits
1314 #define TRISA1 TRISAbits.TRISA1 // bit 1, shadows bit in TRISAbits
1315 #define TRISIO2 TRISAbits.TRISIO2 // bit 2, shadows bit in TRISAbits
1316 #define TRISA2 TRISAbits.TRISA2 // bit 2, shadows bit in TRISAbits
1317 #define TRISIO3 TRISAbits.TRISIO3 // bit 3, shadows bit in TRISAbits
1318 #define TRISA3 TRISAbits.TRISA3 // bit 3, shadows bit in TRISAbits
1319 #define TRISIO4 TRISAbits.TRISIO4 // bit 4, shadows bit in TRISAbits
1320 #define TRISA4 TRISAbits.TRISA4 // bit 4, shadows bit in TRISAbits
1321 #define TRISIO5 TRISAbits.TRISIO5 // bit 5, shadows bit in TRISAbits
1322 #define TRISA5 TRISAbits.TRISA5 // bit 5, shadows bit in TRISAbits
1323
1324 #define VR0 VRCONbits.VR0 // bit 0
1325 #define VR1 VRCONbits.VR1 // bit 1
1326 #define VR2 VRCONbits.VR2 // bit 2
1327 #define VR3 VRCONbits.VR3 // bit 3
1328 #define FBREN VRCONbits.FBREN // bit 4, shadows bit in VRCONbits
1329 #define FVREN VRCONbits.FVREN // bit 4, shadows bit in VRCONbits
1330 #define VP6EN VRCONbits.VP6EN // bit 4, shadows bit in VRCONbits
1331 #define VRR VRCONbits.VRR // bit 5
1332 #define C1VREN VRCONbits.C1VREN // bit 7, shadows bit in VRCONbits
1333 #define CMVREN VRCONbits.CMVREN // bit 7, shadows bit in VRCONbits
1334
1335 #define WPUA0 WPUbits.WPUA0 // bit 0, shadows bit in WPUbits
1336 #define WPU0 WPUbits.WPU0 // bit 0, shadows bit in WPUbits
1337 #define WPUA1 WPUbits.WPUA1 // bit 1, shadows bit in WPUbits
1338 #define WPU1 WPUbits.WPU1 // bit 1, shadows bit in WPUbits
1339 #define WPUA2 WPUbits.WPUA2 // bit 2, shadows bit in WPUbits
1340 #define WPU2 WPUbits.WPU2 // bit 2, shadows bit in WPUbits
1341 #define WPUA4 WPUbits.WPUA4 // bit 4, shadows bit in WPUbits
1342 #define WPU4 WPUbits.WPU4 // bit 4, shadows bit in WPUbits
1343 #define WPUA5 WPUbits.WPUA5 // bit 5, shadows bit in WPUbits
1344 #define WPU5 WPUbits.WPU5 // bit 5, shadows bit in WPUbits
1345
1346 #endif // #ifndef NO_BIT_DEFINES
1347
1348 #endif // #ifndef __PIC12F609_H__
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