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Hackfix and re-enable strtoull and wcstoull, see bug #3798.
[sdcc.git] / sdcc / device / non-free / include / pic14 / pic12f629.h
blob44d95b8c4e5e514b889fbfa7325ff21b120180d1
1 /*
2 * This declarations of the PIC12F629 MCU.
3 *
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
6 *
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:04 UTC.
8 *
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
12 *
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
21 *
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
23 */
24
25 #ifndef __PIC12F629_H__
26 #define __PIC12F629_H__
27
28 //==============================================================================
29 //
30 // Register Addresses
31 //
32 //==============================================================================
33
34 #ifndef NO_ADDR_DEFINES
35
36 #define INDF_ADDR 0x0000
37 #define TMR0_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR_ADDR 0x0004
41 #define GPIO_ADDR 0x0005
42 #define PCLATH_ADDR 0x000A
43 #define INTCON_ADDR 0x000B
44 #define PIR1_ADDR 0x000C
45 #define TMR1_ADDR 0x000E
46 #define TMR1L_ADDR 0x000E
47 #define TMR1H_ADDR 0x000F
48 #define T1CON_ADDR 0x0010
49 #define CMCON_ADDR 0x0019
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISIO_ADDR 0x0085
52 #define PIE1_ADDR 0x008C
53 #define PCON_ADDR 0x008E
54 #define OSCCAL_ADDR 0x0090
55 #define WPU_ADDR 0x0095
56 #define IOC_ADDR 0x0096
57 #define IOCB_ADDR 0x0096
58 #define VRCON_ADDR 0x0099
59 #define EEDAT_ADDR 0x009A
60 #define EEDATA_ADDR 0x009A
61 #define EEADR_ADDR 0x009B
62 #define EECON1_ADDR 0x009C
63 #define EECON2_ADDR 0x009D
64
65 #endif // #ifndef NO_ADDR_DEFINES
66
67 //==============================================================================
68 //
69 // Register Definitions
70 //
71 //==============================================================================
72
73 extern __at(0x0000) __sfr INDF;
74 extern __at(0x0001) __sfr TMR0;
75 extern __at(0x0002) __sfr PCL;
76
77 //==============================================================================
78 // STATUS Bits
79
80 extern __at(0x0003) __sfr STATUS;
81
82 typedef union
83 {
84 struct
85 {
86 unsigned C : 1;
87 unsigned DC : 1;
88 unsigned Z : 1;
89 unsigned NOT_PD : 1;
90 unsigned NOT_TO : 1;
91 unsigned RP0 : 1;
92 unsigned RP1 : 1;
93 unsigned IRP : 1;
94 };
95
96 struct
97 {
98 unsigned : 5;
99 unsigned RP : 2;
100 unsigned : 1;
101 };
102 } __STATUSbits_t;
103
104 extern __at(0x0003) volatile __STATUSbits_t STATUSbits;
105
106 #define _C 0x01
107 #define _DC 0x02
108 #define _Z 0x04
109 #define _NOT_PD 0x08
110 #define _NOT_TO 0x10
111 #define _RP0 0x20
112 #define _RP1 0x40
113 #define _IRP 0x80
114
115 //==============================================================================
116
117 extern __at(0x0004) __sfr FSR;
118
119 //==============================================================================
120 // GPIO Bits
121
122 extern __at(0x0005) __sfr GPIO;
123
124 typedef union
125 {
126 struct
127 {
128 unsigned GP0 : 1;
129 unsigned GP1 : 1;
130 unsigned GP2 : 1;
131 unsigned GP3 : 1;
132 unsigned GP4 : 1;
133 unsigned GP5 : 1;
134 unsigned : 1;
135 unsigned : 1;
136 };
137
138 struct
139 {
140 unsigned GPIO0 : 1;
141 unsigned GPIO1 : 1;
142 unsigned GPIO2 : 1;
143 unsigned GPIO3 : 1;
144 unsigned GPIO4 : 1;
145 unsigned GPIO5 : 1;
146 unsigned : 1;
147 unsigned : 1;
148 };
149
150 struct
151 {
152 unsigned GPIO : 6;
153 unsigned : 2;
154 };
155
156 struct
157 {
158 unsigned GP : 6;
159 unsigned : 2;
160 };
161 } __GPIObits_t;
162
163 extern __at(0x0005) volatile __GPIObits_t GPIObits;
164
165 #define _GP0 0x01
166 #define _GPIO0 0x01
167 #define _GP1 0x02
168 #define _GPIO1 0x02
169 #define _GP2 0x04
170 #define _GPIO2 0x04
171 #define _GP3 0x08
172 #define _GPIO3 0x08
173 #define _GP4 0x10
174 #define _GPIO4 0x10
175 #define _GP5 0x20
176 #define _GPIO5 0x20
177
178 //==============================================================================
179
180 extern __at(0x000A) __sfr PCLATH;
181
182 //==============================================================================
183 // INTCON Bits
184
185 extern __at(0x000B) __sfr INTCON;
186
187 typedef union
188 {
189 struct
190 {
191 unsigned GPIF : 1;
192 unsigned INTF : 1;
193 unsigned T0IF : 1;
194 unsigned GPIE : 1;
195 unsigned INTE : 1;
196 unsigned T0IE : 1;
197 unsigned PEIE : 1;
198 unsigned GIE : 1;
199 };
200
201 struct
202 {
203 unsigned : 1;
204 unsigned : 1;
205 unsigned TMR0IF : 1;
206 unsigned : 1;
207 unsigned : 1;
208 unsigned TMR0IE : 1;
209 unsigned : 1;
210 unsigned : 1;
211 };
212 } __INTCONbits_t;
213
214 extern __at(0x000B) volatile __INTCONbits_t INTCONbits;
215
216 #define _GPIF 0x01
217 #define _INTF 0x02
218 #define _T0IF 0x04
219 #define _TMR0IF 0x04
220 #define _GPIE 0x08
221 #define _INTE 0x10
222 #define _T0IE 0x20
223 #define _TMR0IE 0x20
224 #define _PEIE 0x40
225 #define _GIE 0x80
226
227 //==============================================================================
228
229
230 //==============================================================================
231 // PIR1 Bits
232
233 extern __at(0x000C) __sfr PIR1;
234
235 typedef union
236 {
237 struct
238 {
239 unsigned TMR1IF : 1;
240 unsigned : 1;
241 unsigned : 1;
242 unsigned CMIF : 1;
243 unsigned : 1;
244 unsigned : 1;
245 unsigned : 1;
246 unsigned EEIF : 1;
247 };
248
249 struct
250 {
251 unsigned T1IF : 1;
252 unsigned : 1;
253 unsigned : 1;
254 unsigned : 1;
255 unsigned : 1;
256 unsigned : 1;
257 unsigned : 1;
258 unsigned : 1;
259 };
260 } __PIR1bits_t;
261
262 extern __at(0x000C) volatile __PIR1bits_t PIR1bits;
263
264 #define _TMR1IF 0x01
265 #define _T1IF 0x01
266 #define _CMIF 0x08
267 #define _EEIF 0x80
268
269 //==============================================================================
270
271 extern __at(0x000E) __sfr TMR1;
272 extern __at(0x000E) __sfr TMR1L;
273 extern __at(0x000F) __sfr TMR1H;
274
275 //==============================================================================
276 // T1CON Bits
277
278 extern __at(0x0010) __sfr T1CON;
279
280 typedef union
281 {
282 struct
283 {
284 unsigned TMR1ON : 1;
285 unsigned TMR1CS : 1;
286 unsigned NOT_T1SYNC : 1;
287 unsigned T1OSCEN : 1;
288 unsigned T1CKPS0 : 1;
289 unsigned T1CKPS1 : 1;
290 unsigned TMR1GE : 1;
291 unsigned : 1;
292 };
293
294 struct
295 {
296 unsigned : 4;
297 unsigned T1CKPS : 2;
298 unsigned : 2;
299 };
300 } __T1CONbits_t;
301
302 extern __at(0x0010) volatile __T1CONbits_t T1CONbits;
303
304 #define _TMR1ON 0x01
305 #define _TMR1CS 0x02
306 #define _NOT_T1SYNC 0x04
307 #define _T1OSCEN 0x08
308 #define _T1CKPS0 0x10
309 #define _T1CKPS1 0x20
310 #define _TMR1GE 0x40
311
312 //==============================================================================
313
314
315 //==============================================================================
316 // CMCON Bits
317
318 extern __at(0x0019) __sfr CMCON;
319
320 typedef union
321 {
322 struct
323 {
324 unsigned CM0 : 1;
325 unsigned CM1 : 1;
326 unsigned CM2 : 1;
327 unsigned CIS : 1;
328 unsigned CINV : 1;
329 unsigned : 1;
330 unsigned COUT : 1;
331 unsigned : 1;
332 };
333
334 struct
335 {
336 unsigned CM : 3;
337 unsigned : 5;
338 };
339 } __CMCONbits_t;
340
341 extern __at(0x0019) volatile __CMCONbits_t CMCONbits;
342
343 #define _CM0 0x01
344 #define _CM1 0x02
345 #define _CM2 0x04
346 #define _CIS 0x08
347 #define _CINV 0x10
348 #define _COUT 0x40
349
350 //==============================================================================
351
352
353 //==============================================================================
354 // OPTION_REG Bits
355
356 extern __at(0x0081) __sfr OPTION_REG;
357
358 typedef union
359 {
360 struct
361 {
362 unsigned PS0 : 1;
363 unsigned PS1 : 1;
364 unsigned PS2 : 1;
365 unsigned PSA : 1;
366 unsigned T0SE : 1;
367 unsigned T0CS : 1;
368 unsigned INTEDG : 1;
369 unsigned NOT_GPPU : 1;
370 };
371
372 struct
373 {
374 unsigned PS : 3;
375 unsigned : 5;
376 };
377 } __OPTION_REGbits_t;
378
379 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits;
380
381 #define _PS0 0x01
382 #define _PS1 0x02
383 #define _PS2 0x04
384 #define _PSA 0x08
385 #define _T0SE 0x10
386 #define _T0CS 0x20
387 #define _INTEDG 0x40
388 #define _NOT_GPPU 0x80
389
390 //==============================================================================
391
392
393 //==============================================================================
394 // TRISIO Bits
395
396 extern __at(0x0085) __sfr TRISIO;
397
398 typedef union
399 {
400 struct
401 {
402 unsigned TRISIO0 : 1;
403 unsigned TRISIO1 : 1;
404 unsigned TRISIO2 : 1;
405 unsigned TRISIO3 : 1;
406 unsigned TRISIO4 : 1;
407 unsigned TRISIO5 : 1;
408 unsigned : 1;
409 unsigned : 1;
410 };
411
412 struct
413 {
414 unsigned TRISIO : 6;
415 unsigned : 2;
416 };
417 } __TRISIObits_t;
418
419 extern __at(0x0085) volatile __TRISIObits_t TRISIObits;
420
421 #define _TRISIO0 0x01
422 #define _TRISIO1 0x02
423 #define _TRISIO2 0x04
424 #define _TRISIO3 0x08
425 #define _TRISIO4 0x10
426 #define _TRISIO5 0x20
427
428 //==============================================================================
429
430
431 //==============================================================================
432 // PIE1 Bits
433
434 extern __at(0x008C) __sfr PIE1;
435
436 typedef union
437 {
438 struct
439 {
440 unsigned TMR1IE : 1;
441 unsigned : 1;
442 unsigned : 1;
443 unsigned CMIE : 1;
444 unsigned : 1;
445 unsigned : 1;
446 unsigned : 1;
447 unsigned EEIE : 1;
448 };
449
450 struct
451 {
452 unsigned T1IE : 1;
453 unsigned : 1;
454 unsigned : 1;
455 unsigned : 1;
456 unsigned : 1;
457 unsigned : 1;
458 unsigned : 1;
459 unsigned : 1;
460 };
461 } __PIE1bits_t;
462
463 extern __at(0x008C) volatile __PIE1bits_t PIE1bits;
464
465 #define _TMR1IE 0x01
466 #define _T1IE 0x01
467 #define _CMIE 0x08
468 #define _EEIE 0x80
469
470 //==============================================================================
471
472
473 //==============================================================================
474 // PCON Bits
475
476 extern __at(0x008E) __sfr PCON;
477
478 typedef union
479 {
480 struct
481 {
482 unsigned NOT_BOR : 1;
483 unsigned NOT_POR : 1;
484 unsigned : 1;
485 unsigned : 1;
486 unsigned : 1;
487 unsigned : 1;
488 unsigned : 1;
489 unsigned : 1;
490 };
491
492 struct
493 {
494 unsigned NOT_BOD : 1;
495 unsigned : 1;
496 unsigned : 1;
497 unsigned : 1;
498 unsigned : 1;
499 unsigned : 1;
500 unsigned : 1;
501 unsigned : 1;
502 };
503 } __PCONbits_t;
504
505 extern __at(0x008E) volatile __PCONbits_t PCONbits;
506
507 #define _NOT_BOR 0x01
508 #define _NOT_BOD 0x01
509 #define _NOT_POR 0x02
510
511 //==============================================================================
512
513
514 //==============================================================================
515 // OSCCAL Bits
516
517 extern __at(0x0090) __sfr OSCCAL;
518
519 typedef union
520 {
521 struct
522 {
523 unsigned : 1;
524 unsigned : 1;
525 unsigned CAL0 : 1;
526 unsigned CAL1 : 1;
527 unsigned CAL2 : 1;
528 unsigned CAL3 : 1;
529 unsigned CAL4 : 1;
530 unsigned CAL5 : 1;
531 };
532
533 struct
534 {
535 unsigned : 2;
536 unsigned CAL : 6;
537 };
538 } __OSCCALbits_t;
539
540 extern __at(0x0090) volatile __OSCCALbits_t OSCCALbits;
541
542 #define _CAL0 0x04
543 #define _CAL1 0x08
544 #define _CAL2 0x10
545 #define _CAL3 0x20
546 #define _CAL4 0x40
547 #define _CAL5 0x80
548
549 //==============================================================================
550
551
552 //==============================================================================
553 // WPU Bits
554
555 extern __at(0x0095) __sfr WPU;
556
557 typedef struct
558 {
559 unsigned WPU0 : 1;
560 unsigned WPU1 : 1;
561 unsigned WPU2 : 1;
562 unsigned : 1;
563 unsigned WPU4 : 1;
564 unsigned WPU5 : 1;
565 unsigned : 1;
566 unsigned : 1;
567 } __WPUbits_t;
568
569 extern __at(0x0095) volatile __WPUbits_t WPUbits;
570
571 #define _WPU0 0x01
572 #define _WPU1 0x02
573 #define _WPU2 0x04
574 #define _WPU4 0x10
575 #define _WPU5 0x20
576
577 //==============================================================================
578
579
580 //==============================================================================
581 // IOC Bits
582
583 extern __at(0x0096) __sfr IOC;
584
585 typedef union
586 {
587 struct
588 {
589 unsigned IOC0 : 1;
590 unsigned IOC1 : 1;
591 unsigned IOC2 : 1;
592 unsigned IOC3 : 1;
593 unsigned IOC4 : 1;
594 unsigned IOC5 : 1;
595 unsigned : 1;
596 unsigned : 1;
597 };
598
599 struct
600 {
601 unsigned IOCB0 : 1;
602 unsigned IOCB1 : 1;
603 unsigned IOCB2 : 1;
604 unsigned IOCB3 : 1;
605 unsigned IOCB4 : 1;
606 unsigned IOCB5 : 1;
607 unsigned : 1;
608 unsigned : 1;
609 };
610
611 struct
612 {
613 unsigned IOC : 6;
614 unsigned : 2;
615 };
616
617 struct
618 {
619 unsigned IOCB : 6;
620 unsigned : 2;
621 };
622 } __IOCbits_t;
623
624 extern __at(0x0096) volatile __IOCbits_t IOCbits;
625
626 #define _IOC0 0x01
627 #define _IOCB0 0x01
628 #define _IOC1 0x02
629 #define _IOCB1 0x02
630 #define _IOC2 0x04
631 #define _IOCB2 0x04
632 #define _IOC3 0x08
633 #define _IOCB3 0x08
634 #define _IOC4 0x10
635 #define _IOCB4 0x10
636 #define _IOC5 0x20
637 #define _IOCB5 0x20
638
639 //==============================================================================
640
641
642 //==============================================================================
643 // IOCB Bits
644
645 extern __at(0x0096) __sfr IOCB;
646
647 typedef union
648 {
649 struct
650 {
651 unsigned IOC0 : 1;
652 unsigned IOC1 : 1;
653 unsigned IOC2 : 1;
654 unsigned IOC3 : 1;
655 unsigned IOC4 : 1;
656 unsigned IOC5 : 1;
657 unsigned : 1;
658 unsigned : 1;
659 };
660
661 struct
662 {
663 unsigned IOCB0 : 1;
664 unsigned IOCB1 : 1;
665 unsigned IOCB2 : 1;
666 unsigned IOCB3 : 1;
667 unsigned IOCB4 : 1;
668 unsigned IOCB5 : 1;
669 unsigned : 1;
670 unsigned : 1;
671 };
672
673 struct
674 {
675 unsigned IOC : 6;
676 unsigned : 2;
677 };
678
679 struct
680 {
681 unsigned IOCB : 6;
682 unsigned : 2;
683 };
684 } __IOCBbits_t;
685
686 extern __at(0x0096) volatile __IOCBbits_t IOCBbits;
687
688 #define _IOCB_IOC0 0x01
689 #define _IOCB_IOCB0 0x01
690 #define _IOCB_IOC1 0x02
691 #define _IOCB_IOCB1 0x02
692 #define _IOCB_IOC2 0x04
693 #define _IOCB_IOCB2 0x04
694 #define _IOCB_IOC3 0x08
695 #define _IOCB_IOCB3 0x08
696 #define _IOCB_IOC4 0x10
697 #define _IOCB_IOCB4 0x10
698 #define _IOCB_IOC5 0x20
699 #define _IOCB_IOCB5 0x20
700
701 //==============================================================================
702
703
704 //==============================================================================
705 // VRCON Bits
706
707 extern __at(0x0099) __sfr VRCON;
708
709 typedef union
710 {
711 struct
712 {
713 unsigned VR0 : 1;
714 unsigned VR1 : 1;
715 unsigned VR2 : 1;
716 unsigned VR3 : 1;
717 unsigned : 1;
718 unsigned VRR : 1;
719 unsigned : 1;
720 unsigned VREN : 1;
721 };
722
723 struct
724 {
725 unsigned VR : 4;
726 unsigned : 4;
727 };
728 } __VRCONbits_t;
729
730 extern __at(0x0099) volatile __VRCONbits_t VRCONbits;
731
732 #define _VR0 0x01
733 #define _VR1 0x02
734 #define _VR2 0x04
735 #define _VR3 0x08
736 #define _VRR 0x20
737 #define _VREN 0x80
738
739 //==============================================================================
740
741 extern __at(0x009A) __sfr EEDAT;
742 extern __at(0x009A) __sfr EEDATA;
743 extern __at(0x009B) __sfr EEADR;
744
745 //==============================================================================
746 // EECON1 Bits
747
748 extern __at(0x009C) __sfr EECON1;
749
750 typedef struct
751 {
752 unsigned RD : 1;
753 unsigned WR : 1;
754 unsigned WREN : 1;
755 unsigned WRERR : 1;
756 unsigned : 1;
757 unsigned : 1;
758 unsigned : 1;
759 unsigned : 1;
760 } __EECON1bits_t;
761
762 extern __at(0x009C) volatile __EECON1bits_t EECON1bits;
763
764 #define _RD 0x01
765 #define _WR 0x02
766 #define _WREN 0x04
767 #define _WRERR 0x08
768
769 //==============================================================================
770
771 extern __at(0x009D) __sfr EECON2;
772
773 //==============================================================================
774 //
775 // Configuration Bits
776 //
777 //==============================================================================
778
779 #define _CONFIG 0x2007
780
781 //----------------------------- CONFIG Options -------------------------------
782
783 #define _FOSC_LP 0x3FF8 // LP oscillator: Low power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
784 #define _LP_OSC 0x3FF8 // LP oscillator: Low power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
785 #define _FOSC_XT 0x3FF9 // XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
786 #define _XT_OSC 0x3FF9 // XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
787 #define _FOSC_HS 0x3FFA // HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
788 #define _HS_OSC 0x3FFA // HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN.
789 #define _FOSC_EC 0x3FFB // EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN.
790 #define _EC_OSC 0x3FFB // EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN.
791 #define _FOSC_INTRCIO 0x3FFC // INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN.
792 #define _INTRC_OSC_NOCLKOUT 0x3FFC // INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN.
793 #define _FOSC_INTRCCLK 0x3FFD // INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN.
794 #define _INTRC_OSC_CLKOUT 0x3FFD // INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN.
795 #define _FOSC_EXTRCIO 0x3FFE // RC oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN.
796 #define _EXTRC_OSC_NOCLKOUT 0x3FFE // RC oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN.
797 #define _FOSC_EXTRCCLK 0x3FFF // RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN.
798 #define _EXTRC_OSC_CLKOUT 0x3FFF // RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN.
799 #define _WDTE_OFF 0x3FF7 // WDT disabled.
800 #define _WDT_OFF 0x3FF7 // WDT disabled.
801 #define _WDTE_ON 0x3FFF // WDT enabled.
802 #define _WDT_ON 0x3FFF // WDT enabled.
803 #define _PWRTE_ON 0x3FEF // PWRT enabled.
804 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
805 #define _MCLRE_OFF 0x3FDF // GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD.
806 #define _MCLRE_ON 0x3FFF // GP3/MCLR pin function is MCLR.
807 #define _BOREN_OFF 0x3FBF // BOD disabled.
808 #define _BODEN_OFF 0x3FBF // BOD disabled.
809 #define _BOREN_ON 0x3FFF // BOD enabled.
810 #define _BODEN_ON 0x3FFF // BOD enabled.
811 #define _CP_ON 0x3F7F // Program Memory code protection is enabled.
812 #define _CP_OFF 0x3FFF // Program Memory code protection is disabled.
813 #define _CPD_ON 0x3EFF // Data memory code protection is enabled.
814 #define _CPD_OFF 0x3FFF // Data memory code protection is disabled.
815
816 //==============================================================================
817
818 #define _DEVID1 0x2006
819
820 #define _IDLOC0 0x2000
821 #define _IDLOC1 0x2001
822 #define _IDLOC2 0x2002
823 #define _IDLOC3 0x2003
824
825 //==============================================================================
826
827 #ifndef NO_BIT_DEFINES
828
829 #define CM0 CMCONbits.CM0 // bit 0
830 #define CM1 CMCONbits.CM1 // bit 1
831 #define CM2 CMCONbits.CM2 // bit 2
832 #define CIS CMCONbits.CIS // bit 3
833 #define CINV CMCONbits.CINV // bit 4
834 #define COUT CMCONbits.COUT // bit 6
835
836 #define RD EECON1bits.RD // bit 0
837 #define WR EECON1bits.WR // bit 1
838 #define WREN EECON1bits.WREN // bit 2
839 #define WRERR EECON1bits.WRERR // bit 3
840
841 #define GP0 GPIObits.GP0 // bit 0, shadows bit in GPIObits
842 #define GPIO0 GPIObits.GPIO0 // bit 0, shadows bit in GPIObits
843 #define GP1 GPIObits.GP1 // bit 1, shadows bit in GPIObits
844 #define GPIO1 GPIObits.GPIO1 // bit 1, shadows bit in GPIObits
845 #define GP2 GPIObits.GP2 // bit 2, shadows bit in GPIObits
846 #define GPIO2 GPIObits.GPIO2 // bit 2, shadows bit in GPIObits
847 #define GP3 GPIObits.GP3 // bit 3, shadows bit in GPIObits
848 #define GPIO3 GPIObits.GPIO3 // bit 3, shadows bit in GPIObits
849 #define GP4 GPIObits.GP4 // bit 4, shadows bit in GPIObits
850 #define GPIO4 GPIObits.GPIO4 // bit 4, shadows bit in GPIObits
851 #define GP5 GPIObits.GP5 // bit 5, shadows bit in GPIObits
852 #define GPIO5 GPIObits.GPIO5 // bit 5, shadows bit in GPIObits
853
854 #define GPIF INTCONbits.GPIF // bit 0
855 #define INTF INTCONbits.INTF // bit 1
856 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
857 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
858 #define GPIE INTCONbits.GPIE // bit 3
859 #define INTE INTCONbits.INTE // bit 4
860 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
861 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
862 #define PEIE INTCONbits.PEIE // bit 6
863 #define GIE INTCONbits.GIE // bit 7
864
865 #define IOC0 IOCbits.IOC0 // bit 0, shadows bit in IOCbits
866 #define IOCB0 IOCbits.IOCB0 // bit 0, shadows bit in IOCbits
867 #define IOC1 IOCbits.IOC1 // bit 1, shadows bit in IOCbits
868 #define IOCB1 IOCbits.IOCB1 // bit 1, shadows bit in IOCbits
869 #define IOC2 IOCbits.IOC2 // bit 2, shadows bit in IOCbits
870 #define IOCB2 IOCbits.IOCB2 // bit 2, shadows bit in IOCbits
871 #define IOC3 IOCbits.IOC3 // bit 3, shadows bit in IOCbits
872 #define IOCB3 IOCbits.IOCB3 // bit 3, shadows bit in IOCbits
873 #define IOC4 IOCbits.IOC4 // bit 4, shadows bit in IOCbits
874 #define IOCB4 IOCbits.IOCB4 // bit 4, shadows bit in IOCbits
875 #define IOC5 IOCbits.IOC5 // bit 5, shadows bit in IOCbits
876 #define IOCB5 IOCbits.IOCB5 // bit 5, shadows bit in IOCbits
877
878 #define PS0 OPTION_REGbits.PS0 // bit 0
879 #define PS1 OPTION_REGbits.PS1 // bit 1
880 #define PS2 OPTION_REGbits.PS2 // bit 2
881 #define PSA OPTION_REGbits.PSA // bit 3
882 #define T0SE OPTION_REGbits.T0SE // bit 4
883 #define T0CS OPTION_REGbits.T0CS // bit 5
884 #define INTEDG OPTION_REGbits.INTEDG // bit 6
885 #define NOT_GPPU OPTION_REGbits.NOT_GPPU // bit 7
886
887 #define CAL0 OSCCALbits.CAL0 // bit 2
888 #define CAL1 OSCCALbits.CAL1 // bit 3
889 #define CAL2 OSCCALbits.CAL2 // bit 4
890 #define CAL3 OSCCALbits.CAL3 // bit 5
891 #define CAL4 OSCCALbits.CAL4 // bit 6
892 #define CAL5 OSCCALbits.CAL5 // bit 7
893
894 #define NOT_BOR PCONbits.NOT_BOR // bit 0, shadows bit in PCONbits
895 #define NOT_BOD PCONbits.NOT_BOD // bit 0, shadows bit in PCONbits
896 #define NOT_POR PCONbits.NOT_POR // bit 1
897
898 #define TMR1IE PIE1bits.TMR1IE // bit 0, shadows bit in PIE1bits
899 #define T1IE PIE1bits.T1IE // bit 0, shadows bit in PIE1bits
900 #define CMIE PIE1bits.CMIE // bit 3
901 #define EEIE PIE1bits.EEIE // bit 7
902
903 #define TMR1IF PIR1bits.TMR1IF // bit 0, shadows bit in PIR1bits
904 #define T1IF PIR1bits.T1IF // bit 0, shadows bit in PIR1bits
905 #define CMIF PIR1bits.CMIF // bit 3
906 #define EEIF PIR1bits.EEIF // bit 7
907
908 #define C STATUSbits.C // bit 0
909 #define DC STATUSbits.DC // bit 1
910 #define Z STATUSbits.Z // bit 2
911 #define NOT_PD STATUSbits.NOT_PD // bit 3
912 #define NOT_TO STATUSbits.NOT_TO // bit 4
913 #define RP0 STATUSbits.RP0 // bit 5
914 #define RP1 STATUSbits.RP1 // bit 6
915 #define IRP STATUSbits.IRP // bit 7
916
917 #define TMR1ON T1CONbits.TMR1ON // bit 0
918 #define TMR1CS T1CONbits.TMR1CS // bit 1
919 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
920 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
921 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
922 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
923 #define TMR1GE T1CONbits.TMR1GE // bit 6
924
925 #define TRISIO0 TRISIObits.TRISIO0 // bit 0
926 #define TRISIO1 TRISIObits.TRISIO1 // bit 1
927 #define TRISIO2 TRISIObits.TRISIO2 // bit 2
928 #define TRISIO3 TRISIObits.TRISIO3 // bit 3
929 #define TRISIO4 TRISIObits.TRISIO4 // bit 4
930 #define TRISIO5 TRISIObits.TRISIO5 // bit 5
931
932 #define VR0 VRCONbits.VR0 // bit 0
933 #define VR1 VRCONbits.VR1 // bit 1
934 #define VR2 VRCONbits.VR2 // bit 2
935 #define VR3 VRCONbits.VR3 // bit 3
936 #define VRR VRCONbits.VRR // bit 5
937 #define VREN VRCONbits.VREN // bit 7
938
939 #define WPU0 WPUbits.WPU0 // bit 0
940 #define WPU1 WPUbits.WPU1 // bit 1
941 #define WPU2 WPUbits.WPU2 // bit 2
942 #define WPU4 WPUbits.WPU4 // bit 4
943 #define WPU5 WPUbits.WPU5 // bit 5
944
945 #endif // #ifndef NO_BIT_DEFINES
946
947 #endif // #ifndef __PIC12F629_H__
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