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Hackfix and re-enable strtoull and wcstoull, see bug #3798.
[sdcc.git] / sdcc / device / non-free / include / pic14 / pic16f610.h
blob2acf3ac516eacb1e1056cb1c4d07f63164a24d3d
1 /*
2 * This declarations of the PIC16F610 MCU.
3 *
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
6 *
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:22:56 UTC.
8 *
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
12 *
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
21 *
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
23 */
24
25 #ifndef __PIC16F610_H__
26 #define __PIC16F610_H__
27
28 //==============================================================================
29 //
30 // Register Addresses
31 //
32 //==============================================================================
33
34 #ifndef NO_ADDR_DEFINES
35
36 #define INDF_ADDR 0x0000
37 #define TMR0_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR_ADDR 0x0004
41 #define PORTA_ADDR 0x0005
42 #define PORTC_ADDR 0x0007
43 #define PCLATH_ADDR 0x000A
44 #define INTCON_ADDR 0x000B
45 #define PIR1_ADDR 0x000C
46 #define TMR1_ADDR 0x000E
47 #define TMR1L_ADDR 0x000E
48 #define TMR1H_ADDR 0x000F
49 #define T1CON_ADDR 0x0010
50 #define VRCON_ADDR 0x0019
51 #define CM1CON0_ADDR 0x001A
52 #define CM2CON0_ADDR 0x001B
53 #define CM2CON1_ADDR 0x001C
54 #define OPTION_REG_ADDR 0x0081
55 #define TRISA_ADDR 0x0085
56 #define TRISC_ADDR 0x0087
57 #define PIE1_ADDR 0x008C
58 #define PCON_ADDR 0x008E
59 #define OSCTUNE_ADDR 0x0090
60 #define ANSEL_ADDR 0x0091
61 #define WPU_ADDR 0x0095
62 #define WPUA_ADDR 0x0095
63 #define IOC_ADDR 0x0096
64 #define IOCA_ADDR 0x0096
65 #define SRCON0_ADDR 0x0099
66 #define SRCON1_ADDR 0x009A
67
68 #endif // #ifndef NO_ADDR_DEFINES
69
70 //==============================================================================
71 //
72 // Register Definitions
73 //
74 //==============================================================================
75
76 extern __at(0x0000) __sfr INDF;
77 extern __at(0x0001) __sfr TMR0;
78 extern __at(0x0002) __sfr PCL;
79
80 //==============================================================================
81 // STATUS Bits
82
83 extern __at(0x0003) __sfr STATUS;
84
85 typedef union
86 {
87 struct
88 {
89 unsigned C : 1;
90 unsigned DC : 1;
91 unsigned Z : 1;
92 unsigned NOT_PD : 1;
93 unsigned NOT_TO : 1;
94 unsigned RP0 : 1;
95 unsigned RP1 : 1;
96 unsigned IRP : 1;
97 };
98
99 struct
100 {
101 unsigned : 5;
102 unsigned RP : 2;
103 unsigned : 1;
104 };
105 } __STATUSbits_t;
106
107 extern __at(0x0003) volatile __STATUSbits_t STATUSbits;
108
109 #define _C 0x01
110 #define _DC 0x02
111 #define _Z 0x04
112 #define _NOT_PD 0x08
113 #define _NOT_TO 0x10
114 #define _RP0 0x20
115 #define _RP1 0x40
116 #define _IRP 0x80
117
118 //==============================================================================
119
120 extern __at(0x0004) __sfr FSR;
121
122 //==============================================================================
123 // PORTA Bits
124
125 extern __at(0x0005) __sfr PORTA;
126
127 typedef union
128 {
129 struct
130 {
131 unsigned RA0 : 1;
132 unsigned RA1 : 1;
133 unsigned RA2 : 1;
134 unsigned RA3 : 1;
135 unsigned RA4 : 1;
136 unsigned RA5 : 1;
137 unsigned : 1;
138 unsigned : 1;
139 };
140
141 struct
142 {
143 unsigned RA : 6;
144 unsigned : 2;
145 };
146 } __PORTAbits_t;
147
148 extern __at(0x0005) volatile __PORTAbits_t PORTAbits;
149
150 #define _RA0 0x01
151 #define _RA1 0x02
152 #define _RA2 0x04
153 #define _RA3 0x08
154 #define _RA4 0x10
155 #define _RA5 0x20
156
157 //==============================================================================
158
159
160 //==============================================================================
161 // PORTC Bits
162
163 extern __at(0x0007) __sfr PORTC;
164
165 typedef union
166 {
167 struct
168 {
169 unsigned RC0 : 1;
170 unsigned RC1 : 1;
171 unsigned RC2 : 1;
172 unsigned RC3 : 1;
173 unsigned RC4 : 1;
174 unsigned RC5 : 1;
175 unsigned : 1;
176 unsigned : 1;
177 };
178
179 struct
180 {
181 unsigned RC : 6;
182 unsigned : 2;
183 };
184 } __PORTCbits_t;
185
186 extern __at(0x0007) volatile __PORTCbits_t PORTCbits;
187
188 #define _RC0 0x01
189 #define _RC1 0x02
190 #define _RC2 0x04
191 #define _RC3 0x08
192 #define _RC4 0x10
193 #define _RC5 0x20
194
195 //==============================================================================
196
197 extern __at(0x000A) __sfr PCLATH;
198
199 //==============================================================================
200 // INTCON Bits
201
202 extern __at(0x000B) __sfr INTCON;
203
204 typedef union
205 {
206 struct
207 {
208 unsigned RAIF : 1;
209 unsigned INTF : 1;
210 unsigned TMR0IF : 1;
211 unsigned RAIE : 1;
212 unsigned INTE : 1;
213 unsigned TMR0IE : 1;
214 unsigned PEIE : 1;
215 unsigned GIE : 1;
216 };
217
218 struct
219 {
220 unsigned : 1;
221 unsigned : 1;
222 unsigned T0IF : 1;
223 unsigned : 1;
224 unsigned : 1;
225 unsigned T0IE : 1;
226 unsigned : 1;
227 unsigned : 1;
228 };
229 } __INTCONbits_t;
230
231 extern __at(0x000B) volatile __INTCONbits_t INTCONbits;
232
233 #define _RAIF 0x01
234 #define _INTF 0x02
235 #define _TMR0IF 0x04
236 #define _T0IF 0x04
237 #define _RAIE 0x08
238 #define _INTE 0x10
239 #define _TMR0IE 0x20
240 #define _T0IE 0x20
241 #define _PEIE 0x40
242 #define _GIE 0x80
243
244 //==============================================================================
245
246
247 //==============================================================================
248 // PIR1 Bits
249
250 extern __at(0x000C) __sfr PIR1;
251
252 typedef union
253 {
254 struct
255 {
256 unsigned TMR1IF : 1;
257 unsigned : 1;
258 unsigned : 1;
259 unsigned C1IF : 1;
260 unsigned C2IF : 1;
261 unsigned : 1;
262 unsigned : 1;
263 unsigned : 1;
264 };
265
266 struct
267 {
268 unsigned T1IF : 1;
269 unsigned : 1;
270 unsigned : 1;
271 unsigned : 1;
272 unsigned : 1;
273 unsigned : 1;
274 unsigned : 1;
275 unsigned : 1;
276 };
277 } __PIR1bits_t;
278
279 extern __at(0x000C) volatile __PIR1bits_t PIR1bits;
280
281 #define _TMR1IF 0x01
282 #define _T1IF 0x01
283 #define _C1IF 0x08
284 #define _C2IF 0x10
285
286 //==============================================================================
287
288 extern __at(0x000E) __sfr TMR1;
289 extern __at(0x000E) __sfr TMR1L;
290 extern __at(0x000F) __sfr TMR1H;
291
292 //==============================================================================
293 // T1CON Bits
294
295 extern __at(0x0010) __sfr T1CON;
296
297 typedef union
298 {
299 struct
300 {
301 unsigned TMR1ON : 1;
302 unsigned TMR1CS : 1;
303 unsigned NOT_T1SYNC : 1;
304 unsigned T1OSCEN : 1;
305 unsigned T1CKPS0 : 1;
306 unsigned T1CKPS1 : 1;
307 unsigned TMR1GE : 1;
308 unsigned T1GINV : 1;
309 };
310
311 struct
312 {
313 unsigned : 4;
314 unsigned T1CKPS : 2;
315 unsigned : 2;
316 };
317 } __T1CONbits_t;
318
319 extern __at(0x0010) volatile __T1CONbits_t T1CONbits;
320
321 #define _TMR1ON 0x01
322 #define _TMR1CS 0x02
323 #define _NOT_T1SYNC 0x04
324 #define _T1OSCEN 0x08
325 #define _T1CKPS0 0x10
326 #define _T1CKPS1 0x20
327 #define _TMR1GE 0x40
328 #define _T1GINV 0x80
329
330 //==============================================================================
331
332
333 //==============================================================================
334 // VRCON Bits
335
336 extern __at(0x0019) __sfr VRCON;
337
338 typedef union
339 {
340 struct
341 {
342 unsigned VR0 : 1;
343 unsigned VR1 : 1;
344 unsigned VR2 : 1;
345 unsigned VR3 : 1;
346 unsigned VP6EN : 1;
347 unsigned VRR : 1;
348 unsigned C2VREN : 1;
349 unsigned C1VREN : 1;
350 };
351
352 struct
353 {
354 unsigned : 1;
355 unsigned : 1;
356 unsigned : 1;
357 unsigned : 1;
358 unsigned FVREN : 1;
359 unsigned : 1;
360 unsigned : 1;
361 unsigned : 1;
362 };
363
364 struct
365 {
366 unsigned VR : 4;
367 unsigned : 4;
368 };
369 } __VRCONbits_t;
370
371 extern __at(0x0019) volatile __VRCONbits_t VRCONbits;
372
373 #define _VR0 0x01
374 #define _VR1 0x02
375 #define _VR2 0x04
376 #define _VR3 0x08
377 #define _VP6EN 0x10
378 #define _FVREN 0x10
379 #define _VRR 0x20
380 #define _C2VREN 0x40
381 #define _C1VREN 0x80
382
383 //==============================================================================
384
385
386 //==============================================================================
387 // CM1CON0 Bits
388
389 extern __at(0x001A) __sfr CM1CON0;
390
391 typedef union
392 {
393 struct
394 {
395 unsigned C1CH0 : 1;
396 unsigned C1CH1 : 1;
397 unsigned C1R : 1;
398 unsigned : 1;
399 unsigned C1POL : 1;
400 unsigned C1OE : 1;
401 unsigned C1OUT : 1;
402 unsigned C1ON : 1;
403 };
404
405 struct
406 {
407 unsigned C1CH : 2;
408 unsigned : 6;
409 };
410 } __CM1CON0bits_t;
411
412 extern __at(0x001A) volatile __CM1CON0bits_t CM1CON0bits;
413
414 #define _C1CH0 0x01
415 #define _C1CH1 0x02
416 #define _C1R 0x04
417 #define _C1POL 0x10
418 #define _C1OE 0x20
419 #define _C1OUT 0x40
420 #define _C1ON 0x80
421
422 //==============================================================================
423
424
425 //==============================================================================
426 // CM2CON0 Bits
427
428 extern __at(0x001B) __sfr CM2CON0;
429
430 typedef union
431 {
432 struct
433 {
434 unsigned C2CH0 : 1;
435 unsigned C2CH1 : 1;
436 unsigned C2R : 1;
437 unsigned : 1;
438 unsigned C2POL : 1;
439 unsigned C2OE : 1;
440 unsigned C2OUT : 1;
441 unsigned C2ON : 1;
442 };
443
444 struct
445 {
446 unsigned C2CH : 2;
447 unsigned : 6;
448 };
449 } __CM2CON0bits_t;
450
451 extern __at(0x001B) volatile __CM2CON0bits_t CM2CON0bits;
452
453 #define _C2CH0 0x01
454 #define _C2CH1 0x02
455 #define _C2R 0x04
456 #define _C2POL 0x10
457 #define _C2OE 0x20
458 #define _C2OUT 0x40
459 #define _C2ON 0x80
460
461 //==============================================================================
462
463
464 //==============================================================================
465 // CM2CON1 Bits
466
467 extern __at(0x001C) __sfr CM2CON1;
468
469 typedef struct
470 {
471 unsigned C2SYNC : 1;
472 unsigned T1GSS : 1;
473 unsigned C2HYS : 1;
474 unsigned C1HYS : 1;
475 unsigned T1ACS : 1;
476 unsigned : 1;
477 unsigned MC2OUT : 1;
478 unsigned MC1OUT : 1;
479 } __CM2CON1bits_t;
480
481 extern __at(0x001C) volatile __CM2CON1bits_t CM2CON1bits;
482
483 #define _C2SYNC 0x01
484 #define _T1GSS 0x02
485 #define _C2HYS 0x04
486 #define _C1HYS 0x08
487 #define _T1ACS 0x10
488 #define _MC2OUT 0x40
489 #define _MC1OUT 0x80
490
491 //==============================================================================
492
493
494 //==============================================================================
495 // OPTION_REG Bits
496
497 extern __at(0x0081) __sfr OPTION_REG;
498
499 typedef union
500 {
501 struct
502 {
503 unsigned PS0 : 1;
504 unsigned PS1 : 1;
505 unsigned PS2 : 1;
506 unsigned PSA : 1;
507 unsigned T0SE : 1;
508 unsigned T0CS : 1;
509 unsigned INTEDG : 1;
510 unsigned NOT_RAPU : 1;
511 };
512
513 struct
514 {
515 unsigned PS : 3;
516 unsigned : 5;
517 };
518 } __OPTION_REGbits_t;
519
520 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits;
521
522 #define _PS0 0x01
523 #define _PS1 0x02
524 #define _PS2 0x04
525 #define _PSA 0x08
526 #define _T0SE 0x10
527 #define _T0CS 0x20
528 #define _INTEDG 0x40
529 #define _NOT_RAPU 0x80
530
531 //==============================================================================
532
533
534 //==============================================================================
535 // TRISA Bits
536
537 extern __at(0x0085) __sfr TRISA;
538
539 typedef union
540 {
541 struct
542 {
543 unsigned TRISA0 : 1;
544 unsigned TRISA1 : 1;
545 unsigned TRISA2 : 1;
546 unsigned TRISA3 : 1;
547 unsigned TRISA4 : 1;
548 unsigned TRISA5 : 1;
549 unsigned : 1;
550 unsigned : 1;
551 };
552
553 struct
554 {
555 unsigned TRISA : 6;
556 unsigned : 2;
557 };
558 } __TRISAbits_t;
559
560 extern __at(0x0085) volatile __TRISAbits_t TRISAbits;
561
562 #define _TRISA0 0x01
563 #define _TRISA1 0x02
564 #define _TRISA2 0x04
565 #define _TRISA3 0x08
566 #define _TRISA4 0x10
567 #define _TRISA5 0x20
568
569 //==============================================================================
570
571
572 //==============================================================================
573 // TRISC Bits
574
575 extern __at(0x0087) __sfr TRISC;
576
577 typedef union
578 {
579 struct
580 {
581 unsigned TRISC0 : 1;
582 unsigned TRISC1 : 1;
583 unsigned TRISC2 : 1;
584 unsigned TRISC3 : 1;
585 unsigned TRISC4 : 1;
586 unsigned TRISC5 : 1;
587 unsigned : 1;
588 unsigned : 1;
589 };
590
591 struct
592 {
593 unsigned TRISC : 6;
594 unsigned : 2;
595 };
596 } __TRISCbits_t;
597
598 extern __at(0x0087) volatile __TRISCbits_t TRISCbits;
599
600 #define _TRISC0 0x01
601 #define _TRISC1 0x02
602 #define _TRISC2 0x04
603 #define _TRISC3 0x08
604 #define _TRISC4 0x10
605 #define _TRISC5 0x20
606
607 //==============================================================================
608
609
610 //==============================================================================
611 // PIE1 Bits
612
613 extern __at(0x008C) __sfr PIE1;
614
615 typedef union
616 {
617 struct
618 {
619 unsigned TMR1IE : 1;
620 unsigned : 1;
621 unsigned : 1;
622 unsigned C1IE : 1;
623 unsigned C2IE : 1;
624 unsigned : 1;
625 unsigned : 1;
626 unsigned : 1;
627 };
628
629 struct
630 {
631 unsigned T1IE : 1;
632 unsigned : 1;
633 unsigned : 1;
634 unsigned : 1;
635 unsigned : 1;
636 unsigned : 1;
637 unsigned : 1;
638 unsigned : 1;
639 };
640 } __PIE1bits_t;
641
642 extern __at(0x008C) volatile __PIE1bits_t PIE1bits;
643
644 #define _TMR1IE 0x01
645 #define _T1IE 0x01
646 #define _C1IE 0x08
647 #define _C2IE 0x10
648
649 //==============================================================================
650
651
652 //==============================================================================
653 // PCON Bits
654
655 extern __at(0x008E) __sfr PCON;
656
657 typedef union
658 {
659 struct
660 {
661 unsigned NOT_BOR : 1;
662 unsigned NOT_POR : 1;
663 unsigned : 1;
664 unsigned : 1;
665 unsigned : 1;
666 unsigned : 1;
667 unsigned : 1;
668 unsigned : 1;
669 };
670
671 struct
672 {
673 unsigned NOT_BOD : 1;
674 unsigned : 1;
675 unsigned : 1;
676 unsigned : 1;
677 unsigned : 1;
678 unsigned : 1;
679 unsigned : 1;
680 unsigned : 1;
681 };
682 } __PCONbits_t;
683
684 extern __at(0x008E) volatile __PCONbits_t PCONbits;
685
686 #define _NOT_BOR 0x01
687 #define _NOT_BOD 0x01
688 #define _NOT_POR 0x02
689
690 //==============================================================================
691
692
693 //==============================================================================
694 // OSCTUNE Bits
695
696 extern __at(0x0090) __sfr OSCTUNE;
697
698 typedef union
699 {
700 struct
701 {
702 unsigned TUN0 : 1;
703 unsigned TUN1 : 1;
704 unsigned TUN2 : 1;
705 unsigned TUN3 : 1;
706 unsigned TUN4 : 1;
707 unsigned : 1;
708 unsigned : 1;
709 unsigned : 1;
710 };
711
712 struct
713 {
714 unsigned TUN : 5;
715 unsigned : 3;
716 };
717 } __OSCTUNEbits_t;
718
719 extern __at(0x0090) volatile __OSCTUNEbits_t OSCTUNEbits;
720
721 #define _TUN0 0x01
722 #define _TUN1 0x02
723 #define _TUN2 0x04
724 #define _TUN3 0x08
725 #define _TUN4 0x10
726
727 //==============================================================================
728
729
730 //==============================================================================
731 // ANSEL Bits
732
733 extern __at(0x0091) __sfr ANSEL;
734
735 typedef struct
736 {
737 unsigned ANS0 : 1;
738 unsigned ANS1 : 1;
739 unsigned : 1;
740 unsigned : 1;
741 unsigned ANS4 : 1;
742 unsigned ANS5 : 1;
743 unsigned ANS6 : 1;
744 unsigned ANS7 : 1;
745 } __ANSELbits_t;
746
747 extern __at(0x0091) volatile __ANSELbits_t ANSELbits;
748
749 #define _ANS0 0x01
750 #define _ANS1 0x02
751 #define _ANS4 0x10
752 #define _ANS5 0x20
753 #define _ANS6 0x40
754 #define _ANS7 0x80
755
756 //==============================================================================
757
758
759 //==============================================================================
760 // WPU Bits
761
762 extern __at(0x0095) __sfr WPU;
763
764 typedef union
765 {
766 struct
767 {
768 unsigned WPUA0 : 1;
769 unsigned WPUA1 : 1;
770 unsigned WPUA2 : 1;
771 unsigned : 1;
772 unsigned WPUA4 : 1;
773 unsigned WPUA5 : 1;
774 unsigned : 1;
775 unsigned : 1;
776 };
777
778 struct
779 {
780 unsigned WPU0 : 1;
781 unsigned WPU1 : 1;
782 unsigned WPU2 : 1;
783 unsigned : 1;
784 unsigned WPU4 : 1;
785 unsigned WPU5 : 1;
786 unsigned : 1;
787 unsigned : 1;
788 };
789 } __WPUbits_t;
790
791 extern __at(0x0095) volatile __WPUbits_t WPUbits;
792
793 #define _WPUA0 0x01
794 #define _WPU0 0x01
795 #define _WPUA1 0x02
796 #define _WPU1 0x02
797 #define _WPUA2 0x04
798 #define _WPU2 0x04
799 #define _WPUA4 0x10
800 #define _WPU4 0x10
801 #define _WPUA5 0x20
802 #define _WPU5 0x20
803
804 //==============================================================================
805
806
807 //==============================================================================
808 // WPUA Bits
809
810 extern __at(0x0095) __sfr WPUA;
811
812 typedef union
813 {
814 struct
815 {
816 unsigned WPUA0 : 1;
817 unsigned WPUA1 : 1;
818 unsigned WPUA2 : 1;
819 unsigned : 1;
820 unsigned WPUA4 : 1;
821 unsigned WPUA5 : 1;
822 unsigned : 1;
823 unsigned : 1;
824 };
825
826 struct
827 {
828 unsigned WPU0 : 1;
829 unsigned WPU1 : 1;
830 unsigned WPU2 : 1;
831 unsigned : 1;
832 unsigned WPU4 : 1;
833 unsigned WPU5 : 1;
834 unsigned : 1;
835 unsigned : 1;
836 };
837 } __WPUAbits_t;
838
839 extern __at(0x0095) volatile __WPUAbits_t WPUAbits;
840
841 #define _WPUA_WPUA0 0x01
842 #define _WPUA_WPU0 0x01
843 #define _WPUA_WPUA1 0x02
844 #define _WPUA_WPU1 0x02
845 #define _WPUA_WPUA2 0x04
846 #define _WPUA_WPU2 0x04
847 #define _WPUA_WPUA4 0x10
848 #define _WPUA_WPU4 0x10
849 #define _WPUA_WPUA5 0x20
850 #define _WPUA_WPU5 0x20
851
852 //==============================================================================
853
854
855 //==============================================================================
856 // IOC Bits
857
858 extern __at(0x0096) __sfr IOC;
859
860 typedef union
861 {
862 struct
863 {
864 unsigned IOCA0 : 1;
865 unsigned IOCA1 : 1;
866 unsigned IOCA2 : 1;
867 unsigned IOCA3 : 1;
868 unsigned IOCA4 : 1;
869 unsigned IOCA5 : 1;
870 unsigned : 1;
871 unsigned : 1;
872 };
873
874 struct
875 {
876 unsigned IOC0 : 1;
877 unsigned IOC1 : 1;
878 unsigned IOC2 : 1;
879 unsigned IOC3 : 1;
880 unsigned IOC4 : 1;
881 unsigned IOC5 : 1;
882 unsigned : 1;
883 unsigned : 1;
884 };
885
886 struct
887 {
888 unsigned IOC : 6;
889 unsigned : 2;
890 };
891
892 struct
893 {
894 unsigned IOCA : 6;
895 unsigned : 2;
896 };
897 } __IOCbits_t;
898
899 extern __at(0x0096) volatile __IOCbits_t IOCbits;
900
901 #define _IOCA0 0x01
902 #define _IOC0 0x01
903 #define _IOCA1 0x02
904 #define _IOC1 0x02
905 #define _IOCA2 0x04
906 #define _IOC2 0x04
907 #define _IOCA3 0x08
908 #define _IOC3 0x08
909 #define _IOCA4 0x10
910 #define _IOC4 0x10
911 #define _IOCA5 0x20
912 #define _IOC5 0x20
913
914 //==============================================================================
915
916
917 //==============================================================================
918 // IOCA Bits
919
920 extern __at(0x0096) __sfr IOCA;
921
922 typedef union
923 {
924 struct
925 {
926 unsigned IOCA0 : 1;
927 unsigned IOCA1 : 1;
928 unsigned IOCA2 : 1;
929 unsigned IOCA3 : 1;
930 unsigned IOCA4 : 1;
931 unsigned IOCA5 : 1;
932 unsigned : 1;
933 unsigned : 1;
934 };
935
936 struct
937 {
938 unsigned IOC0 : 1;
939 unsigned IOC1 : 1;
940 unsigned IOC2 : 1;
941 unsigned IOC3 : 1;
942 unsigned IOC4 : 1;
943 unsigned IOC5 : 1;
944 unsigned : 1;
945 unsigned : 1;
946 };
947
948 struct
949 {
950 unsigned IOCA : 6;
951 unsigned : 2;
952 };
953
954 struct
955 {
956 unsigned IOC : 6;
957 unsigned : 2;
958 };
959 } __IOCAbits_t;
960
961 extern __at(0x0096) volatile __IOCAbits_t IOCAbits;
962
963 #define _IOCA_IOCA0 0x01
964 #define _IOCA_IOC0 0x01
965 #define _IOCA_IOCA1 0x02
966 #define _IOCA_IOC1 0x02
967 #define _IOCA_IOCA2 0x04
968 #define _IOCA_IOC2 0x04
969 #define _IOCA_IOCA3 0x08
970 #define _IOCA_IOC3 0x08
971 #define _IOCA_IOCA4 0x10
972 #define _IOCA_IOC4 0x10
973 #define _IOCA_IOCA5 0x20
974 #define _IOCA_IOC5 0x20
975
976 //==============================================================================
977
978
979 //==============================================================================
980 // SRCON0 Bits
981
982 extern __at(0x0099) __sfr SRCON0;
983
984 typedef union
985 {
986 struct
987 {
988 unsigned SRCLKEN : 1;
989 unsigned : 1;
990 unsigned PULSR : 1;
991 unsigned PULSS : 1;
992 unsigned C2REN : 1;
993 unsigned C1SEN : 1;
994 unsigned SR0 : 1;
995 unsigned SR1 : 1;
996 };
997
998 struct
999 {
1000 unsigned : 6;
1001 unsigned SR : 2;
1002 };
1003 } __SRCON0bits_t;
1004
1005 extern __at(0x0099) volatile __SRCON0bits_t SRCON0bits;
1006
1007 #define _SRCLKEN 0x01
1008 #define _PULSR 0x04
1009 #define _PULSS 0x08
1010 #define _C2REN 0x10
1011 #define _C1SEN 0x20
1012 #define _SR0 0x40
1013 #define _SR1 0x80
1014
1015 //==============================================================================
1016
1017
1018 //==============================================================================
1019 // SRCON1 Bits
1020
1021 extern __at(0x009A) __sfr SRCON1;
1022
1023 typedef union
1024 {
1025 struct
1026 {
1027 unsigned : 1;
1028 unsigned : 1;
1029 unsigned : 1;
1030 unsigned : 1;
1031 unsigned : 1;
1032 unsigned : 1;
1033 unsigned SRCS0 : 1;
1034 unsigned SRCS1 : 1;
1035 };
1036
1037 struct
1038 {
1039 unsigned : 6;
1040 unsigned SRCS : 2;
1041 };
1042 } __SRCON1bits_t;
1043
1044 extern __at(0x009A) volatile __SRCON1bits_t SRCON1bits;
1045
1046 #define _SRCS0 0x40
1047 #define _SRCS1 0x80
1048
1049 //==============================================================================
1050
1051
1052 //==============================================================================
1053 //
1054 // Configuration Bits
1055 //
1056 //==============================================================================
1057
1058 #define _CONFIG 0x2007
1059
1060 //----------------------------- CONFIG Options -------------------------------
1061
1062 #define _FOSC_LP 0x3FF8 // LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1063 #define _LP_OSC 0x3FF8 // LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1064 #define _FOSC_XT 0x3FF9 // XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1065 #define _XT_OSC 0x3FF9 // XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1066 #define _FOSC_HS 0x3FFA // HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1067 #define _HS_OSC 0x3FFA // HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1068 #define _FOSC_EC 0x3FFB // EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN.
1069 #define _EC_OSC 0x3FFB // EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN.
1070 #define _FOSC_INTOSCIO 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1071 #define _INTRC_OSC_NOCLKOUT 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1072 #define _INTOSCIO 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1073 #define _FOSC_INTOSCCLK 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1074 #define _INTRC_OSC_CLKOUT 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1075 #define _INTOSC 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1076 #define _FOSC_EXTRCIO 0x3FFE // RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1077 #define _EXTRC_OSC_NOCLKOUT 0x3FFE // RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1078 #define _EXTRCIO 0x3FFE // RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1079 #define _FOSC_EXTRCCLK 0x3FFF // RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1080 #define _EXTRC_OSC_CLKOUT 0x3FFF // RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1081 #define _EXTRC 0x3FFF // RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1082 #define _WDTE_OFF 0x3FF7 // WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
1083 #define _WDT_OFF 0x3FF7 // WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
1084 #define _WDTE_ON 0x3FFF // WDT enabled.
1085 #define _WDT_ON 0x3FFF // WDT enabled.
1086 #define _PWRTE_ON 0x3FEF // PWRT enabled.
1087 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
1088 #define _MCLRE_OFF 0x3FDF // MCLR pin function is digital input, MCLR internally tied to VDD.
1089 #define _MCLRE_ON 0x3FFF // MCLR pin function is MCLR.
1090 #define _CP_ON 0x3FBF // Program memory code protection is enabled.
1091 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
1092 #define _IOSCFS_4MHZ 0x3F7F // 4 MHz.
1093 #define _IOSCFS4 0x3F7F // 4 MHz.
1094 #define _IOSCFS_8MHZ 0x3FFF // 8 MHz.
1095 #define _IOSCFS8 0x3FFF // 8 MHz.
1096 #define _BOREN_OFF 0x3CFF // BOR Disabled.
1097 #define _BOD_OFF 0x3CFF // BOR Disabled.
1098 #define _BOR_OFF 0x3CFF // BOR Disabled.
1099 #define _BOREN_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1100 #define _BOD_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1101 #define _BOR_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1102 #define _BOREN_ON 0x3FFF // BOR enabled.
1103 #define _BOD_ON 0x3FFF // BOR enabled.
1104 #define _BOR_ON 0x3FFF // BOR enabled.
1105
1106 //==============================================================================
1107
1108 #define _DEVID1 0x2006
1109
1110 #define _IDLOC0 0x2000
1111 #define _IDLOC1 0x2001
1112 #define _IDLOC2 0x2002
1113 #define _IDLOC3 0x2003
1114
1115 //==============================================================================
1116
1117 #ifndef NO_BIT_DEFINES
1118
1119 #define ANS0 ANSELbits.ANS0 // bit 0
1120 #define ANS1 ANSELbits.ANS1 // bit 1
1121 #define ANS4 ANSELbits.ANS4 // bit 4
1122 #define ANS5 ANSELbits.ANS5 // bit 5
1123 #define ANS6 ANSELbits.ANS6 // bit 6
1124 #define ANS7 ANSELbits.ANS7 // bit 7
1125
1126 #define C1CH0 CM1CON0bits.C1CH0 // bit 0
1127 #define C1CH1 CM1CON0bits.C1CH1 // bit 1
1128 #define C1R CM1CON0bits.C1R // bit 2
1129 #define C1POL CM1CON0bits.C1POL // bit 4
1130 #define C1OE CM1CON0bits.C1OE // bit 5
1131 #define C1OUT CM1CON0bits.C1OUT // bit 6
1132 #define C1ON CM1CON0bits.C1ON // bit 7
1133
1134 #define C2CH0 CM2CON0bits.C2CH0 // bit 0
1135 #define C2CH1 CM2CON0bits.C2CH1 // bit 1
1136 #define C2R CM2CON0bits.C2R // bit 2
1137 #define C2POL CM2CON0bits.C2POL // bit 4
1138 #define C2OE CM2CON0bits.C2OE // bit 5
1139 #define C2OUT CM2CON0bits.C2OUT // bit 6
1140 #define C2ON CM2CON0bits.C2ON // bit 7
1141
1142 #define C2SYNC CM2CON1bits.C2SYNC // bit 0
1143 #define T1GSS CM2CON1bits.T1GSS // bit 1
1144 #define C2HYS CM2CON1bits.C2HYS // bit 2
1145 #define C1HYS CM2CON1bits.C1HYS // bit 3
1146 #define T1ACS CM2CON1bits.T1ACS // bit 4
1147 #define MC2OUT CM2CON1bits.MC2OUT // bit 6
1148 #define MC1OUT CM2CON1bits.MC1OUT // bit 7
1149
1150 #define RAIF INTCONbits.RAIF // bit 0
1151 #define INTF INTCONbits.INTF // bit 1
1152 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
1153 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
1154 #define RAIE INTCONbits.RAIE // bit 3
1155 #define INTE INTCONbits.INTE // bit 4
1156 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
1157 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
1158 #define PEIE INTCONbits.PEIE // bit 6
1159 #define GIE INTCONbits.GIE // bit 7
1160
1161 #define IOCA0 IOCbits.IOCA0 // bit 0, shadows bit in IOCbits
1162 #define IOC0 IOCbits.IOC0 // bit 0, shadows bit in IOCbits
1163 #define IOCA1 IOCbits.IOCA1 // bit 1, shadows bit in IOCbits
1164 #define IOC1 IOCbits.IOC1 // bit 1, shadows bit in IOCbits
1165 #define IOCA2 IOCbits.IOCA2 // bit 2, shadows bit in IOCbits
1166 #define IOC2 IOCbits.IOC2 // bit 2, shadows bit in IOCbits
1167 #define IOCA3 IOCbits.IOCA3 // bit 3, shadows bit in IOCbits
1168 #define IOC3 IOCbits.IOC3 // bit 3, shadows bit in IOCbits
1169 #define IOCA4 IOCbits.IOCA4 // bit 4, shadows bit in IOCbits
1170 #define IOC4 IOCbits.IOC4 // bit 4, shadows bit in IOCbits
1171 #define IOCA5 IOCbits.IOCA5 // bit 5, shadows bit in IOCbits
1172 #define IOC5 IOCbits.IOC5 // bit 5, shadows bit in IOCbits
1173
1174 #define PS0 OPTION_REGbits.PS0 // bit 0
1175 #define PS1 OPTION_REGbits.PS1 // bit 1
1176 #define PS2 OPTION_REGbits.PS2 // bit 2
1177 #define PSA OPTION_REGbits.PSA // bit 3
1178 #define T0SE OPTION_REGbits.T0SE // bit 4
1179 #define T0CS OPTION_REGbits.T0CS // bit 5
1180 #define INTEDG OPTION_REGbits.INTEDG // bit 6
1181 #define NOT_RAPU OPTION_REGbits.NOT_RAPU // bit 7
1182
1183 #define TUN0 OSCTUNEbits.TUN0 // bit 0
1184 #define TUN1 OSCTUNEbits.TUN1 // bit 1
1185 #define TUN2 OSCTUNEbits.TUN2 // bit 2
1186 #define TUN3 OSCTUNEbits.TUN3 // bit 3
1187 #define TUN4 OSCTUNEbits.TUN4 // bit 4
1188
1189 #define NOT_BOR PCONbits.NOT_BOR // bit 0, shadows bit in PCONbits
1190 #define NOT_BOD PCONbits.NOT_BOD // bit 0, shadows bit in PCONbits
1191 #define NOT_POR PCONbits.NOT_POR // bit 1
1192
1193 #define TMR1IE PIE1bits.TMR1IE // bit 0, shadows bit in PIE1bits
1194 #define T1IE PIE1bits.T1IE // bit 0, shadows bit in PIE1bits
1195 #define C1IE PIE1bits.C1IE // bit 3
1196 #define C2IE PIE1bits.C2IE // bit 4
1197
1198 #define TMR1IF PIR1bits.TMR1IF // bit 0, shadows bit in PIR1bits
1199 #define T1IF PIR1bits.T1IF // bit 0, shadows bit in PIR1bits
1200 #define C1IF PIR1bits.C1IF // bit 3
1201 #define C2IF PIR1bits.C2IF // bit 4
1202
1203 #define RA0 PORTAbits.RA0 // bit 0
1204 #define RA1 PORTAbits.RA1 // bit 1
1205 #define RA2 PORTAbits.RA2 // bit 2
1206 #define RA3 PORTAbits.RA3 // bit 3
1207 #define RA4 PORTAbits.RA4 // bit 4
1208 #define RA5 PORTAbits.RA5 // bit 5
1209
1210 #define RC0 PORTCbits.RC0 // bit 0
1211 #define RC1 PORTCbits.RC1 // bit 1
1212 #define RC2 PORTCbits.RC2 // bit 2
1213 #define RC3 PORTCbits.RC3 // bit 3
1214 #define RC4 PORTCbits.RC4 // bit 4
1215 #define RC5 PORTCbits.RC5 // bit 5
1216
1217 #define SRCLKEN SRCON0bits.SRCLKEN // bit 0
1218 #define PULSR SRCON0bits.PULSR // bit 2
1219 #define PULSS SRCON0bits.PULSS // bit 3
1220 #define C2REN SRCON0bits.C2REN // bit 4
1221 #define C1SEN SRCON0bits.C1SEN // bit 5
1222 #define SR0 SRCON0bits.SR0 // bit 6
1223 #define SR1 SRCON0bits.SR1 // bit 7
1224
1225 #define SRCS0 SRCON1bits.SRCS0 // bit 6
1226 #define SRCS1 SRCON1bits.SRCS1 // bit 7
1227
1228 #define C STATUSbits.C // bit 0
1229 #define DC STATUSbits.DC // bit 1
1230 #define Z STATUSbits.Z // bit 2
1231 #define NOT_PD STATUSbits.NOT_PD // bit 3
1232 #define NOT_TO STATUSbits.NOT_TO // bit 4
1233 #define RP0 STATUSbits.RP0 // bit 5
1234 #define RP1 STATUSbits.RP1 // bit 6
1235 #define IRP STATUSbits.IRP // bit 7
1236
1237 #define TMR1ON T1CONbits.TMR1ON // bit 0
1238 #define TMR1CS T1CONbits.TMR1CS // bit 1
1239 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
1240 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
1241 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
1242 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
1243 #define TMR1GE T1CONbits.TMR1GE // bit 6
1244 #define T1GINV T1CONbits.T1GINV // bit 7
1245
1246 #define TRISA0 TRISAbits.TRISA0 // bit 0
1247 #define TRISA1 TRISAbits.TRISA1 // bit 1
1248 #define TRISA2 TRISAbits.TRISA2 // bit 2
1249 #define TRISA3 TRISAbits.TRISA3 // bit 3
1250 #define TRISA4 TRISAbits.TRISA4 // bit 4
1251 #define TRISA5 TRISAbits.TRISA5 // bit 5
1252
1253 #define TRISC0 TRISCbits.TRISC0 // bit 0
1254 #define TRISC1 TRISCbits.TRISC1 // bit 1
1255 #define TRISC2 TRISCbits.TRISC2 // bit 2
1256 #define TRISC3 TRISCbits.TRISC3 // bit 3
1257 #define TRISC4 TRISCbits.TRISC4 // bit 4
1258 #define TRISC5 TRISCbits.TRISC5 // bit 5
1259
1260 #define VR0 VRCONbits.VR0 // bit 0
1261 #define VR1 VRCONbits.VR1 // bit 1
1262 #define VR2 VRCONbits.VR2 // bit 2
1263 #define VR3 VRCONbits.VR3 // bit 3
1264 #define VP6EN VRCONbits.VP6EN // bit 4, shadows bit in VRCONbits
1265 #define FVREN VRCONbits.FVREN // bit 4, shadows bit in VRCONbits
1266 #define VRR VRCONbits.VRR // bit 5
1267 #define C2VREN VRCONbits.C2VREN // bit 6
1268 #define C1VREN VRCONbits.C1VREN // bit 7
1269
1270 #define WPUA0 WPUbits.WPUA0 // bit 0, shadows bit in WPUbits
1271 #define WPU0 WPUbits.WPU0 // bit 0, shadows bit in WPUbits
1272 #define WPUA1 WPUbits.WPUA1 // bit 1, shadows bit in WPUbits
1273 #define WPU1 WPUbits.WPU1 // bit 1, shadows bit in WPUbits
1274 #define WPUA2 WPUbits.WPUA2 // bit 2, shadows bit in WPUbits
1275 #define WPU2 WPUbits.WPU2 // bit 2, shadows bit in WPUbits
1276 #define WPUA4 WPUbits.WPUA4 // bit 4, shadows bit in WPUbits
1277 #define WPU4 WPUbits.WPU4 // bit 4, shadows bit in WPUbits
1278 #define WPUA5 WPUbits.WPUA5 // bit 5, shadows bit in WPUbits
1279 #define WPU5 WPUbits.WPU5 // bit 5, shadows bit in WPUbits
1280
1281 #endif // #ifndef NO_BIT_DEFINES
1282
1283 #endif // #ifndef __PIC16F610_H__
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