2 * This declarations of the PIC16F628A MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:22:56 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F628A_H__
26 #define __PIC16F628A_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF_ADDR 0x0000
37 #define TMR0_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR_ADDR 0x0004
41 #define PORTA_ADDR 0x0005
42 #define PORTB_ADDR 0x0006
43 #define PCLATH_ADDR 0x000A
44 #define INTCON_ADDR 0x000B
45 #define PIR1_ADDR 0x000C
46 #define TMR1_ADDR 0x000E
47 #define TMR1L_ADDR 0x000E
48 #define TMR1H_ADDR 0x000F
49 #define T1CON_ADDR 0x0010
50 #define TMR2_ADDR 0x0011
51 #define T2CON_ADDR 0x0012
52 #define CCPR1_ADDR 0x0015
53 #define CCPR1L_ADDR 0x0015
54 #define CCPR1H_ADDR 0x0016
55 #define CCP1CON_ADDR 0x0017
56 #define RCSTA_ADDR 0x0018
57 #define TXREG_ADDR 0x0019
58 #define RCREG_ADDR 0x001A
59 #define CMCON_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define PIE1_ADDR 0x008C
64 #define PCON_ADDR 0x008E
65 #define PR2_ADDR 0x0092
66 #define TXSTA_ADDR 0x0098
67 #define SPBRG_ADDR 0x0099
68 #define EEDATA_ADDR 0x009A
69 #define EEADR_ADDR 0x009B
70 #define EECON1_ADDR 0x009C
71 #define EECON2_ADDR 0x009D
72 #define VRCON_ADDR 0x009F
74 #endif // #ifndef NO_ADDR_DEFINES
76 //==============================================================================
78 // Register Definitions
80 //==============================================================================
82 extern __at(0x0000) __sfr INDF
;
83 extern __at(0x0001) __sfr TMR0
;
84 extern __at(0x0002) __sfr PCL
;
86 //==============================================================================
89 extern __at(0x0003) __sfr STATUS
;
113 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
124 //==============================================================================
126 extern __at(0x0004) __sfr FSR
;
128 //==============================================================================
131 extern __at(0x0005) __sfr PORTA
;
145 extern __at(0x0005) volatile __PORTAbits_t PORTAbits
;
156 //==============================================================================
159 //==============================================================================
162 extern __at(0x0006) __sfr PORTB
;
176 extern __at(0x0006) volatile __PORTBbits_t PORTBbits
;
187 //==============================================================================
189 extern __at(0x000A) __sfr PCLATH
;
191 //==============================================================================
194 extern __at(0x000B) __sfr INTCON
;
223 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
236 //==============================================================================
239 //==============================================================================
242 extern __at(0x000C) __sfr PIR1
;
256 extern __at(0x000C) volatile __PIR1bits_t PIR1bits
;
266 //==============================================================================
268 extern __at(0x000E) __sfr TMR1
;
269 extern __at(0x000E) __sfr TMR1L
;
270 extern __at(0x000F) __sfr TMR1H
;
272 //==============================================================================
275 extern __at(0x0010) __sfr T1CON
;
283 unsigned NOT_T1SYNC
: 1;
284 unsigned T1OSCEN
: 1;
285 unsigned T1CKPS0
: 1;
286 unsigned T1CKPS1
: 1;
299 extern __at(0x0010) volatile __T1CONbits_t T1CONbits
;
303 #define _NOT_T1SYNC 0x04
304 #define _T1OSCEN 0x08
305 #define _T1CKPS0 0x10
306 #define _T1CKPS1 0x20
308 //==============================================================================
310 extern __at(0x0011) __sfr TMR2
;
312 //==============================================================================
315 extern __at(0x0012) __sfr T2CON
;
321 unsigned T2CKPS0
: 1;
322 unsigned T2CKPS1
: 1;
324 unsigned TOUTPS0
: 1;
325 unsigned TOUTPS1
: 1;
326 unsigned TOUTPS2
: 1;
327 unsigned TOUTPS3
: 1;
345 extern __at(0x0012) volatile __T2CONbits_t T2CONbits
;
347 #define _T2CKPS0 0x01
348 #define _T2CKPS1 0x02
350 #define _TOUTPS0 0x08
351 #define _TOUTPS1 0x10
352 #define _TOUTPS2 0x20
353 #define _TOUTPS3 0x40
355 //==============================================================================
357 extern __at(0x0015) __sfr CCPR1
;
358 extern __at(0x0015) __sfr CCPR1L
;
359 extern __at(0x0016) __sfr CCPR1H
;
361 //==============================================================================
364 extern __at(0x0017) __sfr CCP1CON
;
387 extern __at(0x0017) volatile __CCP1CONbits_t CCP1CONbits
;
396 //==============================================================================
399 //==============================================================================
402 extern __at(0x0018) __sfr RCSTA
;
431 extern __at(0x0018) volatile __RCSTAbits_t RCSTAbits
;
443 //==============================================================================
445 extern __at(0x0019) __sfr TXREG
;
446 extern __at(0x001A) __sfr RCREG
;
448 //==============================================================================
451 extern __at(0x001F) __sfr CMCON
;
474 extern __at(0x001F) volatile __CMCONbits_t CMCONbits
;
485 //==============================================================================
488 //==============================================================================
491 extern __at(0x0081) __sfr OPTION_REG
;
504 unsigned NOT_RBPU
: 1;
512 } __OPTION_REGbits_t
;
514 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits
;
523 #define _NOT_RBPU 0x80
525 //==============================================================================
528 //==============================================================================
531 extern __at(0x0085) __sfr TRISA
;
545 extern __at(0x0085) volatile __TRISAbits_t TRISAbits
;
556 //==============================================================================
559 //==============================================================================
562 extern __at(0x0086) __sfr TRISB
;
576 extern __at(0x0086) volatile __TRISBbits_t TRISBbits
;
587 //==============================================================================
590 //==============================================================================
593 extern __at(0x008C) __sfr PIE1
;
607 extern __at(0x008C) volatile __PIE1bits_t PIE1bits
;
617 //==============================================================================
620 //==============================================================================
623 extern __at(0x008E) __sfr PCON
;
629 unsigned NOT_BOR
: 1;
630 unsigned NOT_POR
: 1;
653 unsigned NOT_BOD
: 1;
664 extern __at(0x008E) volatile __PCONbits_t PCONbits
;
666 #define _NOT_BOR 0x01
668 #define _NOT_BOD 0x01
669 #define _NOT_POR 0x02
672 //==============================================================================
674 extern __at(0x0092) __sfr PR2
;
676 //==============================================================================
679 extern __at(0x0098) __sfr TXSTA
;
693 extern __at(0x0098) volatile __TXSTAbits_t TXSTAbits
;
703 //==============================================================================
705 extern __at(0x0099) __sfr SPBRG
;
706 extern __at(0x009A) __sfr EEDATA
;
707 extern __at(0x009B) __sfr EEADR
;
709 //==============================================================================
712 extern __at(0x009C) __sfr EECON1
;
726 extern __at(0x009C) volatile __EECON1bits_t EECON1bits
;
733 //==============================================================================
735 extern __at(0x009D) __sfr EECON2
;
737 //==============================================================================
740 extern __at(0x009F) __sfr VRCON
;
763 extern __at(0x009F) volatile __VRCONbits_t VRCONbits
;
773 //==============================================================================
776 //==============================================================================
778 // Configuration Bits
780 //==============================================================================
782 #define _CONFIG 0x2007
784 //----------------------------- CONFIG Options -------------------------------
786 #define _FOSC_LP 0x3FEC // LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
787 #define _LP_OSC 0x3FEC // LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
788 #define _FOSC_XT 0x3FED // XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
789 #define _XT_OSC 0x3FED // XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
790 #define _FOSC_HS 0x3FEE // HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
791 #define _HS_OSC 0x3FEE // HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
792 #define _FOSC_ECIO 0x3FEF // EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN.
793 #define _EXTCLK_OSC 0x3FEF // EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN.
794 #define _FOSC_INTOSCIO 0x3FFC // INTOSC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN.
795 #define _INTOSC_OSC_NOCLKOUT 0x3FFC // INTOSC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN.
796 #define _INTRC_OSC_NOCLKOUT 0x3FFC // INTOSC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN.
797 #define _FOSC_INTOSCCLK 0x3FFD // INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN.
798 #define _INTOSC_OSC_CLKOUT 0x3FFD // INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN.
799 #define _INTRC_OSC_CLKOUT 0x3FFD // INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN.
800 #define _FOSC_EXTRCIO 0x3FFE // RC oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN.
801 #define _RC_OSC_NOCLKOUT 0x3FFE // RC oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN.
802 #define _ER_OSC_NOCLKOUT 0x3FFE // RC oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN.
803 #define _FOSC_EXTRCCLK 0x3FFF // RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN.
804 #define _RC_OSC_CLKOUT 0x3FFF // RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN.
805 #define _ER_OSC_CLKOUT 0x3FFF // RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN.
806 #define _WDTE_OFF 0x3FFB // WDT disabled.
807 #define _WDT_OFF 0x3FFB // WDT disabled.
808 #define _WDTE_ON 0x3FFF // WDT enabled.
809 #define _WDT_ON 0x3FFF // WDT enabled.
810 #define _PWRTE_ON 0x3FF7 // PWRT enabled.
811 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
812 #define _MCLRE_OFF 0x3FDF // RA5/MCLR/VPP pin function is digital input, MCLR internally tied to VDD.
813 #define _MCLRE_ON 0x3FFF // RA5/MCLR/VPP pin function is MCLR.
814 #define _BOREN_OFF 0x3FBF // BOD disabled.
815 #define _BODEN_OFF 0x3FBF // BOD disabled.
816 #define _BOREN_OFF 0x3FBF // BOD disabled.
817 #define _BOREN_ON 0x3FFF // BOD enabled.
818 #define _BODEN_ON 0x3FFF // BOD enabled.
819 #define _BOREN_ON 0x3FFF // BOD enabled.
820 #define _LVP_OFF 0x3F7F // RB4/PGM pin has digital I/O function, HV on MCLR must be used for programming.
821 #define _LVP_ON 0x3FFF // RB4/PGM pin has PGM function, low-voltage programming enabled.
822 #define _CPD_ON 0x3EFF // Data memory code-protected.
823 #define DATA_CP_ON 0x3EFF // Data memory code-protected.
824 #define _CPD_OFF 0x3FFF // Data memory code protection off.
825 #define DATA_CP_OFF 0x3FFF // Data memory code protection off.
826 #define _CP_ON 0x1FFF // 0000h to 07FFh code-protected.
827 #define _CP_OFF 0x3FFF // Code protection off.
829 //==============================================================================
831 #define _DEVID1 0x2006
833 #define _IDLOC0 0x2000
834 #define _IDLOC1 0x2001
835 #define _IDLOC2 0x2002
836 #define _IDLOC3 0x2003
838 //==============================================================================
840 #ifndef NO_BIT_DEFINES
842 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
843 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
844 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
845 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
846 #define CCP1Y CCP1CONbits.CCP1Y // bit 4
847 #define CCP1X CCP1CONbits.CCP1X // bit 5
849 #define CM0 CMCONbits.CM0 // bit 0
850 #define CM1 CMCONbits.CM1 // bit 1
851 #define CM2 CMCONbits.CM2 // bit 2
852 #define CIS CMCONbits.CIS // bit 3
853 #define C1INV CMCONbits.C1INV // bit 4
854 #define C2INV CMCONbits.C2INV // bit 5
855 #define C1OUT CMCONbits.C1OUT // bit 6
856 #define C2OUT CMCONbits.C2OUT // bit 7
858 #define RD EECON1bits.RD // bit 0
859 #define WR EECON1bits.WR // bit 1
860 #define WREN EECON1bits.WREN // bit 2
861 #define WRERR EECON1bits.WRERR // bit 3
863 #define RBIF INTCONbits.RBIF // bit 0
864 #define INTF INTCONbits.INTF // bit 1
865 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
866 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
867 #define RBIE INTCONbits.RBIE // bit 3
868 #define INTE INTCONbits.INTE // bit 4
869 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
870 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
871 #define PEIE INTCONbits.PEIE // bit 6
872 #define GIE INTCONbits.GIE // bit 7
874 #define PS0 OPTION_REGbits.PS0 // bit 0
875 #define PS1 OPTION_REGbits.PS1 // bit 1
876 #define PS2 OPTION_REGbits.PS2 // bit 2
877 #define PSA OPTION_REGbits.PSA // bit 3
878 #define T0SE OPTION_REGbits.T0SE // bit 4
879 #define T0CS OPTION_REGbits.T0CS // bit 5
880 #define INTEDG OPTION_REGbits.INTEDG // bit 6
881 #define NOT_RBPU OPTION_REGbits.NOT_RBPU // bit 7
883 #define NOT_BOR PCONbits.NOT_BOR // bit 0, shadows bit in PCONbits
884 #define NOT_BO PCONbits.NOT_BO // bit 0, shadows bit in PCONbits
885 #define NOT_BOD PCONbits.NOT_BOD // bit 0, shadows bit in PCONbits
886 #define NOT_POR PCONbits.NOT_POR // bit 1
887 #define OSCF PCONbits.OSCF // bit 3
889 #define TMR1IE PIE1bits.TMR1IE // bit 0
890 #define TMR2IE PIE1bits.TMR2IE // bit 1
891 #define CCP1IE PIE1bits.CCP1IE // bit 2
892 #define TXIE PIE1bits.TXIE // bit 4
893 #define RCIE PIE1bits.RCIE // bit 5
894 #define CMIE PIE1bits.CMIE // bit 6
895 #define EEIE PIE1bits.EEIE // bit 7
897 #define TMR1IF PIR1bits.TMR1IF // bit 0
898 #define TMR2IF PIR1bits.TMR2IF // bit 1
899 #define CCP1IF PIR1bits.CCP1IF // bit 2
900 #define TXIF PIR1bits.TXIF // bit 4
901 #define RCIF PIR1bits.RCIF // bit 5
902 #define CMIF PIR1bits.CMIF // bit 6
903 #define EEIF PIR1bits.EEIF // bit 7
905 #define RA0 PORTAbits.RA0 // bit 0
906 #define RA1 PORTAbits.RA1 // bit 1
907 #define RA2 PORTAbits.RA2 // bit 2
908 #define RA3 PORTAbits.RA3 // bit 3
909 #define RA4 PORTAbits.RA4 // bit 4
910 #define RA5 PORTAbits.RA5 // bit 5
911 #define RA6 PORTAbits.RA6 // bit 6
912 #define RA7 PORTAbits.RA7 // bit 7
914 #define RB0 PORTBbits.RB0 // bit 0
915 #define RB1 PORTBbits.RB1 // bit 1
916 #define RB2 PORTBbits.RB2 // bit 2
917 #define RB3 PORTBbits.RB3 // bit 3
918 #define RB4 PORTBbits.RB4 // bit 4
919 #define RB5 PORTBbits.RB5 // bit 5
920 #define RB6 PORTBbits.RB6 // bit 6
921 #define RB7 PORTBbits.RB7 // bit 7
923 #define RX9D RCSTAbits.RX9D // bit 0
924 #define OERR RCSTAbits.OERR // bit 1
925 #define FERR RCSTAbits.FERR // bit 2
926 #define ADEN RCSTAbits.ADEN // bit 3, shadows bit in RCSTAbits
927 #define ADDEN RCSTAbits.ADDEN // bit 3, shadows bit in RCSTAbits
928 #define CREN RCSTAbits.CREN // bit 4
929 #define SREN RCSTAbits.SREN // bit 5
930 #define RX9 RCSTAbits.RX9 // bit 6
931 #define SPEN RCSTAbits.SPEN // bit 7
933 #define C STATUSbits.C // bit 0
934 #define DC STATUSbits.DC // bit 1
935 #define Z STATUSbits.Z // bit 2
936 #define NOT_PD STATUSbits.NOT_PD // bit 3
937 #define NOT_TO STATUSbits.NOT_TO // bit 4
938 #define RP0 STATUSbits.RP0 // bit 5
939 #define RP1 STATUSbits.RP1 // bit 6
940 #define IRP STATUSbits.IRP // bit 7
942 #define TMR1ON T1CONbits.TMR1ON // bit 0
943 #define TMR1CS T1CONbits.TMR1CS // bit 1
944 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
945 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
946 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
947 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
949 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
950 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
951 #define TMR2ON T2CONbits.TMR2ON // bit 2
952 #define TOUTPS0 T2CONbits.TOUTPS0 // bit 3
953 #define TOUTPS1 T2CONbits.TOUTPS1 // bit 4
954 #define TOUTPS2 T2CONbits.TOUTPS2 // bit 5
955 #define TOUTPS3 T2CONbits.TOUTPS3 // bit 6
957 #define TRISA0 TRISAbits.TRISA0 // bit 0
958 #define TRISA1 TRISAbits.TRISA1 // bit 1
959 #define TRISA2 TRISAbits.TRISA2 // bit 2
960 #define TRISA3 TRISAbits.TRISA3 // bit 3
961 #define TRISA4 TRISAbits.TRISA4 // bit 4
962 #define TRISA5 TRISAbits.TRISA5 // bit 5
963 #define TRISA6 TRISAbits.TRISA6 // bit 6
964 #define TRISA7 TRISAbits.TRISA7 // bit 7
966 #define TRISB0 TRISBbits.TRISB0 // bit 0
967 #define TRISB1 TRISBbits.TRISB1 // bit 1
968 #define TRISB2 TRISBbits.TRISB2 // bit 2
969 #define TRISB3 TRISBbits.TRISB3 // bit 3
970 #define TRISB4 TRISBbits.TRISB4 // bit 4
971 #define TRISB5 TRISBbits.TRISB5 // bit 5
972 #define TRISB6 TRISBbits.TRISB6 // bit 6
973 #define TRISB7 TRISBbits.TRISB7 // bit 7
975 #define TX9D TXSTAbits.TX9D // bit 0
976 #define TRMT TXSTAbits.TRMT // bit 1
977 #define BRGH TXSTAbits.BRGH // bit 2
978 #define SYNC TXSTAbits.SYNC // bit 4
979 #define TXEN TXSTAbits.TXEN // bit 5
980 #define TX9 TXSTAbits.TX9 // bit 6
981 #define CSRC TXSTAbits.CSRC // bit 7
983 #define VR0 VRCONbits.VR0 // bit 0
984 #define VR1 VRCONbits.VR1 // bit 1
985 #define VR2 VRCONbits.VR2 // bit 2
986 #define VR3 VRCONbits.VR3 // bit 3
987 #define VRR VRCONbits.VRR // bit 5
988 #define VROE VRCONbits.VROE // bit 6
989 #define VREN VRCONbits.VREN // bit 7
991 #endif // #ifndef NO_BIT_DEFINES
993 #endif // #ifndef __PIC16F628A_H__