2 * This declarations of the PIC16LF1704 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:11 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF1704_H__
26 #define __PIC16LF1704_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTC_ADDR 0x000E
52 #define PIR1_ADDR 0x0011
53 #define PIR2_ADDR 0x0012
54 #define PIR3_ADDR 0x0013
55 #define TMR0_ADDR 0x0015
56 #define TMR1_ADDR 0x0016
57 #define TMR1L_ADDR 0x0016
58 #define TMR1H_ADDR 0x0017
59 #define T1CON_ADDR 0x0018
60 #define T1GCON_ADDR 0x0019
61 #define TMR2_ADDR 0x001A
62 #define PR2_ADDR 0x001B
63 #define T2CON_ADDR 0x001C
64 #define TRISA_ADDR 0x008C
65 #define TRISC_ADDR 0x008E
66 #define PIE1_ADDR 0x0091
67 #define PIE2_ADDR 0x0092
68 #define PIE3_ADDR 0x0093
69 #define OPTION_REG_ADDR 0x0095
70 #define PCON_ADDR 0x0096
71 #define WDTCON_ADDR 0x0097
72 #define OSCTUNE_ADDR 0x0098
73 #define OSCCON_ADDR 0x0099
74 #define OSCSTAT_ADDR 0x009A
75 #define ADRES_ADDR 0x009B
76 #define ADRESL_ADDR 0x009B
77 #define ADRESH_ADDR 0x009C
78 #define ADCON0_ADDR 0x009D
79 #define ADCON1_ADDR 0x009E
80 #define ADCON2_ADDR 0x009F
81 #define LATA_ADDR 0x010C
82 #define LATC_ADDR 0x010E
83 #define CM1CON0_ADDR 0x0111
84 #define CM1CON1_ADDR 0x0112
85 #define CM2CON0_ADDR 0x0113
86 #define CM2CON1_ADDR 0x0114
87 #define CMOUT_ADDR 0x0115
88 #define BORCON_ADDR 0x0116
89 #define FVRCON_ADDR 0x0117
90 #define DAC1CON0_ADDR 0x0118
91 #define DAC1CON1_ADDR 0x0119
92 #define ZCD1CON_ADDR 0x011C
93 #define ANSELA_ADDR 0x018C
94 #define ANSELC_ADDR 0x018E
95 #define PMADR_ADDR 0x0191
96 #define PMADRL_ADDR 0x0191
97 #define PMADRH_ADDR 0x0192
98 #define PMDAT_ADDR 0x0193
99 #define PMDATL_ADDR 0x0193
100 #define PMDATH_ADDR 0x0194
101 #define PMCON1_ADDR 0x0195
102 #define PMCON2_ADDR 0x0196
103 #define RC1REG_ADDR 0x0199
104 #define RCREG_ADDR 0x0199
105 #define RCREG1_ADDR 0x0199
106 #define TX1REG_ADDR 0x019A
107 #define TXREG_ADDR 0x019A
108 #define TXREG1_ADDR 0x019A
109 #define SP1BRG_ADDR 0x019B
110 #define SP1BRGL_ADDR 0x019B
111 #define SPBRG_ADDR 0x019B
112 #define SPBRG1_ADDR 0x019B
113 #define SPBRGL_ADDR 0x019B
114 #define SP1BRGH_ADDR 0x019C
115 #define SPBRGH_ADDR 0x019C
116 #define SPBRGH1_ADDR 0x019C
117 #define RC1STA_ADDR 0x019D
118 #define RCSTA_ADDR 0x019D
119 #define RCSTA1_ADDR 0x019D
120 #define TX1STA_ADDR 0x019E
121 #define TXSTA_ADDR 0x019E
122 #define TXSTA1_ADDR 0x019E
123 #define BAUD1CON_ADDR 0x019F
124 #define BAUDCON_ADDR 0x019F
125 #define BAUDCON1_ADDR 0x019F
126 #define BAUDCTL_ADDR 0x019F
127 #define BAUDCTL1_ADDR 0x019F
128 #define WPUA_ADDR 0x020C
129 #define WPUC_ADDR 0x020E
130 #define SSP1BUF_ADDR 0x0211
131 #define SSPBUF_ADDR 0x0211
132 #define SSP1ADD_ADDR 0x0212
133 #define SSPADD_ADDR 0x0212
134 #define SSP1MSK_ADDR 0x0213
135 #define SSPMSK_ADDR 0x0213
136 #define SSP1STAT_ADDR 0x0214
137 #define SSPSTAT_ADDR 0x0214
138 #define SSP1CON_ADDR 0x0215
139 #define SSP1CON1_ADDR 0x0215
140 #define SSPCON_ADDR 0x0215
141 #define SSPCON1_ADDR 0x0215
142 #define SSP1CON2_ADDR 0x0216
143 #define SSPCON2_ADDR 0x0216
144 #define SSP1CON3_ADDR 0x0217
145 #define SSPCON3_ADDR 0x0217
146 #define ODCONA_ADDR 0x028C
147 #define ODCONC_ADDR 0x028E
148 #define CCPR1_ADDR 0x0291
149 #define CCPR1L_ADDR 0x0291
150 #define CCPR1H_ADDR 0x0292
151 #define CCP1CON_ADDR 0x0293
152 #define ECCP1CON_ADDR 0x0293
153 #define CCPR2_ADDR 0x0298
154 #define CCPR2L_ADDR 0x0298
155 #define CCPR2H_ADDR 0x0299
156 #define CCP2CON_ADDR 0x029A
157 #define ECCP2CON_ADDR 0x029A
158 #define CCPTMRS_ADDR 0x029E
159 #define SLRCONA_ADDR 0x030C
160 #define SLRCONC_ADDR 0x030E
161 #define INLVLA_ADDR 0x038C
162 #define INLVLC_ADDR 0x038E
163 #define IOCAP_ADDR 0x0391
164 #define IOCAN_ADDR 0x0392
165 #define IOCAF_ADDR 0x0393
166 #define IOCCP_ADDR 0x0397
167 #define IOCCN_ADDR 0x0398
168 #define IOCCF_ADDR 0x0399
169 #define TMR4_ADDR 0x0415
170 #define PR4_ADDR 0x0416
171 #define T4CON_ADDR 0x0417
172 #define TMR6_ADDR 0x041C
173 #define PR6_ADDR 0x041D
174 #define T6CON_ADDR 0x041E
175 #define OPA1CON_ADDR 0x0511
176 #define OPA2CON_ADDR 0x0515
177 #define PWM3DCL_ADDR 0x0617
178 #define PWM3DCH_ADDR 0x0618
179 #define PWM3CON_ADDR 0x0619
180 #define PWM3CON0_ADDR 0x0619
181 #define PWM4DCL_ADDR 0x061A
182 #define PWM4DCH_ADDR 0x061B
183 #define PWM4CON_ADDR 0x061C
184 #define PWM4CON0_ADDR 0x061C
185 #define COG1PHR_ADDR 0x0691
186 #define COG1PHF_ADDR 0x0692
187 #define COG1BLKR_ADDR 0x0693
188 #define COG1BLKF_ADDR 0x0694
189 #define COG1DBR_ADDR 0x0695
190 #define COG1DBF_ADDR 0x0696
191 #define COG1CON0_ADDR 0x0697
192 #define COG1CON1_ADDR 0x0698
193 #define COG1RIS_ADDR 0x0699
194 #define COG1RSIM_ADDR 0x069A
195 #define COG1FIS_ADDR 0x069B
196 #define COG1FSIM_ADDR 0x069C
197 #define COG1ASD0_ADDR 0x069D
198 #define COG1ASD1_ADDR 0x069E
199 #define COG1STR_ADDR 0x069F
200 #define PPSLOCK_ADDR 0x0E0F
201 #define INTPPS_ADDR 0x0E10
202 #define T0CKIPPS_ADDR 0x0E11
203 #define T1CKIPPS_ADDR 0x0E12
204 #define T1GPPS_ADDR 0x0E13
205 #define CCP1PPS_ADDR 0x0E14
206 #define CCP2PPS_ADDR 0x0E15
207 #define COGINPPS_ADDR 0x0E17
208 #define SSPCLKPPS_ADDR 0x0E20
209 #define SSPDATPPS_ADDR 0x0E21
210 #define SSPSSPPS_ADDR 0x0E22
211 #define RXPPS_ADDR 0x0E24
212 #define CKPPS_ADDR 0x0E25
213 #define CLCIN0PPS_ADDR 0x0E28
214 #define CLCIN1PPS_ADDR 0x0E29
215 #define CLCIN2PPS_ADDR 0x0E2A
216 #define CLCIN3PPS_ADDR 0x0E2B
217 #define RA0PPS_ADDR 0x0E90
218 #define RA1PPS_ADDR 0x0E91
219 #define RA2PPS_ADDR 0x0E92
220 #define RA4PPS_ADDR 0x0E94
221 #define RA5PPS_ADDR 0x0E95
222 #define RC0PPS_ADDR 0x0EA0
223 #define RC1PPS_ADDR 0x0EA1
224 #define RC2PPS_ADDR 0x0EA2
225 #define RC3PPS_ADDR 0x0EA3
226 #define RC4PPS_ADDR 0x0EA4
227 #define RC5PPS_ADDR 0x0EA5
228 #define CLCDATA_ADDR 0x0F0F
229 #define CLC1CON_ADDR 0x0F10
230 #define CLC1POL_ADDR 0x0F11
231 #define CLC1SEL0_ADDR 0x0F12
232 #define CLC1SEL1_ADDR 0x0F13
233 #define CLC1SEL2_ADDR 0x0F14
234 #define CLC1SEL3_ADDR 0x0F15
235 #define CLC1GLS0_ADDR 0x0F16
236 #define CLC1GLS1_ADDR 0x0F17
237 #define CLC1GLS2_ADDR 0x0F18
238 #define CLC1GLS3_ADDR 0x0F19
239 #define CLC2CON_ADDR 0x0F1A
240 #define CLC2POL_ADDR 0x0F1B
241 #define CLC2SEL0_ADDR 0x0F1C
242 #define CLC2SEL1_ADDR 0x0F1D
243 #define CLC2SEL2_ADDR 0x0F1E
244 #define CLC2SEL3_ADDR 0x0F1F
245 #define CLC2GLS0_ADDR 0x0F20
246 #define CLC2GLS1_ADDR 0x0F21
247 #define CLC2GLS2_ADDR 0x0F22
248 #define CLC2GLS3_ADDR 0x0F23
249 #define CLC3CON_ADDR 0x0F24
250 #define CLC3POL_ADDR 0x0F25
251 #define CLC3SEL0_ADDR 0x0F26
252 #define CLC3SEL1_ADDR 0x0F27
253 #define CLC3SEL2_ADDR 0x0F28
254 #define CLC3SEL3_ADDR 0x0F29
255 #define CLC3GLS0_ADDR 0x0F2A
256 #define CLC3GLS1_ADDR 0x0F2B
257 #define CLC3GLS2_ADDR 0x0F2C
258 #define CLC3GLS3_ADDR 0x0F2D
259 #define STATUS_SHAD_ADDR 0x0FE4
260 #define WREG_SHAD_ADDR 0x0FE5
261 #define BSR_SHAD_ADDR 0x0FE6
262 #define PCLATH_SHAD_ADDR 0x0FE7
263 #define FSR0L_SHAD_ADDR 0x0FE8
264 #define FSR0H_SHAD_ADDR 0x0FE9
265 #define FSR1L_SHAD_ADDR 0x0FEA
266 #define FSR1H_SHAD_ADDR 0x0FEB
267 #define STKPTR_ADDR 0x0FED
268 #define TOSL_ADDR 0x0FEE
269 #define TOSH_ADDR 0x0FEF
271 #endif // #ifndef NO_ADDR_DEFINES
273 //==============================================================================
275 // Register Definitions
277 //==============================================================================
279 extern __at(0x0000) __sfr INDF0
;
280 extern __at(0x0001) __sfr INDF1
;
281 extern __at(0x0002) __sfr PCL
;
283 //==============================================================================
286 extern __at(0x0003) __sfr STATUS
;
300 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
308 //==============================================================================
310 extern __at(0x0004) __sfr FSR0
;
311 extern __at(0x0004) __sfr FSR0L
;
312 extern __at(0x0005) __sfr FSR0H
;
313 extern __at(0x0006) __sfr FSR1
;
314 extern __at(0x0006) __sfr FSR1L
;
315 extern __at(0x0007) __sfr FSR1H
;
317 //==============================================================================
320 extern __at(0x0008) __sfr BSR
;
343 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
351 //==============================================================================
353 extern __at(0x0009) __sfr WREG
;
354 extern __at(0x000A) __sfr PCLATH
;
356 //==============================================================================
359 extern __at(0x000B) __sfr INTCON
;
388 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
401 //==============================================================================
404 //==============================================================================
407 extern __at(0x000C) __sfr PORTA
;
430 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
439 //==============================================================================
442 //==============================================================================
445 extern __at(0x000E) __sfr PORTC
;
468 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
477 //==============================================================================
480 //==============================================================================
483 extern __at(0x0011) __sfr PIR1
;
496 unsigned TMR1GIF
: 1;
512 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
522 #define _TMR1GIF 0x80
524 //==============================================================================
527 //==============================================================================
530 extern __at(0x0012) __sfr PIR2
;
544 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
554 //==============================================================================
557 //==============================================================================
560 extern __at(0x0013) __sfr PIR3
;
574 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
582 //==============================================================================
584 extern __at(0x0015) __sfr TMR0
;
585 extern __at(0x0016) __sfr TMR1
;
586 extern __at(0x0016) __sfr TMR1L
;
587 extern __at(0x0017) __sfr TMR1H
;
589 //==============================================================================
592 extern __at(0x0018) __sfr T1CON
;
600 unsigned NOT_T1SYNC
: 1;
601 unsigned T1OSCEN
: 1;
602 unsigned T1CKPS0
: 1;
603 unsigned T1CKPS1
: 1;
604 unsigned TMR1CS0
: 1;
605 unsigned TMR1CS1
: 1;
622 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
625 #define _NOT_T1SYNC 0x04
626 #define _T1OSCEN 0x08
627 #define _T1CKPS0 0x10
628 #define _T1CKPS1 0x20
629 #define _TMR1CS0 0x40
630 #define _TMR1CS1 0x80
632 //==============================================================================
635 //==============================================================================
638 extern __at(0x0019) __sfr T1GCON
;
647 unsigned T1GGO_NOT_DONE
: 1;
661 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
666 #define _T1GGO_NOT_DONE 0x08
672 //==============================================================================
674 extern __at(0x001A) __sfr TMR2
;
675 extern __at(0x001B) __sfr PR2
;
677 //==============================================================================
680 extern __at(0x001C) __sfr T2CON
;
686 unsigned T2CKPS0
: 1;
687 unsigned T2CKPS1
: 1;
689 unsigned T2OUTPS0
: 1;
690 unsigned T2OUTPS1
: 1;
691 unsigned T2OUTPS2
: 1;
692 unsigned T2OUTPS3
: 1;
705 unsigned T2OUTPS
: 4;
710 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
712 #define _T2CKPS0 0x01
713 #define _T2CKPS1 0x02
715 #define _T2OUTPS0 0x08
716 #define _T2OUTPS1 0x10
717 #define _T2OUTPS2 0x20
718 #define _T2OUTPS3 0x40
720 //==============================================================================
723 //==============================================================================
726 extern __at(0x008C) __sfr TRISA
;
740 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
748 //==============================================================================
751 //==============================================================================
754 extern __at(0x008E) __sfr TRISC
;
777 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
786 //==============================================================================
789 //==============================================================================
792 extern __at(0x0091) __sfr PIE1
;
805 unsigned TMR1GIE
: 1;
821 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
831 #define _TMR1GIE 0x80
833 //==============================================================================
836 //==============================================================================
839 extern __at(0x0092) __sfr PIE2
;
853 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
863 //==============================================================================
866 //==============================================================================
869 extern __at(0x0093) __sfr PIE3
;
883 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
891 //==============================================================================
894 //==============================================================================
897 extern __at(0x0095) __sfr OPTION_REG
;
910 unsigned NOT_WPUEN
: 1;
930 } __OPTION_REGbits_t
;
932 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
943 #define _NOT_WPUEN 0x80
945 //==============================================================================
948 //==============================================================================
951 extern __at(0x0096) __sfr PCON
;
955 unsigned NOT_BOR
: 1;
956 unsigned NOT_POR
: 1;
958 unsigned NOT_RMCLR
: 1;
959 unsigned NOT_RWDT
: 1;
965 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
967 #define _NOT_BOR 0x01
968 #define _NOT_POR 0x02
970 #define _NOT_RMCLR 0x08
971 #define _NOT_RWDT 0x10
975 //==============================================================================
978 //==============================================================================
981 extern __at(0x0097) __sfr WDTCON
;
1005 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1007 #define _SWDTEN 0x01
1008 #define _WDTPS0 0x02
1009 #define _WDTPS1 0x04
1010 #define _WDTPS2 0x08
1011 #define _WDTPS3 0x10
1012 #define _WDTPS4 0x20
1014 //==============================================================================
1017 //==============================================================================
1020 extern __at(0x0098) __sfr OSCTUNE
;
1043 extern __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits
;
1052 //==============================================================================
1055 //==============================================================================
1058 extern __at(0x0099) __sfr OSCCON
;
1071 unsigned SPLLEN
: 1;
1088 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
1096 #define _SPLLEN 0x80
1098 //==============================================================================
1101 //==============================================================================
1104 extern __at(0x009A) __sfr OSCSTAT
;
1108 unsigned HFIOFS
: 1;
1109 unsigned LFIOFR
: 1;
1110 unsigned MFIOFR
: 1;
1111 unsigned HFIOFL
: 1;
1112 unsigned HFIOFR
: 1;
1118 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
1120 #define _HFIOFS 0x01
1121 #define _LFIOFR 0x02
1122 #define _MFIOFR 0x04
1123 #define _HFIOFL 0x08
1124 #define _HFIOFR 0x10
1129 //==============================================================================
1131 extern __at(0x009B) __sfr ADRES
;
1132 extern __at(0x009B) __sfr ADRESL
;
1133 extern __at(0x009C) __sfr ADRESH
;
1135 //==============================================================================
1138 extern __at(0x009D) __sfr ADCON0
;
1145 unsigned GO_NOT_DONE
: 1;
1186 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1189 #define _GO_NOT_DONE 0x02
1198 //==============================================================================
1201 //==============================================================================
1204 extern __at(0x009E) __sfr ADCON1
;
1210 unsigned ADPREF0
: 1;
1211 unsigned ADPREF1
: 1;
1212 unsigned ADNREF
: 1;
1222 unsigned ADPREF
: 2;
1234 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1236 #define _ADPREF0 0x01
1237 #define _ADPREF1 0x02
1238 #define _ADNREF 0x04
1244 //==============================================================================
1247 //==============================================================================
1250 extern __at(0x009F) __sfr ADCON2
;
1260 unsigned TRIGSEL0
: 1;
1261 unsigned TRIGSEL1
: 1;
1262 unsigned TRIGSEL2
: 1;
1263 unsigned TRIGSEL3
: 1;
1269 unsigned TRIGSEL
: 4;
1273 extern __at(0x009F) volatile __ADCON2bits_t ADCON2bits
;
1275 #define _TRIGSEL0 0x10
1276 #define _TRIGSEL1 0x20
1277 #define _TRIGSEL2 0x40
1278 #define _TRIGSEL3 0x80
1280 //==============================================================================
1283 //==============================================================================
1286 extern __at(0x010C) __sfr LATA
;
1300 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1308 //==============================================================================
1311 //==============================================================================
1314 extern __at(0x010E) __sfr LATC
;
1337 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1346 //==============================================================================
1349 //==============================================================================
1352 extern __at(0x0111) __sfr CM1CON0
;
1356 unsigned C1SYNC
: 1;
1366 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1368 #define _C1SYNC 0x01
1376 //==============================================================================
1379 //==============================================================================
1382 extern __at(0x0112) __sfr CM1CON1
;
1388 unsigned C1NCH0
: 1;
1389 unsigned C1NCH1
: 1;
1390 unsigned C1NCH2
: 1;
1391 unsigned C1PCH0
: 1;
1392 unsigned C1PCH1
: 1;
1393 unsigned C1PCH2
: 1;
1394 unsigned C1INTN
: 1;
1395 unsigned C1INTP
: 1;
1412 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1414 #define _C1NCH0 0x01
1415 #define _C1NCH1 0x02
1416 #define _C1NCH2 0x04
1417 #define _C1PCH0 0x08
1418 #define _C1PCH1 0x10
1419 #define _C1PCH2 0x20
1420 #define _C1INTN 0x40
1421 #define _C1INTP 0x80
1423 //==============================================================================
1426 //==============================================================================
1429 extern __at(0x0113) __sfr CM2CON0
;
1433 unsigned C2SYNC
: 1;
1443 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1445 #define _C2SYNC 0x01
1453 //==============================================================================
1456 //==============================================================================
1459 extern __at(0x0114) __sfr CM2CON1
;
1465 unsigned C2NCH0
: 1;
1466 unsigned C2NCH1
: 1;
1467 unsigned C2NCH2
: 1;
1468 unsigned C2PCH0
: 1;
1469 unsigned C2PCH1
: 1;
1470 unsigned C2PCH2
: 1;
1471 unsigned C2INTN
: 1;
1472 unsigned C2INTP
: 1;
1489 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1491 #define _C2NCH0 0x01
1492 #define _C2NCH1 0x02
1493 #define _C2NCH2 0x04
1494 #define _C2PCH0 0x08
1495 #define _C2PCH1 0x10
1496 #define _C2PCH2 0x20
1497 #define _C2INTN 0x40
1498 #define _C2INTP 0x80
1500 //==============================================================================
1503 //==============================================================================
1506 extern __at(0x0115) __sfr CMOUT
;
1510 unsigned MC1OUT
: 1;
1511 unsigned MC2OUT
: 1;
1520 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1522 #define _MC1OUT 0x01
1523 #define _MC2OUT 0x02
1525 //==============================================================================
1528 //==============================================================================
1531 extern __at(0x0116) __sfr BORCON
;
1535 unsigned BORRDY
: 1;
1542 unsigned SBOREN
: 1;
1545 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1547 #define _BORRDY 0x01
1549 #define _SBOREN 0x80
1551 //==============================================================================
1554 //==============================================================================
1557 extern __at(0x0117) __sfr FVRCON
;
1563 unsigned ADFVR0
: 1;
1564 unsigned ADFVR1
: 1;
1565 unsigned CDAFVR0
: 1;
1566 unsigned CDAFVR1
: 1;
1569 unsigned FVRRDY
: 1;
1582 unsigned CDAFVR
: 2;
1587 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1589 #define _ADFVR0 0x01
1590 #define _ADFVR1 0x02
1591 #define _CDAFVR0 0x04
1592 #define _CDAFVR1 0x08
1595 #define _FVRRDY 0x40
1598 //==============================================================================
1601 //==============================================================================
1604 extern __at(0x0118) __sfr DAC1CON0
;
1610 unsigned DAC1NSS
: 1;
1612 unsigned DAC1PSS0
: 1;
1613 unsigned DAC1PSS1
: 1;
1614 unsigned DAC1OE2
: 1;
1615 unsigned DAC1OE1
: 1;
1617 unsigned DAC1EN
: 1;
1622 unsigned DACNSS
: 1;
1624 unsigned DACPSS0
: 1;
1625 unsigned DACPSS1
: 1;
1626 unsigned DACOE0
: 1;
1627 unsigned DACOE1
: 1;
1635 unsigned DACPSS
: 2;
1642 unsigned DAC1PSS
: 2;
1654 extern __at(0x0118) volatile __DAC1CON0bits_t DAC1CON0bits
;
1656 #define _DAC1NSS 0x01
1657 #define _DACNSS 0x01
1658 #define _DAC1PSS0 0x04
1659 #define _DACPSS0 0x04
1660 #define _DAC1PSS1 0x08
1661 #define _DACPSS1 0x08
1662 #define _DAC1OE2 0x10
1663 #define _DACOE0 0x10
1664 #define _DAC1OE1 0x20
1665 #define _DACOE1 0x20
1666 #define _DAC1EN 0x80
1669 //==============================================================================
1672 //==============================================================================
1675 extern __at(0x0119) __sfr DAC1CON1
;
1681 unsigned DAC1R0
: 1;
1682 unsigned DAC1R1
: 1;
1683 unsigned DAC1R2
: 1;
1684 unsigned DAC1R3
: 1;
1685 unsigned DAC1R4
: 1;
1686 unsigned DAC1R5
: 1;
1687 unsigned DAC1R6
: 1;
1688 unsigned DAC1R7
: 1;
1704 extern __at(0x0119) volatile __DAC1CON1bits_t DAC1CON1bits
;
1706 #define _DAC1R0 0x01
1708 #define _DAC1R1 0x02
1710 #define _DAC1R2 0x04
1712 #define _DAC1R3 0x08
1714 #define _DAC1R4 0x10
1716 #define _DAC1R5 0x20
1718 #define _DAC1R6 0x40
1720 #define _DAC1R7 0x80
1723 //==============================================================================
1726 //==============================================================================
1729 extern __at(0x011C) __sfr ZCD1CON
;
1733 unsigned ZCD1INTN
: 1;
1734 unsigned ZCD1INTP
: 1;
1737 unsigned ZCD1POL
: 1;
1738 unsigned ZCD1OUT
: 1;
1740 unsigned ZCD1EN
: 1;
1743 extern __at(0x011C) volatile __ZCD1CONbits_t ZCD1CONbits
;
1745 #define _ZCD1INTN 0x01
1746 #define _ZCD1INTP 0x02
1747 #define _ZCD1POL 0x10
1748 #define _ZCD1OUT 0x20
1749 #define _ZCD1EN 0x80
1751 //==============================================================================
1754 //==============================================================================
1757 extern __at(0x018C) __sfr ANSELA
;
1771 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1779 //==============================================================================
1782 //==============================================================================
1785 extern __at(0x018E) __sfr ANSELC
;
1808 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1817 //==============================================================================
1819 extern __at(0x0191) __sfr PMADR
;
1820 extern __at(0x0191) __sfr PMADRL
;
1821 extern __at(0x0192) __sfr PMADRH
;
1822 extern __at(0x0193) __sfr PMDAT
;
1823 extern __at(0x0193) __sfr PMDATL
;
1824 extern __at(0x0194) __sfr PMDATH
;
1826 //==============================================================================
1829 extern __at(0x0195) __sfr PMCON1
;
1843 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
1853 //==============================================================================
1855 extern __at(0x0196) __sfr PMCON2
;
1856 extern __at(0x0199) __sfr RC1REG
;
1857 extern __at(0x0199) __sfr RCREG
;
1858 extern __at(0x0199) __sfr RCREG1
;
1859 extern __at(0x019A) __sfr TX1REG
;
1860 extern __at(0x019A) __sfr TXREG
;
1861 extern __at(0x019A) __sfr TXREG1
;
1862 extern __at(0x019B) __sfr SP1BRG
;
1863 extern __at(0x019B) __sfr SP1BRGL
;
1864 extern __at(0x019B) __sfr SPBRG
;
1865 extern __at(0x019B) __sfr SPBRG1
;
1866 extern __at(0x019B) __sfr SPBRGL
;
1867 extern __at(0x019C) __sfr SP1BRGH
;
1868 extern __at(0x019C) __sfr SPBRGH
;
1869 extern __at(0x019C) __sfr SPBRGH1
;
1871 //==============================================================================
1874 extern __at(0x019D) __sfr RC1STA
;
1888 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1899 //==============================================================================
1902 //==============================================================================
1905 extern __at(0x019D) __sfr RCSTA
;
1919 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1921 #define _RCSTA_RX9D 0x01
1922 #define _RCSTA_OERR 0x02
1923 #define _RCSTA_FERR 0x04
1924 #define _RCSTA_ADDEN 0x08
1925 #define _RCSTA_CREN 0x10
1926 #define _RCSTA_SREN 0x20
1927 #define _RCSTA_RX9 0x40
1928 #define _RCSTA_SPEN 0x80
1930 //==============================================================================
1933 //==============================================================================
1936 extern __at(0x019D) __sfr RCSTA1
;
1950 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
1952 #define _RCSTA1_RX9D 0x01
1953 #define _RCSTA1_OERR 0x02
1954 #define _RCSTA1_FERR 0x04
1955 #define _RCSTA1_ADDEN 0x08
1956 #define _RCSTA1_CREN 0x10
1957 #define _RCSTA1_SREN 0x20
1958 #define _RCSTA1_RX9 0x40
1959 #define _RCSTA1_SPEN 0x80
1961 //==============================================================================
1964 //==============================================================================
1967 extern __at(0x019E) __sfr TX1STA
;
1981 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
1992 //==============================================================================
1995 //==============================================================================
1998 extern __at(0x019E) __sfr TXSTA
;
2012 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2014 #define _TXSTA_TX9D 0x01
2015 #define _TXSTA_TRMT 0x02
2016 #define _TXSTA_BRGH 0x04
2017 #define _TXSTA_SENDB 0x08
2018 #define _TXSTA_SYNC 0x10
2019 #define _TXSTA_TXEN 0x20
2020 #define _TXSTA_TX9 0x40
2021 #define _TXSTA_CSRC 0x80
2023 //==============================================================================
2026 //==============================================================================
2029 extern __at(0x019E) __sfr TXSTA1
;
2043 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2045 #define _TXSTA1_TX9D 0x01
2046 #define _TXSTA1_TRMT 0x02
2047 #define _TXSTA1_BRGH 0x04
2048 #define _TXSTA1_SENDB 0x08
2049 #define _TXSTA1_SYNC 0x10
2050 #define _TXSTA1_TXEN 0x20
2051 #define _TXSTA1_TX9 0x40
2052 #define _TXSTA1_CSRC 0x80
2054 //==============================================================================
2057 //==============================================================================
2060 extern __at(0x019F) __sfr BAUD1CON
;
2071 unsigned ABDOVF
: 1;
2074 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2081 #define _ABDOVF 0x80
2083 //==============================================================================
2086 //==============================================================================
2089 extern __at(0x019F) __sfr BAUDCON
;
2100 unsigned ABDOVF
: 1;
2103 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2105 #define _BAUDCON_ABDEN 0x01
2106 #define _BAUDCON_WUE 0x02
2107 #define _BAUDCON_BRG16 0x08
2108 #define _BAUDCON_SCKP 0x10
2109 #define _BAUDCON_RCIDL 0x40
2110 #define _BAUDCON_ABDOVF 0x80
2112 //==============================================================================
2115 //==============================================================================
2118 extern __at(0x019F) __sfr BAUDCON1
;
2129 unsigned ABDOVF
: 1;
2132 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2134 #define _BAUDCON1_ABDEN 0x01
2135 #define _BAUDCON1_WUE 0x02
2136 #define _BAUDCON1_BRG16 0x08
2137 #define _BAUDCON1_SCKP 0x10
2138 #define _BAUDCON1_RCIDL 0x40
2139 #define _BAUDCON1_ABDOVF 0x80
2141 //==============================================================================
2144 //==============================================================================
2147 extern __at(0x019F) __sfr BAUDCTL
;
2158 unsigned ABDOVF
: 1;
2161 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2163 #define _BAUDCTL_ABDEN 0x01
2164 #define _BAUDCTL_WUE 0x02
2165 #define _BAUDCTL_BRG16 0x08
2166 #define _BAUDCTL_SCKP 0x10
2167 #define _BAUDCTL_RCIDL 0x40
2168 #define _BAUDCTL_ABDOVF 0x80
2170 //==============================================================================
2173 //==============================================================================
2176 extern __at(0x019F) __sfr BAUDCTL1
;
2187 unsigned ABDOVF
: 1;
2190 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2192 #define _BAUDCTL1_ABDEN 0x01
2193 #define _BAUDCTL1_WUE 0x02
2194 #define _BAUDCTL1_BRG16 0x08
2195 #define _BAUDCTL1_SCKP 0x10
2196 #define _BAUDCTL1_RCIDL 0x40
2197 #define _BAUDCTL1_ABDOVF 0x80
2199 //==============================================================================
2202 //==============================================================================
2205 extern __at(0x020C) __sfr WPUA
;
2228 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2237 //==============================================================================
2240 //==============================================================================
2243 extern __at(0x020E) __sfr WPUC
;
2266 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2275 //==============================================================================
2278 //==============================================================================
2281 extern __at(0x0211) __sfr SSP1BUF
;
2287 unsigned SSP1BUF0
: 1;
2288 unsigned SSP1BUF1
: 1;
2289 unsigned SSP1BUF2
: 1;
2290 unsigned SSP1BUF3
: 1;
2291 unsigned SSP1BUF4
: 1;
2292 unsigned SSP1BUF5
: 1;
2293 unsigned SSP1BUF6
: 1;
2294 unsigned SSP1BUF7
: 1;
2310 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2312 #define _SSP1BUF0 0x01
2314 #define _SSP1BUF1 0x02
2316 #define _SSP1BUF2 0x04
2318 #define _SSP1BUF3 0x08
2320 #define _SSP1BUF4 0x10
2322 #define _SSP1BUF5 0x20
2324 #define _SSP1BUF6 0x40
2326 #define _SSP1BUF7 0x80
2329 //==============================================================================
2332 //==============================================================================
2335 extern __at(0x0211) __sfr SSPBUF
;
2341 unsigned SSP1BUF0
: 1;
2342 unsigned SSP1BUF1
: 1;
2343 unsigned SSP1BUF2
: 1;
2344 unsigned SSP1BUF3
: 1;
2345 unsigned SSP1BUF4
: 1;
2346 unsigned SSP1BUF5
: 1;
2347 unsigned SSP1BUF6
: 1;
2348 unsigned SSP1BUF7
: 1;
2364 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2366 #define _SSPBUF_SSP1BUF0 0x01
2367 #define _SSPBUF_BUF0 0x01
2368 #define _SSPBUF_SSP1BUF1 0x02
2369 #define _SSPBUF_BUF1 0x02
2370 #define _SSPBUF_SSP1BUF2 0x04
2371 #define _SSPBUF_BUF2 0x04
2372 #define _SSPBUF_SSP1BUF3 0x08
2373 #define _SSPBUF_BUF3 0x08
2374 #define _SSPBUF_SSP1BUF4 0x10
2375 #define _SSPBUF_BUF4 0x10
2376 #define _SSPBUF_SSP1BUF5 0x20
2377 #define _SSPBUF_BUF5 0x20
2378 #define _SSPBUF_SSP1BUF6 0x40
2379 #define _SSPBUF_BUF6 0x40
2380 #define _SSPBUF_SSP1BUF7 0x80
2381 #define _SSPBUF_BUF7 0x80
2383 //==============================================================================
2386 //==============================================================================
2389 extern __at(0x0212) __sfr SSP1ADD
;
2395 unsigned SSP1ADD0
: 1;
2396 unsigned SSP1ADD1
: 1;
2397 unsigned SSP1ADD2
: 1;
2398 unsigned SSP1ADD3
: 1;
2399 unsigned SSP1ADD4
: 1;
2400 unsigned SSP1ADD5
: 1;
2401 unsigned SSP1ADD6
: 1;
2402 unsigned SSP1ADD7
: 1;
2418 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2420 #define _SSP1ADD0 0x01
2422 #define _SSP1ADD1 0x02
2424 #define _SSP1ADD2 0x04
2426 #define _SSP1ADD3 0x08
2428 #define _SSP1ADD4 0x10
2430 #define _SSP1ADD5 0x20
2432 #define _SSP1ADD6 0x40
2434 #define _SSP1ADD7 0x80
2437 //==============================================================================
2440 //==============================================================================
2443 extern __at(0x0212) __sfr SSPADD
;
2449 unsigned SSP1ADD0
: 1;
2450 unsigned SSP1ADD1
: 1;
2451 unsigned SSP1ADD2
: 1;
2452 unsigned SSP1ADD3
: 1;
2453 unsigned SSP1ADD4
: 1;
2454 unsigned SSP1ADD5
: 1;
2455 unsigned SSP1ADD6
: 1;
2456 unsigned SSP1ADD7
: 1;
2472 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2474 #define _SSPADD_SSP1ADD0 0x01
2475 #define _SSPADD_ADD0 0x01
2476 #define _SSPADD_SSP1ADD1 0x02
2477 #define _SSPADD_ADD1 0x02
2478 #define _SSPADD_SSP1ADD2 0x04
2479 #define _SSPADD_ADD2 0x04
2480 #define _SSPADD_SSP1ADD3 0x08
2481 #define _SSPADD_ADD3 0x08
2482 #define _SSPADD_SSP1ADD4 0x10
2483 #define _SSPADD_ADD4 0x10
2484 #define _SSPADD_SSP1ADD5 0x20
2485 #define _SSPADD_ADD5 0x20
2486 #define _SSPADD_SSP1ADD6 0x40
2487 #define _SSPADD_ADD6 0x40
2488 #define _SSPADD_SSP1ADD7 0x80
2489 #define _SSPADD_ADD7 0x80
2491 //==============================================================================
2494 //==============================================================================
2497 extern __at(0x0213) __sfr SSP1MSK
;
2503 unsigned SSP1MSK0
: 1;
2504 unsigned SSP1MSK1
: 1;
2505 unsigned SSP1MSK2
: 1;
2506 unsigned SSP1MSK3
: 1;
2507 unsigned SSP1MSK4
: 1;
2508 unsigned SSP1MSK5
: 1;
2509 unsigned SSP1MSK6
: 1;
2510 unsigned SSP1MSK7
: 1;
2526 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2528 #define _SSP1MSK0 0x01
2530 #define _SSP1MSK1 0x02
2532 #define _SSP1MSK2 0x04
2534 #define _SSP1MSK3 0x08
2536 #define _SSP1MSK4 0x10
2538 #define _SSP1MSK5 0x20
2540 #define _SSP1MSK6 0x40
2542 #define _SSP1MSK7 0x80
2545 //==============================================================================
2548 //==============================================================================
2551 extern __at(0x0213) __sfr SSPMSK
;
2557 unsigned SSP1MSK0
: 1;
2558 unsigned SSP1MSK1
: 1;
2559 unsigned SSP1MSK2
: 1;
2560 unsigned SSP1MSK3
: 1;
2561 unsigned SSP1MSK4
: 1;
2562 unsigned SSP1MSK5
: 1;
2563 unsigned SSP1MSK6
: 1;
2564 unsigned SSP1MSK7
: 1;
2580 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2582 #define _SSPMSK_SSP1MSK0 0x01
2583 #define _SSPMSK_MSK0 0x01
2584 #define _SSPMSK_SSP1MSK1 0x02
2585 #define _SSPMSK_MSK1 0x02
2586 #define _SSPMSK_SSP1MSK2 0x04
2587 #define _SSPMSK_MSK2 0x04
2588 #define _SSPMSK_SSP1MSK3 0x08
2589 #define _SSPMSK_MSK3 0x08
2590 #define _SSPMSK_SSP1MSK4 0x10
2591 #define _SSPMSK_MSK4 0x10
2592 #define _SSPMSK_SSP1MSK5 0x20
2593 #define _SSPMSK_MSK5 0x20
2594 #define _SSPMSK_SSP1MSK6 0x40
2595 #define _SSPMSK_MSK6 0x40
2596 #define _SSPMSK_SSP1MSK7 0x80
2597 #define _SSPMSK_MSK7 0x80
2599 //==============================================================================
2602 //==============================================================================
2605 extern __at(0x0214) __sfr SSP1STAT
;
2611 unsigned R_NOT_W
: 1;
2614 unsigned D_NOT_A
: 1;
2619 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2623 #define _R_NOT_W 0x04
2626 #define _D_NOT_A 0x20
2630 //==============================================================================
2633 //==============================================================================
2636 extern __at(0x0214) __sfr SSPSTAT
;
2642 unsigned R_NOT_W
: 1;
2645 unsigned D_NOT_A
: 1;
2650 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2652 #define _SSPSTAT_BF 0x01
2653 #define _SSPSTAT_UA 0x02
2654 #define _SSPSTAT_R_NOT_W 0x04
2655 #define _SSPSTAT_S 0x08
2656 #define _SSPSTAT_P 0x10
2657 #define _SSPSTAT_D_NOT_A 0x20
2658 #define _SSPSTAT_CKE 0x40
2659 #define _SSPSTAT_SMP 0x80
2661 //==============================================================================
2664 //==============================================================================
2667 extern __at(0x0215) __sfr SSP1CON
;
2690 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2701 //==============================================================================
2704 //==============================================================================
2707 extern __at(0x0215) __sfr SSP1CON1
;
2730 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2732 #define _SSP1CON1_SSPM0 0x01
2733 #define _SSP1CON1_SSPM1 0x02
2734 #define _SSP1CON1_SSPM2 0x04
2735 #define _SSP1CON1_SSPM3 0x08
2736 #define _SSP1CON1_CKP 0x10
2737 #define _SSP1CON1_SSPEN 0x20
2738 #define _SSP1CON1_SSPOV 0x40
2739 #define _SSP1CON1_WCOL 0x80
2741 //==============================================================================
2744 //==============================================================================
2747 extern __at(0x0215) __sfr SSPCON
;
2770 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2772 #define _SSPCON_SSPM0 0x01
2773 #define _SSPCON_SSPM1 0x02
2774 #define _SSPCON_SSPM2 0x04
2775 #define _SSPCON_SSPM3 0x08
2776 #define _SSPCON_CKP 0x10
2777 #define _SSPCON_SSPEN 0x20
2778 #define _SSPCON_SSPOV 0x40
2779 #define _SSPCON_WCOL 0x80
2781 //==============================================================================
2784 //==============================================================================
2787 extern __at(0x0215) __sfr SSPCON1
;
2810 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2812 #define _SSPCON1_SSPM0 0x01
2813 #define _SSPCON1_SSPM1 0x02
2814 #define _SSPCON1_SSPM2 0x04
2815 #define _SSPCON1_SSPM3 0x08
2816 #define _SSPCON1_CKP 0x10
2817 #define _SSPCON1_SSPEN 0x20
2818 #define _SSPCON1_SSPOV 0x40
2819 #define _SSPCON1_WCOL 0x80
2821 //==============================================================================
2824 //==============================================================================
2827 extern __at(0x0216) __sfr SSP1CON2
;
2837 unsigned ACKSTAT
: 1;
2841 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2849 #define _ACKSTAT 0x40
2852 //==============================================================================
2855 //==============================================================================
2858 extern __at(0x0216) __sfr SSPCON2
;
2868 unsigned ACKSTAT
: 1;
2872 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2874 #define _SSPCON2_SEN 0x01
2875 #define _SSPCON2_RSEN 0x02
2876 #define _SSPCON2_PEN 0x04
2877 #define _SSPCON2_RCEN 0x08
2878 #define _SSPCON2_ACKEN 0x10
2879 #define _SSPCON2_ACKDT 0x20
2880 #define _SSPCON2_ACKSTAT 0x40
2881 #define _SSPCON2_GCEN 0x80
2883 //==============================================================================
2886 //==============================================================================
2889 extern __at(0x0217) __sfr SSP1CON3
;
2900 unsigned ACKTIM
: 1;
2903 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
2912 #define _ACKTIM 0x80
2914 //==============================================================================
2917 //==============================================================================
2920 extern __at(0x0217) __sfr SSPCON3
;
2931 unsigned ACKTIM
: 1;
2934 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2936 #define _SSPCON3_DHEN 0x01
2937 #define _SSPCON3_AHEN 0x02
2938 #define _SSPCON3_SBCDE 0x04
2939 #define _SSPCON3_SDAHT 0x08
2940 #define _SSPCON3_BOEN 0x10
2941 #define _SSPCON3_SCIE 0x20
2942 #define _SSPCON3_PCIE 0x40
2943 #define _SSPCON3_ACKTIM 0x80
2945 //==============================================================================
2948 //==============================================================================
2951 extern __at(0x028C) __sfr ODCONA
;
2965 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
2973 //==============================================================================
2976 //==============================================================================
2979 extern __at(0x028E) __sfr ODCONC
;
3002 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3011 //==============================================================================
3013 extern __at(0x0291) __sfr CCPR1
;
3014 extern __at(0x0291) __sfr CCPR1L
;
3015 extern __at(0x0292) __sfr CCPR1H
;
3017 //==============================================================================
3020 extern __at(0x0293) __sfr CCP1CON
;
3026 unsigned CCP1M0
: 1;
3027 unsigned CCP1M1
: 1;
3028 unsigned CCP1M2
: 1;
3029 unsigned CCP1M3
: 1;
3062 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3064 #define _CCP1M0 0x01
3065 #define _CCP1M1 0x02
3066 #define _CCP1M2 0x04
3067 #define _CCP1M3 0x08
3073 //==============================================================================
3076 //==============================================================================
3079 extern __at(0x0293) __sfr ECCP1CON
;
3085 unsigned CCP1M0
: 1;
3086 unsigned CCP1M1
: 1;
3087 unsigned CCP1M2
: 1;
3088 unsigned CCP1M3
: 1;
3121 extern __at(0x0293) volatile __ECCP1CONbits_t ECCP1CONbits
;
3123 #define _ECCP1CON_CCP1M0 0x01
3124 #define _ECCP1CON_CCP1M1 0x02
3125 #define _ECCP1CON_CCP1M2 0x04
3126 #define _ECCP1CON_CCP1M3 0x08
3127 #define _ECCP1CON_DC1B0 0x10
3128 #define _ECCP1CON_CCP1Y 0x10
3129 #define _ECCP1CON_DC1B1 0x20
3130 #define _ECCP1CON_CCP1X 0x20
3132 //==============================================================================
3134 extern __at(0x0298) __sfr CCPR2
;
3135 extern __at(0x0298) __sfr CCPR2L
;
3136 extern __at(0x0299) __sfr CCPR2H
;
3138 //==============================================================================
3141 extern __at(0x029A) __sfr CCP2CON
;
3147 unsigned CCP2M0
: 1;
3148 unsigned CCP2M1
: 1;
3149 unsigned CCP2M2
: 1;
3150 unsigned CCP2M3
: 1;
3183 extern __at(0x029A) volatile __CCP2CONbits_t CCP2CONbits
;
3185 #define _CCP2M0 0x01
3186 #define _CCP2M1 0x02
3187 #define _CCP2M2 0x04
3188 #define _CCP2M3 0x08
3194 //==============================================================================
3197 //==============================================================================
3200 extern __at(0x029A) __sfr ECCP2CON
;
3206 unsigned CCP2M0
: 1;
3207 unsigned CCP2M1
: 1;
3208 unsigned CCP2M2
: 1;
3209 unsigned CCP2M3
: 1;
3242 extern __at(0x029A) volatile __ECCP2CONbits_t ECCP2CONbits
;
3244 #define _ECCP2CON_CCP2M0 0x01
3245 #define _ECCP2CON_CCP2M1 0x02
3246 #define _ECCP2CON_CCP2M2 0x04
3247 #define _ECCP2CON_CCP2M3 0x08
3248 #define _ECCP2CON_DC2B0 0x10
3249 #define _ECCP2CON_CCP2Y 0x10
3250 #define _ECCP2CON_DC2B1 0x20
3251 #define _ECCP2CON_CCP2X 0x20
3253 //==============================================================================
3256 //==============================================================================
3259 extern __at(0x029E) __sfr CCPTMRS
;
3265 unsigned C1TSEL0
: 1;
3266 unsigned C1TSEL1
: 1;
3267 unsigned C2TSEL0
: 1;
3268 unsigned C2TSEL1
: 1;
3269 unsigned P3TSEL0
: 1;
3270 unsigned P3TSEL1
: 1;
3271 unsigned P4TSEL0
: 1;
3272 unsigned P4TSEL1
: 1;
3277 unsigned C1TSEL
: 2;
3284 unsigned C2TSEL
: 2;
3291 unsigned P3TSEL
: 2;
3298 unsigned P4TSEL
: 2;
3302 extern __at(0x029E) volatile __CCPTMRSbits_t CCPTMRSbits
;
3304 #define _C1TSEL0 0x01
3305 #define _C1TSEL1 0x02
3306 #define _C2TSEL0 0x04
3307 #define _C2TSEL1 0x08
3308 #define _P3TSEL0 0x10
3309 #define _P3TSEL1 0x20
3310 #define _P4TSEL0 0x40
3311 #define _P4TSEL1 0x80
3313 //==============================================================================
3316 //==============================================================================
3319 extern __at(0x030C) __sfr SLRCONA
;
3333 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3341 //==============================================================================
3344 //==============================================================================
3347 extern __at(0x030E) __sfr SLRCONC
;
3370 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3379 //==============================================================================
3382 //==============================================================================
3385 extern __at(0x038C) __sfr INLVLA
;
3391 unsigned INLVLA0
: 1;
3392 unsigned INLVLA1
: 1;
3393 unsigned INLVLA2
: 1;
3394 unsigned INLVLA3
: 1;
3395 unsigned INLVLA4
: 1;
3396 unsigned INLVLA5
: 1;
3403 unsigned INLVLA
: 6;
3408 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3410 #define _INLVLA0 0x01
3411 #define _INLVLA1 0x02
3412 #define _INLVLA2 0x04
3413 #define _INLVLA3 0x08
3414 #define _INLVLA4 0x10
3415 #define _INLVLA5 0x20
3417 //==============================================================================
3420 //==============================================================================
3423 extern __at(0x038E) __sfr INLVLC
;
3429 unsigned INLVLC0
: 1;
3430 unsigned INLVLC1
: 1;
3431 unsigned INLVLC2
: 1;
3432 unsigned INLVLC3
: 1;
3433 unsigned INLVLC4
: 1;
3434 unsigned INLVLC5
: 1;
3441 unsigned INLVLC
: 6;
3446 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3448 #define _INLVLC0 0x01
3449 #define _INLVLC1 0x02
3450 #define _INLVLC2 0x04
3451 #define _INLVLC3 0x08
3452 #define _INLVLC4 0x10
3453 #define _INLVLC5 0x20
3455 //==============================================================================
3458 //==============================================================================
3461 extern __at(0x0391) __sfr IOCAP
;
3467 unsigned IOCAP0
: 1;
3468 unsigned IOCAP1
: 1;
3469 unsigned IOCAP2
: 1;
3470 unsigned IOCAP3
: 1;
3471 unsigned IOCAP4
: 1;
3472 unsigned IOCAP5
: 1;
3484 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3486 #define _IOCAP0 0x01
3487 #define _IOCAP1 0x02
3488 #define _IOCAP2 0x04
3489 #define _IOCAP3 0x08
3490 #define _IOCAP4 0x10
3491 #define _IOCAP5 0x20
3493 //==============================================================================
3496 //==============================================================================
3499 extern __at(0x0392) __sfr IOCAN
;
3505 unsigned IOCAN0
: 1;
3506 unsigned IOCAN1
: 1;
3507 unsigned IOCAN2
: 1;
3508 unsigned IOCAN3
: 1;
3509 unsigned IOCAN4
: 1;
3510 unsigned IOCAN5
: 1;
3522 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3524 #define _IOCAN0 0x01
3525 #define _IOCAN1 0x02
3526 #define _IOCAN2 0x04
3527 #define _IOCAN3 0x08
3528 #define _IOCAN4 0x10
3529 #define _IOCAN5 0x20
3531 //==============================================================================
3534 //==============================================================================
3537 extern __at(0x0393) __sfr IOCAF
;
3543 unsigned IOCAF0
: 1;
3544 unsigned IOCAF1
: 1;
3545 unsigned IOCAF2
: 1;
3546 unsigned IOCAF3
: 1;
3547 unsigned IOCAF4
: 1;
3548 unsigned IOCAF5
: 1;
3560 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3562 #define _IOCAF0 0x01
3563 #define _IOCAF1 0x02
3564 #define _IOCAF2 0x04
3565 #define _IOCAF3 0x08
3566 #define _IOCAF4 0x10
3567 #define _IOCAF5 0x20
3569 //==============================================================================
3572 //==============================================================================
3575 extern __at(0x0397) __sfr IOCCP
;
3581 unsigned IOCCP0
: 1;
3582 unsigned IOCCP1
: 1;
3583 unsigned IOCCP2
: 1;
3584 unsigned IOCCP3
: 1;
3585 unsigned IOCCP4
: 1;
3586 unsigned IOCCP5
: 1;
3598 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3600 #define _IOCCP0 0x01
3601 #define _IOCCP1 0x02
3602 #define _IOCCP2 0x04
3603 #define _IOCCP3 0x08
3604 #define _IOCCP4 0x10
3605 #define _IOCCP5 0x20
3607 //==============================================================================
3610 //==============================================================================
3613 extern __at(0x0398) __sfr IOCCN
;
3619 unsigned IOCCN0
: 1;
3620 unsigned IOCCN1
: 1;
3621 unsigned IOCCN2
: 1;
3622 unsigned IOCCN3
: 1;
3623 unsigned IOCCN4
: 1;
3624 unsigned IOCCN5
: 1;
3636 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
3638 #define _IOCCN0 0x01
3639 #define _IOCCN1 0x02
3640 #define _IOCCN2 0x04
3641 #define _IOCCN3 0x08
3642 #define _IOCCN4 0x10
3643 #define _IOCCN5 0x20
3645 //==============================================================================
3648 //==============================================================================
3651 extern __at(0x0399) __sfr IOCCF
;
3657 unsigned IOCCF0
: 1;
3658 unsigned IOCCF1
: 1;
3659 unsigned IOCCF2
: 1;
3660 unsigned IOCCF3
: 1;
3661 unsigned IOCCF4
: 1;
3662 unsigned IOCCF5
: 1;
3674 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
3676 #define _IOCCF0 0x01
3677 #define _IOCCF1 0x02
3678 #define _IOCCF2 0x04
3679 #define _IOCCF3 0x08
3680 #define _IOCCF4 0x10
3681 #define _IOCCF5 0x20
3683 //==============================================================================
3685 extern __at(0x0415) __sfr TMR4
;
3686 extern __at(0x0416) __sfr PR4
;
3688 //==============================================================================
3691 extern __at(0x0417) __sfr T4CON
;
3697 unsigned T4CKPS0
: 1;
3698 unsigned T4CKPS1
: 1;
3699 unsigned TMR4ON
: 1;
3700 unsigned T4OUTPS0
: 1;
3701 unsigned T4OUTPS1
: 1;
3702 unsigned T4OUTPS2
: 1;
3703 unsigned T4OUTPS3
: 1;
3709 unsigned T4CKPS
: 2;
3716 unsigned T4OUTPS
: 4;
3721 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
3723 #define _T4CKPS0 0x01
3724 #define _T4CKPS1 0x02
3725 #define _TMR4ON 0x04
3726 #define _T4OUTPS0 0x08
3727 #define _T4OUTPS1 0x10
3728 #define _T4OUTPS2 0x20
3729 #define _T4OUTPS3 0x40
3731 //==============================================================================
3733 extern __at(0x041C) __sfr TMR6
;
3734 extern __at(0x041D) __sfr PR6
;
3736 //==============================================================================
3739 extern __at(0x041E) __sfr T6CON
;
3745 unsigned T6CKPS0
: 1;
3746 unsigned T6CKPS1
: 1;
3747 unsigned TMR6ON
: 1;
3748 unsigned T6OUTPS0
: 1;
3749 unsigned T6OUTPS1
: 1;
3750 unsigned T6OUTPS2
: 1;
3751 unsigned T6OUTPS3
: 1;
3757 unsigned T6CKPS
: 2;
3764 unsigned T6OUTPS
: 4;
3769 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
3771 #define _T6CKPS0 0x01
3772 #define _T6CKPS1 0x02
3773 #define _TMR6ON 0x04
3774 #define _T6OUTPS0 0x08
3775 #define _T6OUTPS1 0x10
3776 #define _T6OUTPS2 0x20
3777 #define _T6OUTPS3 0x40
3779 //==============================================================================
3782 //==============================================================================
3785 extern __at(0x0511) __sfr OPA1CON
;
3791 unsigned OPA1PCH0
: 1;
3792 unsigned OPA1PCH1
: 1;
3795 unsigned OPA1UG
: 1;
3797 unsigned OPA1SP
: 1;
3798 unsigned OPA1EN
: 1;
3803 unsigned OPA1PCH
: 2;
3808 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
3810 #define _OPA1PCH0 0x01
3811 #define _OPA1PCH1 0x02
3812 #define _OPA1UG 0x10
3813 #define _OPA1SP 0x40
3814 #define _OPA1EN 0x80
3816 //==============================================================================
3819 //==============================================================================
3822 extern __at(0x0515) __sfr OPA2CON
;
3828 unsigned OPA2PCH0
: 1;
3829 unsigned OPA2PCH1
: 1;
3832 unsigned OPA2UG
: 1;
3834 unsigned OPA2SP
: 1;
3835 unsigned OPA2EN
: 1;
3840 unsigned OPA2PCH
: 2;
3845 extern __at(0x0515) volatile __OPA2CONbits_t OPA2CONbits
;
3847 #define _OPA2PCH0 0x01
3848 #define _OPA2PCH1 0x02
3849 #define _OPA2UG 0x10
3850 #define _OPA2SP 0x40
3851 #define _OPA2EN 0x80
3853 //==============================================================================
3856 //==============================================================================
3859 extern __at(0x0617) __sfr PWM3DCL
;
3871 unsigned PWM3DCL0
: 1;
3872 unsigned PWM3DCL1
: 1;
3878 unsigned PWM3DCL
: 2;
3882 extern __at(0x0617) volatile __PWM3DCLbits_t PWM3DCLbits
;
3884 #define _PWM3DCL0 0x40
3885 #define _PWM3DCL1 0x80
3887 //==============================================================================
3890 //==============================================================================
3893 extern __at(0x0618) __sfr PWM3DCH
;
3897 unsigned PWM3DCH0
: 1;
3898 unsigned PWM3DCH1
: 1;
3899 unsigned PWM3DCH2
: 1;
3900 unsigned PWM3DCH3
: 1;
3901 unsigned PWM3DCH4
: 1;
3902 unsigned PWM3DCH5
: 1;
3903 unsigned PWM3DCH6
: 1;
3904 unsigned PWM3DCH7
: 1;
3907 extern __at(0x0618) volatile __PWM3DCHbits_t PWM3DCHbits
;
3909 #define _PWM3DCH0 0x01
3910 #define _PWM3DCH1 0x02
3911 #define _PWM3DCH2 0x04
3912 #define _PWM3DCH3 0x08
3913 #define _PWM3DCH4 0x10
3914 #define _PWM3DCH5 0x20
3915 #define _PWM3DCH6 0x40
3916 #define _PWM3DCH7 0x80
3918 //==============================================================================
3921 //==============================================================================
3924 extern __at(0x0619) __sfr PWM3CON
;
3932 unsigned PWM3POL
: 1;
3933 unsigned PWM3OUT
: 1;
3935 unsigned PWM3EN
: 1;
3938 extern __at(0x0619) volatile __PWM3CONbits_t PWM3CONbits
;
3940 #define _PWM3POL 0x10
3941 #define _PWM3OUT 0x20
3942 #define _PWM3EN 0x80
3944 //==============================================================================
3947 //==============================================================================
3950 extern __at(0x0619) __sfr PWM3CON0
;
3958 unsigned PWM3POL
: 1;
3959 unsigned PWM3OUT
: 1;
3961 unsigned PWM3EN
: 1;
3964 extern __at(0x0619) volatile __PWM3CON0bits_t PWM3CON0bits
;
3966 #define _PWM3CON0_PWM3POL 0x10
3967 #define _PWM3CON0_PWM3OUT 0x20
3968 #define _PWM3CON0_PWM3EN 0x80
3970 //==============================================================================
3973 //==============================================================================
3976 extern __at(0x061A) __sfr PWM4DCL
;
3988 unsigned PWM4DCL0
: 1;
3989 unsigned PWM4DCL1
: 1;
3995 unsigned PWM4DCL
: 2;
3999 extern __at(0x061A) volatile __PWM4DCLbits_t PWM4DCLbits
;
4001 #define _PWM4DCL0 0x40
4002 #define _PWM4DCL1 0x80
4004 //==============================================================================
4007 //==============================================================================
4010 extern __at(0x061B) __sfr PWM4DCH
;
4014 unsigned PWM4DCH0
: 1;
4015 unsigned PWM4DCH1
: 1;
4016 unsigned PWM4DCH2
: 1;
4017 unsigned PWM4DCH3
: 1;
4018 unsigned PWM4DCH4
: 1;
4019 unsigned PWM4DCH5
: 1;
4020 unsigned PWM4DCH6
: 1;
4021 unsigned PWM4DCH7
: 1;
4024 extern __at(0x061B) volatile __PWM4DCHbits_t PWM4DCHbits
;
4026 #define _PWM4DCH0 0x01
4027 #define _PWM4DCH1 0x02
4028 #define _PWM4DCH2 0x04
4029 #define _PWM4DCH3 0x08
4030 #define _PWM4DCH4 0x10
4031 #define _PWM4DCH5 0x20
4032 #define _PWM4DCH6 0x40
4033 #define _PWM4DCH7 0x80
4035 //==============================================================================
4038 //==============================================================================
4041 extern __at(0x061C) __sfr PWM4CON
;
4049 unsigned PWM4POL
: 1;
4050 unsigned PWM4OUT
: 1;
4052 unsigned PWM4EN
: 1;
4055 extern __at(0x061C) volatile __PWM4CONbits_t PWM4CONbits
;
4057 #define _PWM4POL 0x10
4058 #define _PWM4OUT 0x20
4059 #define _PWM4EN 0x80
4061 //==============================================================================
4064 //==============================================================================
4067 extern __at(0x061C) __sfr PWM4CON0
;
4075 unsigned PWM4POL
: 1;
4076 unsigned PWM4OUT
: 1;
4078 unsigned PWM4EN
: 1;
4081 extern __at(0x061C) volatile __PWM4CON0bits_t PWM4CON0bits
;
4083 #define _PWM4CON0_PWM4POL 0x10
4084 #define _PWM4CON0_PWM4OUT 0x20
4085 #define _PWM4CON0_PWM4EN 0x80
4087 //==============================================================================
4090 //==============================================================================
4093 extern __at(0x0691) __sfr COG1PHR
;
4099 unsigned G1PHR0
: 1;
4100 unsigned G1PHR1
: 1;
4101 unsigned G1PHR2
: 1;
4102 unsigned G1PHR3
: 1;
4103 unsigned G1PHR4
: 1;
4104 unsigned G1PHR5
: 1;
4116 extern __at(0x0691) volatile __COG1PHRbits_t COG1PHRbits
;
4118 #define _G1PHR0 0x01
4119 #define _G1PHR1 0x02
4120 #define _G1PHR2 0x04
4121 #define _G1PHR3 0x08
4122 #define _G1PHR4 0x10
4123 #define _G1PHR5 0x20
4125 //==============================================================================
4128 //==============================================================================
4131 extern __at(0x0692) __sfr COG1PHF
;
4137 unsigned G1PHF0
: 1;
4138 unsigned G1PHF1
: 1;
4139 unsigned G1PHF2
: 1;
4140 unsigned G1PHF3
: 1;
4141 unsigned G1PHF4
: 1;
4142 unsigned G1PHF5
: 1;
4154 extern __at(0x0692) volatile __COG1PHFbits_t COG1PHFbits
;
4156 #define _G1PHF0 0x01
4157 #define _G1PHF1 0x02
4158 #define _G1PHF2 0x04
4159 #define _G1PHF3 0x08
4160 #define _G1PHF4 0x10
4161 #define _G1PHF5 0x20
4163 //==============================================================================
4166 //==============================================================================
4169 extern __at(0x0693) __sfr COG1BLKR
;
4175 unsigned G1BLKR0
: 1;
4176 unsigned G1BLKR1
: 1;
4177 unsigned G1BLKR2
: 1;
4178 unsigned G1BLKR3
: 1;
4179 unsigned G1BLKR4
: 1;
4180 unsigned G1BLKR5
: 1;
4187 unsigned G1BLKR
: 6;
4192 extern __at(0x0693) volatile __COG1BLKRbits_t COG1BLKRbits
;
4194 #define _G1BLKR0 0x01
4195 #define _G1BLKR1 0x02
4196 #define _G1BLKR2 0x04
4197 #define _G1BLKR3 0x08
4198 #define _G1BLKR4 0x10
4199 #define _G1BLKR5 0x20
4201 //==============================================================================
4204 //==============================================================================
4207 extern __at(0x0694) __sfr COG1BLKF
;
4213 unsigned G1BLKF0
: 1;
4214 unsigned G1BLKF1
: 1;
4215 unsigned G1BLKF2
: 1;
4216 unsigned G1BLKF3
: 1;
4217 unsigned G1BLKF4
: 1;
4218 unsigned G1BLKF5
: 1;
4225 unsigned G1BLKF
: 6;
4230 extern __at(0x0694) volatile __COG1BLKFbits_t COG1BLKFbits
;
4232 #define _G1BLKF0 0x01
4233 #define _G1BLKF1 0x02
4234 #define _G1BLKF2 0x04
4235 #define _G1BLKF3 0x08
4236 #define _G1BLKF4 0x10
4237 #define _G1BLKF5 0x20
4239 //==============================================================================
4242 //==============================================================================
4245 extern __at(0x0695) __sfr COG1DBR
;
4251 unsigned G1DBR0
: 1;
4252 unsigned G1DBR1
: 1;
4253 unsigned G1DBR2
: 1;
4254 unsigned G1DBR3
: 1;
4255 unsigned G1DBR4
: 1;
4256 unsigned G1DBR5
: 1;
4268 extern __at(0x0695) volatile __COG1DBRbits_t COG1DBRbits
;
4270 #define _G1DBR0 0x01
4271 #define _G1DBR1 0x02
4272 #define _G1DBR2 0x04
4273 #define _G1DBR3 0x08
4274 #define _G1DBR4 0x10
4275 #define _G1DBR5 0x20
4277 //==============================================================================
4280 //==============================================================================
4283 extern __at(0x0696) __sfr COG1DBF
;
4289 unsigned G1DBF0
: 1;
4290 unsigned G1DBF1
: 1;
4291 unsigned G1DBF2
: 1;
4292 unsigned G1DBF3
: 1;
4293 unsigned G1DBF4
: 1;
4294 unsigned G1DBF5
: 1;
4306 extern __at(0x0696) volatile __COG1DBFbits_t COG1DBFbits
;
4308 #define _G1DBF0 0x01
4309 #define _G1DBF1 0x02
4310 #define _G1DBF2 0x04
4311 #define _G1DBF3 0x08
4312 #define _G1DBF4 0x10
4313 #define _G1DBF5 0x20
4315 //==============================================================================
4318 //==============================================================================
4321 extern __at(0x0697) __sfr COG1CON0
;
4351 extern __at(0x0697) volatile __COG1CON0bits_t COG1CON0bits
;
4361 //==============================================================================
4364 //==============================================================================
4367 extern __at(0x0698) __sfr COG1CON1
;
4371 unsigned G1POLA
: 1;
4372 unsigned G1POLB
: 1;
4373 unsigned G1POLC
: 1;
4374 unsigned G1POLD
: 1;
4377 unsigned G1FDBS
: 1;
4378 unsigned G1RDBS
: 1;
4381 extern __at(0x0698) volatile __COG1CON1bits_t COG1CON1bits
;
4383 #define _G1POLA 0x01
4384 #define _G1POLB 0x02
4385 #define _G1POLC 0x04
4386 #define _G1POLD 0x08
4387 #define _G1FDBS 0x40
4388 #define _G1RDBS 0x80
4390 //==============================================================================
4393 //==============================================================================
4396 extern __at(0x0699) __sfr COG1RIS
;
4402 unsigned G1RIS0
: 1;
4403 unsigned G1RIS1
: 1;
4404 unsigned G1RIS2
: 1;
4405 unsigned G1RIS3
: 1;
4406 unsigned G1RIS4
: 1;
4407 unsigned G1RIS5
: 1;
4408 unsigned G1RIS6
: 1;
4419 extern __at(0x0699) volatile __COG1RISbits_t COG1RISbits
;
4421 #define _G1RIS0 0x01
4422 #define _G1RIS1 0x02
4423 #define _G1RIS2 0x04
4424 #define _G1RIS3 0x08
4425 #define _G1RIS4 0x10
4426 #define _G1RIS5 0x20
4427 #define _G1RIS6 0x40
4429 //==============================================================================
4432 //==============================================================================
4435 extern __at(0x069A) __sfr COG1RSIM
;
4441 unsigned G1RSIM0
: 1;
4442 unsigned G1RSIM1
: 1;
4443 unsigned G1RSIM2
: 1;
4444 unsigned G1RSIM3
: 1;
4445 unsigned G1RSIM4
: 1;
4446 unsigned G1RSIM5
: 1;
4447 unsigned G1RSIM6
: 1;
4453 unsigned G1RSIM
: 7;
4458 extern __at(0x069A) volatile __COG1RSIMbits_t COG1RSIMbits
;
4460 #define _G1RSIM0 0x01
4461 #define _G1RSIM1 0x02
4462 #define _G1RSIM2 0x04
4463 #define _G1RSIM3 0x08
4464 #define _G1RSIM4 0x10
4465 #define _G1RSIM5 0x20
4466 #define _G1RSIM6 0x40
4468 //==============================================================================
4471 //==============================================================================
4474 extern __at(0x069B) __sfr COG1FIS
;
4480 unsigned G1FIS0
: 1;
4481 unsigned G1FIS1
: 1;
4482 unsigned G1FIS2
: 1;
4483 unsigned G1FIS3
: 1;
4484 unsigned G1FIS4
: 1;
4485 unsigned G1FIS5
: 1;
4486 unsigned G1FIS6
: 1;
4497 extern __at(0x069B) volatile __COG1FISbits_t COG1FISbits
;
4499 #define _G1FIS0 0x01
4500 #define _G1FIS1 0x02
4501 #define _G1FIS2 0x04
4502 #define _G1FIS3 0x08
4503 #define _G1FIS4 0x10
4504 #define _G1FIS5 0x20
4505 #define _G1FIS6 0x40
4507 //==============================================================================
4510 //==============================================================================
4513 extern __at(0x069C) __sfr COG1FSIM
;
4519 unsigned G1FSIM0
: 1;
4520 unsigned G1FSIM1
: 1;
4521 unsigned G1FSIM2
: 1;
4522 unsigned G1FSIM3
: 1;
4523 unsigned G1FSIM4
: 1;
4524 unsigned G1FSIM5
: 1;
4525 unsigned G1FSIM6
: 1;
4531 unsigned G1FSIM
: 7;
4536 extern __at(0x069C) volatile __COG1FSIMbits_t COG1FSIMbits
;
4538 #define _G1FSIM0 0x01
4539 #define _G1FSIM1 0x02
4540 #define _G1FSIM2 0x04
4541 #define _G1FSIM3 0x08
4542 #define _G1FSIM4 0x10
4543 #define _G1FSIM5 0x20
4544 #define _G1FSIM6 0x40
4546 //==============================================================================
4549 //==============================================================================
4552 extern __at(0x069D) __sfr COG1ASD0
;
4560 unsigned G1ASDAC0
: 1;
4561 unsigned G1ASDAC1
: 1;
4562 unsigned G1ASDBD0
: 1;
4563 unsigned G1ASDBD1
: 1;
4564 unsigned G1ARSEN
: 1;
4571 unsigned G1ASDAC
: 2;
4578 unsigned G1ASDBD
: 2;
4583 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
4585 #define _G1ASDAC0 0x04
4586 #define _G1ASDAC1 0x08
4587 #define _G1ASDBD0 0x10
4588 #define _G1ASDBD1 0x20
4589 #define _G1ARSEN 0x40
4592 //==============================================================================
4595 //==============================================================================
4598 extern __at(0x069E) __sfr COG1ASD1
;
4602 unsigned G1AS0E
: 1;
4603 unsigned G1AS1E
: 1;
4604 unsigned G1AS2E
: 1;
4605 unsigned G1AS3E
: 1;
4612 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
4614 #define _G1AS0E 0x01
4615 #define _G1AS1E 0x02
4616 #define _G1AS2E 0x04
4617 #define _G1AS3E 0x08
4619 //==============================================================================
4622 //==============================================================================
4625 extern __at(0x069F) __sfr COG1STR
;
4629 unsigned G1STRA
: 1;
4630 unsigned G1STRB
: 1;
4631 unsigned G1STRC
: 1;
4632 unsigned G1STRD
: 1;
4633 unsigned G1SDATA
: 1;
4634 unsigned G1SDATB
: 1;
4635 unsigned G1SDATC
: 1;
4636 unsigned G1SDATD
: 1;
4639 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
4641 #define _G1STRA 0x01
4642 #define _G1STRB 0x02
4643 #define _G1STRC 0x04
4644 #define _G1STRD 0x08
4645 #define _G1SDATA 0x10
4646 #define _G1SDATB 0x20
4647 #define _G1SDATC 0x40
4648 #define _G1SDATD 0x80
4650 //==============================================================================
4653 //==============================================================================
4656 extern __at(0x0E0F) __sfr PPSLOCK
;
4660 unsigned PPSLOCKED
: 1;
4670 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
4672 #define _PPSLOCKED 0x01
4674 //==============================================================================
4676 extern __at(0x0E10) __sfr INTPPS
;
4677 extern __at(0x0E11) __sfr T0CKIPPS
;
4678 extern __at(0x0E12) __sfr T1CKIPPS
;
4679 extern __at(0x0E13) __sfr T1GPPS
;
4680 extern __at(0x0E14) __sfr CCP1PPS
;
4681 extern __at(0x0E15) __sfr CCP2PPS
;
4682 extern __at(0x0E17) __sfr COGINPPS
;
4683 extern __at(0x0E20) __sfr SSPCLKPPS
;
4684 extern __at(0x0E21) __sfr SSPDATPPS
;
4685 extern __at(0x0E22) __sfr SSPSSPPS
;
4686 extern __at(0x0E24) __sfr RXPPS
;
4687 extern __at(0x0E25) __sfr CKPPS
;
4688 extern __at(0x0E28) __sfr CLCIN0PPS
;
4689 extern __at(0x0E29) __sfr CLCIN1PPS
;
4690 extern __at(0x0E2A) __sfr CLCIN2PPS
;
4691 extern __at(0x0E2B) __sfr CLCIN3PPS
;
4692 extern __at(0x0E90) __sfr RA0PPS
;
4693 extern __at(0x0E91) __sfr RA1PPS
;
4694 extern __at(0x0E92) __sfr RA2PPS
;
4695 extern __at(0x0E94) __sfr RA4PPS
;
4696 extern __at(0x0E95) __sfr RA5PPS
;
4697 extern __at(0x0EA0) __sfr RC0PPS
;
4698 extern __at(0x0EA1) __sfr RC1PPS
;
4699 extern __at(0x0EA2) __sfr RC2PPS
;
4700 extern __at(0x0EA3) __sfr RC3PPS
;
4701 extern __at(0x0EA4) __sfr RC4PPS
;
4702 extern __at(0x0EA5) __sfr RC5PPS
;
4704 //==============================================================================
4707 extern __at(0x0F0F) __sfr CLCDATA
;
4711 unsigned MCLC1OUT
: 1;
4712 unsigned MCLC2OUT
: 1;
4713 unsigned MCLC3OUT
: 1;
4721 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
4723 #define _MCLC1OUT 0x01
4724 #define _MCLC2OUT 0x02
4725 #define _MCLC3OUT 0x04
4727 //==============================================================================
4730 //==============================================================================
4733 extern __at(0x0F10) __sfr CLC1CON
;
4739 unsigned LC1MODE0
: 1;
4740 unsigned LC1MODE1
: 1;
4741 unsigned LC1MODE2
: 1;
4742 unsigned LC1INTN
: 1;
4743 unsigned LC1INTP
: 1;
4744 unsigned LC1OUT
: 1;
4769 unsigned LC1MODE
: 3;
4774 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
4776 #define _LC1MODE0 0x01
4778 #define _LC1MODE1 0x02
4780 #define _LC1MODE2 0x04
4782 #define _LC1INTN 0x08
4784 #define _LC1INTP 0x10
4786 #define _LC1OUT 0x20
4791 //==============================================================================
4794 //==============================================================================
4797 extern __at(0x0F11) __sfr CLC1POL
;
4803 unsigned LC1G1POL
: 1;
4804 unsigned LC1G2POL
: 1;
4805 unsigned LC1G3POL
: 1;
4806 unsigned LC1G4POL
: 1;
4810 unsigned LC1POL
: 1;
4826 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
4828 #define _LC1G1POL 0x01
4830 #define _LC1G2POL 0x02
4832 #define _LC1G3POL 0x04
4834 #define _LC1G4POL 0x08
4836 #define _LC1POL 0x80
4839 //==============================================================================
4842 //==============================================================================
4845 extern __at(0x0F12) __sfr CLC1SEL0
;
4851 unsigned LC1D1S0
: 1;
4852 unsigned LC1D1S1
: 1;
4853 unsigned LC1D1S2
: 1;
4854 unsigned LC1D1S3
: 1;
4855 unsigned LC1D1S4
: 1;
4875 unsigned LC1D1S
: 5;
4886 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
4888 #define _LC1D1S0 0x01
4890 #define _LC1D1S1 0x02
4892 #define _LC1D1S2 0x04
4894 #define _LC1D1S3 0x08
4896 #define _LC1D1S4 0x10
4899 //==============================================================================
4902 //==============================================================================
4905 extern __at(0x0F13) __sfr CLC1SEL1
;
4911 unsigned LC1D2S0
: 1;
4912 unsigned LC1D2S1
: 1;
4913 unsigned LC1D2S2
: 1;
4914 unsigned LC1D2S3
: 1;
4915 unsigned LC1D2S4
: 1;
4935 unsigned LC1D2S
: 5;
4946 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
4948 #define _LC1D2S0 0x01
4950 #define _LC1D2S1 0x02
4952 #define _LC1D2S2 0x04
4954 #define _LC1D2S3 0x08
4956 #define _LC1D2S4 0x10
4959 //==============================================================================
4962 //==============================================================================
4965 extern __at(0x0F14) __sfr CLC1SEL2
;
4971 unsigned LC1D3S0
: 1;
4972 unsigned LC1D3S1
: 1;
4973 unsigned LC1D3S2
: 1;
4974 unsigned LC1D3S3
: 1;
4975 unsigned LC1D3S4
: 1;
5001 unsigned LC1D3S
: 5;
5006 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
5008 #define _LC1D3S0 0x01
5010 #define _LC1D3S1 0x02
5012 #define _LC1D3S2 0x04
5014 #define _LC1D3S3 0x08
5016 #define _LC1D3S4 0x10
5019 //==============================================================================
5022 //==============================================================================
5025 extern __at(0x0F15) __sfr CLC1SEL3
;
5031 unsigned LC1D4S0
: 1;
5032 unsigned LC1D4S1
: 1;
5033 unsigned LC1D4S2
: 1;
5034 unsigned LC1D4S3
: 1;
5035 unsigned LC1D4S4
: 1;
5061 unsigned LC1D4S
: 5;
5066 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
5068 #define _LC1D4S0 0x01
5070 #define _LC1D4S1 0x02
5072 #define _LC1D4S2 0x04
5074 #define _LC1D4S3 0x08
5076 #define _LC1D4S4 0x10
5079 //==============================================================================
5082 //==============================================================================
5085 extern __at(0x0F16) __sfr CLC1GLS0
;
5091 unsigned LC1G1D1N
: 1;
5092 unsigned LC1G1D1T
: 1;
5093 unsigned LC1G1D2N
: 1;
5094 unsigned LC1G1D2T
: 1;
5095 unsigned LC1G1D3N
: 1;
5096 unsigned LC1G1D3T
: 1;
5097 unsigned LC1G1D4N
: 1;
5098 unsigned LC1G1D4T
: 1;
5114 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
5116 #define _LC1G1D1N 0x01
5118 #define _LC1G1D1T 0x02
5120 #define _LC1G1D2N 0x04
5122 #define _LC1G1D2T 0x08
5124 #define _LC1G1D3N 0x10
5126 #define _LC1G1D3T 0x20
5128 #define _LC1G1D4N 0x40
5130 #define _LC1G1D4T 0x80
5133 //==============================================================================
5136 //==============================================================================
5139 extern __at(0x0F17) __sfr CLC1GLS1
;
5145 unsigned LC1G2D1N
: 1;
5146 unsigned LC1G2D1T
: 1;
5147 unsigned LC1G2D2N
: 1;
5148 unsigned LC1G2D2T
: 1;
5149 unsigned LC1G2D3N
: 1;
5150 unsigned LC1G2D3T
: 1;
5151 unsigned LC1G2D4N
: 1;
5152 unsigned LC1G2D4T
: 1;
5168 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
5170 #define _CLC1GLS1_LC1G2D1N 0x01
5171 #define _CLC1GLS1_D1N 0x01
5172 #define _CLC1GLS1_LC1G2D1T 0x02
5173 #define _CLC1GLS1_D1T 0x02
5174 #define _CLC1GLS1_LC1G2D2N 0x04
5175 #define _CLC1GLS1_D2N 0x04
5176 #define _CLC1GLS1_LC1G2D2T 0x08
5177 #define _CLC1GLS1_D2T 0x08
5178 #define _CLC1GLS1_LC1G2D3N 0x10
5179 #define _CLC1GLS1_D3N 0x10
5180 #define _CLC1GLS1_LC1G2D3T 0x20
5181 #define _CLC1GLS1_D3T 0x20
5182 #define _CLC1GLS1_LC1G2D4N 0x40
5183 #define _CLC1GLS1_D4N 0x40
5184 #define _CLC1GLS1_LC1G2D4T 0x80
5185 #define _CLC1GLS1_D4T 0x80
5187 //==============================================================================
5190 //==============================================================================
5193 extern __at(0x0F18) __sfr CLC1GLS2
;
5199 unsigned LC1G3D1N
: 1;
5200 unsigned LC1G3D1T
: 1;
5201 unsigned LC1G3D2N
: 1;
5202 unsigned LC1G3D2T
: 1;
5203 unsigned LC1G3D3N
: 1;
5204 unsigned LC1G3D3T
: 1;
5205 unsigned LC1G3D4N
: 1;
5206 unsigned LC1G3D4T
: 1;
5222 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
5224 #define _CLC1GLS2_LC1G3D1N 0x01
5225 #define _CLC1GLS2_D1N 0x01
5226 #define _CLC1GLS2_LC1G3D1T 0x02
5227 #define _CLC1GLS2_D1T 0x02
5228 #define _CLC1GLS2_LC1G3D2N 0x04
5229 #define _CLC1GLS2_D2N 0x04
5230 #define _CLC1GLS2_LC1G3D2T 0x08
5231 #define _CLC1GLS2_D2T 0x08
5232 #define _CLC1GLS2_LC1G3D3N 0x10
5233 #define _CLC1GLS2_D3N 0x10
5234 #define _CLC1GLS2_LC1G3D3T 0x20
5235 #define _CLC1GLS2_D3T 0x20
5236 #define _CLC1GLS2_LC1G3D4N 0x40
5237 #define _CLC1GLS2_D4N 0x40
5238 #define _CLC1GLS2_LC1G3D4T 0x80
5239 #define _CLC1GLS2_D4T 0x80
5241 //==============================================================================
5244 //==============================================================================
5247 extern __at(0x0F19) __sfr CLC1GLS3
;
5253 unsigned LC1G4D1N
: 1;
5254 unsigned LC1G4D1T
: 1;
5255 unsigned LC1G4D2N
: 1;
5256 unsigned LC1G4D2T
: 1;
5257 unsigned LC1G4D3N
: 1;
5258 unsigned LC1G4D3T
: 1;
5259 unsigned LC1G4D4N
: 1;
5260 unsigned LC1G4D4T
: 1;
5276 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
5278 #define _LC1G4D1N 0x01
5280 #define _LC1G4D1T 0x02
5282 #define _LC1G4D2N 0x04
5284 #define _LC1G4D2T 0x08
5286 #define _LC1G4D3N 0x10
5288 #define _LC1G4D3T 0x20
5290 #define _LC1G4D4N 0x40
5292 #define _LC1G4D4T 0x80
5295 //==============================================================================
5298 //==============================================================================
5301 extern __at(0x0F1A) __sfr CLC2CON
;
5307 unsigned LC2MODE0
: 1;
5308 unsigned LC2MODE1
: 1;
5309 unsigned LC2MODE2
: 1;
5310 unsigned LC2INTN
: 1;
5311 unsigned LC2INTP
: 1;
5312 unsigned LC2OUT
: 1;
5337 unsigned LC2MODE
: 3;
5342 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
5344 #define _CLC2CON_LC2MODE0 0x01
5345 #define _CLC2CON_MODE0 0x01
5346 #define _CLC2CON_LC2MODE1 0x02
5347 #define _CLC2CON_MODE1 0x02
5348 #define _CLC2CON_LC2MODE2 0x04
5349 #define _CLC2CON_MODE2 0x04
5350 #define _CLC2CON_LC2INTN 0x08
5351 #define _CLC2CON_INTN 0x08
5352 #define _CLC2CON_LC2INTP 0x10
5353 #define _CLC2CON_INTP 0x10
5354 #define _CLC2CON_LC2OUT 0x20
5355 #define _CLC2CON_OUT 0x20
5356 #define _CLC2CON_LC2EN 0x80
5357 #define _CLC2CON_EN 0x80
5359 //==============================================================================
5362 //==============================================================================
5365 extern __at(0x0F1B) __sfr CLC2POL
;
5371 unsigned LC2G1POL
: 1;
5372 unsigned LC2G2POL
: 1;
5373 unsigned LC2G3POL
: 1;
5374 unsigned LC2G4POL
: 1;
5378 unsigned LC2POL
: 1;
5394 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
5396 #define _CLC2POL_LC2G1POL 0x01
5397 #define _CLC2POL_G1POL 0x01
5398 #define _CLC2POL_LC2G2POL 0x02
5399 #define _CLC2POL_G2POL 0x02
5400 #define _CLC2POL_LC2G3POL 0x04
5401 #define _CLC2POL_G3POL 0x04
5402 #define _CLC2POL_LC2G4POL 0x08
5403 #define _CLC2POL_G4POL 0x08
5404 #define _CLC2POL_LC2POL 0x80
5405 #define _CLC2POL_POL 0x80
5407 //==============================================================================
5410 //==============================================================================
5413 extern __at(0x0F1C) __sfr CLC2SEL0
;
5419 unsigned LC2D1S0
: 1;
5420 unsigned LC2D1S1
: 1;
5421 unsigned LC2D1S2
: 1;
5422 unsigned LC2D1S3
: 1;
5423 unsigned LC2D1S4
: 1;
5443 unsigned LC2D1S
: 5;
5454 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
5456 #define _CLC2SEL0_LC2D1S0 0x01
5457 #define _CLC2SEL0_D1S0 0x01
5458 #define _CLC2SEL0_LC2D1S1 0x02
5459 #define _CLC2SEL0_D1S1 0x02
5460 #define _CLC2SEL0_LC2D1S2 0x04
5461 #define _CLC2SEL0_D1S2 0x04
5462 #define _CLC2SEL0_LC2D1S3 0x08
5463 #define _CLC2SEL0_D1S3 0x08
5464 #define _CLC2SEL0_LC2D1S4 0x10
5465 #define _CLC2SEL0_D1S4 0x10
5467 //==============================================================================
5470 //==============================================================================
5473 extern __at(0x0F1D) __sfr CLC2SEL1
;
5479 unsigned LC2D2S0
: 1;
5480 unsigned LC2D2S1
: 1;
5481 unsigned LC2D2S2
: 1;
5482 unsigned LC2D2S3
: 1;
5483 unsigned LC2D2S4
: 1;
5509 unsigned LC2D2S
: 5;
5514 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
5516 #define _CLC2SEL1_LC2D2S0 0x01
5517 #define _CLC2SEL1_D2S0 0x01
5518 #define _CLC2SEL1_LC2D2S1 0x02
5519 #define _CLC2SEL1_D2S1 0x02
5520 #define _CLC2SEL1_LC2D2S2 0x04
5521 #define _CLC2SEL1_D2S2 0x04
5522 #define _CLC2SEL1_LC2D2S3 0x08
5523 #define _CLC2SEL1_D2S3 0x08
5524 #define _CLC2SEL1_LC2D2S4 0x10
5525 #define _CLC2SEL1_D2S4 0x10
5527 //==============================================================================
5530 //==============================================================================
5533 extern __at(0x0F1E) __sfr CLC2SEL2
;
5539 unsigned LC2D3S0
: 1;
5540 unsigned LC2D3S1
: 1;
5541 unsigned LC2D3S2
: 1;
5542 unsigned LC2D3S3
: 1;
5543 unsigned LC2D3S4
: 1;
5569 unsigned LC2D3S
: 5;
5574 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
5576 #define _CLC2SEL2_LC2D3S0 0x01
5577 #define _CLC2SEL2_D3S0 0x01
5578 #define _CLC2SEL2_LC2D3S1 0x02
5579 #define _CLC2SEL2_D3S1 0x02
5580 #define _CLC2SEL2_LC2D3S2 0x04
5581 #define _CLC2SEL2_D3S2 0x04
5582 #define _CLC2SEL2_LC2D3S3 0x08
5583 #define _CLC2SEL2_D3S3 0x08
5584 #define _CLC2SEL2_LC2D3S4 0x10
5585 #define _CLC2SEL2_D3S4 0x10
5587 //==============================================================================
5590 //==============================================================================
5593 extern __at(0x0F1F) __sfr CLC2SEL3
;
5599 unsigned LC2D4S0
: 1;
5600 unsigned LC2D4S1
: 1;
5601 unsigned LC2D4S2
: 1;
5602 unsigned LC2D4S3
: 1;
5603 unsigned LC2D4S4
: 1;
5629 unsigned LC2D4S
: 5;
5634 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
5636 #define _CLC2SEL3_LC2D4S0 0x01
5637 #define _CLC2SEL3_D4S0 0x01
5638 #define _CLC2SEL3_LC2D4S1 0x02
5639 #define _CLC2SEL3_D4S1 0x02
5640 #define _CLC2SEL3_LC2D4S2 0x04
5641 #define _CLC2SEL3_D4S2 0x04
5642 #define _CLC2SEL3_LC2D4S3 0x08
5643 #define _CLC2SEL3_D4S3 0x08
5644 #define _CLC2SEL3_LC2D4S4 0x10
5645 #define _CLC2SEL3_D4S4 0x10
5647 //==============================================================================
5650 //==============================================================================
5653 extern __at(0x0F20) __sfr CLC2GLS0
;
5659 unsigned LC2G1D1N
: 1;
5660 unsigned LC2G1D1T
: 1;
5661 unsigned LC2G1D2N
: 1;
5662 unsigned LC2G1D2T
: 1;
5663 unsigned LC2G1D3N
: 1;
5664 unsigned LC2G1D3T
: 1;
5665 unsigned LC2G1D4N
: 1;
5666 unsigned LC2G1D4T
: 1;
5682 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
5684 #define _CLC2GLS0_LC2G1D1N 0x01
5685 #define _CLC2GLS0_D1N 0x01
5686 #define _CLC2GLS0_LC2G1D1T 0x02
5687 #define _CLC2GLS0_D1T 0x02
5688 #define _CLC2GLS0_LC2G1D2N 0x04
5689 #define _CLC2GLS0_D2N 0x04
5690 #define _CLC2GLS0_LC2G1D2T 0x08
5691 #define _CLC2GLS0_D2T 0x08
5692 #define _CLC2GLS0_LC2G1D3N 0x10
5693 #define _CLC2GLS0_D3N 0x10
5694 #define _CLC2GLS0_LC2G1D3T 0x20
5695 #define _CLC2GLS0_D3T 0x20
5696 #define _CLC2GLS0_LC2G1D4N 0x40
5697 #define _CLC2GLS0_D4N 0x40
5698 #define _CLC2GLS0_LC2G1D4T 0x80
5699 #define _CLC2GLS0_D4T 0x80
5701 //==============================================================================
5704 //==============================================================================
5707 extern __at(0x0F21) __sfr CLC2GLS1
;
5713 unsigned LC2G2D1N
: 1;
5714 unsigned LC2G2D1T
: 1;
5715 unsigned LC2G2D2N
: 1;
5716 unsigned LC2G2D2T
: 1;
5717 unsigned LC2G2D3N
: 1;
5718 unsigned LC2G2D3T
: 1;
5719 unsigned LC2G2D4N
: 1;
5720 unsigned LC2G2D4T
: 1;
5736 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
5738 #define _CLC2GLS1_LC2G2D1N 0x01
5739 #define _CLC2GLS1_D1N 0x01
5740 #define _CLC2GLS1_LC2G2D1T 0x02
5741 #define _CLC2GLS1_D1T 0x02
5742 #define _CLC2GLS1_LC2G2D2N 0x04
5743 #define _CLC2GLS1_D2N 0x04
5744 #define _CLC2GLS1_LC2G2D2T 0x08
5745 #define _CLC2GLS1_D2T 0x08
5746 #define _CLC2GLS1_LC2G2D3N 0x10
5747 #define _CLC2GLS1_D3N 0x10
5748 #define _CLC2GLS1_LC2G2D3T 0x20
5749 #define _CLC2GLS1_D3T 0x20
5750 #define _CLC2GLS1_LC2G2D4N 0x40
5751 #define _CLC2GLS1_D4N 0x40
5752 #define _CLC2GLS1_LC2G2D4T 0x80
5753 #define _CLC2GLS1_D4T 0x80
5755 //==============================================================================
5758 //==============================================================================
5761 extern __at(0x0F22) __sfr CLC2GLS2
;
5767 unsigned LC2G3D1N
: 1;
5768 unsigned LC2G3D1T
: 1;
5769 unsigned LC2G3D2N
: 1;
5770 unsigned LC2G3D2T
: 1;
5771 unsigned LC2G3D3N
: 1;
5772 unsigned LC2G3D3T
: 1;
5773 unsigned LC2G3D4N
: 1;
5774 unsigned LC2G3D4T
: 1;
5790 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
5792 #define _CLC2GLS2_LC2G3D1N 0x01
5793 #define _CLC2GLS2_D1N 0x01
5794 #define _CLC2GLS2_LC2G3D1T 0x02
5795 #define _CLC2GLS2_D1T 0x02
5796 #define _CLC2GLS2_LC2G3D2N 0x04
5797 #define _CLC2GLS2_D2N 0x04
5798 #define _CLC2GLS2_LC2G3D2T 0x08
5799 #define _CLC2GLS2_D2T 0x08
5800 #define _CLC2GLS2_LC2G3D3N 0x10
5801 #define _CLC2GLS2_D3N 0x10
5802 #define _CLC2GLS2_LC2G3D3T 0x20
5803 #define _CLC2GLS2_D3T 0x20
5804 #define _CLC2GLS2_LC2G3D4N 0x40
5805 #define _CLC2GLS2_D4N 0x40
5806 #define _CLC2GLS2_LC2G3D4T 0x80
5807 #define _CLC2GLS2_D4T 0x80
5809 //==============================================================================
5812 //==============================================================================
5815 extern __at(0x0F23) __sfr CLC2GLS3
;
5821 unsigned LC2G4D1N
: 1;
5822 unsigned LC2G4D1T
: 1;
5823 unsigned LC2G4D2N
: 1;
5824 unsigned LC2G4D2T
: 1;
5825 unsigned LC2G4D3N
: 1;
5826 unsigned LC2G4D3T
: 1;
5827 unsigned LC2G4D4N
: 1;
5828 unsigned LC2G4D4T
: 1;
5844 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
5846 #define _CLC2GLS3_LC2G4D1N 0x01
5847 #define _CLC2GLS3_G4D1N 0x01
5848 #define _CLC2GLS3_LC2G4D1T 0x02
5849 #define _CLC2GLS3_G4D1T 0x02
5850 #define _CLC2GLS3_LC2G4D2N 0x04
5851 #define _CLC2GLS3_G4D2N 0x04
5852 #define _CLC2GLS3_LC2G4D2T 0x08
5853 #define _CLC2GLS3_G4D2T 0x08
5854 #define _CLC2GLS3_LC2G4D3N 0x10
5855 #define _CLC2GLS3_G4D3N 0x10
5856 #define _CLC2GLS3_LC2G4D3T 0x20
5857 #define _CLC2GLS3_G4D3T 0x20
5858 #define _CLC2GLS3_LC2G4D4N 0x40
5859 #define _CLC2GLS3_G4D4N 0x40
5860 #define _CLC2GLS3_LC2G4D4T 0x80
5861 #define _CLC2GLS3_G4D4T 0x80
5863 //==============================================================================
5866 //==============================================================================
5869 extern __at(0x0F24) __sfr CLC3CON
;
5875 unsigned LC3MODE0
: 1;
5876 unsigned LC3MODE1
: 1;
5877 unsigned LC3MODE2
: 1;
5878 unsigned LC3INTN
: 1;
5879 unsigned LC3INTP
: 1;
5880 unsigned LC3OUT
: 1;
5905 unsigned LC3MODE
: 3;
5910 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
5912 #define _CLC3CON_LC3MODE0 0x01
5913 #define _CLC3CON_MODE0 0x01
5914 #define _CLC3CON_LC3MODE1 0x02
5915 #define _CLC3CON_MODE1 0x02
5916 #define _CLC3CON_LC3MODE2 0x04
5917 #define _CLC3CON_MODE2 0x04
5918 #define _CLC3CON_LC3INTN 0x08
5919 #define _CLC3CON_INTN 0x08
5920 #define _CLC3CON_LC3INTP 0x10
5921 #define _CLC3CON_INTP 0x10
5922 #define _CLC3CON_LC3OUT 0x20
5923 #define _CLC3CON_OUT 0x20
5924 #define _CLC3CON_LC3EN 0x80
5925 #define _CLC3CON_EN 0x80
5927 //==============================================================================
5930 //==============================================================================
5933 extern __at(0x0F25) __sfr CLC3POL
;
5939 unsigned LC3G1POL
: 1;
5940 unsigned LC3G2POL
: 1;
5941 unsigned LC3G3POL
: 1;
5942 unsigned LC3G4POL
: 1;
5946 unsigned LC3POL
: 1;
5962 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
5964 #define _CLC3POL_LC3G1POL 0x01
5965 #define _CLC3POL_G1POL 0x01
5966 #define _CLC3POL_LC3G2POL 0x02
5967 #define _CLC3POL_G2POL 0x02
5968 #define _CLC3POL_LC3G3POL 0x04
5969 #define _CLC3POL_G3POL 0x04
5970 #define _CLC3POL_LC3G4POL 0x08
5971 #define _CLC3POL_G4POL 0x08
5972 #define _CLC3POL_LC3POL 0x80
5973 #define _CLC3POL_POL 0x80
5975 //==============================================================================
5978 //==============================================================================
5981 extern __at(0x0F26) __sfr CLC3SEL0
;
5987 unsigned LC3D1S0
: 1;
5988 unsigned LC3D1S1
: 1;
5989 unsigned LC3D1S2
: 1;
5990 unsigned LC3D1S3
: 1;
5991 unsigned LC3D1S4
: 1;
6017 unsigned LC3D1S
: 5;
6022 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
6024 #define _CLC3SEL0_LC3D1S0 0x01
6025 #define _CLC3SEL0_D1S0 0x01
6026 #define _CLC3SEL0_LC3D1S1 0x02
6027 #define _CLC3SEL0_D1S1 0x02
6028 #define _CLC3SEL0_LC3D1S2 0x04
6029 #define _CLC3SEL0_D1S2 0x04
6030 #define _CLC3SEL0_LC3D1S3 0x08
6031 #define _CLC3SEL0_D1S3 0x08
6032 #define _CLC3SEL0_LC3D1S4 0x10
6033 #define _CLC3SEL0_D1S4 0x10
6035 //==============================================================================
6038 //==============================================================================
6041 extern __at(0x0F27) __sfr CLC3SEL1
;
6047 unsigned LC3D2S0
: 1;
6048 unsigned LC3D2S1
: 1;
6049 unsigned LC3D2S2
: 1;
6050 unsigned LC3D2S3
: 1;
6051 unsigned LC3D2S4
: 1;
6077 unsigned LC3D2S
: 5;
6082 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
6084 #define _CLC3SEL1_LC3D2S0 0x01
6085 #define _CLC3SEL1_D2S0 0x01
6086 #define _CLC3SEL1_LC3D2S1 0x02
6087 #define _CLC3SEL1_D2S1 0x02
6088 #define _CLC3SEL1_LC3D2S2 0x04
6089 #define _CLC3SEL1_D2S2 0x04
6090 #define _CLC3SEL1_LC3D2S3 0x08
6091 #define _CLC3SEL1_D2S3 0x08
6092 #define _CLC3SEL1_LC3D2S4 0x10
6093 #define _CLC3SEL1_D2S4 0x10
6095 //==============================================================================
6098 //==============================================================================
6101 extern __at(0x0F28) __sfr CLC3SEL2
;
6107 unsigned LC3D3S0
: 1;
6108 unsigned LC3D3S1
: 1;
6109 unsigned LC3D3S2
: 1;
6110 unsigned LC3D3S3
: 1;
6111 unsigned LC3D3S4
: 1;
6137 unsigned LC3D3S
: 5;
6142 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
6144 #define _CLC3SEL2_LC3D3S0 0x01
6145 #define _CLC3SEL2_D3S0 0x01
6146 #define _CLC3SEL2_LC3D3S1 0x02
6147 #define _CLC3SEL2_D3S1 0x02
6148 #define _CLC3SEL2_LC3D3S2 0x04
6149 #define _CLC3SEL2_D3S2 0x04
6150 #define _CLC3SEL2_LC3D3S3 0x08
6151 #define _CLC3SEL2_D3S3 0x08
6152 #define _CLC3SEL2_LC3D3S4 0x10
6153 #define _CLC3SEL2_D3S4 0x10
6155 //==============================================================================
6158 //==============================================================================
6161 extern __at(0x0F29) __sfr CLC3SEL3
;
6167 unsigned LC3D4S0
: 1;
6168 unsigned LC3D4S1
: 1;
6169 unsigned LC3D4S2
: 1;
6170 unsigned LC3D4S3
: 1;
6171 unsigned LC3D4S4
: 1;
6197 unsigned LC3D4S
: 5;
6202 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
6204 #define _CLC3SEL3_LC3D4S0 0x01
6205 #define _CLC3SEL3_D4S0 0x01
6206 #define _CLC3SEL3_LC3D4S1 0x02
6207 #define _CLC3SEL3_D4S1 0x02
6208 #define _CLC3SEL3_LC3D4S2 0x04
6209 #define _CLC3SEL3_D4S2 0x04
6210 #define _CLC3SEL3_LC3D4S3 0x08
6211 #define _CLC3SEL3_D4S3 0x08
6212 #define _CLC3SEL3_LC3D4S4 0x10
6213 #define _CLC3SEL3_D4S4 0x10
6215 //==============================================================================
6218 //==============================================================================
6221 extern __at(0x0F2A) __sfr CLC3GLS0
;
6227 unsigned LC3G1D1N
: 1;
6228 unsigned LC3G1D1T
: 1;
6229 unsigned LC3G1D2N
: 1;
6230 unsigned LC3G1D2T
: 1;
6231 unsigned LC3G1D3N
: 1;
6232 unsigned LC3G1D3T
: 1;
6233 unsigned LC3G1D4N
: 1;
6234 unsigned LC3G1D4T
: 1;
6250 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
6252 #define _CLC3GLS0_LC3G1D1N 0x01
6253 #define _CLC3GLS0_D1N 0x01
6254 #define _CLC3GLS0_LC3G1D1T 0x02
6255 #define _CLC3GLS0_D1T 0x02
6256 #define _CLC3GLS0_LC3G1D2N 0x04
6257 #define _CLC3GLS0_D2N 0x04
6258 #define _CLC3GLS0_LC3G1D2T 0x08
6259 #define _CLC3GLS0_D2T 0x08
6260 #define _CLC3GLS0_LC3G1D3N 0x10
6261 #define _CLC3GLS0_D3N 0x10
6262 #define _CLC3GLS0_LC3G1D3T 0x20
6263 #define _CLC3GLS0_D3T 0x20
6264 #define _CLC3GLS0_LC3G1D4N 0x40
6265 #define _CLC3GLS0_D4N 0x40
6266 #define _CLC3GLS0_LC3G1D4T 0x80
6267 #define _CLC3GLS0_D4T 0x80
6269 //==============================================================================
6272 //==============================================================================
6275 extern __at(0x0F2B) __sfr CLC3GLS1
;
6281 unsigned LC3G2D1N
: 1;
6282 unsigned LC3G2D1T
: 1;
6283 unsigned LC3G2D2N
: 1;
6284 unsigned LC3G2D2T
: 1;
6285 unsigned LC3G2D3N
: 1;
6286 unsigned LC3G2D3T
: 1;
6287 unsigned LC3G2D4N
: 1;
6288 unsigned LC3G2D4T
: 1;
6304 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
6306 #define _CLC3GLS1_LC3G2D1N 0x01
6307 #define _CLC3GLS1_D1N 0x01
6308 #define _CLC3GLS1_LC3G2D1T 0x02
6309 #define _CLC3GLS1_D1T 0x02
6310 #define _CLC3GLS1_LC3G2D2N 0x04
6311 #define _CLC3GLS1_D2N 0x04
6312 #define _CLC3GLS1_LC3G2D2T 0x08
6313 #define _CLC3GLS1_D2T 0x08
6314 #define _CLC3GLS1_LC3G2D3N 0x10
6315 #define _CLC3GLS1_D3N 0x10
6316 #define _CLC3GLS1_LC3G2D3T 0x20
6317 #define _CLC3GLS1_D3T 0x20
6318 #define _CLC3GLS1_LC3G2D4N 0x40
6319 #define _CLC3GLS1_D4N 0x40
6320 #define _CLC3GLS1_LC3G2D4T 0x80
6321 #define _CLC3GLS1_D4T 0x80
6323 //==============================================================================
6326 //==============================================================================
6329 extern __at(0x0F2C) __sfr CLC3GLS2
;
6335 unsigned LC3G3D1N
: 1;
6336 unsigned LC3G3D1T
: 1;
6337 unsigned LC3G3D2N
: 1;
6338 unsigned LC3G3D2T
: 1;
6339 unsigned LC3G3D3N
: 1;
6340 unsigned LC3G3D3T
: 1;
6341 unsigned LC3G3D4N
: 1;
6342 unsigned LC3G3D4T
: 1;
6358 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
6360 #define _CLC3GLS2_LC3G3D1N 0x01
6361 #define _CLC3GLS2_D1N 0x01
6362 #define _CLC3GLS2_LC3G3D1T 0x02
6363 #define _CLC3GLS2_D1T 0x02
6364 #define _CLC3GLS2_LC3G3D2N 0x04
6365 #define _CLC3GLS2_D2N 0x04
6366 #define _CLC3GLS2_LC3G3D2T 0x08
6367 #define _CLC3GLS2_D2T 0x08
6368 #define _CLC3GLS2_LC3G3D3N 0x10
6369 #define _CLC3GLS2_D3N 0x10
6370 #define _CLC3GLS2_LC3G3D3T 0x20
6371 #define _CLC3GLS2_D3T 0x20
6372 #define _CLC3GLS2_LC3G3D4N 0x40
6373 #define _CLC3GLS2_D4N 0x40
6374 #define _CLC3GLS2_LC3G3D4T 0x80
6375 #define _CLC3GLS2_D4T 0x80
6377 //==============================================================================
6380 //==============================================================================
6383 extern __at(0x0F2D) __sfr CLC3GLS3
;
6389 unsigned LC3G4D1N
: 1;
6390 unsigned LC3G4D1T
: 1;
6391 unsigned LC3G4D2N
: 1;
6392 unsigned LC3G4D2T
: 1;
6393 unsigned LC3G4D3N
: 1;
6394 unsigned LC3G4D3T
: 1;
6395 unsigned LC3G4D4N
: 1;
6396 unsigned LC3G4D4T
: 1;
6412 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
6414 #define _CLC3GLS3_LC3G4D1N 0x01
6415 #define _CLC3GLS3_G4D1N 0x01
6416 #define _CLC3GLS3_LC3G4D1T 0x02
6417 #define _CLC3GLS3_G4D1T 0x02
6418 #define _CLC3GLS3_LC3G4D2N 0x04
6419 #define _CLC3GLS3_G4D2N 0x04
6420 #define _CLC3GLS3_LC3G4D2T 0x08
6421 #define _CLC3GLS3_G4D2T 0x08
6422 #define _CLC3GLS3_LC3G4D3N 0x10
6423 #define _CLC3GLS3_G4D3N 0x10
6424 #define _CLC3GLS3_LC3G4D3T 0x20
6425 #define _CLC3GLS3_G4D3T 0x20
6426 #define _CLC3GLS3_LC3G4D4N 0x40
6427 #define _CLC3GLS3_G4D4N 0x40
6428 #define _CLC3GLS3_LC3G4D4T 0x80
6429 #define _CLC3GLS3_G4D4T 0x80
6431 //==============================================================================
6434 //==============================================================================
6437 extern __at(0x0FE4) __sfr STATUS_SHAD
;
6441 unsigned C_SHAD
: 1;
6442 unsigned DC_SHAD
: 1;
6443 unsigned Z_SHAD
: 1;
6449 } __STATUS_SHADbits_t
;
6451 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
6453 #define _C_SHAD 0x01
6454 #define _DC_SHAD 0x02
6455 #define _Z_SHAD 0x04
6457 //==============================================================================
6459 extern __at(0x0FE5) __sfr WREG_SHAD
;
6460 extern __at(0x0FE6) __sfr BSR_SHAD
;
6461 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
6462 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
6463 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
6464 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
6465 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
6466 extern __at(0x0FED) __sfr STKPTR
;
6467 extern __at(0x0FEE) __sfr TOSL
;
6468 extern __at(0x0FEF) __sfr TOSH
;
6470 //==============================================================================
6472 // Configuration Bits
6474 //==============================================================================
6476 #define _CONFIG1 0x8007
6477 #define _CONFIG2 0x8008
6479 //----------------------------- CONFIG1 Options -------------------------------
6481 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
6482 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
6483 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
6484 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
6485 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
6486 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
6487 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
6488 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
6489 #define _WDTE_OFF 0x3FE7 // WDT disabled.
6490 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
6491 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
6492 #define _WDTE_ON 0x3FFF // WDT enabled.
6493 #define _PWRTE_ON 0x3FDF // PWRT enabled.
6494 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
6495 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
6496 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
6497 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
6498 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
6499 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
6500 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
6501 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
6502 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
6503 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
6504 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
6505 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
6506 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
6507 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
6508 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
6510 //----------------------------- CONFIG2 Options -------------------------------
6512 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
6513 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
6514 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
6515 #define _WRT_OFF 0x3FFF // Write protection off.
6516 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
6517 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
6518 #define _ZCDDIS_OFF 0x3F7F // Zero-cross detect circuit is enabled at POR.
6519 #define _ZCDDIS_ON 0x3FFF // Zero-cross detect circuit is disabled at POR.
6520 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
6521 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
6522 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
6523 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
6524 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
6525 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
6526 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
6527 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
6528 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
6529 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
6530 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
6531 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
6533 //==============================================================================
6535 #define _DEVID1 0x8006
6537 #define _IDLOC0 0x8000
6538 #define _IDLOC1 0x8001
6539 #define _IDLOC2 0x8002
6540 #define _IDLOC3 0x8003
6542 //==============================================================================
6544 #ifndef NO_BIT_DEFINES
6546 #define ADON ADCON0bits.ADON // bit 0
6547 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
6548 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
6549 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
6550 #define CHS0 ADCON0bits.CHS0 // bit 2
6551 #define CHS1 ADCON0bits.CHS1 // bit 3
6552 #define CHS2 ADCON0bits.CHS2 // bit 4
6553 #define CHS3 ADCON0bits.CHS3 // bit 5
6554 #define CHS4 ADCON0bits.CHS4 // bit 6
6556 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
6557 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
6558 #define ADNREF ADCON1bits.ADNREF // bit 2
6559 #define ADCS0 ADCON1bits.ADCS0 // bit 4
6560 #define ADCS1 ADCON1bits.ADCS1 // bit 5
6561 #define ADCS2 ADCON1bits.ADCS2 // bit 6
6562 #define ADFM ADCON1bits.ADFM // bit 7
6564 #define TRIGSEL0 ADCON2bits.TRIGSEL0 // bit 4
6565 #define TRIGSEL1 ADCON2bits.TRIGSEL1 // bit 5
6566 #define TRIGSEL2 ADCON2bits.TRIGSEL2 // bit 6
6567 #define TRIGSEL3 ADCON2bits.TRIGSEL3 // bit 7
6569 #define ANSA0 ANSELAbits.ANSA0 // bit 0
6570 #define ANSA1 ANSELAbits.ANSA1 // bit 1
6571 #define ANSA2 ANSELAbits.ANSA2 // bit 2
6572 #define ANSA4 ANSELAbits.ANSA4 // bit 4
6573 #define ANS5 ANSELAbits.ANS5 // bit 5
6575 #define ANSC0 ANSELCbits.ANSC0 // bit 0
6576 #define ANSC1 ANSELCbits.ANSC1 // bit 1
6577 #define ANSC2 ANSELCbits.ANSC2 // bit 2
6578 #define ANSC3 ANSELCbits.ANSC3 // bit 3
6579 #define ANSC4 ANSELCbits.ANSC4 // bit 4
6580 #define ANSC5 ANSELCbits.ANSC5 // bit 5
6582 #define ABDEN BAUD1CONbits.ABDEN // bit 0
6583 #define WUE BAUD1CONbits.WUE // bit 1
6584 #define BRG16 BAUD1CONbits.BRG16 // bit 3
6585 #define SCKP BAUD1CONbits.SCKP // bit 4
6586 #define RCIDL BAUD1CONbits.RCIDL // bit 6
6587 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
6589 #define BORRDY BORCONbits.BORRDY // bit 0
6590 #define BORFS BORCONbits.BORFS // bit 6
6591 #define SBOREN BORCONbits.SBOREN // bit 7
6593 #define BSR0 BSRbits.BSR0 // bit 0
6594 #define BSR1 BSRbits.BSR1 // bit 1
6595 #define BSR2 BSRbits.BSR2 // bit 2
6596 #define BSR3 BSRbits.BSR3 // bit 3
6597 #define BSR4 BSRbits.BSR4 // bit 4
6599 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
6600 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
6601 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
6602 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
6603 #define DC1B0 CCP1CONbits.DC1B0 // bit 4, shadows bit in CCP1CONbits
6604 #define CCP1Y CCP1CONbits.CCP1Y // bit 4, shadows bit in CCP1CONbits
6605 #define DC1B1 CCP1CONbits.DC1B1 // bit 5, shadows bit in CCP1CONbits
6606 #define CCP1X CCP1CONbits.CCP1X // bit 5, shadows bit in CCP1CONbits
6608 #define CCP2M0 CCP2CONbits.CCP2M0 // bit 0
6609 #define CCP2M1 CCP2CONbits.CCP2M1 // bit 1
6610 #define CCP2M2 CCP2CONbits.CCP2M2 // bit 2
6611 #define CCP2M3 CCP2CONbits.CCP2M3 // bit 3
6612 #define DC2B0 CCP2CONbits.DC2B0 // bit 4, shadows bit in CCP2CONbits
6613 #define CCP2Y CCP2CONbits.CCP2Y // bit 4, shadows bit in CCP2CONbits
6614 #define DC2B1 CCP2CONbits.DC2B1 // bit 5, shadows bit in CCP2CONbits
6615 #define CCP2X CCP2CONbits.CCP2X // bit 5, shadows bit in CCP2CONbits
6617 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
6618 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
6619 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
6620 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
6621 #define P3TSEL0 CCPTMRSbits.P3TSEL0 // bit 4
6622 #define P3TSEL1 CCPTMRSbits.P3TSEL1 // bit 5
6623 #define P4TSEL0 CCPTMRSbits.P4TSEL0 // bit 6
6624 #define P4TSEL1 CCPTMRSbits.P4TSEL1 // bit 7
6626 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
6627 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
6628 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
6629 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
6630 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
6631 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
6632 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
6633 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
6634 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
6635 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
6636 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
6637 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
6638 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
6639 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
6641 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
6642 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
6643 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
6644 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
6645 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
6646 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
6647 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
6648 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
6649 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
6650 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
6651 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
6652 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
6653 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
6654 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
6655 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
6656 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
6658 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
6659 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
6660 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
6661 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
6662 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
6663 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
6664 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
6665 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
6666 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
6667 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
6668 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
6669 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
6670 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
6671 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
6672 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
6673 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
6675 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
6676 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
6677 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
6678 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
6679 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
6680 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
6681 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
6682 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
6683 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
6684 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
6686 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
6687 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
6688 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
6689 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
6690 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
6691 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
6692 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
6693 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
6694 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
6695 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
6697 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
6698 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
6699 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
6700 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
6701 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
6702 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
6703 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
6704 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
6705 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
6706 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
6708 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
6709 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
6710 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
6711 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
6712 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
6713 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
6714 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
6715 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
6716 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
6717 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
6719 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
6720 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
6721 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
6722 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
6723 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
6724 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
6725 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
6726 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
6727 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
6728 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
6730 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
6731 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
6732 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
6734 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
6735 #define C1HYS CM1CON0bits.C1HYS // bit 1
6736 #define C1SP CM1CON0bits.C1SP // bit 2
6737 #define C1ZLF CM1CON0bits.C1ZLF // bit 3
6738 #define C1POL CM1CON0bits.C1POL // bit 4
6739 #define C1OUT CM1CON0bits.C1OUT // bit 6
6740 #define C1ON CM1CON0bits.C1ON // bit 7
6742 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
6743 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
6744 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
6745 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
6746 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
6747 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
6748 #define C1INTN CM1CON1bits.C1INTN // bit 6
6749 #define C1INTP CM1CON1bits.C1INTP // bit 7
6751 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
6752 #define C2HYS CM2CON0bits.C2HYS // bit 1
6753 #define C2SP CM2CON0bits.C2SP // bit 2
6754 #define C2ZLF CM2CON0bits.C2ZLF // bit 3
6755 #define C2POL CM2CON0bits.C2POL // bit 4
6756 #define C2OUT CM2CON0bits.C2OUT // bit 6
6757 #define C2ON CM2CON0bits.C2ON // bit 7
6759 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
6760 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
6761 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
6762 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
6763 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
6764 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
6765 #define C2INTN CM2CON1bits.C2INTN // bit 6
6766 #define C2INTP CM2CON1bits.C2INTP // bit 7
6768 #define MC1OUT CMOUTbits.MC1OUT // bit 0
6769 #define MC2OUT CMOUTbits.MC2OUT // bit 1
6771 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2
6772 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3
6773 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4
6774 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5
6775 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6
6776 #define G1ASE COG1ASD0bits.G1ASE // bit 7
6778 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0
6779 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1
6780 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2
6781 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3
6783 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0
6784 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1
6785 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2
6786 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3
6787 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4
6788 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5
6790 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0
6791 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1
6792 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2
6793 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3
6794 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4
6795 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5
6797 #define G1MD0 COG1CON0bits.G1MD0 // bit 0
6798 #define G1MD1 COG1CON0bits.G1MD1 // bit 1
6799 #define G1MD2 COG1CON0bits.G1MD2 // bit 2
6800 #define G1CS0 COG1CON0bits.G1CS0 // bit 3
6801 #define G1CS1 COG1CON0bits.G1CS1 // bit 4
6802 #define G1LD COG1CON0bits.G1LD // bit 6
6803 #define G1EN COG1CON0bits.G1EN // bit 7
6805 #define G1POLA COG1CON1bits.G1POLA // bit 0
6806 #define G1POLB COG1CON1bits.G1POLB // bit 1
6807 #define G1POLC COG1CON1bits.G1POLC // bit 2
6808 #define G1POLD COG1CON1bits.G1POLD // bit 3
6809 #define G1FDBS COG1CON1bits.G1FDBS // bit 6
6810 #define G1RDBS COG1CON1bits.G1RDBS // bit 7
6812 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0
6813 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1
6814 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2
6815 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3
6816 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4
6817 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5
6819 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0
6820 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1
6821 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2
6822 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3
6823 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4
6824 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5
6826 #define G1FIS0 COG1FISbits.G1FIS0 // bit 0
6827 #define G1FIS1 COG1FISbits.G1FIS1 // bit 1
6828 #define G1FIS2 COG1FISbits.G1FIS2 // bit 2
6829 #define G1FIS3 COG1FISbits.G1FIS3 // bit 3
6830 #define G1FIS4 COG1FISbits.G1FIS4 // bit 4
6831 #define G1FIS5 COG1FISbits.G1FIS5 // bit 5
6832 #define G1FIS6 COG1FISbits.G1FIS6 // bit 6
6834 #define G1FSIM0 COG1FSIMbits.G1FSIM0 // bit 0
6835 #define G1FSIM1 COG1FSIMbits.G1FSIM1 // bit 1
6836 #define G1FSIM2 COG1FSIMbits.G1FSIM2 // bit 2
6837 #define G1FSIM3 COG1FSIMbits.G1FSIM3 // bit 3
6838 #define G1FSIM4 COG1FSIMbits.G1FSIM4 // bit 4
6839 #define G1FSIM5 COG1FSIMbits.G1FSIM5 // bit 5
6840 #define G1FSIM6 COG1FSIMbits.G1FSIM6 // bit 6
6842 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0
6843 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1
6844 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2
6845 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3
6846 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4
6847 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5
6849 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0
6850 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1
6851 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2
6852 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3
6853 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4
6854 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5
6856 #define G1RIS0 COG1RISbits.G1RIS0 // bit 0
6857 #define G1RIS1 COG1RISbits.G1RIS1 // bit 1
6858 #define G1RIS2 COG1RISbits.G1RIS2 // bit 2
6859 #define G1RIS3 COG1RISbits.G1RIS3 // bit 3
6860 #define G1RIS4 COG1RISbits.G1RIS4 // bit 4
6861 #define G1RIS5 COG1RISbits.G1RIS5 // bit 5
6862 #define G1RIS6 COG1RISbits.G1RIS6 // bit 6
6864 #define G1RSIM0 COG1RSIMbits.G1RSIM0 // bit 0
6865 #define G1RSIM1 COG1RSIMbits.G1RSIM1 // bit 1
6866 #define G1RSIM2 COG1RSIMbits.G1RSIM2 // bit 2
6867 #define G1RSIM3 COG1RSIMbits.G1RSIM3 // bit 3
6868 #define G1RSIM4 COG1RSIMbits.G1RSIM4 // bit 4
6869 #define G1RSIM5 COG1RSIMbits.G1RSIM5 // bit 5
6870 #define G1RSIM6 COG1RSIMbits.G1RSIM6 // bit 6
6872 #define G1STRA COG1STRbits.G1STRA // bit 0
6873 #define G1STRB COG1STRbits.G1STRB // bit 1
6874 #define G1STRC COG1STRbits.G1STRC // bit 2
6875 #define G1STRD COG1STRbits.G1STRD // bit 3
6876 #define G1SDATA COG1STRbits.G1SDATA // bit 4
6877 #define G1SDATB COG1STRbits.G1SDATB // bit 5
6878 #define G1SDATC COG1STRbits.G1SDATC // bit 6
6879 #define G1SDATD COG1STRbits.G1SDATD // bit 7
6881 #define DAC1NSS DAC1CON0bits.DAC1NSS // bit 0, shadows bit in DAC1CON0bits
6882 #define DACNSS DAC1CON0bits.DACNSS // bit 0, shadows bit in DAC1CON0bits
6883 #define DAC1PSS0 DAC1CON0bits.DAC1PSS0 // bit 2, shadows bit in DAC1CON0bits
6884 #define DACPSS0 DAC1CON0bits.DACPSS0 // bit 2, shadows bit in DAC1CON0bits
6885 #define DAC1PSS1 DAC1CON0bits.DAC1PSS1 // bit 3, shadows bit in DAC1CON0bits
6886 #define DACPSS1 DAC1CON0bits.DACPSS1 // bit 3, shadows bit in DAC1CON0bits
6887 #define DAC1OE2 DAC1CON0bits.DAC1OE2 // bit 4, shadows bit in DAC1CON0bits
6888 #define DACOE0 DAC1CON0bits.DACOE0 // bit 4, shadows bit in DAC1CON0bits
6889 #define DAC1OE1 DAC1CON0bits.DAC1OE1 // bit 5, shadows bit in DAC1CON0bits
6890 #define DACOE1 DAC1CON0bits.DACOE1 // bit 5, shadows bit in DAC1CON0bits
6891 #define DAC1EN DAC1CON0bits.DAC1EN // bit 7, shadows bit in DAC1CON0bits
6892 #define DACEN DAC1CON0bits.DACEN // bit 7, shadows bit in DAC1CON0bits
6894 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
6895 #define DACR0 DAC1CON1bits.DACR0 // bit 0, shadows bit in DAC1CON1bits
6896 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
6897 #define DACR1 DAC1CON1bits.DACR1 // bit 1, shadows bit in DAC1CON1bits
6898 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
6899 #define DACR2 DAC1CON1bits.DACR2 // bit 2, shadows bit in DAC1CON1bits
6900 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
6901 #define DACR3 DAC1CON1bits.DACR3 // bit 3, shadows bit in DAC1CON1bits
6902 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
6903 #define DACR4 DAC1CON1bits.DACR4 // bit 4, shadows bit in DAC1CON1bits
6904 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
6905 #define DACR5 DAC1CON1bits.DACR5 // bit 5, shadows bit in DAC1CON1bits
6906 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
6907 #define DACR6 DAC1CON1bits.DACR6 // bit 6, shadows bit in DAC1CON1bits
6908 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
6909 #define DACR7 DAC1CON1bits.DACR7 // bit 7, shadows bit in DAC1CON1bits
6911 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
6912 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
6913 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
6914 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
6915 #define TSRNG FVRCONbits.TSRNG // bit 4
6916 #define TSEN FVRCONbits.TSEN // bit 5
6917 #define FVRRDY FVRCONbits.FVRRDY // bit 6
6918 #define FVREN FVRCONbits.FVREN // bit 7
6920 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
6921 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
6922 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
6923 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
6924 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
6925 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
6927 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
6928 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
6929 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
6930 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
6931 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
6932 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
6934 #define IOCIF INTCONbits.IOCIF // bit 0
6935 #define INTF INTCONbits.INTF // bit 1
6936 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
6937 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
6938 #define IOCIE INTCONbits.IOCIE // bit 3
6939 #define INTE INTCONbits.INTE // bit 4
6940 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
6941 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
6942 #define PEIE INTCONbits.PEIE // bit 6
6943 #define GIE INTCONbits.GIE // bit 7
6945 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
6946 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
6947 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
6948 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
6949 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
6950 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
6952 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
6953 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
6954 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
6955 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
6956 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
6957 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
6959 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
6960 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
6961 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
6962 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
6963 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
6964 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
6966 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
6967 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
6968 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
6969 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
6970 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
6971 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
6973 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
6974 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
6975 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
6976 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
6977 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
6978 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
6980 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
6981 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
6982 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
6983 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
6984 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
6985 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
6987 #define LATA0 LATAbits.LATA0 // bit 0
6988 #define LATA1 LATAbits.LATA1 // bit 1
6989 #define LATA2 LATAbits.LATA2 // bit 2
6990 #define LATA4 LATAbits.LATA4 // bit 4
6991 #define LATA5 LATAbits.LATA5 // bit 5
6993 #define LATC0 LATCbits.LATC0 // bit 0
6994 #define LATC1 LATCbits.LATC1 // bit 1
6995 #define LATC2 LATCbits.LATC2 // bit 2
6996 #define LATC3 LATCbits.LATC3 // bit 3
6997 #define LATC4 LATCbits.LATC4 // bit 4
6998 #define LATC5 LATCbits.LATC5 // bit 5
7000 #define ODA0 ODCONAbits.ODA0 // bit 0
7001 #define ODA1 ODCONAbits.ODA1 // bit 1
7002 #define ODA2 ODCONAbits.ODA2 // bit 2
7003 #define ODA4 ODCONAbits.ODA4 // bit 4
7004 #define ODA5 ODCONAbits.ODA5 // bit 5
7006 #define ODC0 ODCONCbits.ODC0 // bit 0
7007 #define ODC1 ODCONCbits.ODC1 // bit 1
7008 #define ODC2 ODCONCbits.ODC2 // bit 2
7009 #define ODC3 ODCONCbits.ODC3 // bit 3
7010 #define ODC4 ODCONCbits.ODC4 // bit 4
7011 #define ODC5 ODCONCbits.ODC5 // bit 5
7013 #define OPA1PCH0 OPA1CONbits.OPA1PCH0 // bit 0
7014 #define OPA1PCH1 OPA1CONbits.OPA1PCH1 // bit 1
7015 #define OPA1UG OPA1CONbits.OPA1UG // bit 4
7016 #define OPA1SP OPA1CONbits.OPA1SP // bit 6
7017 #define OPA1EN OPA1CONbits.OPA1EN // bit 7
7019 #define OPA2PCH0 OPA2CONbits.OPA2PCH0 // bit 0
7020 #define OPA2PCH1 OPA2CONbits.OPA2PCH1 // bit 1
7021 #define OPA2UG OPA2CONbits.OPA2UG // bit 4
7022 #define OPA2SP OPA2CONbits.OPA2SP // bit 6
7023 #define OPA2EN OPA2CONbits.OPA2EN // bit 7
7025 #define PS0 OPTION_REGbits.PS0 // bit 0
7026 #define PS1 OPTION_REGbits.PS1 // bit 1
7027 #define PS2 OPTION_REGbits.PS2 // bit 2
7028 #define PSA OPTION_REGbits.PSA // bit 3
7029 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
7030 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
7031 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
7032 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
7033 #define INTEDG OPTION_REGbits.INTEDG // bit 6
7034 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
7036 #define SCS0 OSCCONbits.SCS0 // bit 0
7037 #define SCS1 OSCCONbits.SCS1 // bit 1
7038 #define IRCF0 OSCCONbits.IRCF0 // bit 3
7039 #define IRCF1 OSCCONbits.IRCF1 // bit 4
7040 #define IRCF2 OSCCONbits.IRCF2 // bit 5
7041 #define IRCF3 OSCCONbits.IRCF3 // bit 6
7042 #define SPLLEN OSCCONbits.SPLLEN // bit 7
7044 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
7045 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
7046 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
7047 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
7048 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
7049 #define OSTS OSCSTATbits.OSTS // bit 5
7050 #define PLLR OSCSTATbits.PLLR // bit 6
7051 #define SOSCR OSCSTATbits.SOSCR // bit 7
7053 #define TUN0 OSCTUNEbits.TUN0 // bit 0
7054 #define TUN1 OSCTUNEbits.TUN1 // bit 1
7055 #define TUN2 OSCTUNEbits.TUN2 // bit 2
7056 #define TUN3 OSCTUNEbits.TUN3 // bit 3
7057 #define TUN4 OSCTUNEbits.TUN4 // bit 4
7058 #define TUN5 OSCTUNEbits.TUN5 // bit 5
7060 #define NOT_BOR PCONbits.NOT_BOR // bit 0
7061 #define NOT_POR PCONbits.NOT_POR // bit 1
7062 #define NOT_RI PCONbits.NOT_RI // bit 2
7063 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
7064 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
7065 #define STKUNF PCONbits.STKUNF // bit 6
7066 #define STKOVF PCONbits.STKOVF // bit 7
7068 #define TMR1IE PIE1bits.TMR1IE // bit 0
7069 #define TMR2IE PIE1bits.TMR2IE // bit 1
7070 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
7071 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
7072 #define SSP1IE PIE1bits.SSP1IE // bit 3
7073 #define TXIE PIE1bits.TXIE // bit 4
7074 #define RCIE PIE1bits.RCIE // bit 5
7075 #define ADIE PIE1bits.ADIE // bit 6
7076 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
7078 #define CCP2IE PIE2bits.CCP2IE // bit 0
7079 #define TMR4IE PIE2bits.TMR4IE // bit 1
7080 #define TMR6IE PIE2bits.TMR6IE // bit 2
7081 #define BCL1IE PIE2bits.BCL1IE // bit 3
7082 #define C1IE PIE2bits.C1IE // bit 5
7083 #define C2IE PIE2bits.C2IE // bit 6
7084 #define OSFIE PIE2bits.OSFIE // bit 7
7086 #define CLC1IE PIE3bits.CLC1IE // bit 0
7087 #define CLC2IE PIE3bits.CLC2IE // bit 1
7088 #define CLC3IE PIE3bits.CLC3IE // bit 2
7089 #define ZCDIE PIE3bits.ZCDIE // bit 4
7090 #define COGIE PIE3bits.COGIE // bit 5
7092 #define TMR1IF PIR1bits.TMR1IF // bit 0
7093 #define TMR2IF PIR1bits.TMR2IF // bit 1
7094 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
7095 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
7096 #define SSP1IF PIR1bits.SSP1IF // bit 3
7097 #define TXIF PIR1bits.TXIF // bit 4
7098 #define RCIF PIR1bits.RCIF // bit 5
7099 #define ADIF PIR1bits.ADIF // bit 6
7100 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
7102 #define CCP2IF PIR2bits.CCP2IF // bit 0
7103 #define TMR4IF PIR2bits.TMR4IF // bit 1
7104 #define TMR6IF PIR2bits.TMR6IF // bit 2
7105 #define BCL1IF PIR2bits.BCL1IF // bit 3
7106 #define C1IF PIR2bits.C1IF // bit 5
7107 #define C2IF PIR2bits.C2IF // bit 6
7108 #define OSFIF PIR2bits.OSFIF // bit 7
7110 #define CLC1IF PIR3bits.CLC1IF // bit 0
7111 #define CLC2IF PIR3bits.CLC2IF // bit 1
7112 #define CLC3IF PIR3bits.CLC3IF // bit 2
7113 #define ZCDIF PIR3bits.ZCDIF // bit 4
7114 #define COGIF PIR3bits.COGIF // bit 5
7116 #define RD PMCON1bits.RD // bit 0
7117 #define WR PMCON1bits.WR // bit 1
7118 #define WREN PMCON1bits.WREN // bit 2
7119 #define WRERR PMCON1bits.WRERR // bit 3
7120 #define FREE PMCON1bits.FREE // bit 4
7121 #define LWLO PMCON1bits.LWLO // bit 5
7122 #define CFGS PMCON1bits.CFGS // bit 6
7124 #define RA0 PORTAbits.RA0 // bit 0
7125 #define RA1 PORTAbits.RA1 // bit 1
7126 #define RA2 PORTAbits.RA2 // bit 2
7127 #define RA3 PORTAbits.RA3 // bit 3
7128 #define RA4 PORTAbits.RA4 // bit 4
7129 #define RA5 PORTAbits.RA5 // bit 5
7131 #define RC0 PORTCbits.RC0 // bit 0
7132 #define RC1 PORTCbits.RC1 // bit 1
7133 #define RC2 PORTCbits.RC2 // bit 2
7134 #define RC3 PORTCbits.RC3 // bit 3
7135 #define RC4 PORTCbits.RC4 // bit 4
7136 #define RC5 PORTCbits.RC5 // bit 5
7138 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
7140 #define PWM3POL PWM3CONbits.PWM3POL // bit 4
7141 #define PWM3OUT PWM3CONbits.PWM3OUT // bit 5
7142 #define PWM3EN PWM3CONbits.PWM3EN // bit 7
7144 #define PWM3DCH0 PWM3DCHbits.PWM3DCH0 // bit 0
7145 #define PWM3DCH1 PWM3DCHbits.PWM3DCH1 // bit 1
7146 #define PWM3DCH2 PWM3DCHbits.PWM3DCH2 // bit 2
7147 #define PWM3DCH3 PWM3DCHbits.PWM3DCH3 // bit 3
7148 #define PWM3DCH4 PWM3DCHbits.PWM3DCH4 // bit 4
7149 #define PWM3DCH5 PWM3DCHbits.PWM3DCH5 // bit 5
7150 #define PWM3DCH6 PWM3DCHbits.PWM3DCH6 // bit 6
7151 #define PWM3DCH7 PWM3DCHbits.PWM3DCH7 // bit 7
7153 #define PWM3DCL0 PWM3DCLbits.PWM3DCL0 // bit 6
7154 #define PWM3DCL1 PWM3DCLbits.PWM3DCL1 // bit 7
7156 #define PWM4POL PWM4CONbits.PWM4POL // bit 4
7157 #define PWM4OUT PWM4CONbits.PWM4OUT // bit 5
7158 #define PWM4EN PWM4CONbits.PWM4EN // bit 7
7160 #define PWM4DCH0 PWM4DCHbits.PWM4DCH0 // bit 0
7161 #define PWM4DCH1 PWM4DCHbits.PWM4DCH1 // bit 1
7162 #define PWM4DCH2 PWM4DCHbits.PWM4DCH2 // bit 2
7163 #define PWM4DCH3 PWM4DCHbits.PWM4DCH3 // bit 3
7164 #define PWM4DCH4 PWM4DCHbits.PWM4DCH4 // bit 4
7165 #define PWM4DCH5 PWM4DCHbits.PWM4DCH5 // bit 5
7166 #define PWM4DCH6 PWM4DCHbits.PWM4DCH6 // bit 6
7167 #define PWM4DCH7 PWM4DCHbits.PWM4DCH7 // bit 7
7169 #define PWM4DCL0 PWM4DCLbits.PWM4DCL0 // bit 6
7170 #define PWM4DCL1 PWM4DCLbits.PWM4DCL1 // bit 7
7172 #define RX9D RC1STAbits.RX9D // bit 0
7173 #define OERR RC1STAbits.OERR // bit 1
7174 #define FERR RC1STAbits.FERR // bit 2
7175 #define ADDEN RC1STAbits.ADDEN // bit 3
7176 #define CREN RC1STAbits.CREN // bit 4
7177 #define SREN RC1STAbits.SREN // bit 5
7178 #define RX9 RC1STAbits.RX9 // bit 6
7179 #define SPEN RC1STAbits.SPEN // bit 7
7181 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
7182 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
7183 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
7184 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
7185 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
7187 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
7188 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
7189 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
7190 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
7191 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
7192 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
7194 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
7195 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
7196 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
7197 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
7198 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
7199 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
7200 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
7201 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
7202 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
7203 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
7204 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
7205 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
7206 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
7207 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
7208 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
7209 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
7211 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
7212 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
7213 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
7214 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
7215 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
7216 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
7217 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
7218 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
7219 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
7220 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
7221 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
7222 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
7223 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
7224 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
7225 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
7226 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
7228 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
7229 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
7230 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
7231 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
7232 #define CKP SSP1CONbits.CKP // bit 4
7233 #define SSPEN SSP1CONbits.SSPEN // bit 5
7234 #define SSPOV SSP1CONbits.SSPOV // bit 6
7235 #define WCOL SSP1CONbits.WCOL // bit 7
7237 #define SEN SSP1CON2bits.SEN // bit 0
7238 #define RSEN SSP1CON2bits.RSEN // bit 1
7239 #define PEN SSP1CON2bits.PEN // bit 2
7240 #define RCEN SSP1CON2bits.RCEN // bit 3
7241 #define ACKEN SSP1CON2bits.ACKEN // bit 4
7242 #define ACKDT SSP1CON2bits.ACKDT // bit 5
7243 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
7244 #define GCEN SSP1CON2bits.GCEN // bit 7
7246 #define DHEN SSP1CON3bits.DHEN // bit 0
7247 #define AHEN SSP1CON3bits.AHEN // bit 1
7248 #define SBCDE SSP1CON3bits.SBCDE // bit 2
7249 #define SDAHT SSP1CON3bits.SDAHT // bit 3
7250 #define BOEN SSP1CON3bits.BOEN // bit 4
7251 #define SCIE SSP1CON3bits.SCIE // bit 5
7252 #define PCIE SSP1CON3bits.PCIE // bit 6
7253 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
7255 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
7256 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
7257 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
7258 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
7259 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
7260 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
7261 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
7262 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
7263 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
7264 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
7265 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
7266 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
7267 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
7268 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
7269 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
7270 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
7272 #define BF SSP1STATbits.BF // bit 0
7273 #define UA SSP1STATbits.UA // bit 1
7274 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
7275 #define S SSP1STATbits.S // bit 3
7276 #define P SSP1STATbits.P // bit 4
7277 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
7278 #define CKE SSP1STATbits.CKE // bit 6
7279 #define SMP SSP1STATbits.SMP // bit 7
7281 #define C STATUSbits.C // bit 0
7282 #define DC STATUSbits.DC // bit 1
7283 #define Z STATUSbits.Z // bit 2
7284 #define NOT_PD STATUSbits.NOT_PD // bit 3
7285 #define NOT_TO STATUSbits.NOT_TO // bit 4
7287 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
7288 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
7289 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
7291 #define TMR1ON T1CONbits.TMR1ON // bit 0
7292 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
7293 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
7294 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
7295 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
7296 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
7297 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
7299 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
7300 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
7301 #define T1GVAL T1GCONbits.T1GVAL // bit 2
7302 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
7303 #define T1GSPM T1GCONbits.T1GSPM // bit 4
7304 #define T1GTM T1GCONbits.T1GTM // bit 5
7305 #define T1GPOL T1GCONbits.T1GPOL // bit 6
7306 #define TMR1GE T1GCONbits.TMR1GE // bit 7
7308 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
7309 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
7310 #define TMR2ON T2CONbits.TMR2ON // bit 2
7311 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
7312 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
7313 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
7314 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
7316 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
7317 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
7318 #define TMR4ON T4CONbits.TMR4ON // bit 2
7319 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
7320 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
7321 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
7322 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
7324 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
7325 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
7326 #define TMR6ON T6CONbits.TMR6ON // bit 2
7327 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
7328 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
7329 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
7330 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
7332 #define TRISA0 TRISAbits.TRISA0 // bit 0
7333 #define TRISA1 TRISAbits.TRISA1 // bit 1
7334 #define TRISA2 TRISAbits.TRISA2 // bit 2
7335 #define TRISA4 TRISAbits.TRISA4 // bit 4
7336 #define TRISA5 TRISAbits.TRISA5 // bit 5
7338 #define TRISC0 TRISCbits.TRISC0 // bit 0
7339 #define TRISC1 TRISCbits.TRISC1 // bit 1
7340 #define TRISC2 TRISCbits.TRISC2 // bit 2
7341 #define TRISC3 TRISCbits.TRISC3 // bit 3
7342 #define TRISC4 TRISCbits.TRISC4 // bit 4
7343 #define TRISC5 TRISCbits.TRISC5 // bit 5
7345 #define TX9D TX1STAbits.TX9D // bit 0
7346 #define TRMT TX1STAbits.TRMT // bit 1
7347 #define BRGH TX1STAbits.BRGH // bit 2
7348 #define SENDB TX1STAbits.SENDB // bit 3
7349 #define SYNC TX1STAbits.SYNC // bit 4
7350 #define TXEN TX1STAbits.TXEN // bit 5
7351 #define TX9 TX1STAbits.TX9 // bit 6
7352 #define CSRC TX1STAbits.CSRC // bit 7
7354 #define SWDTEN WDTCONbits.SWDTEN // bit 0
7355 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
7356 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
7357 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
7358 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
7359 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
7361 #define WPUA0 WPUAbits.WPUA0 // bit 0
7362 #define WPUA1 WPUAbits.WPUA1 // bit 1
7363 #define WPUA2 WPUAbits.WPUA2 // bit 2
7364 #define WPUA3 WPUAbits.WPUA3 // bit 3
7365 #define WPUA4 WPUAbits.WPUA4 // bit 4
7366 #define WPUA5 WPUAbits.WPUA5 // bit 5
7368 #define WPUC0 WPUCbits.WPUC0 // bit 0
7369 #define WPUC1 WPUCbits.WPUC1 // bit 1
7370 #define WPUC2 WPUCbits.WPUC2 // bit 2
7371 #define WPUC3 WPUCbits.WPUC3 // bit 3
7372 #define WPUC4 WPUCbits.WPUC4 // bit 4
7373 #define WPUC5 WPUCbits.WPUC5 // bit 5
7375 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
7376 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
7377 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
7378 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
7379 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
7381 #endif // #ifndef NO_BIT_DEFINES
7383 #endif // #ifndef __PIC16LF1704_H__