2 * This declarations of the PIC16LF1769 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:14 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF1769_H__
26 #define __PIC16LF1769_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define PIR4_ADDR 0x0014
57 #define TMR0_ADDR 0x0015
58 #define TMR1_ADDR 0x0016
59 #define TMR1L_ADDR 0x0016
60 #define TMR1H_ADDR 0x0017
61 #define T1CON_ADDR 0x0018
62 #define T1GCON_ADDR 0x0019
63 #define T2TMR_ADDR 0x001A
64 #define TMR2_ADDR 0x001A
65 #define PR2_ADDR 0x001B
66 #define T2PR_ADDR 0x001B
67 #define T2CON_ADDR 0x001C
68 #define T2HLT_ADDR 0x001D
69 #define T2CLKCON_ADDR 0x001E
70 #define T2RST_ADDR 0x001F
71 #define TRISA_ADDR 0x008C
72 #define TRISB_ADDR 0x008D
73 #define TRISC_ADDR 0x008E
74 #define PIE1_ADDR 0x0091
75 #define PIE2_ADDR 0x0092
76 #define PIE3_ADDR 0x0093
77 #define PIE4_ADDR 0x0094
78 #define OPTION_REG_ADDR 0x0095
79 #define PCON_ADDR 0x0096
80 #define WDTCON_ADDR 0x0097
81 #define OSCTUNE_ADDR 0x0098
82 #define OSCCON_ADDR 0x0099
83 #define OSCSTAT_ADDR 0x009A
84 #define ADRES_ADDR 0x009B
85 #define ADRESL_ADDR 0x009B
86 #define ADRESH_ADDR 0x009C
87 #define ADCON0_ADDR 0x009D
88 #define ADCON1_ADDR 0x009E
89 #define ADCON2_ADDR 0x009F
90 #define LATA_ADDR 0x010C
91 #define LATB_ADDR 0x010D
92 #define LATC_ADDR 0x010E
93 #define CMOUT_ADDR 0x010F
94 #define CM1CON0_ADDR 0x0110
95 #define CM1CON1_ADDR 0x0111
96 #define CM1NSEL_ADDR 0x0112
97 #define CM1PSEL_ADDR 0x0113
98 #define CM2CON0_ADDR 0x0114
99 #define CM2CON1_ADDR 0x0115
100 #define CM2NSEL_ADDR 0x0116
101 #define CM2PSEL_ADDR 0x0117
102 #define CM3CON0_ADDR 0x0118
103 #define CM3CON1_ADDR 0x0119
104 #define CM3NSEL_ADDR 0x011A
105 #define CM3PSEL_ADDR 0x011B
106 #define CM4CON0_ADDR 0x011C
107 #define CM4CON1_ADDR 0x011D
108 #define CM4NSEL_ADDR 0x011E
109 #define CM4PSEL_ADDR 0x011F
110 #define ANSELA_ADDR 0x018C
111 #define ANSELB_ADDR 0x018D
112 #define ANSELC_ADDR 0x018E
113 #define PMADR_ADDR 0x0191
114 #define PMADRL_ADDR 0x0191
115 #define PMADRH_ADDR 0x0192
116 #define PMDAT_ADDR 0x0193
117 #define PMDATL_ADDR 0x0193
118 #define PMDATH_ADDR 0x0194
119 #define PMCON1_ADDR 0x0195
120 #define PMCON2_ADDR 0x0196
121 #define RC1REG_ADDR 0x0199
122 #define RCREG_ADDR 0x0199
123 #define RCREG1_ADDR 0x0199
124 #define TX1REG_ADDR 0x019A
125 #define TXREG_ADDR 0x019A
126 #define TXREG1_ADDR 0x019A
127 #define SP1BRG_ADDR 0x019B
128 #define SP1BRGL_ADDR 0x019B
129 #define SPBRG_ADDR 0x019B
130 #define SPBRG1_ADDR 0x019B
131 #define SPBRGL_ADDR 0x019B
132 #define SP1BRGH_ADDR 0x019C
133 #define SPBRGH_ADDR 0x019C
134 #define SPBRGH1_ADDR 0x019C
135 #define RC1STA_ADDR 0x019D
136 #define RCSTA_ADDR 0x019D
137 #define RCSTA1_ADDR 0x019D
138 #define TX1STA_ADDR 0x019E
139 #define TXSTA_ADDR 0x019E
140 #define TXSTA1_ADDR 0x019E
141 #define BAUD1CON_ADDR 0x019F
142 #define BAUDCON_ADDR 0x019F
143 #define BAUDCON1_ADDR 0x019F
144 #define BAUDCTL_ADDR 0x019F
145 #define BAUDCTL1_ADDR 0x019F
146 #define WPUA_ADDR 0x020C
147 #define WPUB_ADDR 0x020D
148 #define WPUC_ADDR 0x020E
149 #define SSP1BUF_ADDR 0x0211
150 #define SSPBUF_ADDR 0x0211
151 #define SSP1ADD_ADDR 0x0212
152 #define SSPADD_ADDR 0x0212
153 #define SSP1MSK_ADDR 0x0213
154 #define SSPMSK_ADDR 0x0213
155 #define SSP1STAT_ADDR 0x0214
156 #define SSPSTAT_ADDR 0x0214
157 #define SSP1CON_ADDR 0x0215
158 #define SSP1CON1_ADDR 0x0215
159 #define SSPCON_ADDR 0x0215
160 #define SSPCON1_ADDR 0x0215
161 #define SSP1CON2_ADDR 0x0216
162 #define SSPCON2_ADDR 0x0216
163 #define SSP1CON3_ADDR 0x0217
164 #define SSPCON3_ADDR 0x0217
165 #define BORCON_ADDR 0x021D
166 #define FVRCON_ADDR 0x021E
167 #define ZCD1CON_ADDR 0x021F
168 #define ODCONA_ADDR 0x028C
169 #define ODCONB_ADDR 0x028D
170 #define ODCONC_ADDR 0x028E
171 #define CCPR1_ADDR 0x0291
172 #define CCPR1L_ADDR 0x0291
173 #define CCPR1H_ADDR 0x0292
174 #define CCP1CON_ADDR 0x0293
175 #define CCP1CAP_ADDR 0x0294
176 #define CCPR2_ADDR 0x0298
177 #define CCPR2L_ADDR 0x0298
178 #define CCPR2H_ADDR 0x0299
179 #define CCP2CON_ADDR 0x029A
180 #define CCP2CAP_ADDR 0x029B
181 #define CCPTMRS_ADDR 0x029E
182 #define SLRCONA_ADDR 0x030C
183 #define SLRCONB_ADDR 0x030D
184 #define SLRCONC_ADDR 0x030E
185 #define MD2CON0_ADDR 0x031B
186 #define MD2CON1_ADDR 0x031C
187 #define MD2SRC_ADDR 0x031D
188 #define MD2CARL_ADDR 0x031E
189 #define MD2CARH_ADDR 0x031F
190 #define INLVLA_ADDR 0x038C
191 #define INLVLB_ADDR 0x038D
192 #define INLVLC_ADDR 0x038E
193 #define IOCAP_ADDR 0x0391
194 #define IOCAN_ADDR 0x0392
195 #define IOCAF_ADDR 0x0393
196 #define IOCBP_ADDR 0x0394
197 #define IOCBN_ADDR 0x0395
198 #define IOCBF_ADDR 0x0396
199 #define IOCCP_ADDR 0x0397
200 #define IOCCN_ADDR 0x0398
201 #define IOCCF_ADDR 0x0399
202 #define MD1CON0_ADDR 0x039B
203 #define MD1CON1_ADDR 0x039C
204 #define MD1SRC_ADDR 0x039D
205 #define MD1CARL_ADDR 0x039E
206 #define MD1CARH_ADDR 0x039F
207 #define HIDRVC_ADDR 0x040E
208 #define T4TMR_ADDR 0x0413
209 #define TMR4_ADDR 0x0413
210 #define PR4_ADDR 0x0414
211 #define T4PR_ADDR 0x0414
212 #define T4CON_ADDR 0x0415
213 #define T4HLT_ADDR 0x0416
214 #define T4CLKCON_ADDR 0x0417
215 #define T4RST_ADDR 0x0418
216 #define T6TMR_ADDR 0x041A
217 #define TMR6_ADDR 0x041A
218 #define PR6_ADDR 0x041B
219 #define T6PR_ADDR 0x041B
220 #define T6CON_ADDR 0x041C
221 #define T6HLT_ADDR 0x041D
222 #define T6CLKCON_ADDR 0x041E
223 #define T6RST_ADDR 0x041F
224 #define TMR3_ADDR 0x0493
225 #define TMR3L_ADDR 0x0493
226 #define TMR3H_ADDR 0x0494
227 #define T3CON_ADDR 0x0495
228 #define T3GCON_ADDR 0x0496
229 #define TMR5_ADDR 0x049A
230 #define TMR5L_ADDR 0x049A
231 #define TMR5H_ADDR 0x049B
232 #define T5CON_ADDR 0x049C
233 #define T5GCON_ADDR 0x049D
234 #define OPA1NCHS_ADDR 0x050F
235 #define OPA1PCHS_ADDR 0x0510
236 #define OPA1CON_ADDR 0x0511
237 #define OPA1ORS_ADDR 0x0512
238 #define OPA2NCHS_ADDR 0x0513
239 #define OPA2PCHS_ADDR 0x0514
240 #define OPA2CON_ADDR 0x0515
241 #define OPA2ORS_ADDR 0x0516
242 #define DACLD_ADDR 0x0590
243 #define DAC1CON0_ADDR 0x0591
244 #define DAC1CON1_ADDR 0x0592
245 #define DAC1REF_ADDR 0x0592
246 #define DAC1REFL_ADDR 0x0592
247 #define DAC1CON2_ADDR 0x0593
248 #define DAC1REFH_ADDR 0x0593
249 #define DAC2CON0_ADDR 0x0594
250 #define DAC2CON1_ADDR 0x0595
251 #define DAC2REF_ADDR 0x0595
252 #define DAC2REFL_ADDR 0x0595
253 #define DAC2CON2_ADDR 0x0596
254 #define DAC2REFH_ADDR 0x0596
255 #define DAC3CON0_ADDR 0x0597
256 #define DAC3CON1_ADDR 0x0598
257 #define DAC3REF_ADDR 0x0598
258 #define DAC4CON0_ADDR 0x0599
259 #define DAC4CON1_ADDR 0x059A
260 #define DAC4REF_ADDR 0x059A
261 #define PWM3DCL_ADDR 0x0617
262 #define PWM3DCH_ADDR 0x0618
263 #define PWM3CON_ADDR 0x0619
264 #define PWM4DCL_ADDR 0x061A
265 #define PWM4DCH_ADDR 0x061B
266 #define PWM4CON_ADDR 0x061C
267 #define COG1PHR_ADDR 0x068D
268 #define COG1PHF_ADDR 0x068E
269 #define COG1BLKR_ADDR 0x068F
270 #define COG1BLKF_ADDR 0x0690
271 #define COG1DBR_ADDR 0x0691
272 #define COG1DBF_ADDR 0x0692
273 #define COG1CON0_ADDR 0x0693
274 #define COG1CON1_ADDR 0x0694
275 #define COG1RIS0_ADDR 0x0695
276 #define COG1RIS1_ADDR 0x0696
277 #define COG1RSIM0_ADDR 0x0697
278 #define COG1RSIM1_ADDR 0x0698
279 #define COG1FIS0_ADDR 0x0699
280 #define COG1FIS1_ADDR 0x069A
281 #define COG1FSIM0_ADDR 0x069B
282 #define COG1FSIM1_ADDR 0x069C
283 #define COG1ASD0_ADDR 0x069D
284 #define COG1ASD1_ADDR 0x069E
285 #define COG1STR_ADDR 0x069F
286 #define COG2PHR_ADDR 0x070D
287 #define COG2PHF_ADDR 0x070E
288 #define COG2BLKR_ADDR 0x070F
289 #define COG2BLKF_ADDR 0x0710
290 #define COG2DBR_ADDR 0x0711
291 #define COG2DBF_ADDR 0x0712
292 #define COG2CON0_ADDR 0x0713
293 #define COG2CON1_ADDR 0x0714
294 #define COG2RIS0_ADDR 0x0715
295 #define COG2RIS1_ADDR 0x0716
296 #define COG2RSIM0_ADDR 0x0717
297 #define COG2RSIM1_ADDR 0x0718
298 #define COG2FIS0_ADDR 0x0719
299 #define COG2FIS1_ADDR 0x071A
300 #define COG2FSIM0_ADDR 0x071B
301 #define COG2FSIM1_ADDR 0x071C
302 #define COG2ASD0_ADDR 0x071D
303 #define COG2ASD1_ADDR 0x071E
304 #define COG2STR_ADDR 0x071F
305 #define PRG1RTSS_ADDR 0x0794
306 #define PRG1FTSS_ADDR 0x0795
307 #define PRG1INS_ADDR 0x0796
308 #define PRG1CON0_ADDR 0x0797
309 #define PRG1CON1_ADDR 0x0798
310 #define PRG1CON2_ADDR 0x0799
311 #define PRG2RTSS_ADDR 0x079A
312 #define PRG2FTSS_ADDR 0x079B
313 #define PRG2INS_ADDR 0x079C
314 #define PRG2CON0_ADDR 0x079D
315 #define PRG2CON1_ADDR 0x079E
316 #define PRG2CON2_ADDR 0x079F
317 #define PWMEN_ADDR 0x0D8E
318 #define PWMLD_ADDR 0x0D8F
319 #define PWMOUT_ADDR 0x0D90
320 #define PWM5PH_ADDR 0x0D91
321 #define PWM5PHL_ADDR 0x0D91
322 #define PWM5PHH_ADDR 0x0D92
323 #define PWM5DC_ADDR 0x0D93
324 #define PWM5DCL_ADDR 0x0D93
325 #define PWM5DCH_ADDR 0x0D94
326 #define PWM5PR_ADDR 0x0D95
327 #define PWM5PRL_ADDR 0x0D95
328 #define PWM5PRH_ADDR 0x0D96
329 #define PWM5OF_ADDR 0x0D97
330 #define PWM5OFL_ADDR 0x0D97
331 #define PWM5OFH_ADDR 0x0D98
332 #define PWM5TMR_ADDR 0x0D99
333 #define PWM5TMRL_ADDR 0x0D99
334 #define PWM5TMRH_ADDR 0x0D9A
335 #define PWM5CON_ADDR 0x0D9B
336 #define PWM5INTCON_ADDR 0x0D9C
337 #define PWM5INTE_ADDR 0x0D9C
338 #define PWM5INTF_ADDR 0x0D9D
339 #define PWM5INTFLG_ADDR 0x0D9D
340 #define PWM5CLKCON_ADDR 0x0D9E
341 #define PWM5LDCON_ADDR 0x0D9F
342 #define PWM5OFCON_ADDR 0x0DA0
343 #define PWM6PH_ADDR 0x0DA1
344 #define PWM6PHL_ADDR 0x0DA1
345 #define PWM6PHH_ADDR 0x0DA2
346 #define PWM6DC_ADDR 0x0DA3
347 #define PWM6DCL_ADDR 0x0DA3
348 #define PWM6DCH_ADDR 0x0DA4
349 #define PWM6PR_ADDR 0x0DA5
350 #define PWM6PRL_ADDR 0x0DA5
351 #define PWM6PRH_ADDR 0x0DA6
352 #define PWM6OF_ADDR 0x0DA7
353 #define PWM6OFL_ADDR 0x0DA7
354 #define PWM6OFH_ADDR 0x0DA8
355 #define PWM6TMR_ADDR 0x0DA9
356 #define PWM6TMRL_ADDR 0x0DA9
357 #define PWM6TMRH_ADDR 0x0DAA
358 #define PWM6CON_ADDR 0x0DAB
359 #define PWM6INTCON_ADDR 0x0DAC
360 #define PWM6INTE_ADDR 0x0DAC
361 #define PWM6INTF_ADDR 0x0DAD
362 #define PWM6INTFLG_ADDR 0x0DAD
363 #define PWM6CLKCON_ADDR 0x0DAE
364 #define PWM6LDCON_ADDR 0x0DAF
365 #define PWM6OFCON_ADDR 0x0DB0
366 #define PPSLOCK_ADDR 0x0E0F
367 #define INTPPS_ADDR 0x0E10
368 #define T0CKIPPS_ADDR 0x0E11
369 #define T1CKIPPS_ADDR 0x0E12
370 #define T1GPPS_ADDR 0x0E13
371 #define CCP1PPS_ADDR 0x0E14
372 #define CCP2PPS_ADDR 0x0E15
373 #define COG1INPPS_ADDR 0x0E16
374 #define COG2INPPS_ADDR 0x0E17
375 #define T2CKIPPS_ADDR 0x0E19
376 #define T3CKIPPS_ADDR 0x0E1A
377 #define T3GPPS_ADDR 0x0E1B
378 #define T4CKIPPS_ADDR 0x0E1C
379 #define T5CKIPPS_ADDR 0x0E1D
380 #define T5GPPS_ADDR 0x0E1E
381 #define T6CKIPPS_ADDR 0x0E1F
382 #define SSPCLKPPS_ADDR 0x0E20
383 #define SSPDATPPS_ADDR 0x0E21
384 #define SSPSSPPS_ADDR 0x0E22
385 #define RXPPS_ADDR 0x0E24
386 #define CKPPS_ADDR 0x0E25
387 #define CLCIN0PPS_ADDR 0x0E28
388 #define CLCIN1PPS_ADDR 0x0E29
389 #define CLCIN2PPS_ADDR 0x0E2A
390 #define CLCIN3PPS_ADDR 0x0E2B
391 #define PRG1RPPS_ADDR 0x0E2C
392 #define PRG1FPPS_ADDR 0x0E2D
393 #define PRG2RPPS_ADDR 0x0E2E
394 #define PRG2FPPS_ADDR 0x0E2F
395 #define MD1CHPPS_ADDR 0x0E30
396 #define MD1CLPPS_ADDR 0x0E31
397 #define MD1MODPPS_ADDR 0x0E32
398 #define MD2CHPPS_ADDR 0x0E33
399 #define MD2CLPPS_ADDR 0x0E34
400 #define MD2MODPPS_ADDR 0x0E35
401 #define RA0PPS_ADDR 0x0E90
402 #define RA1PPS_ADDR 0x0E91
403 #define RA2PPS_ADDR 0x0E92
404 #define RA4PPS_ADDR 0x0E94
405 #define RA5PPS_ADDR 0x0E95
406 #define RB4PPS_ADDR 0x0E9C
407 #define RB5PPS_ADDR 0x0E9D
408 #define RB6PPS_ADDR 0x0E9E
409 #define RB7PPS_ADDR 0x0E9F
410 #define RC0PPS_ADDR 0x0EA0
411 #define RC1PPS_ADDR 0x0EA1
412 #define RC2PPS_ADDR 0x0EA2
413 #define RC3PPS_ADDR 0x0EA3
414 #define RC4PPS_ADDR 0x0EA4
415 #define RC5PPS_ADDR 0x0EA5
416 #define RC6PPS_ADDR 0x0EA6
417 #define RC7PPS_ADDR 0x0EA7
418 #define CLCDATA_ADDR 0x0F0F
419 #define CLC1CON_ADDR 0x0F10
420 #define CLC1POL_ADDR 0x0F11
421 #define CLC1SEL0_ADDR 0x0F12
422 #define CLC1SEL1_ADDR 0x0F13
423 #define CLC1SEL2_ADDR 0x0F14
424 #define CLC1SEL3_ADDR 0x0F15
425 #define CLC1GLS0_ADDR 0x0F16
426 #define CLC1GLS1_ADDR 0x0F17
427 #define CLC1GLS2_ADDR 0x0F18
428 #define CLC1GLS3_ADDR 0x0F19
429 #define CLC2CON_ADDR 0x0F1A
430 #define CLC2POL_ADDR 0x0F1B
431 #define CLC2SEL0_ADDR 0x0F1C
432 #define CLC2SEL1_ADDR 0x0F1D
433 #define CLC2SEL2_ADDR 0x0F1E
434 #define CLC2SEL3_ADDR 0x0F1F
435 #define CLC2GLS0_ADDR 0x0F20
436 #define CLC2GLS1_ADDR 0x0F21
437 #define CLC2GLS2_ADDR 0x0F22
438 #define CLC2GLS3_ADDR 0x0F23
439 #define CLC3CON_ADDR 0x0F24
440 #define CLC3POL_ADDR 0x0F25
441 #define CLC3SEL0_ADDR 0x0F26
442 #define CLC3SEL1_ADDR 0x0F27
443 #define CLC3SEL2_ADDR 0x0F28
444 #define CLC3SEL3_ADDR 0x0F29
445 #define CLC3GLS0_ADDR 0x0F2A
446 #define CLC3GLS1_ADDR 0x0F2B
447 #define CLC3GLS2_ADDR 0x0F2C
448 #define CLC3GLS3_ADDR 0x0F2D
449 #define STATUS_SHAD_ADDR 0x0FE4
450 #define WREG_SHAD_ADDR 0x0FE5
451 #define BSR_SHAD_ADDR 0x0FE6
452 #define PCLATH_SHAD_ADDR 0x0FE7
453 #define FSR0L_SHAD_ADDR 0x0FE8
454 #define FSR0H_SHAD_ADDR 0x0FE9
455 #define FSR1L_SHAD_ADDR 0x0FEA
456 #define FSR1H_SHAD_ADDR 0x0FEB
457 #define STKPTR_ADDR 0x0FED
458 #define TOSL_ADDR 0x0FEE
459 #define TOSH_ADDR 0x0FEF
461 #endif // #ifndef NO_ADDR_DEFINES
463 //==============================================================================
465 // Register Definitions
467 //==============================================================================
469 extern __at(0x0000) __sfr INDF0
;
470 extern __at(0x0001) __sfr INDF1
;
471 extern __at(0x0002) __sfr PCL
;
473 //==============================================================================
476 extern __at(0x0003) __sfr STATUS
;
490 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
498 //==============================================================================
500 extern __at(0x0004) __sfr FSR0
;
501 extern __at(0x0004) __sfr FSR0L
;
502 extern __at(0x0005) __sfr FSR0H
;
503 extern __at(0x0006) __sfr FSR1
;
504 extern __at(0x0006) __sfr FSR1L
;
505 extern __at(0x0007) __sfr FSR1H
;
507 //==============================================================================
510 extern __at(0x0008) __sfr BSR
;
533 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
541 //==============================================================================
543 extern __at(0x0009) __sfr WREG
;
544 extern __at(0x000A) __sfr PCLATH
;
546 //==============================================================================
549 extern __at(0x000B) __sfr INTCON
;
578 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
591 //==============================================================================
594 //==============================================================================
597 extern __at(0x000C) __sfr PORTA
;
620 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
629 //==============================================================================
632 //==============================================================================
635 extern __at(0x000D) __sfr PORTB
;
649 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
656 //==============================================================================
659 //==============================================================================
662 extern __at(0x000E) __sfr PORTC
;
676 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
687 //==============================================================================
690 //==============================================================================
693 extern __at(0x0011) __sfr PIR1
;
706 unsigned TMR1GIF
: 1;
722 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
732 #define _TMR1GIF 0x80
734 //==============================================================================
737 //==============================================================================
740 extern __at(0x0012) __sfr PIR2
;
754 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
764 //==============================================================================
767 //==============================================================================
770 extern __at(0x0013) __sfr PIR3
;
784 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
795 //==============================================================================
798 //==============================================================================
801 extern __at(0x0014) __sfr PIR4
;
808 unsigned TMR3GIF
: 1;
810 unsigned TMR5GIF
: 1;
815 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
820 #define _TMR3GIF 0x08
822 #define _TMR5GIF 0x20
824 //==============================================================================
826 extern __at(0x0015) __sfr TMR0
;
827 extern __at(0x0016) __sfr TMR1
;
828 extern __at(0x0016) __sfr TMR1L
;
829 extern __at(0x0017) __sfr TMR1H
;
831 //==============================================================================
834 extern __at(0x0018) __sfr T1CON
;
842 unsigned NOT_SYNC
: 1;
856 unsigned T1CKPS0
: 1;
857 unsigned T1CKPS1
: 1;
866 unsigned NOT_T1SYNC
: 1;
867 unsigned T1OSCEN
: 1;
870 unsigned TMR1CS0
: 1;
871 unsigned TMR1CS1
: 1;
919 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
921 #define _T1CON_ON 0x01
922 #define _T1CON_TMRON 0x01
923 #define _T1CON_TMR1ON 0x01
924 #define _T1CON_T1ON 0x01
925 #define _T1CON_NOT_SYNC 0x04
926 #define _T1CON_SYNC 0x04
927 #define _T1CON_NOT_T1SYNC 0x04
928 #define _T1CON_OSCEN 0x08
929 #define _T1CON_SOSCEN 0x08
930 #define _T1CON_T1OSCEN 0x08
931 #define _T1CON_CKPS0 0x10
932 #define _T1CON_T1CKPS0 0x10
933 #define _T1CON_CKPS1 0x20
934 #define _T1CON_T1CKPS1 0x20
935 #define _T1CON_CS0 0x40
936 #define _T1CON_T1CS0 0x40
937 #define _T1CON_TMR1CS0 0x40
938 #define _T1CON_CS1 0x80
939 #define _T1CON_T1CS1 0x80
940 #define _T1CON_TMR1CS1 0x80
942 //==============================================================================
945 //==============================================================================
948 extern __at(0x0019) __sfr T1GCON
;
957 unsigned GGO_NOT_DONE
: 1;
969 unsigned T1GGO_NOT_DONE
: 1;
1001 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
1004 #define _T1GSS0 0x01
1006 #define _T1GSS1 0x02
1008 #define _T1GVAL 0x04
1009 #define _GGO_NOT_DONE 0x08
1010 #define _T1GGO_NOT_DONE 0x08
1012 #define _T1GSPM 0x10
1016 #define _T1GPOL 0x40
1019 #define _TMR1GE 0x80
1021 //==============================================================================
1023 extern __at(0x001A) __sfr T2TMR
;
1024 extern __at(0x001A) __sfr TMR2
;
1025 extern __at(0x001B) __sfr PR2
;
1026 extern __at(0x001B) __sfr T2PR
;
1028 //==============================================================================
1031 extern __at(0x001C) __sfr T2CON
;
1037 unsigned OUTPS0
: 1;
1038 unsigned OUTPS1
: 1;
1039 unsigned OUTPS2
: 1;
1040 unsigned OUTPS3
: 1;
1049 unsigned T2OUTPS0
: 1;
1050 unsigned T2OUTPS1
: 1;
1051 unsigned T2OUTPS2
: 1;
1052 unsigned T2OUTPS3
: 1;
1053 unsigned T2CKPS0
: 1;
1054 unsigned T2CKPS1
: 1;
1055 unsigned T2CKPS2
: 1;
1068 unsigned TMR2ON
: 1;
1079 unsigned T2OUTPS
: 4;
1093 unsigned T2CKPS
: 3;
1098 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
1100 #define _T2CON_OUTPS0 0x01
1101 #define _T2CON_T2OUTPS0 0x01
1102 #define _T2CON_OUTPS1 0x02
1103 #define _T2CON_T2OUTPS1 0x02
1104 #define _T2CON_OUTPS2 0x04
1105 #define _T2CON_T2OUTPS2 0x04
1106 #define _T2CON_OUTPS3 0x08
1107 #define _T2CON_T2OUTPS3 0x08
1108 #define _T2CON_CKPS0 0x10
1109 #define _T2CON_T2CKPS0 0x10
1110 #define _T2CON_CKPS1 0x20
1111 #define _T2CON_T2CKPS1 0x20
1112 #define _T2CON_CKPS2 0x40
1113 #define _T2CON_T2CKPS2 0x40
1114 #define _T2CON_ON 0x80
1115 #define _T2CON_T2ON 0x80
1116 #define _T2CON_TMR2ON 0x80
1118 //==============================================================================
1121 //==============================================================================
1124 extern __at(0x001D) __sfr T2HLT
;
1135 unsigned CKSYNC
: 1;
1142 unsigned T2MODE0
: 1;
1143 unsigned T2MODE1
: 1;
1144 unsigned T2MODE2
: 1;
1145 unsigned T2MODE3
: 1;
1146 unsigned T2MODE4
: 1;
1147 unsigned T2CKSYNC
: 1;
1148 unsigned T2CKPOL
: 1;
1149 unsigned T2PSYNC
: 1;
1154 unsigned T2MODE
: 5;
1165 extern __at(0x001D) volatile __T2HLTbits_t T2HLTbits
;
1167 #define _T2HLT_MODE0 0x01
1168 #define _T2HLT_T2MODE0 0x01
1169 #define _T2HLT_MODE1 0x02
1170 #define _T2HLT_T2MODE1 0x02
1171 #define _T2HLT_MODE2 0x04
1172 #define _T2HLT_T2MODE2 0x04
1173 #define _T2HLT_MODE3 0x08
1174 #define _T2HLT_T2MODE3 0x08
1175 #define _T2HLT_MODE4 0x10
1176 #define _T2HLT_T2MODE4 0x10
1177 #define _T2HLT_CKSYNC 0x20
1178 #define _T2HLT_T2CKSYNC 0x20
1179 #define _T2HLT_CKPOL 0x40
1180 #define _T2HLT_T2CKPOL 0x40
1181 #define _T2HLT_PSYNC 0x80
1182 #define _T2HLT_T2PSYNC 0x80
1184 //==============================================================================
1187 //==============================================================================
1190 extern __at(0x001E) __sfr T2CLKCON
;
1231 extern __at(0x001E) volatile __T2CLKCONbits_t T2CLKCONbits
;
1233 #define _T2CLKCON_CS0 0x01
1234 #define _T2CLKCON_T2CS0 0x01
1235 #define _T2CLKCON_CS1 0x02
1236 #define _T2CLKCON_T2CS1 0x02
1237 #define _T2CLKCON_CS2 0x04
1238 #define _T2CLKCON_T2CS2 0x04
1239 #define _T2CLKCON_CS3 0x08
1240 #define _T2CLKCON_T2CS3 0x08
1242 //==============================================================================
1245 //==============================================================================
1248 extern __at(0x001F) __sfr T2RST
;
1266 unsigned T2RSEL0
: 1;
1267 unsigned T2RSEL1
: 1;
1268 unsigned T2RSEL2
: 1;
1269 unsigned T2RSEL3
: 1;
1284 unsigned T2RSEL
: 4;
1289 extern __at(0x001F) volatile __T2RSTbits_t T2RSTbits
;
1292 #define _T2RSEL0 0x01
1294 #define _T2RSEL1 0x02
1296 #define _T2RSEL2 0x04
1298 #define _T2RSEL3 0x08
1300 //==============================================================================
1303 //==============================================================================
1306 extern __at(0x008C) __sfr TRISA
;
1310 unsigned TRISA0
: 1;
1311 unsigned TRISA1
: 1;
1312 unsigned TRISA2
: 1;
1314 unsigned TRISA4
: 1;
1315 unsigned TRISA5
: 1;
1320 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1322 #define _TRISA0 0x01
1323 #define _TRISA1 0x02
1324 #define _TRISA2 0x04
1325 #define _TRISA4 0x10
1326 #define _TRISA5 0x20
1328 //==============================================================================
1331 //==============================================================================
1334 extern __at(0x008D) __sfr TRISB
;
1342 unsigned TRISB4
: 1;
1343 unsigned TRISB5
: 1;
1344 unsigned TRISB6
: 1;
1345 unsigned TRISB7
: 1;
1348 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
1350 #define _TRISB4 0x10
1351 #define _TRISB5 0x20
1352 #define _TRISB6 0x40
1353 #define _TRISB7 0x80
1355 //==============================================================================
1358 //==============================================================================
1361 extern __at(0x008E) __sfr TRISC
;
1365 unsigned TRISC0
: 1;
1366 unsigned TRISC1
: 1;
1367 unsigned TRISC2
: 1;
1368 unsigned TRISC3
: 1;
1369 unsigned TRISC4
: 1;
1370 unsigned TRISC5
: 1;
1371 unsigned TRISC6
: 1;
1372 unsigned TRISC7
: 1;
1375 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1377 #define _TRISC0 0x01
1378 #define _TRISC1 0x02
1379 #define _TRISC2 0x04
1380 #define _TRISC3 0x08
1381 #define _TRISC4 0x10
1382 #define _TRISC5 0x20
1383 #define _TRISC6 0x40
1384 #define _TRISC7 0x80
1386 //==============================================================================
1389 //==============================================================================
1392 extern __at(0x0091) __sfr PIE1
;
1398 unsigned TMR1IE
: 1;
1399 unsigned TMR2IE
: 1;
1400 unsigned CCP1IE
: 1;
1401 unsigned SSP1IE
: 1;
1405 unsigned TMR1GIE
: 1;
1421 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1423 #define _TMR1IE 0x01
1424 #define _TMR2IE 0x02
1425 #define _CCP1IE 0x04
1427 #define _SSP1IE 0x08
1431 #define _TMR1GIE 0x80
1433 //==============================================================================
1436 //==============================================================================
1439 extern __at(0x0092) __sfr PIE2
;
1443 unsigned CCP2IE
: 1;
1446 unsigned BCL1IE
: 1;
1453 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1455 #define _CCP2IE 0x01
1458 #define _BCL1IE 0x08
1463 //==============================================================================
1466 //==============================================================================
1469 extern __at(0x0093) __sfr PIE3
;
1473 unsigned CLC1IE
: 1;
1474 unsigned CLC2IE
: 1;
1475 unsigned CLC3IE
: 1;
1476 unsigned COG2IE
: 1;
1479 unsigned PWM5IE
: 1;
1480 unsigned PWM6IE
: 1;
1483 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1485 #define _CLC1IE 0x01
1486 #define _CLC2IE 0x02
1487 #define _CLC3IE 0x04
1488 #define _COG2IE 0x08
1491 #define _PWM5IE 0x40
1492 #define _PWM6IE 0x80
1494 //==============================================================================
1497 //==============================================================================
1500 extern __at(0x0094) __sfr PIE4
;
1504 unsigned TMR4IE
: 1;
1505 unsigned TMR6IE
: 1;
1506 unsigned TMR3IE
: 1;
1507 unsigned TMR3GIE
: 1;
1508 unsigned TMR5IE
: 1;
1509 unsigned TMR5GIE
: 1;
1514 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1516 #define _TMR4IE 0x01
1517 #define _TMR6IE 0x02
1518 #define _TMR3IE 0x04
1519 #define _TMR3GIE 0x08
1520 #define _TMR5IE 0x10
1521 #define _TMR5GIE 0x20
1523 //==============================================================================
1526 //==============================================================================
1529 extern __at(0x0095) __sfr OPTION_REG
;
1539 unsigned TMR0SE
: 1;
1540 unsigned TMR0CS
: 1;
1541 unsigned INTEDG
: 1;
1542 unsigned NOT_WPUEN
: 1;
1562 } __OPTION_REGbits_t
;
1564 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
1570 #define _TMR0SE 0x10
1572 #define _TMR0CS 0x20
1574 #define _INTEDG 0x40
1575 #define _NOT_WPUEN 0x80
1577 //==============================================================================
1580 //==============================================================================
1583 extern __at(0x0096) __sfr PCON
;
1587 unsigned NOT_BOR
: 1;
1588 unsigned NOT_POR
: 1;
1589 unsigned NOT_RI
: 1;
1590 unsigned NOT_RMCLR
: 1;
1591 unsigned NOT_RWDT
: 1;
1593 unsigned STKUNF
: 1;
1594 unsigned STKOVF
: 1;
1597 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
1599 #define _NOT_BOR 0x01
1600 #define _NOT_POR 0x02
1601 #define _NOT_RI 0x04
1602 #define _NOT_RMCLR 0x08
1603 #define _NOT_RWDT 0x10
1604 #define _STKUNF 0x40
1605 #define _STKOVF 0x80
1607 //==============================================================================
1610 //==============================================================================
1613 extern __at(0x0097) __sfr WDTCON
;
1619 unsigned SWDTEN
: 1;
1620 unsigned WDTPS0
: 1;
1621 unsigned WDTPS1
: 1;
1622 unsigned WDTPS2
: 1;
1623 unsigned WDTPS3
: 1;
1624 unsigned WDTPS4
: 1;
1637 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1639 #define _SWDTEN 0x01
1640 #define _WDTPS0 0x02
1641 #define _WDTPS1 0x04
1642 #define _WDTPS2 0x08
1643 #define _WDTPS3 0x10
1644 #define _WDTPS4 0x20
1646 //==============================================================================
1649 //==============================================================================
1652 extern __at(0x0098) __sfr OSCTUNE
;
1675 extern __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits
;
1684 //==============================================================================
1687 //==============================================================================
1690 extern __at(0x0099) __sfr OSCCON
;
1703 unsigned SPLLEN
: 1;
1720 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
1728 #define _SPLLEN 0x80
1730 //==============================================================================
1733 //==============================================================================
1736 extern __at(0x009A) __sfr OSCSTAT
;
1740 unsigned HFIOFS
: 1;
1741 unsigned LFIOFR
: 1;
1742 unsigned MFIOFR
: 1;
1743 unsigned HFIOFL
: 1;
1744 unsigned HFIOFR
: 1;
1750 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
1752 #define _HFIOFS 0x01
1753 #define _LFIOFR 0x02
1754 #define _MFIOFR 0x04
1755 #define _HFIOFL 0x08
1756 #define _HFIOFR 0x10
1761 //==============================================================================
1763 extern __at(0x009B) __sfr ADRES
;
1764 extern __at(0x009B) __sfr ADRESL
;
1765 extern __at(0x009C) __sfr ADRESH
;
1767 //==============================================================================
1770 extern __at(0x009D) __sfr ADCON0
;
1777 unsigned GO_NOT_DONE
: 1;
1818 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1821 #define _GO_NOT_DONE 0x02
1830 //==============================================================================
1833 //==============================================================================
1836 extern __at(0x009E) __sfr ADCON1
;
1842 unsigned ADPREF0
: 1;
1843 unsigned ADPREF1
: 1;
1844 unsigned ADNREF
: 1;
1854 unsigned ADPREF
: 2;
1859 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1861 #define _ADPREF0 0x01
1862 #define _ADPREF1 0x02
1863 #define _ADNREF 0x04
1866 //==============================================================================
1869 //==============================================================================
1872 extern __at(0x009F) __sfr ADCON2
;
1881 unsigned TRIGSEL0
: 1;
1882 unsigned TRIGSEL1
: 1;
1883 unsigned TRIGSEL2
: 1;
1884 unsigned TRIGSEL3
: 1;
1885 unsigned TRIGSEL4
: 1;
1891 unsigned TRIGSEL
: 5;
1895 extern __at(0x009F) volatile __ADCON2bits_t ADCON2bits
;
1897 #define _TRIGSEL0 0x08
1898 #define _TRIGSEL1 0x10
1899 #define _TRIGSEL2 0x20
1900 #define _TRIGSEL3 0x40
1901 #define _TRIGSEL4 0x80
1903 //==============================================================================
1906 //==============================================================================
1909 extern __at(0x010C) __sfr LATA
;
1923 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1931 //==============================================================================
1934 //==============================================================================
1937 extern __at(0x010D) __sfr LATB
;
1951 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
1958 //==============================================================================
1961 //==============================================================================
1964 extern __at(0x010E) __sfr LATC
;
1978 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1989 //==============================================================================
1992 //==============================================================================
1995 extern __at(0x010F) __sfr CMOUT
;
1999 unsigned MC1OUT
: 1;
2000 unsigned MC2OUT
: 1;
2001 unsigned MC3OUT
: 1;
2002 unsigned MC4OUT
: 1;
2009 extern __at(0x010F) volatile __CMOUTbits_t CMOUTbits
;
2011 #define _MC1OUT 0x01
2012 #define _MC2OUT 0x02
2013 #define _MC3OUT 0x04
2014 #define _MC4OUT 0x08
2016 //==============================================================================
2019 //==============================================================================
2022 extern __at(0x0110) __sfr CM1CON0
;
2030 unsigned Reserved
: 1;
2040 unsigned C1SYNC
: 1;
2051 extern __at(0x0110) volatile __CM1CON0bits_t CM1CON0bits
;
2053 #define _CM1CON0_SYNC 0x01
2054 #define _CM1CON0_C1SYNC 0x01
2055 #define _CM1CON0_HYS 0x02
2056 #define _CM1CON0_C1HYS 0x02
2057 #define _CM1CON0_Reserved 0x04
2058 #define _CM1CON0_C1SP 0x04
2059 #define _CM1CON0_ZLF 0x08
2060 #define _CM1CON0_C1ZLF 0x08
2061 #define _CM1CON0_POL 0x10
2062 #define _CM1CON0_C1POL 0x10
2063 #define _CM1CON0_OUT 0x40
2064 #define _CM1CON0_C1OUT 0x40
2065 #define _CM1CON0_ON 0x80
2066 #define _CM1CON0_C1ON 0x80
2068 //==============================================================================
2071 //==============================================================================
2074 extern __at(0x0111) __sfr CM1CON1
;
2092 unsigned C1INTN
: 1;
2093 unsigned C1INTP
: 1;
2103 extern __at(0x0111) volatile __CM1CON1bits_t CM1CON1bits
;
2105 #define _CM1CON1_INTN 0x01
2106 #define _CM1CON1_C1INTN 0x01
2107 #define _CM1CON1_INTP 0x02
2108 #define _CM1CON1_C1INTP 0x02
2110 //==============================================================================
2113 //==============================================================================
2116 extern __at(0x0112) __sfr CM1NSEL
;
2134 unsigned C1NCH0
: 1;
2135 unsigned C1NCH1
: 1;
2136 unsigned C1NCH2
: 1;
2157 extern __at(0x0112) volatile __CM1NSELbits_t CM1NSELbits
;
2160 #define _C1NCH0 0x01
2162 #define _C1NCH1 0x02
2164 #define _C1NCH2 0x04
2166 //==============================================================================
2169 //==============================================================================
2172 extern __at(0x0113) __sfr CM1PSEL
;
2190 unsigned C1PCH0
: 1;
2191 unsigned C1PCH1
: 1;
2192 unsigned C1PCH2
: 1;
2193 unsigned C1PCH3
: 1;
2213 extern __at(0x0113) volatile __CM1PSELbits_t CM1PSELbits
;
2216 #define _C1PCH0 0x01
2218 #define _C1PCH1 0x02
2220 #define _C1PCH2 0x04
2222 #define _C1PCH3 0x08
2224 //==============================================================================
2227 //==============================================================================
2230 extern __at(0x0114) __sfr CM2CON0
;
2238 unsigned Reserved
: 1;
2248 unsigned C2SYNC
: 1;
2259 extern __at(0x0114) volatile __CM2CON0bits_t CM2CON0bits
;
2261 #define _CM2CON0_SYNC 0x01
2262 #define _CM2CON0_C2SYNC 0x01
2263 #define _CM2CON0_HYS 0x02
2264 #define _CM2CON0_C2HYS 0x02
2265 #define _CM2CON0_Reserved 0x04
2266 #define _CM2CON0_C2SP 0x04
2267 #define _CM2CON0_ZLF 0x08
2268 #define _CM2CON0_C2ZLF 0x08
2269 #define _CM2CON0_POL 0x10
2270 #define _CM2CON0_C2POL 0x10
2271 #define _CM2CON0_OUT 0x40
2272 #define _CM2CON0_C2OUT 0x40
2273 #define _CM2CON0_ON 0x80
2274 #define _CM2CON0_C2ON 0x80
2276 //==============================================================================
2279 //==============================================================================
2282 extern __at(0x0115) __sfr CM2CON1
;
2300 unsigned C2INTN
: 1;
2301 unsigned C2INTP
: 1;
2311 extern __at(0x0115) volatile __CM2CON1bits_t CM2CON1bits
;
2313 #define _CM2CON1_INTN 0x01
2314 #define _CM2CON1_C2INTN 0x01
2315 #define _CM2CON1_INTP 0x02
2316 #define _CM2CON1_C2INTP 0x02
2318 //==============================================================================
2321 //==============================================================================
2324 extern __at(0x0116) __sfr CM2NSEL
;
2342 unsigned C2NCH0
: 1;
2343 unsigned C2NCH1
: 1;
2344 unsigned C2NCH2
: 1;
2365 extern __at(0x0116) volatile __CM2NSELbits_t CM2NSELbits
;
2367 #define _CM2NSEL_NCH0 0x01
2368 #define _CM2NSEL_C2NCH0 0x01
2369 #define _CM2NSEL_NCH1 0x02
2370 #define _CM2NSEL_C2NCH1 0x02
2371 #define _CM2NSEL_NCH2 0x04
2372 #define _CM2NSEL_C2NCH2 0x04
2374 //==============================================================================
2377 //==============================================================================
2380 extern __at(0x0117) __sfr CM2PSEL
;
2398 unsigned C2PCH0
: 1;
2399 unsigned C2PCH1
: 1;
2400 unsigned C2PCH2
: 1;
2401 unsigned C2PCH3
: 1;
2421 extern __at(0x0117) volatile __CM2PSELbits_t CM2PSELbits
;
2423 #define _CM2PSEL_PCH0 0x01
2424 #define _CM2PSEL_C2PCH0 0x01
2425 #define _CM2PSEL_PCH1 0x02
2426 #define _CM2PSEL_C2PCH1 0x02
2427 #define _CM2PSEL_PCH2 0x04
2428 #define _CM2PSEL_C2PCH2 0x04
2429 #define _CM2PSEL_PCH3 0x08
2430 #define _CM2PSEL_C2PCH3 0x08
2432 //==============================================================================
2435 //==============================================================================
2438 extern __at(0x0118) __sfr CM3CON0
;
2446 unsigned Reserved
: 1;
2456 unsigned C3SYNC
: 1;
2467 extern __at(0x0118) volatile __CM3CON0bits_t CM3CON0bits
;
2469 #define _CM3CON0_SYNC 0x01
2470 #define _CM3CON0_C3SYNC 0x01
2471 #define _CM3CON0_HYS 0x02
2472 #define _CM3CON0_C3HYS 0x02
2473 #define _CM3CON0_Reserved 0x04
2474 #define _CM3CON0_C3SP 0x04
2475 #define _CM3CON0_ZLF 0x08
2476 #define _CM3CON0_C3ZLF 0x08
2477 #define _CM3CON0_POL 0x10
2478 #define _CM3CON0_C3POL 0x10
2479 #define _CM3CON0_OUT 0x40
2480 #define _CM3CON0_C3OUT 0x40
2481 #define _CM3CON0_ON 0x80
2482 #define _CM3CON0_C3ON 0x80
2484 //==============================================================================
2487 //==============================================================================
2490 extern __at(0x0119) __sfr CM3CON1
;
2508 unsigned C3INTN
: 1;
2509 unsigned C3INTP
: 1;
2519 extern __at(0x0119) volatile __CM3CON1bits_t CM3CON1bits
;
2521 #define _CM3CON1_INTN 0x01
2522 #define _CM3CON1_C3INTN 0x01
2523 #define _CM3CON1_INTP 0x02
2524 #define _CM3CON1_C3INTP 0x02
2526 //==============================================================================
2529 //==============================================================================
2532 extern __at(0x011A) __sfr CM3NSEL
;
2550 unsigned C3NCH0
: 1;
2551 unsigned C3NCH1
: 1;
2552 unsigned C3NCH2
: 1;
2573 extern __at(0x011A) volatile __CM3NSELbits_t CM3NSELbits
;
2575 #define _CM3NSEL_NCH0 0x01
2576 #define _CM3NSEL_C3NCH0 0x01
2577 #define _CM3NSEL_NCH1 0x02
2578 #define _CM3NSEL_C3NCH1 0x02
2579 #define _CM3NSEL_NCH2 0x04
2580 #define _CM3NSEL_C3NCH2 0x04
2582 //==============================================================================
2585 //==============================================================================
2588 extern __at(0x011B) __sfr CM3PSEL
;
2606 unsigned C3PCH0
: 1;
2607 unsigned C3PCH1
: 1;
2608 unsigned C3PCH2
: 1;
2609 unsigned C3PCH3
: 1;
2629 extern __at(0x011B) volatile __CM3PSELbits_t CM3PSELbits
;
2631 #define _CM3PSEL_PCH0 0x01
2632 #define _CM3PSEL_C3PCH0 0x01
2633 #define _CM3PSEL_PCH1 0x02
2634 #define _CM3PSEL_C3PCH1 0x02
2635 #define _CM3PSEL_PCH2 0x04
2636 #define _CM3PSEL_C3PCH2 0x04
2637 #define _CM3PSEL_PCH3 0x08
2638 #define _CM3PSEL_C3PCH3 0x08
2640 //==============================================================================
2643 //==============================================================================
2646 extern __at(0x011C) __sfr CM4CON0
;
2654 unsigned Reserved
: 1;
2664 unsigned C4SYNC
: 1;
2675 extern __at(0x011C) volatile __CM4CON0bits_t CM4CON0bits
;
2677 #define _CM4CON0_SYNC 0x01
2678 #define _CM4CON0_C4SYNC 0x01
2679 #define _CM4CON0_HYS 0x02
2680 #define _CM4CON0_C4HYS 0x02
2681 #define _CM4CON0_Reserved 0x04
2682 #define _CM4CON0_C4SP 0x04
2683 #define _CM4CON0_ZLF 0x08
2684 #define _CM4CON0_C4ZLF 0x08
2685 #define _CM4CON0_POL 0x10
2686 #define _CM4CON0_C4POL 0x10
2687 #define _CM4CON0_OUT 0x40
2688 #define _CM4CON0_C4OUT 0x40
2689 #define _CM4CON0_ON 0x80
2690 #define _CM4CON0_C4ON 0x80
2692 //==============================================================================
2695 //==============================================================================
2698 extern __at(0x011D) __sfr CM4CON1
;
2716 unsigned C4INTN
: 1;
2717 unsigned C4INTP
: 1;
2727 extern __at(0x011D) volatile __CM4CON1bits_t CM4CON1bits
;
2729 #define _CM4CON1_INTN 0x01
2730 #define _CM4CON1_C4INTN 0x01
2731 #define _CM4CON1_INTP 0x02
2732 #define _CM4CON1_C4INTP 0x02
2734 //==============================================================================
2737 //==============================================================================
2740 extern __at(0x011E) __sfr CM4NSEL
;
2758 unsigned C4NCH0
: 1;
2759 unsigned C4NCH1
: 1;
2760 unsigned C4NCH2
: 1;
2781 extern __at(0x011E) volatile __CM4NSELbits_t CM4NSELbits
;
2783 #define _CM4NSEL_NCH0 0x01
2784 #define _CM4NSEL_C4NCH0 0x01
2785 #define _CM4NSEL_NCH1 0x02
2786 #define _CM4NSEL_C4NCH1 0x02
2787 #define _CM4NSEL_NCH2 0x04
2788 #define _CM4NSEL_C4NCH2 0x04
2790 //==============================================================================
2793 //==============================================================================
2796 extern __at(0x011F) __sfr CM4PSEL
;
2814 unsigned C4PCH0
: 1;
2815 unsigned C4PCH1
: 1;
2816 unsigned C4PCH2
: 1;
2817 unsigned C4PCH3
: 1;
2837 extern __at(0x011F) volatile __CM4PSELbits_t CM4PSELbits
;
2839 #define _CM4PSEL_PCH0 0x01
2840 #define _CM4PSEL_C4PCH0 0x01
2841 #define _CM4PSEL_PCH1 0x02
2842 #define _CM4PSEL_C4PCH1 0x02
2843 #define _CM4PSEL_PCH2 0x04
2844 #define _CM4PSEL_C4PCH2 0x04
2845 #define _CM4PSEL_PCH3 0x08
2846 #define _CM4PSEL_C4PCH3 0x08
2848 //==============================================================================
2851 //==============================================================================
2854 extern __at(0x018C) __sfr ANSELA
;
2868 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
2875 //==============================================================================
2878 //==============================================================================
2881 extern __at(0x018D) __sfr ANSELB
;
2895 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
2902 //==============================================================================
2905 //==============================================================================
2908 extern __at(0x018E) __sfr ANSELC
;
2922 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
2931 //==============================================================================
2933 extern __at(0x0191) __sfr PMADR
;
2934 extern __at(0x0191) __sfr PMADRL
;
2935 extern __at(0x0192) __sfr PMADRH
;
2936 extern __at(0x0193) __sfr PMDAT
;
2937 extern __at(0x0193) __sfr PMDATL
;
2938 extern __at(0x0194) __sfr PMDATH
;
2940 //==============================================================================
2943 extern __at(0x0195) __sfr PMCON1
;
2957 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
2967 //==============================================================================
2969 extern __at(0x0196) __sfr PMCON2
;
2970 extern __at(0x0199) __sfr RC1REG
;
2971 extern __at(0x0199) __sfr RCREG
;
2972 extern __at(0x0199) __sfr RCREG1
;
2973 extern __at(0x019A) __sfr TX1REG
;
2974 extern __at(0x019A) __sfr TXREG
;
2975 extern __at(0x019A) __sfr TXREG1
;
2976 extern __at(0x019B) __sfr SP1BRG
;
2977 extern __at(0x019B) __sfr SP1BRGL
;
2978 extern __at(0x019B) __sfr SPBRG
;
2979 extern __at(0x019B) __sfr SPBRG1
;
2980 extern __at(0x019B) __sfr SPBRGL
;
2981 extern __at(0x019C) __sfr SP1BRGH
;
2982 extern __at(0x019C) __sfr SPBRGH
;
2983 extern __at(0x019C) __sfr SPBRGH1
;
2985 //==============================================================================
2988 extern __at(0x019D) __sfr RC1STA
;
3002 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
3013 //==============================================================================
3016 //==============================================================================
3019 extern __at(0x019D) __sfr RCSTA
;
3033 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
3035 #define _RCSTA_RX9D 0x01
3036 #define _RCSTA_OERR 0x02
3037 #define _RCSTA_FERR 0x04
3038 #define _RCSTA_ADDEN 0x08
3039 #define _RCSTA_CREN 0x10
3040 #define _RCSTA_SREN 0x20
3041 #define _RCSTA_RX9 0x40
3042 #define _RCSTA_SPEN 0x80
3044 //==============================================================================
3047 //==============================================================================
3050 extern __at(0x019D) __sfr RCSTA1
;
3064 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
3066 #define _RCSTA1_RX9D 0x01
3067 #define _RCSTA1_OERR 0x02
3068 #define _RCSTA1_FERR 0x04
3069 #define _RCSTA1_ADDEN 0x08
3070 #define _RCSTA1_CREN 0x10
3071 #define _RCSTA1_SREN 0x20
3072 #define _RCSTA1_RX9 0x40
3073 #define _RCSTA1_SPEN 0x80
3075 //==============================================================================
3078 //==============================================================================
3081 extern __at(0x019E) __sfr TX1STA
;
3095 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
3097 #define _TX1STA_TX9D 0x01
3098 #define _TX1STA_TRMT 0x02
3099 #define _TX1STA_BRGH 0x04
3100 #define _TX1STA_SENDB 0x08
3101 #define _TX1STA_SYNC 0x10
3102 #define _TX1STA_TXEN 0x20
3103 #define _TX1STA_TX9 0x40
3104 #define _TX1STA_CSRC 0x80
3106 //==============================================================================
3109 //==============================================================================
3112 extern __at(0x019E) __sfr TXSTA
;
3126 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
3128 #define _TXSTA_TX9D 0x01
3129 #define _TXSTA_TRMT 0x02
3130 #define _TXSTA_BRGH 0x04
3131 #define _TXSTA_SENDB 0x08
3132 #define _TXSTA_SYNC 0x10
3133 #define _TXSTA_TXEN 0x20
3134 #define _TXSTA_TX9 0x40
3135 #define _TXSTA_CSRC 0x80
3137 //==============================================================================
3140 //==============================================================================
3143 extern __at(0x019E) __sfr TXSTA1
;
3157 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
3159 #define _TXSTA1_TX9D 0x01
3160 #define _TXSTA1_TRMT 0x02
3161 #define _TXSTA1_BRGH 0x04
3162 #define _TXSTA1_SENDB 0x08
3163 #define _TXSTA1_SYNC 0x10
3164 #define _TXSTA1_TXEN 0x20
3165 #define _TXSTA1_TX9 0x40
3166 #define _TXSTA1_CSRC 0x80
3168 //==============================================================================
3171 //==============================================================================
3174 extern __at(0x019F) __sfr BAUD1CON
;
3185 unsigned ABDOVF
: 1;
3188 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
3195 #define _ABDOVF 0x80
3197 //==============================================================================
3200 //==============================================================================
3203 extern __at(0x019F) __sfr BAUDCON
;
3214 unsigned ABDOVF
: 1;
3217 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
3219 #define _BAUDCON_ABDEN 0x01
3220 #define _BAUDCON_WUE 0x02
3221 #define _BAUDCON_BRG16 0x08
3222 #define _BAUDCON_SCKP 0x10
3223 #define _BAUDCON_RCIDL 0x40
3224 #define _BAUDCON_ABDOVF 0x80
3226 //==============================================================================
3229 //==============================================================================
3232 extern __at(0x019F) __sfr BAUDCON1
;
3243 unsigned ABDOVF
: 1;
3246 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
3248 #define _BAUDCON1_ABDEN 0x01
3249 #define _BAUDCON1_WUE 0x02
3250 #define _BAUDCON1_BRG16 0x08
3251 #define _BAUDCON1_SCKP 0x10
3252 #define _BAUDCON1_RCIDL 0x40
3253 #define _BAUDCON1_ABDOVF 0x80
3255 //==============================================================================
3258 //==============================================================================
3261 extern __at(0x019F) __sfr BAUDCTL
;
3272 unsigned ABDOVF
: 1;
3275 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
3277 #define _BAUDCTL_ABDEN 0x01
3278 #define _BAUDCTL_WUE 0x02
3279 #define _BAUDCTL_BRG16 0x08
3280 #define _BAUDCTL_SCKP 0x10
3281 #define _BAUDCTL_RCIDL 0x40
3282 #define _BAUDCTL_ABDOVF 0x80
3284 //==============================================================================
3287 //==============================================================================
3290 extern __at(0x019F) __sfr BAUDCTL1
;
3301 unsigned ABDOVF
: 1;
3304 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
3306 #define _BAUDCTL1_ABDEN 0x01
3307 #define _BAUDCTL1_WUE 0x02
3308 #define _BAUDCTL1_BRG16 0x08
3309 #define _BAUDCTL1_SCKP 0x10
3310 #define _BAUDCTL1_RCIDL 0x40
3311 #define _BAUDCTL1_ABDOVF 0x80
3313 //==============================================================================
3316 //==============================================================================
3319 extern __at(0x020C) __sfr WPUA
;
3342 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
3351 //==============================================================================
3354 //==============================================================================
3357 extern __at(0x020D) __sfr WPUB
;
3371 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
3378 //==============================================================================
3381 //==============================================================================
3384 extern __at(0x020E) __sfr WPUC
;
3398 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
3409 //==============================================================================
3412 //==============================================================================
3415 extern __at(0x0211) __sfr SSP1BUF
;
3421 unsigned SSP1BUF0
: 1;
3422 unsigned SSP1BUF1
: 1;
3423 unsigned SSP1BUF2
: 1;
3424 unsigned SSP1BUF3
: 1;
3425 unsigned SSP1BUF4
: 1;
3426 unsigned SSP1BUF5
: 1;
3427 unsigned SSP1BUF6
: 1;
3428 unsigned SSP1BUF7
: 1;
3444 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
3446 #define _SSP1BUF0 0x01
3448 #define _SSP1BUF1 0x02
3450 #define _SSP1BUF2 0x04
3452 #define _SSP1BUF3 0x08
3454 #define _SSP1BUF4 0x10
3456 #define _SSP1BUF5 0x20
3458 #define _SSP1BUF6 0x40
3460 #define _SSP1BUF7 0x80
3463 //==============================================================================
3466 //==============================================================================
3469 extern __at(0x0211) __sfr SSPBUF
;
3475 unsigned SSP1BUF0
: 1;
3476 unsigned SSP1BUF1
: 1;
3477 unsigned SSP1BUF2
: 1;
3478 unsigned SSP1BUF3
: 1;
3479 unsigned SSP1BUF4
: 1;
3480 unsigned SSP1BUF5
: 1;
3481 unsigned SSP1BUF6
: 1;
3482 unsigned SSP1BUF7
: 1;
3498 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
3500 #define _SSPBUF_SSP1BUF0 0x01
3501 #define _SSPBUF_BUF0 0x01
3502 #define _SSPBUF_SSP1BUF1 0x02
3503 #define _SSPBUF_BUF1 0x02
3504 #define _SSPBUF_SSP1BUF2 0x04
3505 #define _SSPBUF_BUF2 0x04
3506 #define _SSPBUF_SSP1BUF3 0x08
3507 #define _SSPBUF_BUF3 0x08
3508 #define _SSPBUF_SSP1BUF4 0x10
3509 #define _SSPBUF_BUF4 0x10
3510 #define _SSPBUF_SSP1BUF5 0x20
3511 #define _SSPBUF_BUF5 0x20
3512 #define _SSPBUF_SSP1BUF6 0x40
3513 #define _SSPBUF_BUF6 0x40
3514 #define _SSPBUF_SSP1BUF7 0x80
3515 #define _SSPBUF_BUF7 0x80
3517 //==============================================================================
3520 //==============================================================================
3523 extern __at(0x0212) __sfr SSP1ADD
;
3529 unsigned SSP1ADD0
: 1;
3530 unsigned SSP1ADD1
: 1;
3531 unsigned SSP1ADD2
: 1;
3532 unsigned SSP1ADD3
: 1;
3533 unsigned SSP1ADD4
: 1;
3534 unsigned SSP1ADD5
: 1;
3535 unsigned SSP1ADD6
: 1;
3536 unsigned SSP1ADD7
: 1;
3552 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
3554 #define _SSP1ADD0 0x01
3556 #define _SSP1ADD1 0x02
3558 #define _SSP1ADD2 0x04
3560 #define _SSP1ADD3 0x08
3562 #define _SSP1ADD4 0x10
3564 #define _SSP1ADD5 0x20
3566 #define _SSP1ADD6 0x40
3568 #define _SSP1ADD7 0x80
3571 //==============================================================================
3574 //==============================================================================
3577 extern __at(0x0212) __sfr SSPADD
;
3583 unsigned SSP1ADD0
: 1;
3584 unsigned SSP1ADD1
: 1;
3585 unsigned SSP1ADD2
: 1;
3586 unsigned SSP1ADD3
: 1;
3587 unsigned SSP1ADD4
: 1;
3588 unsigned SSP1ADD5
: 1;
3589 unsigned SSP1ADD6
: 1;
3590 unsigned SSP1ADD7
: 1;
3606 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
3608 #define _SSPADD_SSP1ADD0 0x01
3609 #define _SSPADD_ADD0 0x01
3610 #define _SSPADD_SSP1ADD1 0x02
3611 #define _SSPADD_ADD1 0x02
3612 #define _SSPADD_SSP1ADD2 0x04
3613 #define _SSPADD_ADD2 0x04
3614 #define _SSPADD_SSP1ADD3 0x08
3615 #define _SSPADD_ADD3 0x08
3616 #define _SSPADD_SSP1ADD4 0x10
3617 #define _SSPADD_ADD4 0x10
3618 #define _SSPADD_SSP1ADD5 0x20
3619 #define _SSPADD_ADD5 0x20
3620 #define _SSPADD_SSP1ADD6 0x40
3621 #define _SSPADD_ADD6 0x40
3622 #define _SSPADD_SSP1ADD7 0x80
3623 #define _SSPADD_ADD7 0x80
3625 //==============================================================================
3628 //==============================================================================
3631 extern __at(0x0213) __sfr SSP1MSK
;
3637 unsigned SSP1MSK0
: 1;
3638 unsigned SSP1MSK1
: 1;
3639 unsigned SSP1MSK2
: 1;
3640 unsigned SSP1MSK3
: 1;
3641 unsigned SSP1MSK4
: 1;
3642 unsigned SSP1MSK5
: 1;
3643 unsigned SSP1MSK6
: 1;
3644 unsigned SSP1MSK7
: 1;
3660 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
3662 #define _SSP1MSK0 0x01
3664 #define _SSP1MSK1 0x02
3666 #define _SSP1MSK2 0x04
3668 #define _SSP1MSK3 0x08
3670 #define _SSP1MSK4 0x10
3672 #define _SSP1MSK5 0x20
3674 #define _SSP1MSK6 0x40
3676 #define _SSP1MSK7 0x80
3679 //==============================================================================
3682 //==============================================================================
3685 extern __at(0x0213) __sfr SSPMSK
;
3691 unsigned SSP1MSK0
: 1;
3692 unsigned SSP1MSK1
: 1;
3693 unsigned SSP1MSK2
: 1;
3694 unsigned SSP1MSK3
: 1;
3695 unsigned SSP1MSK4
: 1;
3696 unsigned SSP1MSK5
: 1;
3697 unsigned SSP1MSK6
: 1;
3698 unsigned SSP1MSK7
: 1;
3714 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
3716 #define _SSPMSK_SSP1MSK0 0x01
3717 #define _SSPMSK_MSK0 0x01
3718 #define _SSPMSK_SSP1MSK1 0x02
3719 #define _SSPMSK_MSK1 0x02
3720 #define _SSPMSK_SSP1MSK2 0x04
3721 #define _SSPMSK_MSK2 0x04
3722 #define _SSPMSK_SSP1MSK3 0x08
3723 #define _SSPMSK_MSK3 0x08
3724 #define _SSPMSK_SSP1MSK4 0x10
3725 #define _SSPMSK_MSK4 0x10
3726 #define _SSPMSK_SSP1MSK5 0x20
3727 #define _SSPMSK_MSK5 0x20
3728 #define _SSPMSK_SSP1MSK6 0x40
3729 #define _SSPMSK_MSK6 0x40
3730 #define _SSPMSK_SSP1MSK7 0x80
3731 #define _SSPMSK_MSK7 0x80
3733 //==============================================================================
3736 //==============================================================================
3739 extern __at(0x0214) __sfr SSP1STAT
;
3745 unsigned R_NOT_W
: 1;
3748 unsigned D_NOT_A
: 1;
3753 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
3757 #define _R_NOT_W 0x04
3760 #define _D_NOT_A 0x20
3764 //==============================================================================
3767 //==============================================================================
3770 extern __at(0x0214) __sfr SSPSTAT
;
3776 unsigned R_NOT_W
: 1;
3779 unsigned D_NOT_A
: 1;
3784 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
3786 #define _SSPSTAT_BF 0x01
3787 #define _SSPSTAT_UA 0x02
3788 #define _SSPSTAT_R_NOT_W 0x04
3789 #define _SSPSTAT_S 0x08
3790 #define _SSPSTAT_P 0x10
3791 #define _SSPSTAT_D_NOT_A 0x20
3792 #define _SSPSTAT_CKE 0x40
3793 #define _SSPSTAT_SMP 0x80
3795 //==============================================================================
3798 //==============================================================================
3801 extern __at(0x0215) __sfr SSP1CON
;
3824 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
3835 //==============================================================================
3838 //==============================================================================
3841 extern __at(0x0215) __sfr SSP1CON1
;
3864 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
3866 #define _SSP1CON1_SSPM0 0x01
3867 #define _SSP1CON1_SSPM1 0x02
3868 #define _SSP1CON1_SSPM2 0x04
3869 #define _SSP1CON1_SSPM3 0x08
3870 #define _SSP1CON1_CKP 0x10
3871 #define _SSP1CON1_SSPEN 0x20
3872 #define _SSP1CON1_SSPOV 0x40
3873 #define _SSP1CON1_WCOL 0x80
3875 //==============================================================================
3878 //==============================================================================
3881 extern __at(0x0215) __sfr SSPCON
;
3904 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
3906 #define _SSPCON_SSPM0 0x01
3907 #define _SSPCON_SSPM1 0x02
3908 #define _SSPCON_SSPM2 0x04
3909 #define _SSPCON_SSPM3 0x08
3910 #define _SSPCON_CKP 0x10
3911 #define _SSPCON_SSPEN 0x20
3912 #define _SSPCON_SSPOV 0x40
3913 #define _SSPCON_WCOL 0x80
3915 //==============================================================================
3918 //==============================================================================
3921 extern __at(0x0215) __sfr SSPCON1
;
3944 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
3946 #define _SSPCON1_SSPM0 0x01
3947 #define _SSPCON1_SSPM1 0x02
3948 #define _SSPCON1_SSPM2 0x04
3949 #define _SSPCON1_SSPM3 0x08
3950 #define _SSPCON1_CKP 0x10
3951 #define _SSPCON1_SSPEN 0x20
3952 #define _SSPCON1_SSPOV 0x40
3953 #define _SSPCON1_WCOL 0x80
3955 //==============================================================================
3958 //==============================================================================
3961 extern __at(0x0216) __sfr SSP1CON2
;
3971 unsigned ACKSTAT
: 1;
3975 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
3983 #define _ACKSTAT 0x40
3986 //==============================================================================
3989 //==============================================================================
3992 extern __at(0x0216) __sfr SSPCON2
;
4002 unsigned ACKSTAT
: 1;
4006 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
4008 #define _SSPCON2_SEN 0x01
4009 #define _SSPCON2_RSEN 0x02
4010 #define _SSPCON2_PEN 0x04
4011 #define _SSPCON2_RCEN 0x08
4012 #define _SSPCON2_ACKEN 0x10
4013 #define _SSPCON2_ACKDT 0x20
4014 #define _SSPCON2_ACKSTAT 0x40
4015 #define _SSPCON2_GCEN 0x80
4017 //==============================================================================
4020 //==============================================================================
4023 extern __at(0x0217) __sfr SSP1CON3
;
4034 unsigned ACKTIM
: 1;
4037 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
4046 #define _ACKTIM 0x80
4048 //==============================================================================
4051 //==============================================================================
4054 extern __at(0x0217) __sfr SSPCON3
;
4065 unsigned ACKTIM
: 1;
4068 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
4070 #define _SSPCON3_DHEN 0x01
4071 #define _SSPCON3_AHEN 0x02
4072 #define _SSPCON3_SBCDE 0x04
4073 #define _SSPCON3_SDAHT 0x08
4074 #define _SSPCON3_BOEN 0x10
4075 #define _SSPCON3_SCIE 0x20
4076 #define _SSPCON3_PCIE 0x40
4077 #define _SSPCON3_ACKTIM 0x80
4079 //==============================================================================
4082 //==============================================================================
4085 extern __at(0x021D) __sfr BORCON
;
4089 unsigned BORRDY
: 1;
4096 unsigned SBOREN
: 1;
4099 extern __at(0x021D) volatile __BORCONbits_t BORCONbits
;
4101 #define _BORRDY 0x01
4103 #define _SBOREN 0x80
4105 //==============================================================================
4108 //==============================================================================
4111 extern __at(0x021E) __sfr FVRCON
;
4121 unsigned FVRRDY
: 1;
4125 extern __at(0x021E) volatile __FVRCONbits_t FVRCONbits
;
4129 #define _FVRRDY 0x40
4132 //==============================================================================
4135 //==============================================================================
4138 extern __at(0x021F) __sfr ZCD1CON
;
4142 unsigned ZCD1INTN
: 1;
4143 unsigned ZCD1INTP
: 1;
4146 unsigned ZCD1POL
: 1;
4147 unsigned ZCD1OUT
: 1;
4149 unsigned ZCD1EN
: 1;
4152 extern __at(0x021F) volatile __ZCD1CONbits_t ZCD1CONbits
;
4154 #define _ZCD1INTN 0x01
4155 #define _ZCD1INTP 0x02
4156 #define _ZCD1POL 0x10
4157 #define _ZCD1OUT 0x20
4158 #define _ZCD1EN 0x80
4160 //==============================================================================
4163 //==============================================================================
4166 extern __at(0x028C) __sfr ODCONA
;
4180 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
4188 //==============================================================================
4191 //==============================================================================
4194 extern __at(0x028D) __sfr ODCONB
;
4208 extern __at(0x028D) volatile __ODCONBbits_t ODCONBbits
;
4215 //==============================================================================
4218 //==============================================================================
4221 extern __at(0x028E) __sfr ODCONC
;
4235 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
4246 //==============================================================================
4248 extern __at(0x0291) __sfr CCPR1
;
4249 extern __at(0x0291) __sfr CCPR1L
;
4250 extern __at(0x0292) __sfr CCPR1H
;
4252 //==============================================================================
4255 extern __at(0x0293) __sfr CCP1CON
;
4273 unsigned CCP1MODE0
: 1;
4274 unsigned CCP1MODE1
: 1;
4275 unsigned CCP1MODE2
: 1;
4276 unsigned CCP1MODE3
: 1;
4277 unsigned CCP1FMT
: 1;
4278 unsigned CCP1OUT
: 1;
4280 unsigned CCP1EN
: 1;
4285 unsigned CCP1MODE
: 4;
4296 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
4299 #define _CCP1MODE0 0x01
4301 #define _CCP1MODE1 0x02
4303 #define _CCP1MODE2 0x04
4305 #define _CCP1MODE3 0x08
4307 #define _CCP1FMT 0x10
4309 #define _CCP1OUT 0x20
4311 #define _CCP1EN 0x80
4313 //==============================================================================
4316 //==============================================================================
4319 extern __at(0x0294) __sfr CCP1CAP
;
4337 unsigned CCP1CTS0
: 1;
4338 unsigned CCP1CTS1
: 1;
4339 unsigned CCP1CTS2
: 1;
4355 unsigned CCP1CTS
: 3;
4360 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
4363 #define _CCP1CTS0 0x01
4365 #define _CCP1CTS1 0x02
4367 #define _CCP1CTS2 0x04
4369 //==============================================================================
4371 extern __at(0x0298) __sfr CCPR2
;
4372 extern __at(0x0298) __sfr CCPR2L
;
4373 extern __at(0x0299) __sfr CCPR2H
;
4375 //==============================================================================
4378 extern __at(0x029A) __sfr CCP2CON
;
4396 unsigned CCP2MODE0
: 1;
4397 unsigned CCP2MODE1
: 1;
4398 unsigned CCP2MODE2
: 1;
4399 unsigned CCP2MODE3
: 1;
4400 unsigned CCP2FMT
: 1;
4401 unsigned CCP2OUT
: 1;
4403 unsigned CCP2EN
: 1;
4414 unsigned CCP2MODE
: 4;
4419 extern __at(0x029A) volatile __CCP2CONbits_t CCP2CONbits
;
4421 #define _CCP2CON_MODE0 0x01
4422 #define _CCP2CON_CCP2MODE0 0x01
4423 #define _CCP2CON_MODE1 0x02
4424 #define _CCP2CON_CCP2MODE1 0x02
4425 #define _CCP2CON_MODE2 0x04
4426 #define _CCP2CON_CCP2MODE2 0x04
4427 #define _CCP2CON_MODE3 0x08
4428 #define _CCP2CON_CCP2MODE3 0x08
4429 #define _CCP2CON_FMT 0x10
4430 #define _CCP2CON_CCP2FMT 0x10
4431 #define _CCP2CON_OUT 0x20
4432 #define _CCP2CON_CCP2OUT 0x20
4433 #define _CCP2CON_EN 0x80
4434 #define _CCP2CON_CCP2EN 0x80
4436 //==============================================================================
4439 //==============================================================================
4442 extern __at(0x029B) __sfr CCP2CAP
;
4460 unsigned CCP2CTS0
: 1;
4461 unsigned CCP2CTS1
: 1;
4462 unsigned CCP2CTS2
: 1;
4472 unsigned CCP2CTS
: 3;
4483 extern __at(0x029B) volatile __CCP2CAPbits_t CCP2CAPbits
;
4485 #define _CCP2CAP_CTS0 0x01
4486 #define _CCP2CAP_CCP2CTS0 0x01
4487 #define _CCP2CAP_CTS1 0x02
4488 #define _CCP2CAP_CCP2CTS1 0x02
4489 #define _CCP2CAP_CTS2 0x04
4490 #define _CCP2CAP_CCP2CTS2 0x04
4492 //==============================================================================
4495 //==============================================================================
4498 extern __at(0x029E) __sfr CCPTMRS
;
4504 unsigned C1TSEL0
: 1;
4505 unsigned C1TSEL1
: 1;
4506 unsigned C2TSEL0
: 1;
4507 unsigned C2TSEL1
: 1;
4508 unsigned P3TSEL0
: 1;
4509 unsigned P3TSEL1
: 1;
4510 unsigned P4TSEL0
: 1;
4511 unsigned P4TSEL1
: 1;
4516 unsigned C1TSEL
: 2;
4523 unsigned C2TSEL
: 2;
4530 unsigned P3TSEL
: 2;
4537 unsigned P4TSEL
: 2;
4541 extern __at(0x029E) volatile __CCPTMRSbits_t CCPTMRSbits
;
4543 #define _C1TSEL0 0x01
4544 #define _C1TSEL1 0x02
4545 #define _C2TSEL0 0x04
4546 #define _C2TSEL1 0x08
4547 #define _P3TSEL0 0x10
4548 #define _P3TSEL1 0x20
4549 #define _P4TSEL0 0x40
4550 #define _P4TSEL1 0x80
4552 //==============================================================================
4555 //==============================================================================
4558 extern __at(0x030C) __sfr SLRCONA
;
4572 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
4580 //==============================================================================
4583 //==============================================================================
4586 extern __at(0x030D) __sfr SLRCONB
;
4600 extern __at(0x030D) volatile __SLRCONBbits_t SLRCONBbits
;
4607 //==============================================================================
4610 //==============================================================================
4613 extern __at(0x030E) __sfr SLRCONC
;
4627 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
4638 //==============================================================================
4641 //==============================================================================
4644 extern __at(0x031B) __sfr MD2CON0
;
4662 unsigned MD2BIT
: 1;
4666 unsigned MD2OPOL
: 1;
4667 unsigned MD2OUT
: 1;
4673 extern __at(0x031B) volatile __MD2CON0bits_t MD2CON0bits
;
4675 #define _MD2CON0_BIT 0x01
4676 #define _MD2CON0_MD2BIT 0x01
4677 #define _MD2CON0_OPOL 0x10
4678 #define _MD2CON0_MD2OPOL 0x10
4679 #define _MD2CON0_OUT 0x20
4680 #define _MD2CON0_MD2OUT 0x20
4681 #define _MD2CON0_EN 0x80
4682 #define _MD2CON0_MD2EN 0x80
4684 //==============================================================================
4687 //==============================================================================
4690 extern __at(0x031C) __sfr MD2CON1
;
4696 unsigned CLSYNC
: 1;
4700 unsigned CHSYNC
: 1;
4708 unsigned MD2CLSYNC
: 1;
4709 unsigned MD2CLPOL
: 1;
4712 unsigned MD2CHSYNC
: 1;
4713 unsigned MD2CHPOL
: 1;
4719 extern __at(0x031C) volatile __MD2CON1bits_t MD2CON1bits
;
4721 #define _MD2CON1_CLSYNC 0x01
4722 #define _MD2CON1_MD2CLSYNC 0x01
4723 #define _MD2CON1_CLPOL 0x02
4724 #define _MD2CON1_MD2CLPOL 0x02
4725 #define _MD2CON1_CHSYNC 0x10
4726 #define _MD2CON1_MD2CHSYNC 0x10
4727 #define _MD2CON1_CHPOL 0x20
4728 #define _MD2CON1_MD2CHPOL 0x20
4730 //==============================================================================
4733 //==============================================================================
4736 extern __at(0x031D) __sfr MD2SRC
;
4754 unsigned MD2MS0
: 1;
4755 unsigned MD2MS1
: 1;
4756 unsigned MD2MS2
: 1;
4757 unsigned MD2MS3
: 1;
4758 unsigned MD2MS4
: 1;
4777 extern __at(0x031D) volatile __MD2SRCbits_t MD2SRCbits
;
4779 #define _MD2SRC_MS0 0x01
4780 #define _MD2SRC_MD2MS0 0x01
4781 #define _MD2SRC_MS1 0x02
4782 #define _MD2SRC_MD2MS1 0x02
4783 #define _MD2SRC_MS2 0x04
4784 #define _MD2SRC_MD2MS2 0x04
4785 #define _MD2SRC_MS3 0x08
4786 #define _MD2SRC_MD2MS3 0x08
4787 #define _MD2SRC_MS4 0x10
4788 #define _MD2SRC_MD2MS4 0x10
4790 //==============================================================================
4793 //==============================================================================
4796 extern __at(0x031E) __sfr MD2CARL
;
4814 unsigned MD2CL0
: 1;
4815 unsigned MD2CL1
: 1;
4816 unsigned MD2CL2
: 1;
4817 unsigned MD2CL3
: 1;
4837 extern __at(0x031E) volatile __MD2CARLbits_t MD2CARLbits
;
4839 #define _MD2CARL_CL0 0x01
4840 #define _MD2CARL_MD2CL0 0x01
4841 #define _MD2CARL_CL1 0x02
4842 #define _MD2CARL_MD2CL1 0x02
4843 #define _MD2CARL_CL2 0x04
4844 #define _MD2CARL_MD2CL2 0x04
4845 #define _MD2CARL_CL3 0x08
4846 #define _MD2CARL_MD2CL3 0x08
4848 //==============================================================================
4851 //==============================================================================
4854 extern __at(0x031F) __sfr MD2CARH
;
4872 unsigned MD2CH0
: 1;
4873 unsigned MD2CH1
: 1;
4874 unsigned MD2CH2
: 1;
4875 unsigned MD2CH3
: 1;
4895 extern __at(0x031F) volatile __MD2CARHbits_t MD2CARHbits
;
4897 #define _MD2CARH_CH0 0x01
4898 #define _MD2CARH_MD2CH0 0x01
4899 #define _MD2CARH_CH1 0x02
4900 #define _MD2CARH_MD2CH1 0x02
4901 #define _MD2CARH_CH2 0x04
4902 #define _MD2CARH_MD2CH2 0x04
4903 #define _MD2CARH_CH3 0x08
4904 #define _MD2CARH_MD2CH3 0x08
4906 //==============================================================================
4909 //==============================================================================
4912 extern __at(0x038C) __sfr INLVLA
;
4918 unsigned INLVLA0
: 1;
4919 unsigned INLVLA1
: 1;
4920 unsigned INLVLA2
: 1;
4921 unsigned INLVLA3
: 1;
4922 unsigned INLVLA4
: 1;
4923 unsigned INLVLA5
: 1;
4930 unsigned INLVLA
: 6;
4935 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
4937 #define _INLVLA0 0x01
4938 #define _INLVLA1 0x02
4939 #define _INLVLA2 0x04
4940 #define _INLVLA3 0x08
4941 #define _INLVLA4 0x10
4942 #define _INLVLA5 0x20
4944 //==============================================================================
4947 //==============================================================================
4950 extern __at(0x038D) __sfr INLVLB
;
4958 unsigned INLVLB4
: 1;
4959 unsigned INLVLB5
: 1;
4960 unsigned INLVLB6
: 1;
4961 unsigned INLVLB7
: 1;
4964 extern __at(0x038D) volatile __INLVLBbits_t INLVLBbits
;
4966 #define _INLVLB4 0x10
4967 #define _INLVLB5 0x20
4968 #define _INLVLB6 0x40
4969 #define _INLVLB7 0x80
4971 //==============================================================================
4974 //==============================================================================
4977 extern __at(0x038E) __sfr INLVLC
;
4981 unsigned INLVLC0
: 1;
4982 unsigned INLVLC1
: 1;
4983 unsigned INLVLC2
: 1;
4984 unsigned INLVLC3
: 1;
4985 unsigned INLVLC4
: 1;
4986 unsigned INLVLC5
: 1;
4987 unsigned INLVLC6
: 1;
4988 unsigned INLVLC7
: 1;
4991 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
4993 #define _INLVLC0 0x01
4994 #define _INLVLC1 0x02
4995 #define _INLVLC2 0x04
4996 #define _INLVLC3 0x08
4997 #define _INLVLC4 0x10
4998 #define _INLVLC5 0x20
4999 #define _INLVLC6 0x40
5000 #define _INLVLC7 0x80
5002 //==============================================================================
5005 //==============================================================================
5008 extern __at(0x0391) __sfr IOCAP
;
5014 unsigned IOCAP0
: 1;
5015 unsigned IOCAP1
: 1;
5016 unsigned IOCAP2
: 1;
5017 unsigned IOCAP3
: 1;
5018 unsigned IOCAP4
: 1;
5019 unsigned IOCAP5
: 1;
5031 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
5033 #define _IOCAP0 0x01
5034 #define _IOCAP1 0x02
5035 #define _IOCAP2 0x04
5036 #define _IOCAP3 0x08
5037 #define _IOCAP4 0x10
5038 #define _IOCAP5 0x20
5040 //==============================================================================
5043 //==============================================================================
5046 extern __at(0x0392) __sfr IOCAN
;
5052 unsigned IOCAN0
: 1;
5053 unsigned IOCAN1
: 1;
5054 unsigned IOCAN2
: 1;
5055 unsigned IOCAN3
: 1;
5056 unsigned IOCAN4
: 1;
5057 unsigned IOCAN5
: 1;
5069 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
5071 #define _IOCAN0 0x01
5072 #define _IOCAN1 0x02
5073 #define _IOCAN2 0x04
5074 #define _IOCAN3 0x08
5075 #define _IOCAN4 0x10
5076 #define _IOCAN5 0x20
5078 //==============================================================================
5081 //==============================================================================
5084 extern __at(0x0393) __sfr IOCAF
;
5090 unsigned IOCAF0
: 1;
5091 unsigned IOCAF1
: 1;
5092 unsigned IOCAF2
: 1;
5093 unsigned IOCAF3
: 1;
5094 unsigned IOCAF4
: 1;
5095 unsigned IOCAF5
: 1;
5107 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
5109 #define _IOCAF0 0x01
5110 #define _IOCAF1 0x02
5111 #define _IOCAF2 0x04
5112 #define _IOCAF3 0x08
5113 #define _IOCAF4 0x10
5114 #define _IOCAF5 0x20
5116 //==============================================================================
5119 //==============================================================================
5122 extern __at(0x0394) __sfr IOCBP
;
5130 unsigned IOCBP4
: 1;
5131 unsigned IOCBP5
: 1;
5132 unsigned IOCBP6
: 1;
5133 unsigned IOCBP7
: 1;
5136 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
5138 #define _IOCBP4 0x10
5139 #define _IOCBP5 0x20
5140 #define _IOCBP6 0x40
5141 #define _IOCBP7 0x80
5143 //==============================================================================
5146 //==============================================================================
5149 extern __at(0x0395) __sfr IOCBN
;
5157 unsigned IOCBN4
: 1;
5158 unsigned IOCBN5
: 1;
5159 unsigned IOCBN6
: 1;
5160 unsigned IOCBN7
: 1;
5163 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
5165 #define _IOCBN4 0x10
5166 #define _IOCBN5 0x20
5167 #define _IOCBN6 0x40
5168 #define _IOCBN7 0x80
5170 //==============================================================================
5173 //==============================================================================
5176 extern __at(0x0396) __sfr IOCBF
;
5184 unsigned IOCBF4
: 1;
5185 unsigned IOCBF5
: 1;
5186 unsigned IOCBF6
: 1;
5187 unsigned IOCBF7
: 1;
5190 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
5192 #define _IOCBF4 0x10
5193 #define _IOCBF5 0x20
5194 #define _IOCBF6 0x40
5195 #define _IOCBF7 0x80
5197 //==============================================================================
5200 //==============================================================================
5203 extern __at(0x0397) __sfr IOCCP
;
5207 unsigned IOCCP0
: 1;
5208 unsigned IOCCP1
: 1;
5209 unsigned IOCCP2
: 1;
5210 unsigned IOCCP3
: 1;
5211 unsigned IOCCP4
: 1;
5212 unsigned IOCCP5
: 1;
5213 unsigned IOCCP6
: 1;
5214 unsigned IOCCP7
: 1;
5217 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
5219 #define _IOCCP0 0x01
5220 #define _IOCCP1 0x02
5221 #define _IOCCP2 0x04
5222 #define _IOCCP3 0x08
5223 #define _IOCCP4 0x10
5224 #define _IOCCP5 0x20
5225 #define _IOCCP6 0x40
5226 #define _IOCCP7 0x80
5228 //==============================================================================
5231 //==============================================================================
5234 extern __at(0x0398) __sfr IOCCN
;
5238 unsigned IOCCN0
: 1;
5239 unsigned IOCCN1
: 1;
5240 unsigned IOCCN2
: 1;
5241 unsigned IOCCN3
: 1;
5242 unsigned IOCCN4
: 1;
5243 unsigned IOCCN5
: 1;
5244 unsigned IOCCN6
: 1;
5245 unsigned IOCCN7
: 1;
5248 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
5250 #define _IOCCN0 0x01
5251 #define _IOCCN1 0x02
5252 #define _IOCCN2 0x04
5253 #define _IOCCN3 0x08
5254 #define _IOCCN4 0x10
5255 #define _IOCCN5 0x20
5256 #define _IOCCN6 0x40
5257 #define _IOCCN7 0x80
5259 //==============================================================================
5262 //==============================================================================
5265 extern __at(0x0399) __sfr IOCCF
;
5269 unsigned IOCCF0
: 1;
5270 unsigned IOCCF1
: 1;
5271 unsigned IOCCF2
: 1;
5272 unsigned IOCCF3
: 1;
5273 unsigned IOCCF4
: 1;
5274 unsigned IOCCF5
: 1;
5275 unsigned IOCCF6
: 1;
5276 unsigned IOCCF7
: 1;
5279 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
5281 #define _IOCCF0 0x01
5282 #define _IOCCF1 0x02
5283 #define _IOCCF2 0x04
5284 #define _IOCCF3 0x08
5285 #define _IOCCF4 0x10
5286 #define _IOCCF5 0x20
5287 #define _IOCCF6 0x40
5288 #define _IOCCF7 0x80
5290 //==============================================================================
5293 //==============================================================================
5296 extern __at(0x039B) __sfr MD1CON0
;
5314 unsigned MD1BIT
: 1;
5318 unsigned MD1OPOL
: 1;
5319 unsigned MD1OUT
: 1;
5325 extern __at(0x039B) volatile __MD1CON0bits_t MD1CON0bits
;
5327 #define _MD1CON0_BIT 0x01
5328 #define _MD1CON0_MD1BIT 0x01
5329 #define _MD1CON0_OPOL 0x10
5330 #define _MD1CON0_MD1OPOL 0x10
5331 #define _MD1CON0_OUT 0x20
5332 #define _MD1CON0_MD1OUT 0x20
5333 #define _MD1CON0_EN 0x80
5334 #define _MD1CON0_MD1EN 0x80
5336 //==============================================================================
5339 //==============================================================================
5342 extern __at(0x039C) __sfr MD1CON1
;
5348 unsigned CLSYNC
: 1;
5352 unsigned CHSYNC
: 1;
5360 unsigned MD1CLSYNC
: 1;
5361 unsigned MD1CLPOL
: 1;
5364 unsigned MD1CHSYNC
: 1;
5365 unsigned MD1CHPOL
: 1;
5371 extern __at(0x039C) volatile __MD1CON1bits_t MD1CON1bits
;
5373 #define _CLSYNC 0x01
5374 #define _MD1CLSYNC 0x01
5376 #define _MD1CLPOL 0x02
5377 #define _CHSYNC 0x10
5378 #define _MD1CHSYNC 0x10
5380 #define _MD1CHPOL 0x20
5382 //==============================================================================
5385 //==============================================================================
5388 extern __at(0x039D) __sfr MD1SRC
;
5406 unsigned MD1MS0
: 1;
5407 unsigned MD1MS1
: 1;
5408 unsigned MD1MS2
: 1;
5409 unsigned MD1MS3
: 1;
5410 unsigned MD1MS4
: 1;
5429 extern __at(0x039D) volatile __MD1SRCbits_t MD1SRCbits
;
5432 #define _MD1MS0 0x01
5434 #define _MD1MS1 0x02
5436 #define _MD1MS2 0x04
5438 #define _MD1MS3 0x08
5440 #define _MD1MS4 0x10
5442 //==============================================================================
5445 //==============================================================================
5448 extern __at(0x039E) __sfr MD1CARL
;
5466 unsigned MD1CL0
: 1;
5467 unsigned MD1CL1
: 1;
5468 unsigned MD1CL2
: 1;
5469 unsigned MD1CL3
: 1;
5489 extern __at(0x039E) volatile __MD1CARLbits_t MD1CARLbits
;
5492 #define _MD1CL0 0x01
5494 #define _MD1CL1 0x02
5496 #define _MD1CL2 0x04
5498 #define _MD1CL3 0x08
5500 //==============================================================================
5503 //==============================================================================
5506 extern __at(0x039F) __sfr MD1CARH
;
5524 unsigned MD1CH0
: 1;
5525 unsigned MD1CH1
: 1;
5526 unsigned MD1CH2
: 1;
5527 unsigned MD1CH3
: 1;
5547 extern __at(0x039F) volatile __MD1CARHbits_t MD1CARHbits
;
5550 #define _MD1CH0 0x01
5552 #define _MD1CH1 0x02
5554 #define _MD1CH2 0x04
5556 #define _MD1CH3 0x08
5558 //==============================================================================
5561 //==============================================================================
5564 extern __at(0x040E) __sfr HIDRVC
;
5578 extern __at(0x040E) volatile __HIDRVCbits_t HIDRVCbits
;
5583 //==============================================================================
5585 extern __at(0x0413) __sfr T4TMR
;
5586 extern __at(0x0413) __sfr TMR4
;
5587 extern __at(0x0414) __sfr PR4
;
5588 extern __at(0x0414) __sfr T4PR
;
5590 //==============================================================================
5593 extern __at(0x0415) __sfr T4CON
;
5599 unsigned OUTPS0
: 1;
5600 unsigned OUTPS1
: 1;
5601 unsigned OUTPS2
: 1;
5602 unsigned OUTPS3
: 1;
5611 unsigned T4OUTPS0
: 1;
5612 unsigned T4OUTPS1
: 1;
5613 unsigned T4OUTPS2
: 1;
5614 unsigned T4OUTPS3
: 1;
5615 unsigned T4CKPS0
: 1;
5616 unsigned T4CKPS1
: 1;
5617 unsigned T4CKPS2
: 1;
5630 unsigned TMR4ON
: 1;
5641 unsigned T4OUTPS
: 4;
5655 unsigned T4CKPS
: 3;
5660 extern __at(0x0415) volatile __T4CONbits_t T4CONbits
;
5662 #define _T4CON_OUTPS0 0x01
5663 #define _T4CON_T4OUTPS0 0x01
5664 #define _T4CON_OUTPS1 0x02
5665 #define _T4CON_T4OUTPS1 0x02
5666 #define _T4CON_OUTPS2 0x04
5667 #define _T4CON_T4OUTPS2 0x04
5668 #define _T4CON_OUTPS3 0x08
5669 #define _T4CON_T4OUTPS3 0x08
5670 #define _T4CON_CKPS0 0x10
5671 #define _T4CON_T4CKPS0 0x10
5672 #define _T4CON_CKPS1 0x20
5673 #define _T4CON_T4CKPS1 0x20
5674 #define _T4CON_CKPS2 0x40
5675 #define _T4CON_T4CKPS2 0x40
5676 #define _T4CON_ON 0x80
5677 #define _T4CON_T4ON 0x80
5678 #define _T4CON_TMR4ON 0x80
5680 //==============================================================================
5683 //==============================================================================
5686 extern __at(0x0416) __sfr T4HLT
;
5697 unsigned CKSYNC
: 1;
5704 unsigned T4MODE0
: 1;
5705 unsigned T4MODE1
: 1;
5706 unsigned T4MODE2
: 1;
5707 unsigned T4MODE3
: 1;
5708 unsigned T4MODE4
: 1;
5709 unsigned T4CKSYNC
: 1;
5710 unsigned T4CKPOL
: 1;
5711 unsigned T4PSYNC
: 1;
5722 unsigned T4MODE
: 5;
5727 extern __at(0x0416) volatile __T4HLTbits_t T4HLTbits
;
5729 #define _T4HLT_MODE0 0x01
5730 #define _T4HLT_T4MODE0 0x01
5731 #define _T4HLT_MODE1 0x02
5732 #define _T4HLT_T4MODE1 0x02
5733 #define _T4HLT_MODE2 0x04
5734 #define _T4HLT_T4MODE2 0x04
5735 #define _T4HLT_MODE3 0x08
5736 #define _T4HLT_T4MODE3 0x08
5737 #define _T4HLT_MODE4 0x10
5738 #define _T4HLT_T4MODE4 0x10
5739 #define _T4HLT_CKSYNC 0x20
5740 #define _T4HLT_T4CKSYNC 0x20
5741 #define _T4HLT_CKPOL 0x40
5742 #define _T4HLT_T4CKPOL 0x40
5743 #define _T4HLT_PSYNC 0x80
5744 #define _T4HLT_T4PSYNC 0x80
5746 //==============================================================================
5749 //==============================================================================
5752 extern __at(0x0417) __sfr T4CLKCON
;
5793 extern __at(0x0417) volatile __T4CLKCONbits_t T4CLKCONbits
;
5795 #define _T4CLKCON_CS0 0x01
5796 #define _T4CLKCON_T4CS0 0x01
5797 #define _T4CLKCON_CS1 0x02
5798 #define _T4CLKCON_T4CS1 0x02
5799 #define _T4CLKCON_CS2 0x04
5800 #define _T4CLKCON_T4CS2 0x04
5801 #define _T4CLKCON_CS3 0x08
5802 #define _T4CLKCON_T4CS3 0x08
5804 //==============================================================================
5807 //==============================================================================
5810 extern __at(0x0418) __sfr T4RST
;
5828 unsigned T4RSEL0
: 1;
5829 unsigned T4RSEL1
: 1;
5830 unsigned T4RSEL2
: 1;
5831 unsigned T4RSEL3
: 1;
5846 unsigned T4RSEL
: 4;
5851 extern __at(0x0418) volatile __T4RSTbits_t T4RSTbits
;
5853 #define _T4RST_RSEL0 0x01
5854 #define _T4RST_T4RSEL0 0x01
5855 #define _T4RST_RSEL1 0x02
5856 #define _T4RST_T4RSEL1 0x02
5857 #define _T4RST_RSEL2 0x04
5858 #define _T4RST_T4RSEL2 0x04
5859 #define _T4RST_RSEL3 0x08
5860 #define _T4RST_T4RSEL3 0x08
5862 //==============================================================================
5864 extern __at(0x041A) __sfr T6TMR
;
5865 extern __at(0x041A) __sfr TMR6
;
5866 extern __at(0x041B) __sfr PR6
;
5867 extern __at(0x041B) __sfr T6PR
;
5869 //==============================================================================
5872 extern __at(0x041C) __sfr T6CON
;
5878 unsigned OUTPS0
: 1;
5879 unsigned OUTPS1
: 1;
5880 unsigned OUTPS2
: 1;
5881 unsigned OUTPS3
: 1;
5890 unsigned T6OUTPS0
: 1;
5891 unsigned T6OUTPS1
: 1;
5892 unsigned T6OUTPS2
: 1;
5893 unsigned T6OUTPS3
: 1;
5894 unsigned T6CKPS0
: 1;
5895 unsigned T6CKPS1
: 1;
5896 unsigned T6CKPS2
: 1;
5909 unsigned TMR6ON
: 1;
5914 unsigned T6OUTPS
: 4;
5927 unsigned T6CKPS
: 3;
5939 extern __at(0x041C) volatile __T6CONbits_t T6CONbits
;
5941 #define _T6CON_OUTPS0 0x01
5942 #define _T6CON_T6OUTPS0 0x01
5943 #define _T6CON_OUTPS1 0x02
5944 #define _T6CON_T6OUTPS1 0x02
5945 #define _T6CON_OUTPS2 0x04
5946 #define _T6CON_T6OUTPS2 0x04
5947 #define _T6CON_OUTPS3 0x08
5948 #define _T6CON_T6OUTPS3 0x08
5949 #define _T6CON_CKPS0 0x10
5950 #define _T6CON_T6CKPS0 0x10
5951 #define _T6CON_CKPS1 0x20
5952 #define _T6CON_T6CKPS1 0x20
5953 #define _T6CON_CKPS2 0x40
5954 #define _T6CON_T6CKPS2 0x40
5955 #define _T6CON_ON 0x80
5956 #define _T6CON_T6ON 0x80
5957 #define _T6CON_TMR6ON 0x80
5959 //==============================================================================
5962 //==============================================================================
5965 extern __at(0x041D) __sfr T6HLT
;
5976 unsigned CKSYNC
: 1;
5983 unsigned T6MODE0
: 1;
5984 unsigned T6MODE1
: 1;
5985 unsigned T6MODE2
: 1;
5986 unsigned T6MODE3
: 1;
5987 unsigned T6MODE4
: 1;
5988 unsigned T6CKSYNC
: 1;
5989 unsigned T6CKPOL
: 1;
5990 unsigned T6PSYNC
: 1;
6001 unsigned T6MODE
: 5;
6006 extern __at(0x041D) volatile __T6HLTbits_t T6HLTbits
;
6008 #define _T6HLT_MODE0 0x01
6009 #define _T6HLT_T6MODE0 0x01
6010 #define _T6HLT_MODE1 0x02
6011 #define _T6HLT_T6MODE1 0x02
6012 #define _T6HLT_MODE2 0x04
6013 #define _T6HLT_T6MODE2 0x04
6014 #define _T6HLT_MODE3 0x08
6015 #define _T6HLT_T6MODE3 0x08
6016 #define _T6HLT_MODE4 0x10
6017 #define _T6HLT_T6MODE4 0x10
6018 #define _T6HLT_CKSYNC 0x20
6019 #define _T6HLT_T6CKSYNC 0x20
6020 #define _T6HLT_CKPOL 0x40
6021 #define _T6HLT_T6CKPOL 0x40
6022 #define _T6HLT_PSYNC 0x80
6023 #define _T6HLT_T6PSYNC 0x80
6025 //==============================================================================
6028 //==============================================================================
6031 extern __at(0x041E) __sfr T6CLKCON
;
6072 extern __at(0x041E) volatile __T6CLKCONbits_t T6CLKCONbits
;
6074 #define _T6CLKCON_CS0 0x01
6075 #define _T6CLKCON_T6CS0 0x01
6076 #define _T6CLKCON_CS1 0x02
6077 #define _T6CLKCON_T6CS1 0x02
6078 #define _T6CLKCON_CS2 0x04
6079 #define _T6CLKCON_T6CS2 0x04
6080 #define _T6CLKCON_CS3 0x08
6081 #define _T6CLKCON_T6CS3 0x08
6083 //==============================================================================
6086 //==============================================================================
6089 extern __at(0x041F) __sfr T6RST
;
6107 unsigned T6RSEL0
: 1;
6108 unsigned T6RSEL1
: 1;
6109 unsigned T6RSEL2
: 1;
6110 unsigned T6RSEL3
: 1;
6125 unsigned T6RSEL
: 4;
6130 extern __at(0x041F) volatile __T6RSTbits_t T6RSTbits
;
6132 #define _T6RST_RSEL0 0x01
6133 #define _T6RST_T6RSEL0 0x01
6134 #define _T6RST_RSEL1 0x02
6135 #define _T6RST_T6RSEL1 0x02
6136 #define _T6RST_RSEL2 0x04
6137 #define _T6RST_T6RSEL2 0x04
6138 #define _T6RST_RSEL3 0x08
6139 #define _T6RST_T6RSEL3 0x08
6141 //==============================================================================
6143 extern __at(0x0493) __sfr TMR3
;
6144 extern __at(0x0493) __sfr TMR3L
;
6145 extern __at(0x0494) __sfr TMR3H
;
6147 //==============================================================================
6150 extern __at(0x0495) __sfr T3CON
;
6158 unsigned NOT_SYNC
: 1;
6172 unsigned T3CKPS0
: 1;
6173 unsigned T3CKPS1
: 1;
6180 unsigned TMR3ON
: 1;
6182 unsigned NOT_T3SYNC
: 1;
6186 unsigned TMR3CS0
: 1;
6187 unsigned TMR3CS1
: 1;
6205 unsigned T3CKPS
: 2;
6219 unsigned TMR3CS
: 2;
6235 extern __at(0x0495) volatile __T3CONbits_t T3CONbits
;
6237 #define _T3CON_ON 0x01
6238 #define _T3CON_TMRON 0x01
6239 #define _T3CON_TMR3ON 0x01
6240 #define _T3CON_T3ON 0x01
6241 #define _T3CON_NOT_SYNC 0x04
6242 #define _T3CON_SYNC 0x04
6243 #define _T3CON_NOT_T3SYNC 0x04
6244 #define _T3CON_CKPS0 0x10
6245 #define _T3CON_T3CKPS0 0x10
6246 #define _T3CON_CKPS1 0x20
6247 #define _T3CON_T3CKPS1 0x20
6248 #define _T3CON_CS0 0x40
6249 #define _T3CON_T3CS0 0x40
6250 #define _T3CON_TMR3CS0 0x40
6251 #define _T3CON_CS1 0x80
6252 #define _T3CON_T3CS1 0x80
6253 #define _T3CON_TMR3CS1 0x80
6255 //==============================================================================
6258 //==============================================================================
6261 extern __at(0x0496) __sfr T3GCON
;
6270 unsigned GGO_NOT_DONE
: 1;
6279 unsigned T3GSS0
: 1;
6280 unsigned T3GSS1
: 1;
6281 unsigned T3GVAL
: 1;
6282 unsigned T3GGO_NOT_DONE
: 1;
6283 unsigned T3GSPM
: 1;
6285 unsigned T3GPOL
: 1;
6298 unsigned TMR3GE
: 1;
6314 extern __at(0x0496) volatile __T3GCONbits_t T3GCONbits
;
6316 #define _T3GCON_GSS0 0x01
6317 #define _T3GCON_T3GSS0 0x01
6318 #define _T3GCON_GSS1 0x02
6319 #define _T3GCON_T3GSS1 0x02
6320 #define _T3GCON_GVAL 0x04
6321 #define _T3GCON_T3GVAL 0x04
6322 #define _T3GCON_GGO_NOT_DONE 0x08
6323 #define _T3GCON_T3GGO_NOT_DONE 0x08
6324 #define _T3GCON_GSPM 0x10
6325 #define _T3GCON_T3GSPM 0x10
6326 #define _T3GCON_GTM 0x20
6327 #define _T3GCON_T3GTM 0x20
6328 #define _T3GCON_GPOL 0x40
6329 #define _T3GCON_T3GPOL 0x40
6330 #define _T3GCON_GE 0x80
6331 #define _T3GCON_T3GE 0x80
6332 #define _T3GCON_TMR3GE 0x80
6334 //==============================================================================
6336 extern __at(0x049A) __sfr TMR5
;
6337 extern __at(0x049A) __sfr TMR5L
;
6338 extern __at(0x049B) __sfr TMR5H
;
6340 //==============================================================================
6343 extern __at(0x049C) __sfr T5CON
;
6351 unsigned NOT_SYNC
: 1;
6365 unsigned T5CKPS0
: 1;
6366 unsigned T5CKPS1
: 1;
6373 unsigned TMR5ON
: 1;
6375 unsigned NOT_T5SYNC
: 1;
6379 unsigned TMR5CS0
: 1;
6380 unsigned TMR5CS1
: 1;
6405 unsigned T5CKPS
: 2;
6424 unsigned TMR5CS
: 2;
6428 extern __at(0x049C) volatile __T5CONbits_t T5CONbits
;
6430 #define _T5CON_ON 0x01
6431 #define _T5CON_TMRON 0x01
6432 #define _T5CON_TMR5ON 0x01
6433 #define _T5CON_T5ON 0x01
6434 #define _T5CON_NOT_SYNC 0x04
6435 #define _T5CON_SYNC 0x04
6436 #define _T5CON_NOT_T5SYNC 0x04
6437 #define _T5CON_CKPS0 0x10
6438 #define _T5CON_T5CKPS0 0x10
6439 #define _T5CON_CKPS1 0x20
6440 #define _T5CON_T5CKPS1 0x20
6441 #define _T5CON_CS0 0x40
6442 #define _T5CON_T5CS0 0x40
6443 #define _T5CON_TMR5CS0 0x40
6444 #define _T5CON_CS1 0x80
6445 #define _T5CON_T5CS1 0x80
6446 #define _T5CON_TMR5CS1 0x80
6448 //==============================================================================
6451 //==============================================================================
6454 extern __at(0x049D) __sfr T5GCON
;
6463 unsigned GGO_NOT_DONE
: 1;
6472 unsigned T5GSS0
: 1;
6473 unsigned T5GSS1
: 1;
6474 unsigned T5GVAL
: 1;
6475 unsigned T5GGO_NOT_DONE
: 1;
6476 unsigned T5GSPM
: 1;
6478 unsigned T5GPOL
: 1;
6491 unsigned TMR5GE
: 1;
6507 extern __at(0x049D) volatile __T5GCONbits_t T5GCONbits
;
6509 #define _T5GCON_GSS0 0x01
6510 #define _T5GCON_T5GSS0 0x01
6511 #define _T5GCON_GSS1 0x02
6512 #define _T5GCON_T5GSS1 0x02
6513 #define _T5GCON_GVAL 0x04
6514 #define _T5GCON_T5GVAL 0x04
6515 #define _T5GCON_GGO_NOT_DONE 0x08
6516 #define _T5GCON_T5GGO_NOT_DONE 0x08
6517 #define _T5GCON_GSPM 0x10
6518 #define _T5GCON_T5GSPM 0x10
6519 #define _T5GCON_GTM 0x20
6520 #define _T5GCON_T5GTM 0x20
6521 #define _T5GCON_GPOL 0x40
6522 #define _T5GCON_T5GPOL 0x40
6523 #define _T5GCON_GE 0x80
6524 #define _T5GCON_T5GE 0x80
6525 #define _T5GCON_TMR5GE 0x80
6527 //==============================================================================
6529 extern __at(0x050F) __sfr OPA1NCHS
;
6530 extern __at(0x0510) __sfr OPA1PCHS
;
6532 //==============================================================================
6535 extern __at(0x0511) __sfr OPA1CON
;
6553 unsigned OPA1ORM0
: 1;
6554 unsigned OPA1ORM1
: 1;
6555 unsigned OPA1ORPOL
: 1;
6557 unsigned OPA1UG
: 1;
6560 unsigned OPA1EN
: 1;
6571 unsigned OPA1ORM
: 2;
6576 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
6578 #define _OPA1CON_ORM0 0x01
6579 #define _OPA1CON_OPA1ORM0 0x01
6580 #define _OPA1CON_ORM1 0x02
6581 #define _OPA1CON_OPA1ORM1 0x02
6582 #define _OPA1CON_ORPOL 0x04
6583 #define _OPA1CON_OPA1ORPOL 0x04
6584 #define _OPA1CON_UG 0x10
6585 #define _OPA1CON_OPA1UG 0x10
6586 #define _OPA1CON_EN 0x80
6587 #define _OPA1CON_OPA1EN 0x80
6589 //==============================================================================
6591 extern __at(0x0512) __sfr OPA1ORS
;
6592 extern __at(0x0513) __sfr OPA2NCHS
;
6593 extern __at(0x0514) __sfr OPA2PCHS
;
6595 //==============================================================================
6598 extern __at(0x0515) __sfr OPA2CON
;
6616 unsigned OPA2ORM0
: 1;
6617 unsigned OPA2ORM1
: 1;
6618 unsigned OPA2ORPOL
: 1;
6620 unsigned OPA2UG
: 1;
6623 unsigned OPA2EN
: 1;
6628 unsigned OPA2ORM
: 2;
6639 extern __at(0x0515) volatile __OPA2CONbits_t OPA2CONbits
;
6641 #define _OPA2CON_ORM0 0x01
6642 #define _OPA2CON_OPA2ORM0 0x01
6643 #define _OPA2CON_ORM1 0x02
6644 #define _OPA2CON_OPA2ORM1 0x02
6645 #define _OPA2CON_ORPOL 0x04
6646 #define _OPA2CON_OPA2ORPOL 0x04
6647 #define _OPA2CON_UG 0x10
6648 #define _OPA2CON_OPA2UG 0x10
6649 #define _OPA2CON_EN 0x80
6650 #define _OPA2CON_OPA2EN 0x80
6652 //==============================================================================
6654 extern __at(0x0516) __sfr OPA2ORS
;
6656 //==============================================================================
6659 extern __at(0x0590) __sfr DACLD
;
6663 unsigned DAC1LD
: 1;
6664 unsigned DAC2LD
: 1;
6673 extern __at(0x0590) volatile __DACLDbits_t DACLDbits
;
6675 #define _DAC1LD 0x01
6676 #define _DAC2LD 0x02
6678 //==============================================================================
6681 //==============================================================================
6684 extern __at(0x0591) __sfr DAC1CON0
;
6702 unsigned DACNSS0
: 1;
6704 unsigned DACPSS0
: 1;
6705 unsigned DACPSS1
: 1;
6714 unsigned DAC1NSS0
: 1;
6716 unsigned DAC1PSS0
: 1;
6717 unsigned DAC1PSS1
: 1;
6719 unsigned DACOE1
: 1;
6720 unsigned DAC1FM
: 1;
6721 unsigned DAC1EN
: 1;
6743 unsigned DAC1OE1
: 1;
6758 unsigned DACPSS
: 2;
6765 unsigned DAC1PSS
: 2;
6770 extern __at(0x0591) volatile __DAC1CON0bits_t DAC1CON0bits
;
6772 #define _DAC1CON0_NSS0 0x01
6773 #define _DAC1CON0_DACNSS0 0x01
6774 #define _DAC1CON0_DAC1NSS0 0x01
6775 #define _DAC1CON0_PSS0 0x04
6776 #define _DAC1CON0_DACPSS0 0x04
6777 #define _DAC1CON0_DAC1PSS0 0x04
6778 #define _DAC1CON0_PSS1 0x08
6779 #define _DAC1CON0_DACPSS1 0x08
6780 #define _DAC1CON0_DAC1PSS1 0x08
6781 #define _DAC1CON0_OE1 0x20
6782 #define _DAC1CON0_OE 0x20
6783 #define _DAC1CON0_DACOE1 0x20
6784 #define _DAC1CON0_DACOE 0x20
6785 #define _DAC1CON0_DAC1OE1 0x20
6786 #define _DAC1CON0_FM 0x40
6787 #define _DAC1CON0_DACFM 0x40
6788 #define _DAC1CON0_DAC1FM 0x40
6789 #define _DAC1CON0_EN 0x80
6790 #define _DAC1CON0_DACEN 0x80
6791 #define _DAC1CON0_DAC1EN 0x80
6793 //==============================================================================
6796 //==============================================================================
6799 extern __at(0x0592) __sfr DAC1CON1
;
6817 unsigned DAC1REF0
: 1;
6818 unsigned DAC1REF1
: 1;
6819 unsigned DAC1REF2
: 1;
6820 unsigned DAC1REF3
: 1;
6821 unsigned DAC1REF4
: 1;
6822 unsigned DAC1REF5
: 1;
6823 unsigned DAC1REF6
: 1;
6824 unsigned DAC1REF7
: 1;
6841 unsigned DAC1R0
: 1;
6842 unsigned DAC1R1
: 1;
6843 unsigned DAC1R2
: 1;
6844 unsigned DAC1R3
: 1;
6845 unsigned DAC1R4
: 1;
6846 unsigned DAC1R5
: 1;
6847 unsigned DAC1R6
: 1;
6848 unsigned DAC1R7
: 1;
6852 extern __at(0x0592) volatile __DAC1CON1bits_t DAC1CON1bits
;
6855 #define _DAC1REF0 0x01
6857 #define _DAC1R0 0x01
6859 #define _DAC1REF1 0x02
6861 #define _DAC1R1 0x02
6863 #define _DAC1REF2 0x04
6865 #define _DAC1R2 0x04
6867 #define _DAC1REF3 0x08
6869 #define _DAC1R3 0x08
6871 #define _DAC1REF4 0x10
6873 #define _DAC1R4 0x10
6875 #define _DAC1REF5 0x20
6877 #define _DAC1R5 0x20
6879 #define _DAC1REF6 0x40
6881 #define _DAC1R6 0x40
6883 #define _DAC1REF7 0x80
6885 #define _DAC1R7 0x80
6887 //==============================================================================
6889 extern __at(0x0592) __sfr DAC1REF
;
6891 //==============================================================================
6894 extern __at(0x0592) __sfr DAC1REFL
;
6912 unsigned DAC1REF0
: 1;
6913 unsigned DAC1REF1
: 1;
6914 unsigned DAC1REF2
: 1;
6915 unsigned DAC1REF3
: 1;
6916 unsigned DAC1REF4
: 1;
6917 unsigned DAC1REF5
: 1;
6918 unsigned DAC1REF6
: 1;
6919 unsigned DAC1REF7
: 1;
6936 unsigned DAC1R0
: 1;
6937 unsigned DAC1R1
: 1;
6938 unsigned DAC1R2
: 1;
6939 unsigned DAC1R3
: 1;
6940 unsigned DAC1R4
: 1;
6941 unsigned DAC1R5
: 1;
6942 unsigned DAC1R6
: 1;
6943 unsigned DAC1R7
: 1;
6947 extern __at(0x0592) volatile __DAC1REFLbits_t DAC1REFLbits
;
6949 #define _DAC1REFL_REF0 0x01
6950 #define _DAC1REFL_DAC1REF0 0x01
6951 #define _DAC1REFL_R0 0x01
6952 #define _DAC1REFL_DAC1R0 0x01
6953 #define _DAC1REFL_REF1 0x02
6954 #define _DAC1REFL_DAC1REF1 0x02
6955 #define _DAC1REFL_R1 0x02
6956 #define _DAC1REFL_DAC1R1 0x02
6957 #define _DAC1REFL_REF2 0x04
6958 #define _DAC1REFL_DAC1REF2 0x04
6959 #define _DAC1REFL_R2 0x04
6960 #define _DAC1REFL_DAC1R2 0x04
6961 #define _DAC1REFL_REF3 0x08
6962 #define _DAC1REFL_DAC1REF3 0x08
6963 #define _DAC1REFL_R3 0x08
6964 #define _DAC1REFL_DAC1R3 0x08
6965 #define _DAC1REFL_REF4 0x10
6966 #define _DAC1REFL_DAC1REF4 0x10
6967 #define _DAC1REFL_R4 0x10
6968 #define _DAC1REFL_DAC1R4 0x10
6969 #define _DAC1REFL_REF5 0x20
6970 #define _DAC1REFL_DAC1REF5 0x20
6971 #define _DAC1REFL_R5 0x20
6972 #define _DAC1REFL_DAC1R5 0x20
6973 #define _DAC1REFL_REF6 0x40
6974 #define _DAC1REFL_DAC1REF6 0x40
6975 #define _DAC1REFL_R6 0x40
6976 #define _DAC1REFL_DAC1R6 0x40
6977 #define _DAC1REFL_REF7 0x80
6978 #define _DAC1REFL_DAC1REF7 0x80
6979 #define _DAC1REFL_R7 0x80
6980 #define _DAC1REFL_DAC1R7 0x80
6982 //==============================================================================
6985 //==============================================================================
6988 extern __at(0x0593) __sfr DAC1CON2
;
7006 unsigned DAC1REF8
: 1;
7007 unsigned DAC1REF9
: 1;
7008 unsigned DAC1REF10
: 1;
7009 unsigned DAC1REF11
: 1;
7010 unsigned DAC1REF12
: 1;
7011 unsigned DAC1REF13
: 1;
7012 unsigned DAC1REF14
: 1;
7013 unsigned DAC1REF15
: 1;
7030 unsigned DAC1R8
: 1;
7031 unsigned DAC1R9
: 1;
7032 unsigned DAC1R10
: 1;
7033 unsigned DAC1R11
: 1;
7034 unsigned DAC1R12
: 1;
7035 unsigned DAC1R13
: 1;
7036 unsigned DAC1R14
: 1;
7037 unsigned DAC1R15
: 1;
7041 extern __at(0x0593) volatile __DAC1CON2bits_t DAC1CON2bits
;
7044 #define _DAC1REF8 0x01
7046 #define _DAC1R8 0x01
7048 #define _DAC1REF9 0x02
7050 #define _DAC1R9 0x02
7052 #define _DAC1REF10 0x04
7054 #define _DAC1R10 0x04
7056 #define _DAC1REF11 0x08
7058 #define _DAC1R11 0x08
7060 #define _DAC1REF12 0x10
7062 #define _DAC1R12 0x10
7064 #define _DAC1REF13 0x20
7066 #define _DAC1R13 0x20
7068 #define _DAC1REF14 0x40
7070 #define _DAC1R14 0x40
7072 #define _DAC1REF15 0x80
7074 #define _DAC1R15 0x80
7076 //==============================================================================
7079 //==============================================================================
7082 extern __at(0x0593) __sfr DAC1REFH
;
7100 unsigned DAC1REF8
: 1;
7101 unsigned DAC1REF9
: 1;
7102 unsigned DAC1REF10
: 1;
7103 unsigned DAC1REF11
: 1;
7104 unsigned DAC1REF12
: 1;
7105 unsigned DAC1REF13
: 1;
7106 unsigned DAC1REF14
: 1;
7107 unsigned DAC1REF15
: 1;
7124 unsigned DAC1R8
: 1;
7125 unsigned DAC1R9
: 1;
7126 unsigned DAC1R10
: 1;
7127 unsigned DAC1R11
: 1;
7128 unsigned DAC1R12
: 1;
7129 unsigned DAC1R13
: 1;
7130 unsigned DAC1R14
: 1;
7131 unsigned DAC1R15
: 1;
7135 extern __at(0x0593) volatile __DAC1REFHbits_t DAC1REFHbits
;
7137 #define _DAC1REFH_REF8 0x01
7138 #define _DAC1REFH_DAC1REF8 0x01
7139 #define _DAC1REFH_R8 0x01
7140 #define _DAC1REFH_DAC1R8 0x01
7141 #define _DAC1REFH_REF9 0x02
7142 #define _DAC1REFH_DAC1REF9 0x02
7143 #define _DAC1REFH_R9 0x02
7144 #define _DAC1REFH_DAC1R9 0x02
7145 #define _DAC1REFH_REF10 0x04
7146 #define _DAC1REFH_DAC1REF10 0x04
7147 #define _DAC1REFH_R10 0x04
7148 #define _DAC1REFH_DAC1R10 0x04
7149 #define _DAC1REFH_REF11 0x08
7150 #define _DAC1REFH_DAC1REF11 0x08
7151 #define _DAC1REFH_R11 0x08
7152 #define _DAC1REFH_DAC1R11 0x08
7153 #define _DAC1REFH_REF12 0x10
7154 #define _DAC1REFH_DAC1REF12 0x10
7155 #define _DAC1REFH_R12 0x10
7156 #define _DAC1REFH_DAC1R12 0x10
7157 #define _DAC1REFH_REF13 0x20
7158 #define _DAC1REFH_DAC1REF13 0x20
7159 #define _DAC1REFH_R13 0x20
7160 #define _DAC1REFH_DAC1R13 0x20
7161 #define _DAC1REFH_REF14 0x40
7162 #define _DAC1REFH_DAC1REF14 0x40
7163 #define _DAC1REFH_R14 0x40
7164 #define _DAC1REFH_DAC1R14 0x40
7165 #define _DAC1REFH_REF15 0x80
7166 #define _DAC1REFH_DAC1REF15 0x80
7167 #define _DAC1REFH_R15 0x80
7168 #define _DAC1REFH_DAC1R15 0x80
7170 //==============================================================================
7173 //==============================================================================
7176 extern __at(0x0594) __sfr DAC2CON0
;
7194 unsigned DACNSS0
: 1;
7196 unsigned DACPSS0
: 1;
7197 unsigned DACPSS1
: 1;
7206 unsigned DAC2NSS0
: 1;
7208 unsigned DAC2PSS0
: 1;
7209 unsigned DAC2PSS1
: 1;
7211 unsigned DACOE1
: 1;
7212 unsigned DAC2FM
: 1;
7213 unsigned DAC2EN
: 1;
7235 unsigned DAC2OE1
: 1;
7243 unsigned DAC2PSS
: 2;
7250 unsigned DACPSS
: 2;
7262 extern __at(0x0594) volatile __DAC2CON0bits_t DAC2CON0bits
;
7264 #define _DAC2CON0_NSS0 0x01
7265 #define _DAC2CON0_DACNSS0 0x01
7266 #define _DAC2CON0_DAC2NSS0 0x01
7267 #define _DAC2CON0_PSS0 0x04
7268 #define _DAC2CON0_DACPSS0 0x04
7269 #define _DAC2CON0_DAC2PSS0 0x04
7270 #define _DAC2CON0_PSS1 0x08
7271 #define _DAC2CON0_DACPSS1 0x08
7272 #define _DAC2CON0_DAC2PSS1 0x08
7273 #define _DAC2CON0_OE1 0x20
7274 #define _DAC2CON0_OE 0x20
7275 #define _DAC2CON0_DACOE1 0x20
7276 #define _DAC2CON0_DACOE 0x20
7277 #define _DAC2CON0_DAC2OE1 0x20
7278 #define _DAC2CON0_FM 0x40
7279 #define _DAC2CON0_DACFM 0x40
7280 #define _DAC2CON0_DAC2FM 0x40
7281 #define _DAC2CON0_EN 0x80
7282 #define _DAC2CON0_DACEN 0x80
7283 #define _DAC2CON0_DAC2EN 0x80
7285 //==============================================================================
7288 //==============================================================================
7291 extern __at(0x0595) __sfr DAC2CON1
;
7309 unsigned DAC2REF0
: 1;
7310 unsigned DAC2REF1
: 1;
7311 unsigned DAC2REF2
: 1;
7312 unsigned DAC2REF3
: 1;
7313 unsigned DAC2REF4
: 1;
7314 unsigned DAC2REF5
: 1;
7315 unsigned DAC2REF6
: 1;
7316 unsigned DAC2REF7
: 1;
7333 unsigned DAC2R0
: 1;
7334 unsigned DAC2R1
: 1;
7335 unsigned DAC2R2
: 1;
7336 unsigned DAC2R3
: 1;
7337 unsigned DAC2R4
: 1;
7338 unsigned DAC2R5
: 1;
7339 unsigned DAC2R6
: 1;
7340 unsigned DAC2R7
: 1;
7344 extern __at(0x0595) volatile __DAC2CON1bits_t DAC2CON1bits
;
7346 #define _DAC2CON1_REF0 0x01
7347 #define _DAC2CON1_DAC2REF0 0x01
7348 #define _DAC2CON1_R0 0x01
7349 #define _DAC2CON1_DAC2R0 0x01
7350 #define _DAC2CON1_REF1 0x02
7351 #define _DAC2CON1_DAC2REF1 0x02
7352 #define _DAC2CON1_R1 0x02
7353 #define _DAC2CON1_DAC2R1 0x02
7354 #define _DAC2CON1_REF2 0x04
7355 #define _DAC2CON1_DAC2REF2 0x04
7356 #define _DAC2CON1_R2 0x04
7357 #define _DAC2CON1_DAC2R2 0x04
7358 #define _DAC2CON1_REF3 0x08
7359 #define _DAC2CON1_DAC2REF3 0x08
7360 #define _DAC2CON1_R3 0x08
7361 #define _DAC2CON1_DAC2R3 0x08
7362 #define _DAC2CON1_REF4 0x10
7363 #define _DAC2CON1_DAC2REF4 0x10
7364 #define _DAC2CON1_R4 0x10
7365 #define _DAC2CON1_DAC2R4 0x10
7366 #define _DAC2CON1_REF5 0x20
7367 #define _DAC2CON1_DAC2REF5 0x20
7368 #define _DAC2CON1_R5 0x20
7369 #define _DAC2CON1_DAC2R5 0x20
7370 #define _DAC2CON1_REF6 0x40
7371 #define _DAC2CON1_DAC2REF6 0x40
7372 #define _DAC2CON1_R6 0x40
7373 #define _DAC2CON1_DAC2R6 0x40
7374 #define _DAC2CON1_REF7 0x80
7375 #define _DAC2CON1_DAC2REF7 0x80
7376 #define _DAC2CON1_R7 0x80
7377 #define _DAC2CON1_DAC2R7 0x80
7379 //==============================================================================
7381 extern __at(0x0595) __sfr DAC2REF
;
7383 //==============================================================================
7386 extern __at(0x0595) __sfr DAC2REFL
;
7404 unsigned DAC2REF0
: 1;
7405 unsigned DAC2REF1
: 1;
7406 unsigned DAC2REF2
: 1;
7407 unsigned DAC2REF3
: 1;
7408 unsigned DAC2REF4
: 1;
7409 unsigned DAC2REF5
: 1;
7410 unsigned DAC2REF6
: 1;
7411 unsigned DAC2REF7
: 1;
7428 unsigned DAC2R0
: 1;
7429 unsigned DAC2R1
: 1;
7430 unsigned DAC2R2
: 1;
7431 unsigned DAC2R3
: 1;
7432 unsigned DAC2R4
: 1;
7433 unsigned DAC2R5
: 1;
7434 unsigned DAC2R6
: 1;
7435 unsigned DAC2R7
: 1;
7439 extern __at(0x0595) volatile __DAC2REFLbits_t DAC2REFLbits
;
7441 #define _DAC2REFL_REF0 0x01
7442 #define _DAC2REFL_DAC2REF0 0x01
7443 #define _DAC2REFL_R0 0x01
7444 #define _DAC2REFL_DAC2R0 0x01
7445 #define _DAC2REFL_REF1 0x02
7446 #define _DAC2REFL_DAC2REF1 0x02
7447 #define _DAC2REFL_R1 0x02
7448 #define _DAC2REFL_DAC2R1 0x02
7449 #define _DAC2REFL_REF2 0x04
7450 #define _DAC2REFL_DAC2REF2 0x04
7451 #define _DAC2REFL_R2 0x04
7452 #define _DAC2REFL_DAC2R2 0x04
7453 #define _DAC2REFL_REF3 0x08
7454 #define _DAC2REFL_DAC2REF3 0x08
7455 #define _DAC2REFL_R3 0x08
7456 #define _DAC2REFL_DAC2R3 0x08
7457 #define _DAC2REFL_REF4 0x10
7458 #define _DAC2REFL_DAC2REF4 0x10
7459 #define _DAC2REFL_R4 0x10
7460 #define _DAC2REFL_DAC2R4 0x10
7461 #define _DAC2REFL_REF5 0x20
7462 #define _DAC2REFL_DAC2REF5 0x20
7463 #define _DAC2REFL_R5 0x20
7464 #define _DAC2REFL_DAC2R5 0x20
7465 #define _DAC2REFL_REF6 0x40
7466 #define _DAC2REFL_DAC2REF6 0x40
7467 #define _DAC2REFL_R6 0x40
7468 #define _DAC2REFL_DAC2R6 0x40
7469 #define _DAC2REFL_REF7 0x80
7470 #define _DAC2REFL_DAC2REF7 0x80
7471 #define _DAC2REFL_R7 0x80
7472 #define _DAC2REFL_DAC2R7 0x80
7474 //==============================================================================
7477 //==============================================================================
7480 extern __at(0x0596) __sfr DAC2CON2
;
7498 unsigned DAC2REF8
: 1;
7499 unsigned DAC2REF9
: 1;
7500 unsigned DAC2REF10
: 1;
7501 unsigned DAC2REF11
: 1;
7502 unsigned DAC2REF12
: 1;
7503 unsigned DAC2REF13
: 1;
7504 unsigned DAC2REF14
: 1;
7505 unsigned DAC2REF15
: 1;
7522 unsigned DAC2R8
: 1;
7523 unsigned DAC2R9
: 1;
7524 unsigned DAC2R10
: 1;
7525 unsigned DAC2R11
: 1;
7526 unsigned DAC2R12
: 1;
7527 unsigned DAC2R13
: 1;
7528 unsigned DAC2R14
: 1;
7529 unsigned DAC2R15
: 1;
7533 extern __at(0x0596) volatile __DAC2CON2bits_t DAC2CON2bits
;
7535 #define _DAC2CON2_REF8 0x01
7536 #define _DAC2CON2_DAC2REF8 0x01
7537 #define _DAC2CON2_R8 0x01
7538 #define _DAC2CON2_DAC2R8 0x01
7539 #define _DAC2CON2_REF9 0x02
7540 #define _DAC2CON2_DAC2REF9 0x02
7541 #define _DAC2CON2_R9 0x02
7542 #define _DAC2CON2_DAC2R9 0x02
7543 #define _DAC2CON2_REF10 0x04
7544 #define _DAC2CON2_DAC2REF10 0x04
7545 #define _DAC2CON2_R10 0x04
7546 #define _DAC2CON2_DAC2R10 0x04
7547 #define _DAC2CON2_REF11 0x08
7548 #define _DAC2CON2_DAC2REF11 0x08
7549 #define _DAC2CON2_R11 0x08
7550 #define _DAC2CON2_DAC2R11 0x08
7551 #define _DAC2CON2_REF12 0x10
7552 #define _DAC2CON2_DAC2REF12 0x10
7553 #define _DAC2CON2_R12 0x10
7554 #define _DAC2CON2_DAC2R12 0x10
7555 #define _DAC2CON2_REF13 0x20
7556 #define _DAC2CON2_DAC2REF13 0x20
7557 #define _DAC2CON2_R13 0x20
7558 #define _DAC2CON2_DAC2R13 0x20
7559 #define _DAC2CON2_REF14 0x40
7560 #define _DAC2CON2_DAC2REF14 0x40
7561 #define _DAC2CON2_R14 0x40
7562 #define _DAC2CON2_DAC2R14 0x40
7563 #define _DAC2CON2_REF15 0x80
7564 #define _DAC2CON2_DAC2REF15 0x80
7565 #define _DAC2CON2_R15 0x80
7566 #define _DAC2CON2_DAC2R15 0x80
7568 //==============================================================================
7571 //==============================================================================
7574 extern __at(0x0596) __sfr DAC2REFH
;
7592 unsigned DAC2REF8
: 1;
7593 unsigned DAC2REF9
: 1;
7594 unsigned DAC2REF10
: 1;
7595 unsigned DAC2REF11
: 1;
7596 unsigned DAC2REF12
: 1;
7597 unsigned DAC2REF13
: 1;
7598 unsigned DAC2REF14
: 1;
7599 unsigned DAC2REF15
: 1;
7616 unsigned DAC2R8
: 1;
7617 unsigned DAC2R9
: 1;
7618 unsigned DAC2R10
: 1;
7619 unsigned DAC2R11
: 1;
7620 unsigned DAC2R12
: 1;
7621 unsigned DAC2R13
: 1;
7622 unsigned DAC2R14
: 1;
7623 unsigned DAC2R15
: 1;
7627 extern __at(0x0596) volatile __DAC2REFHbits_t DAC2REFHbits
;
7629 #define _DAC2REFH_REF8 0x01
7630 #define _DAC2REFH_DAC2REF8 0x01
7631 #define _DAC2REFH_R8 0x01
7632 #define _DAC2REFH_DAC2R8 0x01
7633 #define _DAC2REFH_REF9 0x02
7634 #define _DAC2REFH_DAC2REF9 0x02
7635 #define _DAC2REFH_R9 0x02
7636 #define _DAC2REFH_DAC2R9 0x02
7637 #define _DAC2REFH_REF10 0x04
7638 #define _DAC2REFH_DAC2REF10 0x04
7639 #define _DAC2REFH_R10 0x04
7640 #define _DAC2REFH_DAC2R10 0x04
7641 #define _DAC2REFH_REF11 0x08
7642 #define _DAC2REFH_DAC2REF11 0x08
7643 #define _DAC2REFH_R11 0x08
7644 #define _DAC2REFH_DAC2R11 0x08
7645 #define _DAC2REFH_REF12 0x10
7646 #define _DAC2REFH_DAC2REF12 0x10
7647 #define _DAC2REFH_R12 0x10
7648 #define _DAC2REFH_DAC2R12 0x10
7649 #define _DAC2REFH_REF13 0x20
7650 #define _DAC2REFH_DAC2REF13 0x20
7651 #define _DAC2REFH_R13 0x20
7652 #define _DAC2REFH_DAC2R13 0x20
7653 #define _DAC2REFH_REF14 0x40
7654 #define _DAC2REFH_DAC2REF14 0x40
7655 #define _DAC2REFH_R14 0x40
7656 #define _DAC2REFH_DAC2R14 0x40
7657 #define _DAC2REFH_REF15 0x80
7658 #define _DAC2REFH_DAC2REF15 0x80
7659 #define _DAC2REFH_R15 0x80
7660 #define _DAC2REFH_DAC2R15 0x80
7662 //==============================================================================
7665 //==============================================================================
7668 extern __at(0x0597) __sfr DAC3CON0
;
7686 unsigned DACNSS
: 1;
7688 unsigned DACPSS0
: 1;
7689 unsigned DACPSS1
: 1;
7691 unsigned DACOE1
: 1;
7698 unsigned DAC3NSS
: 1;
7700 unsigned DAC3PSS0
: 1;
7701 unsigned DAC3PSS1
: 1;
7703 unsigned DAC3OE1
: 1;
7705 unsigned DAC3EN
: 1;
7718 unsigned DACPSS
: 2;
7725 unsigned DAC3PSS
: 2;
7730 extern __at(0x0597) volatile __DAC3CON0bits_t DAC3CON0bits
;
7732 #define _DAC3CON0_NSS 0x01
7733 #define _DAC3CON0_DACNSS 0x01
7734 #define _DAC3CON0_DAC3NSS 0x01
7735 #define _DAC3CON0_PSS0 0x04
7736 #define _DAC3CON0_DACPSS0 0x04
7737 #define _DAC3CON0_DAC3PSS0 0x04
7738 #define _DAC3CON0_PSS1 0x08
7739 #define _DAC3CON0_DACPSS1 0x08
7740 #define _DAC3CON0_DAC3PSS1 0x08
7741 #define _DAC3CON0_OE1 0x20
7742 #define _DAC3CON0_DACOE1 0x20
7743 #define _DAC3CON0_DAC3OE1 0x20
7744 #define _DAC3CON0_EN 0x80
7745 #define _DAC3CON0_DACEN 0x80
7746 #define _DAC3CON0_DAC3EN 0x80
7748 //==============================================================================
7751 //==============================================================================
7754 extern __at(0x0598) __sfr DAC3CON1
;
7777 unsigned DAC3REF5
: 1;
7784 unsigned DAC3R0
: 1;
7785 unsigned DAC3R1
: 1;
7786 unsigned DAC3R2
: 1;
7787 unsigned DAC3R3
: 1;
7788 unsigned DAC3R4
: 1;
7808 unsigned DAC3REF0
: 1;
7809 unsigned DAC3REF1
: 1;
7810 unsigned DAC3REF2
: 1;
7811 unsigned DAC3REF3
: 1;
7812 unsigned DAC3REF4
: 1;
7838 unsigned DAC3REF
: 6;
7849 extern __at(0x0598) volatile __DAC3CON1bits_t DAC3CON1bits
;
7851 #define _DAC3CON1_DACR0 0x01
7852 #define _DAC3CON1_R0 0x01
7853 #define _DAC3CON1_DAC3R0 0x01
7854 #define _DAC3CON1_REF0 0x01
7855 #define _DAC3CON1_DAC3REF0 0x01
7856 #define _DAC3CON1_DACR1 0x02
7857 #define _DAC3CON1_R1 0x02
7858 #define _DAC3CON1_DAC3R1 0x02
7859 #define _DAC3CON1_REF1 0x02
7860 #define _DAC3CON1_DAC3REF1 0x02
7861 #define _DAC3CON1_DACR2 0x04
7862 #define _DAC3CON1_R2 0x04
7863 #define _DAC3CON1_DAC3R2 0x04
7864 #define _DAC3CON1_REF2 0x04
7865 #define _DAC3CON1_DAC3REF2 0x04
7866 #define _DAC3CON1_DACR3 0x08
7867 #define _DAC3CON1_R3 0x08
7868 #define _DAC3CON1_DAC3R3 0x08
7869 #define _DAC3CON1_REF3 0x08
7870 #define _DAC3CON1_DAC3REF3 0x08
7871 #define _DAC3CON1_DACR4 0x10
7872 #define _DAC3CON1_R4 0x10
7873 #define _DAC3CON1_DAC3R4 0x10
7874 #define _DAC3CON1_REF4 0x10
7875 #define _DAC3CON1_DAC3REF4 0x10
7876 #define _DAC3CON1_REF5 0x20
7877 #define _DAC3CON1_DAC3REF5 0x20
7879 //==============================================================================
7882 //==============================================================================
7885 extern __at(0x0598) __sfr DAC3REF
;
7908 unsigned DAC3REF5
: 1;
7915 unsigned DAC3R0
: 1;
7916 unsigned DAC3R1
: 1;
7917 unsigned DAC3R2
: 1;
7918 unsigned DAC3R3
: 1;
7919 unsigned DAC3R4
: 1;
7939 unsigned DAC3REF0
: 1;
7940 unsigned DAC3REF1
: 1;
7941 unsigned DAC3REF2
: 1;
7942 unsigned DAC3REF3
: 1;
7943 unsigned DAC3REF4
: 1;
7957 unsigned DAC3REF
: 6;
7980 extern __at(0x0598) volatile __DAC3REFbits_t DAC3REFbits
;
7982 #define _DAC3REF_DACR0 0x01
7983 #define _DAC3REF_R0 0x01
7984 #define _DAC3REF_DAC3R0 0x01
7985 #define _DAC3REF_REF0 0x01
7986 #define _DAC3REF_DAC3REF0 0x01
7987 #define _DAC3REF_DACR1 0x02
7988 #define _DAC3REF_R1 0x02
7989 #define _DAC3REF_DAC3R1 0x02
7990 #define _DAC3REF_REF1 0x02
7991 #define _DAC3REF_DAC3REF1 0x02
7992 #define _DAC3REF_DACR2 0x04
7993 #define _DAC3REF_R2 0x04
7994 #define _DAC3REF_DAC3R2 0x04
7995 #define _DAC3REF_REF2 0x04
7996 #define _DAC3REF_DAC3REF2 0x04
7997 #define _DAC3REF_DACR3 0x08
7998 #define _DAC3REF_R3 0x08
7999 #define _DAC3REF_DAC3R3 0x08
8000 #define _DAC3REF_REF3 0x08
8001 #define _DAC3REF_DAC3REF3 0x08
8002 #define _DAC3REF_DACR4 0x10
8003 #define _DAC3REF_R4 0x10
8004 #define _DAC3REF_DAC3R4 0x10
8005 #define _DAC3REF_REF4 0x10
8006 #define _DAC3REF_DAC3REF4 0x10
8007 #define _DAC3REF_REF5 0x20
8008 #define _DAC3REF_DAC3REF5 0x20
8010 //==============================================================================
8013 //==============================================================================
8016 extern __at(0x0599) __sfr DAC4CON0
;
8034 unsigned DACNSS
: 1;
8036 unsigned DACPSS0
: 1;
8037 unsigned DACPSS1
: 1;
8039 unsigned DACOE1
: 1;
8046 unsigned DAC4NSS
: 1;
8048 unsigned DAC4PSS0
: 1;
8049 unsigned DAC4PSS1
: 1;
8051 unsigned DAC4OE1
: 1;
8053 unsigned DAC4EN
: 1;
8059 unsigned DAC4PSS
: 2;
8073 unsigned DACPSS
: 2;
8078 extern __at(0x0599) volatile __DAC4CON0bits_t DAC4CON0bits
;
8080 #define _DAC4CON0_NSS 0x01
8081 #define _DAC4CON0_DACNSS 0x01
8082 #define _DAC4CON0_DAC4NSS 0x01
8083 #define _DAC4CON0_PSS0 0x04
8084 #define _DAC4CON0_DACPSS0 0x04
8085 #define _DAC4CON0_DAC4PSS0 0x04
8086 #define _DAC4CON0_PSS1 0x08
8087 #define _DAC4CON0_DACPSS1 0x08
8088 #define _DAC4CON0_DAC4PSS1 0x08
8089 #define _DAC4CON0_OE1 0x20
8090 #define _DAC4CON0_DACOE1 0x20
8091 #define _DAC4CON0_DAC4OE1 0x20
8092 #define _DAC4CON0_EN 0x80
8093 #define _DAC4CON0_DACEN 0x80
8094 #define _DAC4CON0_DAC4EN 0x80
8096 //==============================================================================
8099 //==============================================================================
8102 extern __at(0x059A) __sfr DAC4CON1
;
8125 unsigned DAC4REF5
: 1;
8132 unsigned DAC4R0
: 1;
8133 unsigned DAC4R1
: 1;
8134 unsigned DAC4R2
: 1;
8135 unsigned DAC4R3
: 1;
8136 unsigned DAC4R4
: 1;
8156 unsigned DAC4REF0
: 1;
8157 unsigned DAC4REF1
: 1;
8158 unsigned DAC4REF2
: 1;
8159 unsigned DAC4REF3
: 1;
8160 unsigned DAC4REF4
: 1;
8174 unsigned DAC4REF
: 6;
8197 extern __at(0x059A) volatile __DAC4CON1bits_t DAC4CON1bits
;
8199 #define _DAC4CON1_DACR0 0x01
8200 #define _DAC4CON1_R0 0x01
8201 #define _DAC4CON1_DAC4R0 0x01
8202 #define _DAC4CON1_REF0 0x01
8203 #define _DAC4CON1_DAC4REF0 0x01
8204 #define _DAC4CON1_DACR1 0x02
8205 #define _DAC4CON1_R1 0x02
8206 #define _DAC4CON1_DAC4R1 0x02
8207 #define _DAC4CON1_REF1 0x02
8208 #define _DAC4CON1_DAC4REF1 0x02
8209 #define _DAC4CON1_DACR2 0x04
8210 #define _DAC4CON1_R2 0x04
8211 #define _DAC4CON1_DAC4R2 0x04
8212 #define _DAC4CON1_REF2 0x04
8213 #define _DAC4CON1_DAC4REF2 0x04
8214 #define _DAC4CON1_DACR3 0x08
8215 #define _DAC4CON1_R3 0x08
8216 #define _DAC4CON1_DAC4R3 0x08
8217 #define _DAC4CON1_REF3 0x08
8218 #define _DAC4CON1_DAC4REF3 0x08
8219 #define _DAC4CON1_DACR4 0x10
8220 #define _DAC4CON1_R4 0x10
8221 #define _DAC4CON1_DAC4R4 0x10
8222 #define _DAC4CON1_REF4 0x10
8223 #define _DAC4CON1_DAC4REF4 0x10
8224 #define _DAC4CON1_REF5 0x20
8225 #define _DAC4CON1_DAC4REF5 0x20
8227 //==============================================================================
8230 //==============================================================================
8233 extern __at(0x059A) __sfr DAC4REF
;
8256 unsigned DAC4REF5
: 1;
8263 unsigned DAC4R0
: 1;
8264 unsigned DAC4R1
: 1;
8265 unsigned DAC4R2
: 1;
8266 unsigned DAC4R3
: 1;
8267 unsigned DAC4R4
: 1;
8287 unsigned DAC4REF0
: 1;
8288 unsigned DAC4REF1
: 1;
8289 unsigned DAC4REF2
: 1;
8290 unsigned DAC4REF3
: 1;
8291 unsigned DAC4REF4
: 1;
8311 unsigned DAC4REF
: 6;
8328 extern __at(0x059A) volatile __DAC4REFbits_t DAC4REFbits
;
8330 #define _DAC4REF_DACR0 0x01
8331 #define _DAC4REF_R0 0x01
8332 #define _DAC4REF_DAC4R0 0x01
8333 #define _DAC4REF_REF0 0x01
8334 #define _DAC4REF_DAC4REF0 0x01
8335 #define _DAC4REF_DACR1 0x02
8336 #define _DAC4REF_R1 0x02
8337 #define _DAC4REF_DAC4R1 0x02
8338 #define _DAC4REF_REF1 0x02
8339 #define _DAC4REF_DAC4REF1 0x02
8340 #define _DAC4REF_DACR2 0x04
8341 #define _DAC4REF_R2 0x04
8342 #define _DAC4REF_DAC4R2 0x04
8343 #define _DAC4REF_REF2 0x04
8344 #define _DAC4REF_DAC4REF2 0x04
8345 #define _DAC4REF_DACR3 0x08
8346 #define _DAC4REF_R3 0x08
8347 #define _DAC4REF_DAC4R3 0x08
8348 #define _DAC4REF_REF3 0x08
8349 #define _DAC4REF_DAC4REF3 0x08
8350 #define _DAC4REF_DACR4 0x10
8351 #define _DAC4REF_R4 0x10
8352 #define _DAC4REF_DAC4R4 0x10
8353 #define _DAC4REF_REF4 0x10
8354 #define _DAC4REF_DAC4REF4 0x10
8355 #define _DAC4REF_REF5 0x20
8356 #define _DAC4REF_DAC4REF5 0x20
8358 //==============================================================================
8361 //==============================================================================
8364 extern __at(0x0617) __sfr PWM3DCL
;
8388 unsigned PWM3DC0
: 1;
8389 unsigned PWM3DC1
: 1;
8400 unsigned PWMPW0
: 1;
8401 unsigned PWMPW1
: 1;
8419 unsigned PWM3DC
: 2;
8423 extern __at(0x0617) volatile __PWM3DCLbits_t PWM3DCLbits
;
8426 #define _PWM3DC0 0x40
8427 #define _PWMPW0 0x40
8429 #define _PWM3DC1 0x80
8430 #define _PWMPW1 0x80
8432 //==============================================================================
8435 //==============================================================================
8438 extern __at(0x0618) __sfr PWM3DCH
;
8456 unsigned PWM3DC2
: 1;
8457 unsigned PWM3DC3
: 1;
8458 unsigned PWM3DC4
: 1;
8459 unsigned PWM3DC5
: 1;
8460 unsigned PWM3DC6
: 1;
8461 unsigned PWM3DC7
: 1;
8462 unsigned PWM3DC8
: 1;
8463 unsigned PWM3DC9
: 1;
8468 unsigned PWMPW2
: 1;
8469 unsigned PWMPW3
: 1;
8470 unsigned PWMPW4
: 1;
8471 unsigned PWMPW5
: 1;
8472 unsigned PWMPW6
: 1;
8473 unsigned PWMPW7
: 1;
8474 unsigned PWMPW8
: 1;
8475 unsigned PWMPW9
: 1;
8479 extern __at(0x0618) volatile __PWM3DCHbits_t PWM3DCHbits
;
8482 #define _PWM3DC2 0x01
8483 #define _PWMPW2 0x01
8485 #define _PWM3DC3 0x02
8486 #define _PWMPW3 0x02
8488 #define _PWM3DC4 0x04
8489 #define _PWMPW4 0x04
8491 #define _PWM3DC5 0x08
8492 #define _PWMPW5 0x08
8494 #define _PWM3DC6 0x10
8495 #define _PWMPW6 0x10
8497 #define _PWM3DC7 0x20
8498 #define _PWMPW7 0x20
8500 #define _PWM3DC8 0x40
8501 #define _PWMPW8 0x40
8503 #define _PWM3DC9 0x80
8504 #define _PWMPW9 0x80
8506 //==============================================================================
8509 //==============================================================================
8512 extern __at(0x0619) __sfr PWM3CON
;
8534 unsigned PWM3POL
: 1;
8535 unsigned PWM3OUT
: 1;
8537 unsigned PWM3EN
: 1;
8541 extern __at(0x0619) volatile __PWM3CONbits_t PWM3CONbits
;
8543 #define _PWM3CON_POL 0x10
8544 #define _PWM3CON_PWM3POL 0x10
8545 #define _PWM3CON_OUT 0x20
8546 #define _PWM3CON_PWM3OUT 0x20
8547 #define _PWM3CON_EN 0x80
8548 #define _PWM3CON_PWM3EN 0x80
8550 //==============================================================================
8553 //==============================================================================
8556 extern __at(0x061A) __sfr PWM4DCL
;
8580 unsigned PWM4DC0
: 1;
8581 unsigned PWM4DC1
: 1;
8592 unsigned PWMPW0
: 1;
8593 unsigned PWMPW1
: 1;
8611 unsigned PWM4DC
: 2;
8615 extern __at(0x061A) volatile __PWM4DCLbits_t PWM4DCLbits
;
8617 #define _PWM4DCL_DC0 0x40
8618 #define _PWM4DCL_PWM4DC0 0x40
8619 #define _PWM4DCL_PWMPW0 0x40
8620 #define _PWM4DCL_DC1 0x80
8621 #define _PWM4DCL_PWM4DC1 0x80
8622 #define _PWM4DCL_PWMPW1 0x80
8624 //==============================================================================
8627 //==============================================================================
8630 extern __at(0x061B) __sfr PWM4DCH
;
8648 unsigned PWM4DC2
: 1;
8649 unsigned PWM4DC3
: 1;
8650 unsigned PWM4DC4
: 1;
8651 unsigned PWM4DC5
: 1;
8652 unsigned PWM4DC6
: 1;
8653 unsigned PWM4DC7
: 1;
8654 unsigned PWM4DC8
: 1;
8655 unsigned PWM4DC9
: 1;
8660 unsigned PWMPW2
: 1;
8661 unsigned PWMPW3
: 1;
8662 unsigned PWMPW4
: 1;
8663 unsigned PWMPW5
: 1;
8664 unsigned PWMPW6
: 1;
8665 unsigned PWMPW7
: 1;
8666 unsigned PWMPW8
: 1;
8667 unsigned PWMPW9
: 1;
8671 extern __at(0x061B) volatile __PWM4DCHbits_t PWM4DCHbits
;
8673 #define _PWM4DCH_DC2 0x01
8674 #define _PWM4DCH_PWM4DC2 0x01
8675 #define _PWM4DCH_PWMPW2 0x01
8676 #define _PWM4DCH_DC3 0x02
8677 #define _PWM4DCH_PWM4DC3 0x02
8678 #define _PWM4DCH_PWMPW3 0x02
8679 #define _PWM4DCH_DC4 0x04
8680 #define _PWM4DCH_PWM4DC4 0x04
8681 #define _PWM4DCH_PWMPW4 0x04
8682 #define _PWM4DCH_DC5 0x08
8683 #define _PWM4DCH_PWM4DC5 0x08
8684 #define _PWM4DCH_PWMPW5 0x08
8685 #define _PWM4DCH_DC6 0x10
8686 #define _PWM4DCH_PWM4DC6 0x10
8687 #define _PWM4DCH_PWMPW6 0x10
8688 #define _PWM4DCH_DC7 0x20
8689 #define _PWM4DCH_PWM4DC7 0x20
8690 #define _PWM4DCH_PWMPW7 0x20
8691 #define _PWM4DCH_DC8 0x40
8692 #define _PWM4DCH_PWM4DC8 0x40
8693 #define _PWM4DCH_PWMPW8 0x40
8694 #define _PWM4DCH_DC9 0x80
8695 #define _PWM4DCH_PWM4DC9 0x80
8696 #define _PWM4DCH_PWMPW9 0x80
8698 //==============================================================================
8701 //==============================================================================
8704 extern __at(0x061C) __sfr PWM4CON
;
8726 unsigned PWM4POL
: 1;
8727 unsigned PWM4OUT
: 1;
8729 unsigned PWM4EN
: 1;
8733 extern __at(0x061C) volatile __PWM4CONbits_t PWM4CONbits
;
8735 #define _PWM4CON_POL 0x10
8736 #define _PWM4CON_PWM4POL 0x10
8737 #define _PWM4CON_OUT 0x20
8738 #define _PWM4CON_PWM4OUT 0x20
8739 #define _PWM4CON_EN 0x80
8740 #define _PWM4CON_PWM4EN 0x80
8742 //==============================================================================
8745 //==============================================================================
8748 extern __at(0x068D) __sfr COG1PHR
;
8766 unsigned G1PHR0
: 1;
8767 unsigned G1PHR1
: 1;
8768 unsigned G1PHR2
: 1;
8769 unsigned G1PHR3
: 1;
8770 unsigned G1PHR4
: 1;
8771 unsigned G1PHR5
: 1;
8789 extern __at(0x068D) volatile __COG1PHRbits_t COG1PHRbits
;
8792 #define _G1PHR0 0x01
8794 #define _G1PHR1 0x02
8796 #define _G1PHR2 0x04
8798 #define _G1PHR3 0x08
8800 #define _G1PHR4 0x10
8802 #define _G1PHR5 0x20
8804 //==============================================================================
8807 //==============================================================================
8810 extern __at(0x068E) __sfr COG1PHF
;
8828 unsigned G1PHF0
: 1;
8829 unsigned G1PHF1
: 1;
8830 unsigned G1PHF2
: 1;
8831 unsigned G1PHF3
: 1;
8832 unsigned G1PHF4
: 1;
8833 unsigned G1PHF5
: 1;
8851 extern __at(0x068E) volatile __COG1PHFbits_t COG1PHFbits
;
8854 #define _G1PHF0 0x01
8856 #define _G1PHF1 0x02
8858 #define _G1PHF2 0x04
8860 #define _G1PHF3 0x08
8862 #define _G1PHF4 0x10
8864 #define _G1PHF5 0x20
8866 //==============================================================================
8869 //==============================================================================
8872 extern __at(0x068F) __sfr COG1BLKR
;
8890 unsigned G1BLKR0
: 1;
8891 unsigned G1BLKR1
: 1;
8892 unsigned G1BLKR2
: 1;
8893 unsigned G1BLKR3
: 1;
8894 unsigned G1BLKR4
: 1;
8895 unsigned G1BLKR5
: 1;
8908 unsigned G1BLKR
: 6;
8913 extern __at(0x068F) volatile __COG1BLKRbits_t COG1BLKRbits
;
8916 #define _G1BLKR0 0x01
8918 #define _G1BLKR1 0x02
8920 #define _G1BLKR2 0x04
8922 #define _G1BLKR3 0x08
8924 #define _G1BLKR4 0x10
8926 #define _G1BLKR5 0x20
8928 //==============================================================================
8931 //==============================================================================
8934 extern __at(0x0690) __sfr COG1BLKF
;
8952 unsigned G1BLKF0
: 1;
8953 unsigned G1BLKF1
: 1;
8954 unsigned G1BLKF2
: 1;
8955 unsigned G1BLKF3
: 1;
8956 unsigned G1BLKF4
: 1;
8957 unsigned G1BLKF5
: 1;
8964 unsigned G1BLKF
: 6;
8975 extern __at(0x0690) volatile __COG1BLKFbits_t COG1BLKFbits
;
8978 #define _G1BLKF0 0x01
8980 #define _G1BLKF1 0x02
8982 #define _G1BLKF2 0x04
8984 #define _G1BLKF3 0x08
8986 #define _G1BLKF4 0x10
8988 #define _G1BLKF5 0x20
8990 //==============================================================================
8993 //==============================================================================
8996 extern __at(0x0691) __sfr COG1DBR
;
9014 unsigned G1DBR0
: 1;
9015 unsigned G1DBR1
: 1;
9016 unsigned G1DBR2
: 1;
9017 unsigned G1DBR3
: 1;
9018 unsigned G1DBR4
: 1;
9019 unsigned G1DBR5
: 1;
9037 extern __at(0x0691) volatile __COG1DBRbits_t COG1DBRbits
;
9040 #define _G1DBR0 0x01
9042 #define _G1DBR1 0x02
9044 #define _G1DBR2 0x04
9046 #define _G1DBR3 0x08
9048 #define _G1DBR4 0x10
9050 #define _G1DBR5 0x20
9052 //==============================================================================
9055 //==============================================================================
9058 extern __at(0x0692) __sfr COG1DBF
;
9076 unsigned G1DBF0
: 1;
9077 unsigned G1DBF1
: 1;
9078 unsigned G1DBF2
: 1;
9079 unsigned G1DBF3
: 1;
9080 unsigned G1DBF4
: 1;
9081 unsigned G1DBF5
: 1;
9099 extern __at(0x0692) volatile __COG1DBFbits_t COG1DBFbits
;
9102 #define _G1DBF0 0x01
9104 #define _G1DBF1 0x02
9106 #define _G1DBF2 0x04
9108 #define _G1DBF3 0x08
9110 #define _G1DBF4 0x10
9112 #define _G1DBF5 0x20
9114 //==============================================================================
9117 //==============================================================================
9120 extern __at(0x0693) __sfr COG1CON0
;
9175 extern __at(0x0693) volatile __COG1CON0bits_t COG1CON0bits
;
9177 #define _COG1CON0_MD0 0x01
9178 #define _COG1CON0_G1MD0 0x01
9179 #define _COG1CON0_MD1 0x02
9180 #define _COG1CON0_G1MD1 0x02
9181 #define _COG1CON0_MD2 0x04
9182 #define _COG1CON0_G1MD2 0x04
9183 #define _COG1CON0_CS0 0x08
9184 #define _COG1CON0_G1CS0 0x08
9185 #define _COG1CON0_CS1 0x10
9186 #define _COG1CON0_G1CS1 0x10
9187 #define _COG1CON0_LD 0x40
9188 #define _COG1CON0_G1LD 0x40
9189 #define _COG1CON0_EN 0x80
9190 #define _COG1CON0_G1EN 0x80
9192 //==============================================================================
9195 //==============================================================================
9198 extern __at(0x0694) __sfr COG1CON1
;
9216 unsigned G1POLA
: 1;
9217 unsigned G1POLB
: 1;
9218 unsigned G1POLC
: 1;
9219 unsigned G1POLD
: 1;
9222 unsigned G1FDBS
: 1;
9223 unsigned G1RDBS
: 1;
9227 extern __at(0x0694) volatile __COG1CON1bits_t COG1CON1bits
;
9230 #define _G1POLA 0x01
9232 #define _G1POLB 0x02
9234 #define _G1POLC 0x04
9236 #define _G1POLD 0x08
9238 #define _G1FDBS 0x40
9240 #define _G1RDBS 0x80
9242 //==============================================================================
9245 //==============================================================================
9248 extern __at(0x0695) __sfr COG1RIS0
;
9266 unsigned G1RIS0
: 1;
9267 unsigned G1RIS1
: 1;
9268 unsigned G1RIS2
: 1;
9269 unsigned G1RIS3
: 1;
9270 unsigned G1RIS4
: 1;
9271 unsigned G1RIS5
: 1;
9272 unsigned G1RIS6
: 1;
9273 unsigned G1RIS7
: 1;
9277 extern __at(0x0695) volatile __COG1RIS0bits_t COG1RIS0bits
;
9280 #define _G1RIS0 0x01
9282 #define _G1RIS1 0x02
9284 #define _G1RIS2 0x04
9286 #define _G1RIS3 0x08
9288 #define _G1RIS4 0x10
9290 #define _G1RIS5 0x20
9292 #define _G1RIS6 0x40
9294 #define _G1RIS7 0x80
9296 //==============================================================================
9299 //==============================================================================
9302 extern __at(0x0696) __sfr COG1RIS1
;
9320 unsigned G1RIS8
: 1;
9321 unsigned G1RIS9
: 1;
9322 unsigned G1RIS10
: 1;
9323 unsigned G1RIS11
: 1;
9324 unsigned G1RIS12
: 1;
9325 unsigned G1RIS13
: 1;
9326 unsigned G1RIS14
: 1;
9327 unsigned G1RIS15
: 1;
9331 extern __at(0x0696) volatile __COG1RIS1bits_t COG1RIS1bits
;
9334 #define _G1RIS8 0x01
9336 #define _G1RIS9 0x02
9338 #define _G1RIS10 0x04
9340 #define _G1RIS11 0x08
9342 #define _G1RIS12 0x10
9344 #define _G1RIS13 0x20
9346 #define _G1RIS14 0x40
9348 #define _G1RIS15 0x80
9350 //==============================================================================
9353 //==============================================================================
9356 extern __at(0x0697) __sfr COG1RSIM0
;
9374 unsigned G1RSIM0
: 1;
9375 unsigned G1RSIM1
: 1;
9376 unsigned G1RSIM2
: 1;
9377 unsigned G1RSIM3
: 1;
9378 unsigned G1RSIM4
: 1;
9379 unsigned G1RSIM5
: 1;
9380 unsigned G1RSIM6
: 1;
9381 unsigned G1RSIM7
: 1;
9383 } __COG1RSIM0bits_t
;
9385 extern __at(0x0697) volatile __COG1RSIM0bits_t COG1RSIM0bits
;
9388 #define _G1RSIM0 0x01
9390 #define _G1RSIM1 0x02
9392 #define _G1RSIM2 0x04
9394 #define _G1RSIM3 0x08
9396 #define _G1RSIM4 0x10
9398 #define _G1RSIM5 0x20
9400 #define _G1RSIM6 0x40
9402 #define _G1RSIM7 0x80
9404 //==============================================================================
9407 //==============================================================================
9410 extern __at(0x0698) __sfr COG1RSIM1
;
9418 unsigned RSIM10
: 1;
9419 unsigned RSIM11
: 1;
9420 unsigned RSIM12
: 1;
9421 unsigned RSIM13
: 1;
9422 unsigned RSIM14
: 1;
9423 unsigned RSIM15
: 1;
9428 unsigned G1RSIM8
: 1;
9429 unsigned G1RSIM9
: 1;
9430 unsigned G1RSIM10
: 1;
9431 unsigned G1RSIM11
: 1;
9432 unsigned G1RSIM12
: 1;
9433 unsigned G1RSIM13
: 1;
9434 unsigned G1RSIM14
: 1;
9435 unsigned G1RSIM15
: 1;
9437 } __COG1RSIM1bits_t
;
9439 extern __at(0x0698) volatile __COG1RSIM1bits_t COG1RSIM1bits
;
9442 #define _G1RSIM8 0x01
9444 #define _G1RSIM9 0x02
9445 #define _RSIM10 0x04
9446 #define _G1RSIM10 0x04
9447 #define _RSIM11 0x08
9448 #define _G1RSIM11 0x08
9449 #define _RSIM12 0x10
9450 #define _G1RSIM12 0x10
9451 #define _RSIM13 0x20
9452 #define _G1RSIM13 0x20
9453 #define _RSIM14 0x40
9454 #define _G1RSIM14 0x40
9455 #define _RSIM15 0x80
9456 #define _G1RSIM15 0x80
9458 //==============================================================================
9461 //==============================================================================
9464 extern __at(0x0699) __sfr COG1FIS0
;
9482 unsigned G1FIS0
: 1;
9483 unsigned G1FIS1
: 1;
9484 unsigned G1FIS2
: 1;
9485 unsigned G1FIS3
: 1;
9486 unsigned G1FIS4
: 1;
9487 unsigned G1FIS5
: 1;
9488 unsigned G1FIS6
: 1;
9489 unsigned G1FIS7
: 1;
9493 extern __at(0x0699) volatile __COG1FIS0bits_t COG1FIS0bits
;
9496 #define _G1FIS0 0x01
9498 #define _G1FIS1 0x02
9500 #define _G1FIS2 0x04
9502 #define _G1FIS3 0x08
9504 #define _G1FIS4 0x10
9506 #define _G1FIS5 0x20
9508 #define _G1FIS6 0x40
9510 #define _G1FIS7 0x80
9512 //==============================================================================
9515 //==============================================================================
9518 extern __at(0x069A) __sfr COG1FIS1
;
9536 unsigned G1FIS8
: 1;
9537 unsigned G1FIS9
: 1;
9538 unsigned G1FIS10
: 1;
9539 unsigned G1FIS11
: 1;
9540 unsigned G1FIS12
: 1;
9541 unsigned G1FIS13
: 1;
9542 unsigned G1FIS14
: 1;
9543 unsigned G1FIS15
: 1;
9547 extern __at(0x069A) volatile __COG1FIS1bits_t COG1FIS1bits
;
9550 #define _G1FIS8 0x01
9552 #define _G1FIS9 0x02
9554 #define _G1FIS10 0x04
9556 #define _G1FIS11 0x08
9558 #define _G1FIS12 0x10
9560 #define _G1FIS13 0x20
9562 #define _G1FIS14 0x40
9564 #define _G1FIS15 0x80
9566 //==============================================================================
9569 //==============================================================================
9572 extern __at(0x069B) __sfr COG1FSIM0
;
9590 unsigned G1FSIM0
: 1;
9591 unsigned G1FSIM1
: 1;
9592 unsigned G1FSIM2
: 1;
9593 unsigned G1FSIM3
: 1;
9594 unsigned G1FSIM4
: 1;
9595 unsigned G1FSIM5
: 1;
9596 unsigned G1FSIM6
: 1;
9597 unsigned G1FSIM7
: 1;
9599 } __COG1FSIM0bits_t
;
9601 extern __at(0x069B) volatile __COG1FSIM0bits_t COG1FSIM0bits
;
9604 #define _G1FSIM0 0x01
9606 #define _G1FSIM1 0x02
9608 #define _G1FSIM2 0x04
9610 #define _G1FSIM3 0x08
9612 #define _G1FSIM4 0x10
9614 #define _G1FSIM5 0x20
9616 #define _G1FSIM6 0x40
9618 #define _G1FSIM7 0x80
9620 //==============================================================================
9623 //==============================================================================
9626 extern __at(0x069C) __sfr COG1FSIM1
;
9634 unsigned FSIM10
: 1;
9635 unsigned FSIM11
: 1;
9636 unsigned FSIM12
: 1;
9637 unsigned FSIM13
: 1;
9638 unsigned FSIM14
: 1;
9639 unsigned FSIM15
: 1;
9644 unsigned G1FSIM8
: 1;
9645 unsigned G1FSIM9
: 1;
9646 unsigned G1FSIM10
: 1;
9647 unsigned G1FSIM11
: 1;
9648 unsigned G1FSIM12
: 1;
9649 unsigned G1FSIM13
: 1;
9650 unsigned G1FSIM14
: 1;
9651 unsigned G1FSIM15
: 1;
9653 } __COG1FSIM1bits_t
;
9655 extern __at(0x069C) volatile __COG1FSIM1bits_t COG1FSIM1bits
;
9658 #define _G1FSIM8 0x01
9660 #define _G1FSIM9 0x02
9661 #define _FSIM10 0x04
9662 #define _G1FSIM10 0x04
9663 #define _FSIM11 0x08
9664 #define _G1FSIM11 0x08
9665 #define _FSIM12 0x10
9666 #define _G1FSIM12 0x10
9667 #define _FSIM13 0x20
9668 #define _G1FSIM13 0x20
9669 #define _FSIM14 0x40
9670 #define _G1FSIM14 0x40
9671 #define _FSIM15 0x80
9672 #define _G1FSIM15 0x80
9674 //==============================================================================
9677 //==============================================================================
9680 extern __at(0x069D) __sfr COG1ASD0
;
9688 unsigned ASDAC0
: 1;
9689 unsigned ASDAC1
: 1;
9690 unsigned ASDBD0
: 1;
9691 unsigned ASDBD1
: 1;
9700 unsigned G1ASDAC0
: 1;
9701 unsigned G1ASDAC1
: 1;
9702 unsigned G1ASDBD0
: 1;
9703 unsigned G1ASDBD1
: 1;
9716 unsigned G1ARSEN
: 1;
9728 unsigned G1ASREN
: 1;
9742 unsigned G1ASDAC
: 2;
9749 unsigned G1ASDBD
: 2;
9761 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
9763 #define _ASDAC0 0x04
9764 #define _G1ASDAC0 0x04
9765 #define _ASDAC1 0x08
9766 #define _G1ASDAC1 0x08
9767 #define _ASDBD0 0x10
9768 #define _G1ASDBD0 0x10
9769 #define _ASDBD1 0x20
9770 #define _G1ASDBD1 0x20
9773 #define _G1ARSEN 0x40
9774 #define _G1ASREN 0x40
9778 //==============================================================================
9781 //==============================================================================
9784 extern __at(0x069E) __sfr COG1ASD1
;
9802 unsigned G1AS0E
: 1;
9803 unsigned G1AS1E
: 1;
9804 unsigned G1AS2E
: 1;
9805 unsigned G1AS3E
: 1;
9806 unsigned G1AS4E
: 1;
9807 unsigned G1AS5E
: 1;
9808 unsigned G1AS6E
: 1;
9809 unsigned G1AS7E
: 1;
9813 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
9816 #define _G1AS0E 0x01
9818 #define _G1AS1E 0x02
9820 #define _G1AS2E 0x04
9822 #define _G1AS3E 0x08
9824 #define _G1AS4E 0x10
9826 #define _G1AS5E 0x20
9828 #define _G1AS6E 0x40
9830 #define _G1AS7E 0x80
9832 //==============================================================================
9835 //==============================================================================
9838 extern __at(0x069F) __sfr COG1STR
;
9856 unsigned G1STRA
: 1;
9857 unsigned G1STRB
: 1;
9858 unsigned G1STRC
: 1;
9859 unsigned G1STRD
: 1;
9860 unsigned G1SDATA
: 1;
9861 unsigned G1SDATB
: 1;
9862 unsigned G1SDATC
: 1;
9863 unsigned G1SDATD
: 1;
9867 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
9870 #define _G1STRA 0x01
9872 #define _G1STRB 0x02
9874 #define _G1STRC 0x04
9876 #define _G1STRD 0x08
9878 #define _G1SDATA 0x10
9880 #define _G1SDATB 0x20
9882 #define _G1SDATC 0x40
9884 #define _G1SDATD 0x80
9886 //==============================================================================
9889 //==============================================================================
9892 extern __at(0x070D) __sfr COG2PHR
;
9910 unsigned G2PHR0
: 1;
9911 unsigned G2PHR1
: 1;
9912 unsigned G2PHR2
: 1;
9913 unsigned G2PHR3
: 1;
9914 unsigned G2PHR4
: 1;
9915 unsigned G2PHR5
: 1;
9933 extern __at(0x070D) volatile __COG2PHRbits_t COG2PHRbits
;
9935 #define _COG2PHR_PHR0 0x01
9936 #define _COG2PHR_G2PHR0 0x01
9937 #define _COG2PHR_PHR1 0x02
9938 #define _COG2PHR_G2PHR1 0x02
9939 #define _COG2PHR_PHR2 0x04
9940 #define _COG2PHR_G2PHR2 0x04
9941 #define _COG2PHR_PHR3 0x08
9942 #define _COG2PHR_G2PHR3 0x08
9943 #define _COG2PHR_PHR4 0x10
9944 #define _COG2PHR_G2PHR4 0x10
9945 #define _COG2PHR_PHR5 0x20
9946 #define _COG2PHR_G2PHR5 0x20
9948 //==============================================================================
9951 //==============================================================================
9954 extern __at(0x070E) __sfr COG2PHF
;
9972 unsigned G2PHF0
: 1;
9973 unsigned G2PHF1
: 1;
9974 unsigned G2PHF2
: 1;
9975 unsigned G2PHF3
: 1;
9976 unsigned G2PHF4
: 1;
9977 unsigned G2PHF5
: 1;
9995 extern __at(0x070E) volatile __COG2PHFbits_t COG2PHFbits
;
9997 #define _COG2PHF_PHF0 0x01
9998 #define _COG2PHF_G2PHF0 0x01
9999 #define _COG2PHF_PHF1 0x02
10000 #define _COG2PHF_G2PHF1 0x02
10001 #define _COG2PHF_PHF2 0x04
10002 #define _COG2PHF_G2PHF2 0x04
10003 #define _COG2PHF_PHF3 0x08
10004 #define _COG2PHF_G2PHF3 0x08
10005 #define _COG2PHF_PHF4 0x10
10006 #define _COG2PHF_G2PHF4 0x10
10007 #define _COG2PHF_PHF5 0x20
10008 #define _COG2PHF_G2PHF5 0x20
10010 //==============================================================================
10013 //==============================================================================
10016 extern __at(0x070F) __sfr COG2BLKR
;
10022 unsigned BLKR0
: 1;
10023 unsigned BLKR1
: 1;
10024 unsigned BLKR2
: 1;
10025 unsigned BLKR3
: 1;
10026 unsigned BLKR4
: 1;
10027 unsigned BLKR5
: 1;
10034 unsigned G2BLKR0
: 1;
10035 unsigned G2BLKR1
: 1;
10036 unsigned G2BLKR2
: 1;
10037 unsigned G2BLKR3
: 1;
10038 unsigned G2BLKR4
: 1;
10039 unsigned G2BLKR5
: 1;
10046 unsigned G2BLKR
: 6;
10055 } __COG2BLKRbits_t
;
10057 extern __at(0x070F) volatile __COG2BLKRbits_t COG2BLKRbits
;
10059 #define _COG2BLKR_BLKR0 0x01
10060 #define _COG2BLKR_G2BLKR0 0x01
10061 #define _COG2BLKR_BLKR1 0x02
10062 #define _COG2BLKR_G2BLKR1 0x02
10063 #define _COG2BLKR_BLKR2 0x04
10064 #define _COG2BLKR_G2BLKR2 0x04
10065 #define _COG2BLKR_BLKR3 0x08
10066 #define _COG2BLKR_G2BLKR3 0x08
10067 #define _COG2BLKR_BLKR4 0x10
10068 #define _COG2BLKR_G2BLKR4 0x10
10069 #define _COG2BLKR_BLKR5 0x20
10070 #define _COG2BLKR_G2BLKR5 0x20
10072 //==============================================================================
10075 //==============================================================================
10078 extern __at(0x0710) __sfr COG2BLKF
;
10084 unsigned BLKF0
: 1;
10085 unsigned BLKF1
: 1;
10086 unsigned BLKF2
: 1;
10087 unsigned BLKF3
: 1;
10088 unsigned BLKF4
: 1;
10089 unsigned BLKF5
: 1;
10096 unsigned G2BLKF0
: 1;
10097 unsigned G2BLKF1
: 1;
10098 unsigned G2BLKF2
: 1;
10099 unsigned G2BLKF3
: 1;
10100 unsigned G2BLKF4
: 1;
10101 unsigned G2BLKF5
: 1;
10114 unsigned G2BLKF
: 6;
10117 } __COG2BLKFbits_t
;
10119 extern __at(0x0710) volatile __COG2BLKFbits_t COG2BLKFbits
;
10121 #define _COG2BLKF_BLKF0 0x01
10122 #define _COG2BLKF_G2BLKF0 0x01
10123 #define _COG2BLKF_BLKF1 0x02
10124 #define _COG2BLKF_G2BLKF1 0x02
10125 #define _COG2BLKF_BLKF2 0x04
10126 #define _COG2BLKF_G2BLKF2 0x04
10127 #define _COG2BLKF_BLKF3 0x08
10128 #define _COG2BLKF_G2BLKF3 0x08
10129 #define _COG2BLKF_BLKF4 0x10
10130 #define _COG2BLKF_G2BLKF4 0x10
10131 #define _COG2BLKF_BLKF5 0x20
10132 #define _COG2BLKF_G2BLKF5 0x20
10134 //==============================================================================
10137 //==============================================================================
10140 extern __at(0x0711) __sfr COG2DBR
;
10158 unsigned G2DBR0
: 1;
10159 unsigned G2DBR1
: 1;
10160 unsigned G2DBR2
: 1;
10161 unsigned G2DBR3
: 1;
10162 unsigned G2DBR4
: 1;
10163 unsigned G2DBR5
: 1;
10176 unsigned G2DBR
: 6;
10181 extern __at(0x0711) volatile __COG2DBRbits_t COG2DBRbits
;
10183 #define _COG2DBR_DBR0 0x01
10184 #define _COG2DBR_G2DBR0 0x01
10185 #define _COG2DBR_DBR1 0x02
10186 #define _COG2DBR_G2DBR1 0x02
10187 #define _COG2DBR_DBR2 0x04
10188 #define _COG2DBR_G2DBR2 0x04
10189 #define _COG2DBR_DBR3 0x08
10190 #define _COG2DBR_G2DBR3 0x08
10191 #define _COG2DBR_DBR4 0x10
10192 #define _COG2DBR_G2DBR4 0x10
10193 #define _COG2DBR_DBR5 0x20
10194 #define _COG2DBR_G2DBR5 0x20
10196 //==============================================================================
10199 //==============================================================================
10202 extern __at(0x0712) __sfr COG2DBF
;
10220 unsigned G2DBF0
: 1;
10221 unsigned G2DBF1
: 1;
10222 unsigned G2DBF2
: 1;
10223 unsigned G2DBF3
: 1;
10224 unsigned G2DBF4
: 1;
10225 unsigned G2DBF5
: 1;
10238 unsigned G2DBF
: 6;
10243 extern __at(0x0712) volatile __COG2DBFbits_t COG2DBFbits
;
10245 #define _COG2DBF_DBF0 0x01
10246 #define _COG2DBF_G2DBF0 0x01
10247 #define _COG2DBF_DBF1 0x02
10248 #define _COG2DBF_G2DBF1 0x02
10249 #define _COG2DBF_DBF2 0x04
10250 #define _COG2DBF_G2DBF2 0x04
10251 #define _COG2DBF_DBF3 0x08
10252 #define _COG2DBF_G2DBF3 0x08
10253 #define _COG2DBF_DBF4 0x10
10254 #define _COG2DBF_G2DBF4 0x10
10255 #define _COG2DBF_DBF5 0x20
10256 #define _COG2DBF_G2DBF5 0x20
10258 //==============================================================================
10261 //==============================================================================
10264 extern __at(0x0713) __sfr COG2CON0
;
10282 unsigned G2MD0
: 1;
10283 unsigned G2MD1
: 1;
10284 unsigned G2MD2
: 1;
10285 unsigned G2CS0
: 1;
10286 unsigned G2CS1
: 1;
10317 } __COG2CON0bits_t
;
10319 extern __at(0x0713) volatile __COG2CON0bits_t COG2CON0bits
;
10321 #define _COG2CON0_MD0 0x01
10322 #define _COG2CON0_G2MD0 0x01
10323 #define _COG2CON0_MD1 0x02
10324 #define _COG2CON0_G2MD1 0x02
10325 #define _COG2CON0_MD2 0x04
10326 #define _COG2CON0_G2MD2 0x04
10327 #define _COG2CON0_CS0 0x08
10328 #define _COG2CON0_G2CS0 0x08
10329 #define _COG2CON0_CS1 0x10
10330 #define _COG2CON0_G2CS1 0x10
10331 #define _COG2CON0_LD 0x40
10332 #define _COG2CON0_G2LD 0x40
10333 #define _COG2CON0_EN 0x80
10334 #define _COG2CON0_G2EN 0x80
10336 //==============================================================================
10339 //==============================================================================
10342 extern __at(0x0714) __sfr COG2CON1
;
10360 unsigned G2POLA
: 1;
10361 unsigned G2POLB
: 1;
10362 unsigned G2POLC
: 1;
10363 unsigned G2POLD
: 1;
10366 unsigned G2FDBS
: 1;
10367 unsigned G2RDBS
: 1;
10369 } __COG2CON1bits_t
;
10371 extern __at(0x0714) volatile __COG2CON1bits_t COG2CON1bits
;
10373 #define _COG2CON1_POLA 0x01
10374 #define _COG2CON1_G2POLA 0x01
10375 #define _COG2CON1_POLB 0x02
10376 #define _COG2CON1_G2POLB 0x02
10377 #define _COG2CON1_POLC 0x04
10378 #define _COG2CON1_G2POLC 0x04
10379 #define _COG2CON1_POLD 0x08
10380 #define _COG2CON1_G2POLD 0x08
10381 #define _COG2CON1_FDBS 0x40
10382 #define _COG2CON1_G2FDBS 0x40
10383 #define _COG2CON1_RDBS 0x80
10384 #define _COG2CON1_G2RDBS 0x80
10386 //==============================================================================
10389 //==============================================================================
10392 extern __at(0x0715) __sfr COG2RIS0
;
10410 unsigned G2RIS0
: 1;
10411 unsigned G2RIS1
: 1;
10412 unsigned G2RIS2
: 1;
10413 unsigned G2RIS3
: 1;
10414 unsigned G2RIS4
: 1;
10415 unsigned G2RIS5
: 1;
10416 unsigned G2RIS6
: 1;
10417 unsigned G2RIS7
: 1;
10419 } __COG2RIS0bits_t
;
10421 extern __at(0x0715) volatile __COG2RIS0bits_t COG2RIS0bits
;
10423 #define _COG2RIS0_RIS0 0x01
10424 #define _COG2RIS0_G2RIS0 0x01
10425 #define _COG2RIS0_RIS1 0x02
10426 #define _COG2RIS0_G2RIS1 0x02
10427 #define _COG2RIS0_RIS2 0x04
10428 #define _COG2RIS0_G2RIS2 0x04
10429 #define _COG2RIS0_RIS3 0x08
10430 #define _COG2RIS0_G2RIS3 0x08
10431 #define _COG2RIS0_RIS4 0x10
10432 #define _COG2RIS0_G2RIS4 0x10
10433 #define _COG2RIS0_RIS5 0x20
10434 #define _COG2RIS0_G2RIS5 0x20
10435 #define _COG2RIS0_RIS6 0x40
10436 #define _COG2RIS0_G2RIS6 0x40
10437 #define _COG2RIS0_RIS7 0x80
10438 #define _COG2RIS0_G2RIS7 0x80
10440 //==============================================================================
10443 //==============================================================================
10446 extern __at(0x0716) __sfr COG2RIS1
;
10454 unsigned RIS10
: 1;
10455 unsigned RIS11
: 1;
10456 unsigned RIS12
: 1;
10457 unsigned RIS13
: 1;
10464 unsigned G2RIS8
: 1;
10465 unsigned G2RIS9
: 1;
10466 unsigned G2RIS10
: 1;
10467 unsigned G2RIS11
: 1;
10468 unsigned G2RIS12
: 1;
10469 unsigned G2RIS13
: 1;
10473 } __COG2RIS1bits_t
;
10475 extern __at(0x0716) volatile __COG2RIS1bits_t COG2RIS1bits
;
10477 #define _COG2RIS1_RIS8 0x01
10478 #define _COG2RIS1_G2RIS8 0x01
10479 #define _COG2RIS1_RIS9 0x02
10480 #define _COG2RIS1_G2RIS9 0x02
10481 #define _COG2RIS1_RIS10 0x04
10482 #define _COG2RIS1_G2RIS10 0x04
10483 #define _COG2RIS1_RIS11 0x08
10484 #define _COG2RIS1_G2RIS11 0x08
10485 #define _COG2RIS1_RIS12 0x10
10486 #define _COG2RIS1_G2RIS12 0x10
10487 #define _COG2RIS1_RIS13 0x20
10488 #define _COG2RIS1_G2RIS13 0x20
10490 //==============================================================================
10493 //==============================================================================
10496 extern __at(0x0717) __sfr COG2RSIM0
;
10502 unsigned RSIM0
: 1;
10503 unsigned RSIM1
: 1;
10504 unsigned RSIM2
: 1;
10505 unsigned RSIM3
: 1;
10506 unsigned RSIM4
: 1;
10507 unsigned RSIM5
: 1;
10508 unsigned RSIM6
: 1;
10509 unsigned RSIM7
: 1;
10514 unsigned G2RSIM0
: 1;
10515 unsigned G2RSIM1
: 1;
10516 unsigned G2RSIM2
: 1;
10517 unsigned G2RSIM3
: 1;
10518 unsigned G2RSIM4
: 1;
10519 unsigned G2RSIM5
: 1;
10520 unsigned G2RSIM6
: 1;
10521 unsigned G2RSIM7
: 1;
10523 } __COG2RSIM0bits_t
;
10525 extern __at(0x0717) volatile __COG2RSIM0bits_t COG2RSIM0bits
;
10527 #define _COG2RSIM0_RSIM0 0x01
10528 #define _COG2RSIM0_G2RSIM0 0x01
10529 #define _COG2RSIM0_RSIM1 0x02
10530 #define _COG2RSIM0_G2RSIM1 0x02
10531 #define _COG2RSIM0_RSIM2 0x04
10532 #define _COG2RSIM0_G2RSIM2 0x04
10533 #define _COG2RSIM0_RSIM3 0x08
10534 #define _COG2RSIM0_G2RSIM3 0x08
10535 #define _COG2RSIM0_RSIM4 0x10
10536 #define _COG2RSIM0_G2RSIM4 0x10
10537 #define _COG2RSIM0_RSIM5 0x20
10538 #define _COG2RSIM0_G2RSIM5 0x20
10539 #define _COG2RSIM0_RSIM6 0x40
10540 #define _COG2RSIM0_G2RSIM6 0x40
10541 #define _COG2RSIM0_RSIM7 0x80
10542 #define _COG2RSIM0_G2RSIM7 0x80
10544 //==============================================================================
10547 //==============================================================================
10550 extern __at(0x0718) __sfr COG2RSIM1
;
10556 unsigned RSIM8
: 1;
10557 unsigned RSIM9
: 1;
10558 unsigned RSIM10
: 1;
10559 unsigned RSIM11
: 1;
10560 unsigned RSIM12
: 1;
10561 unsigned RSIM13
: 1;
10568 unsigned G2RSIM8
: 1;
10569 unsigned G2RSIM9
: 1;
10570 unsigned G2RSIM10
: 1;
10571 unsigned G2RSIM11
: 1;
10572 unsigned G2RSIM12
: 1;
10573 unsigned G2RSIM13
: 1;
10577 } __COG2RSIM1bits_t
;
10579 extern __at(0x0718) volatile __COG2RSIM1bits_t COG2RSIM1bits
;
10581 #define _COG2RSIM1_RSIM8 0x01
10582 #define _COG2RSIM1_G2RSIM8 0x01
10583 #define _COG2RSIM1_RSIM9 0x02
10584 #define _COG2RSIM1_G2RSIM9 0x02
10585 #define _COG2RSIM1_RSIM10 0x04
10586 #define _COG2RSIM1_G2RSIM10 0x04
10587 #define _COG2RSIM1_RSIM11 0x08
10588 #define _COG2RSIM1_G2RSIM11 0x08
10589 #define _COG2RSIM1_RSIM12 0x10
10590 #define _COG2RSIM1_G2RSIM12 0x10
10591 #define _COG2RSIM1_RSIM13 0x20
10592 #define _COG2RSIM1_G2RSIM13 0x20
10594 //==============================================================================
10597 //==============================================================================
10600 extern __at(0x0719) __sfr COG2FIS0
;
10618 unsigned G2FIS0
: 1;
10619 unsigned G2FIS1
: 1;
10620 unsigned G2FIS2
: 1;
10621 unsigned G2FIS3
: 1;
10622 unsigned G2FIS4
: 1;
10623 unsigned G2FIS5
: 1;
10624 unsigned G2FIS6
: 1;
10625 unsigned G2FIS7
: 1;
10627 } __COG2FIS0bits_t
;
10629 extern __at(0x0719) volatile __COG2FIS0bits_t COG2FIS0bits
;
10631 #define _COG2FIS0_FIS0 0x01
10632 #define _COG2FIS0_G2FIS0 0x01
10633 #define _COG2FIS0_FIS1 0x02
10634 #define _COG2FIS0_G2FIS1 0x02
10635 #define _COG2FIS0_FIS2 0x04
10636 #define _COG2FIS0_G2FIS2 0x04
10637 #define _COG2FIS0_FIS3 0x08
10638 #define _COG2FIS0_G2FIS3 0x08
10639 #define _COG2FIS0_FIS4 0x10
10640 #define _COG2FIS0_G2FIS4 0x10
10641 #define _COG2FIS0_FIS5 0x20
10642 #define _COG2FIS0_G2FIS5 0x20
10643 #define _COG2FIS0_FIS6 0x40
10644 #define _COG2FIS0_G2FIS6 0x40
10645 #define _COG2FIS0_FIS7 0x80
10646 #define _COG2FIS0_G2FIS7 0x80
10648 //==============================================================================
10651 //==============================================================================
10654 extern __at(0x071A) __sfr COG2FIS1
;
10662 unsigned FIS10
: 1;
10663 unsigned FIS11
: 1;
10664 unsigned FIS12
: 1;
10665 unsigned FIS13
: 1;
10672 unsigned G2FIS8
: 1;
10673 unsigned G2FIS9
: 1;
10674 unsigned G2FIS10
: 1;
10675 unsigned G2FIS11
: 1;
10676 unsigned G2FIS12
: 1;
10677 unsigned G2FIS13
: 1;
10681 } __COG2FIS1bits_t
;
10683 extern __at(0x071A) volatile __COG2FIS1bits_t COG2FIS1bits
;
10685 #define _COG2FIS1_FIS8 0x01
10686 #define _COG2FIS1_G2FIS8 0x01
10687 #define _COG2FIS1_FIS9 0x02
10688 #define _COG2FIS1_G2FIS9 0x02
10689 #define _COG2FIS1_FIS10 0x04
10690 #define _COG2FIS1_G2FIS10 0x04
10691 #define _COG2FIS1_FIS11 0x08
10692 #define _COG2FIS1_G2FIS11 0x08
10693 #define _COG2FIS1_FIS12 0x10
10694 #define _COG2FIS1_G2FIS12 0x10
10695 #define _COG2FIS1_FIS13 0x20
10696 #define _COG2FIS1_G2FIS13 0x20
10698 //==============================================================================
10701 //==============================================================================
10704 extern __at(0x071B) __sfr COG2FSIM0
;
10710 unsigned FSIM0
: 1;
10711 unsigned FSIM1
: 1;
10712 unsigned FSIM2
: 1;
10713 unsigned FSIM3
: 1;
10714 unsigned FSIM4
: 1;
10715 unsigned FSIM5
: 1;
10716 unsigned FSIM6
: 1;
10717 unsigned FSIM7
: 1;
10722 unsigned G2FSIM0
: 1;
10723 unsigned G2FSIM1
: 1;
10724 unsigned G2FSIM2
: 1;
10725 unsigned G2FSIM3
: 1;
10726 unsigned G2FSIM4
: 1;
10727 unsigned G2FSIM5
: 1;
10728 unsigned G2FSIM6
: 1;
10729 unsigned G2FSIM7
: 1;
10731 } __COG2FSIM0bits_t
;
10733 extern __at(0x071B) volatile __COG2FSIM0bits_t COG2FSIM0bits
;
10735 #define _COG2FSIM0_FSIM0 0x01
10736 #define _COG2FSIM0_G2FSIM0 0x01
10737 #define _COG2FSIM0_FSIM1 0x02
10738 #define _COG2FSIM0_G2FSIM1 0x02
10739 #define _COG2FSIM0_FSIM2 0x04
10740 #define _COG2FSIM0_G2FSIM2 0x04
10741 #define _COG2FSIM0_FSIM3 0x08
10742 #define _COG2FSIM0_G2FSIM3 0x08
10743 #define _COG2FSIM0_FSIM4 0x10
10744 #define _COG2FSIM0_G2FSIM4 0x10
10745 #define _COG2FSIM0_FSIM5 0x20
10746 #define _COG2FSIM0_G2FSIM5 0x20
10747 #define _COG2FSIM0_FSIM6 0x40
10748 #define _COG2FSIM0_G2FSIM6 0x40
10749 #define _COG2FSIM0_FSIM7 0x80
10750 #define _COG2FSIM0_G2FSIM7 0x80
10752 //==============================================================================
10755 //==============================================================================
10758 extern __at(0x071C) __sfr COG2FSIM1
;
10764 unsigned FSIM8
: 1;
10765 unsigned FSIM9
: 1;
10766 unsigned FSIM10
: 1;
10767 unsigned FSIM11
: 1;
10768 unsigned FSIM12
: 1;
10769 unsigned FSIM13
: 1;
10776 unsigned G2FSIM8
: 1;
10777 unsigned G2FSIM9
: 1;
10778 unsigned G2FSIM10
: 1;
10779 unsigned G2FSIM11
: 1;
10780 unsigned G2FSIM12
: 1;
10781 unsigned G2FSIM13
: 1;
10785 } __COG2FSIM1bits_t
;
10787 extern __at(0x071C) volatile __COG2FSIM1bits_t COG2FSIM1bits
;
10789 #define _COG2FSIM1_FSIM8 0x01
10790 #define _COG2FSIM1_G2FSIM8 0x01
10791 #define _COG2FSIM1_FSIM9 0x02
10792 #define _COG2FSIM1_G2FSIM9 0x02
10793 #define _COG2FSIM1_FSIM10 0x04
10794 #define _COG2FSIM1_G2FSIM10 0x04
10795 #define _COG2FSIM1_FSIM11 0x08
10796 #define _COG2FSIM1_G2FSIM11 0x08
10797 #define _COG2FSIM1_FSIM12 0x10
10798 #define _COG2FSIM1_G2FSIM12 0x10
10799 #define _COG2FSIM1_FSIM13 0x20
10800 #define _COG2FSIM1_G2FSIM13 0x20
10802 //==============================================================================
10805 //==============================================================================
10808 extern __at(0x071D) __sfr COG2ASD0
;
10816 unsigned ASDAC0
: 1;
10817 unsigned ASDAC1
: 1;
10818 unsigned ASDBD0
: 1;
10819 unsigned ASDBD1
: 1;
10820 unsigned ASREN
: 1;
10828 unsigned G2ASDAC0
: 1;
10829 unsigned G2ASDAC1
: 1;
10830 unsigned G2ASDBD0
: 1;
10831 unsigned G2ASDBD1
: 1;
10832 unsigned ARSEN
: 1;
10833 unsigned G2ASE
: 1;
10844 unsigned G2ARSEN
: 1;
10856 unsigned G2ASREN
: 1;
10863 unsigned ASDAC
: 2;
10870 unsigned G2ASDAC
: 2;
10877 unsigned ASDBD
: 2;
10884 unsigned G2ASDBD
: 2;
10887 } __COG2ASD0bits_t
;
10889 extern __at(0x071D) volatile __COG2ASD0bits_t COG2ASD0bits
;
10891 #define _COG2ASD0_ASDAC0 0x04
10892 #define _COG2ASD0_G2ASDAC0 0x04
10893 #define _COG2ASD0_ASDAC1 0x08
10894 #define _COG2ASD0_G2ASDAC1 0x08
10895 #define _COG2ASD0_ASDBD0 0x10
10896 #define _COG2ASD0_G2ASDBD0 0x10
10897 #define _COG2ASD0_ASDBD1 0x20
10898 #define _COG2ASD0_G2ASDBD1 0x20
10899 #define _COG2ASD0_ASREN 0x40
10900 #define _COG2ASD0_ARSEN 0x40
10901 #define _COG2ASD0_G2ARSEN 0x40
10902 #define _COG2ASD0_G2ASREN 0x40
10903 #define _COG2ASD0_ASE 0x80
10904 #define _COG2ASD0_G2ASE 0x80
10906 //==============================================================================
10909 //==============================================================================
10912 extern __at(0x071E) __sfr COG2ASD1
;
10930 unsigned G2AS0E
: 1;
10931 unsigned G2AS1E
: 1;
10932 unsigned G2AS2E
: 1;
10933 unsigned G2AS3E
: 1;
10934 unsigned G2AS4E
: 1;
10935 unsigned G2AS5E
: 1;
10936 unsigned G2AS6E
: 1;
10937 unsigned G2AS7E
: 1;
10939 } __COG2ASD1bits_t
;
10941 extern __at(0x071E) volatile __COG2ASD1bits_t COG2ASD1bits
;
10943 #define _COG2ASD1_AS0E 0x01
10944 #define _COG2ASD1_G2AS0E 0x01
10945 #define _COG2ASD1_AS1E 0x02
10946 #define _COG2ASD1_G2AS1E 0x02
10947 #define _COG2ASD1_AS2E 0x04
10948 #define _COG2ASD1_G2AS2E 0x04
10949 #define _COG2ASD1_AS3E 0x08
10950 #define _COG2ASD1_G2AS3E 0x08
10951 #define _COG2ASD1_AS4E 0x10
10952 #define _COG2ASD1_G2AS4E 0x10
10953 #define _COG2ASD1_AS5E 0x20
10954 #define _COG2ASD1_G2AS5E 0x20
10955 #define _COG2ASD1_AS6E 0x40
10956 #define _COG2ASD1_G2AS6E 0x40
10957 #define _COG2ASD1_AS7E 0x80
10958 #define _COG2ASD1_G2AS7E 0x80
10960 //==============================================================================
10963 //==============================================================================
10966 extern __at(0x071F) __sfr COG2STR
;
10976 unsigned SDATA
: 1;
10977 unsigned SDATB
: 1;
10978 unsigned SDATC
: 1;
10979 unsigned SDATD
: 1;
10984 unsigned G2STRA
: 1;
10985 unsigned G2STRB
: 1;
10986 unsigned G2STRC
: 1;
10987 unsigned G2STRD
: 1;
10988 unsigned G2SDATA
: 1;
10989 unsigned G2SDATB
: 1;
10990 unsigned G2SDATC
: 1;
10991 unsigned G2SDATD
: 1;
10995 extern __at(0x071F) volatile __COG2STRbits_t COG2STRbits
;
10997 #define _COG2STR_STRA 0x01
10998 #define _COG2STR_G2STRA 0x01
10999 #define _COG2STR_STRB 0x02
11000 #define _COG2STR_G2STRB 0x02
11001 #define _COG2STR_STRC 0x04
11002 #define _COG2STR_G2STRC 0x04
11003 #define _COG2STR_STRD 0x08
11004 #define _COG2STR_G2STRD 0x08
11005 #define _COG2STR_SDATA 0x10
11006 #define _COG2STR_G2SDATA 0x10
11007 #define _COG2STR_SDATB 0x20
11008 #define _COG2STR_G2SDATB 0x20
11009 #define _COG2STR_SDATC 0x40
11010 #define _COG2STR_G2SDATC 0x40
11011 #define _COG2STR_SDATD 0x80
11012 #define _COG2STR_G2SDATD 0x80
11014 //==============================================================================
11017 //==============================================================================
11020 extern __at(0x0794) __sfr PRG1RTSS
;
11026 unsigned RTSS0
: 1;
11027 unsigned RTSS1
: 1;
11028 unsigned RTSS2
: 1;
11029 unsigned RTSS3
: 1;
11038 unsigned RG1RTSS0
: 1;
11039 unsigned RG1RTSS1
: 1;
11040 unsigned RG1RTSS2
: 1;
11041 unsigned RG1RTSS3
: 1;
11056 unsigned RG1RTSS
: 4;
11059 } __PRG1RTSSbits_t
;
11061 extern __at(0x0794) volatile __PRG1RTSSbits_t PRG1RTSSbits
;
11063 #define _RTSS0 0x01
11064 #define _RG1RTSS0 0x01
11065 #define _RTSS1 0x02
11066 #define _RG1RTSS1 0x02
11067 #define _RTSS2 0x04
11068 #define _RG1RTSS2 0x04
11069 #define _RTSS3 0x08
11070 #define _RG1RTSS3 0x08
11072 //==============================================================================
11075 //==============================================================================
11078 extern __at(0x0795) __sfr PRG1FTSS
;
11084 unsigned FTSS0
: 1;
11085 unsigned FTSS1
: 1;
11086 unsigned FTSS2
: 1;
11087 unsigned FTSS3
: 1;
11096 unsigned RG1FTSS0
: 1;
11097 unsigned RG1FTSS1
: 1;
11098 unsigned RG1FTSS2
: 1;
11099 unsigned RG1FTSS3
: 1;
11114 unsigned RG1FTSS
: 4;
11117 } __PRG1FTSSbits_t
;
11119 extern __at(0x0795) volatile __PRG1FTSSbits_t PRG1FTSSbits
;
11121 #define _FTSS0 0x01
11122 #define _RG1FTSS0 0x01
11123 #define _FTSS1 0x02
11124 #define _RG1FTSS1 0x02
11125 #define _FTSS2 0x04
11126 #define _RG1FTSS2 0x04
11127 #define _FTSS3 0x08
11128 #define _RG1FTSS3 0x08
11130 //==============================================================================
11133 //==============================================================================
11136 extern __at(0x0796) __sfr PRG1INS
;
11154 unsigned RG1INS0
: 1;
11155 unsigned RG1INS1
: 1;
11156 unsigned RG1INS2
: 1;
11157 unsigned RG1INS3
: 1;
11166 unsigned RG1INS
: 4;
11177 extern __at(0x0796) volatile __PRG1INSbits_t PRG1INSbits
;
11180 #define _RG1INS0 0x01
11182 #define _RG1INS1 0x02
11184 #define _RG1INS2 0x04
11186 #define _RG1INS3 0x08
11188 //==============================================================================
11191 //==============================================================================
11194 extern __at(0x0797) __sfr PRG1CON0
;
11202 unsigned MODE0
: 1;
11203 unsigned MODE1
: 1;
11212 unsigned RG1GO
: 1;
11213 unsigned RG1OS
: 1;
11214 unsigned RG1MODE0
: 1;
11215 unsigned RG1MODE1
: 1;
11216 unsigned RG1REDG
: 1;
11217 unsigned RG1FEDG
: 1;
11219 unsigned RG1EN
: 1;
11232 unsigned RG1MODE
: 2;
11235 } __PRG1CON0bits_t
;
11237 extern __at(0x0797) volatile __PRG1CON0bits_t PRG1CON0bits
;
11239 #define _PRG1CON0_GO 0x01
11240 #define _PRG1CON0_RG1GO 0x01
11241 #define _PRG1CON0_OS 0x02
11242 #define _PRG1CON0_RG1OS 0x02
11243 #define _PRG1CON0_MODE0 0x04
11244 #define _PRG1CON0_RG1MODE0 0x04
11245 #define _PRG1CON0_MODE1 0x08
11246 #define _PRG1CON0_RG1MODE1 0x08
11247 #define _PRG1CON0_REDG 0x10
11248 #define _PRG1CON0_RG1REDG 0x10
11249 #define _PRG1CON0_FEDG 0x20
11250 #define _PRG1CON0_RG1FEDG 0x20
11251 #define _PRG1CON0_EN 0x80
11252 #define _PRG1CON0_RG1EN 0x80
11254 //==============================================================================
11257 //==============================================================================
11260 extern __at(0x0798) __sfr PRG1CON1
;
11278 unsigned RG1RPOL
: 1;
11279 unsigned RG1FPOL
: 1;
11280 unsigned RG1RDY
: 1;
11287 } __PRG1CON1bits_t
;
11289 extern __at(0x0798) volatile __PRG1CON1bits_t PRG1CON1bits
;
11292 #define _RG1RPOL 0x01
11294 #define _RG1FPOL 0x02
11296 #define _RG1RDY 0x04
11298 //==============================================================================
11301 //==============================================================================
11304 extern __at(0x0799) __sfr PRG1CON2
;
11310 unsigned ISET0
: 1;
11311 unsigned ISET1
: 1;
11312 unsigned ISET2
: 1;
11313 unsigned ISET3
: 1;
11314 unsigned ISET4
: 1;
11322 unsigned RG1ISET0
: 1;
11323 unsigned RG1ISET1
: 1;
11324 unsigned RG1ISET2
: 1;
11325 unsigned RG1ISET3
: 1;
11326 unsigned RG1ISET4
: 1;
11340 unsigned RG1ISET
: 5;
11343 } __PRG1CON2bits_t
;
11345 extern __at(0x0799) volatile __PRG1CON2bits_t PRG1CON2bits
;
11347 #define _ISET0 0x01
11348 #define _RG1ISET0 0x01
11349 #define _ISET1 0x02
11350 #define _RG1ISET1 0x02
11351 #define _ISET2 0x04
11352 #define _RG1ISET2 0x04
11353 #define _ISET3 0x08
11354 #define _RG1ISET3 0x08
11355 #define _ISET4 0x10
11356 #define _RG1ISET4 0x10
11358 //==============================================================================
11361 //==============================================================================
11364 extern __at(0x079A) __sfr PRG2RTSS
;
11370 unsigned RTSS0
: 1;
11371 unsigned RTSS1
: 1;
11372 unsigned RTSS2
: 1;
11373 unsigned RTSS3
: 1;
11382 unsigned RG2RTSS0
: 1;
11383 unsigned RG2RTSS1
: 1;
11384 unsigned RG2RTSS2
: 1;
11385 unsigned RG2RTSS3
: 1;
11394 unsigned RG2RTSS
: 4;
11403 } __PRG2RTSSbits_t
;
11405 extern __at(0x079A) volatile __PRG2RTSSbits_t PRG2RTSSbits
;
11407 #define _PRG2RTSS_RTSS0 0x01
11408 #define _PRG2RTSS_RG2RTSS0 0x01
11409 #define _PRG2RTSS_RTSS1 0x02
11410 #define _PRG2RTSS_RG2RTSS1 0x02
11411 #define _PRG2RTSS_RTSS2 0x04
11412 #define _PRG2RTSS_RG2RTSS2 0x04
11413 #define _PRG2RTSS_RTSS3 0x08
11414 #define _PRG2RTSS_RG2RTSS3 0x08
11416 //==============================================================================
11419 //==============================================================================
11422 extern __at(0x079B) __sfr PRG2FTSS
;
11428 unsigned FTSS0
: 1;
11429 unsigned FTSS1
: 1;
11430 unsigned FTSS2
: 1;
11431 unsigned FTSS3
: 1;
11440 unsigned RG2FTSS0
: 1;
11441 unsigned RG2FTSS1
: 1;
11442 unsigned RG2FTSS2
: 1;
11443 unsigned RG2FTSS3
: 1;
11458 unsigned RG2FTSS
: 4;
11461 } __PRG2FTSSbits_t
;
11463 extern __at(0x079B) volatile __PRG2FTSSbits_t PRG2FTSSbits
;
11465 #define _PRG2FTSS_FTSS0 0x01
11466 #define _PRG2FTSS_RG2FTSS0 0x01
11467 #define _PRG2FTSS_FTSS1 0x02
11468 #define _PRG2FTSS_RG2FTSS1 0x02
11469 #define _PRG2FTSS_FTSS2 0x04
11470 #define _PRG2FTSS_RG2FTSS2 0x04
11471 #define _PRG2FTSS_FTSS3 0x08
11472 #define _PRG2FTSS_RG2FTSS3 0x08
11474 //==============================================================================
11477 //==============================================================================
11480 extern __at(0x079C) __sfr PRG2INS
;
11498 unsigned RG2INS0
: 1;
11499 unsigned RG2INS1
: 1;
11500 unsigned RG2INS2
: 1;
11501 unsigned RG2INS3
: 1;
11510 unsigned RG2INS
: 4;
11521 extern __at(0x079C) volatile __PRG2INSbits_t PRG2INSbits
;
11523 #define _PRG2INS_INS0 0x01
11524 #define _PRG2INS_RG2INS0 0x01
11525 #define _PRG2INS_INS1 0x02
11526 #define _PRG2INS_RG2INS1 0x02
11527 #define _PRG2INS_INS2 0x04
11528 #define _PRG2INS_RG2INS2 0x04
11529 #define _PRG2INS_INS3 0x08
11530 #define _PRG2INS_RG2INS3 0x08
11532 //==============================================================================
11535 //==============================================================================
11538 extern __at(0x079D) __sfr PRG2CON0
;
11546 unsigned MODE0
: 1;
11547 unsigned MODE1
: 1;
11556 unsigned RG2GO
: 1;
11557 unsigned RG2OS
: 1;
11558 unsigned RG2MODE0
: 1;
11559 unsigned RG2MODE1
: 1;
11560 unsigned RG2REDG
: 1;
11561 unsigned RG2FEDG
: 1;
11563 unsigned RG2EN
: 1;
11569 unsigned RG2MODE
: 2;
11579 } __PRG2CON0bits_t
;
11581 extern __at(0x079D) volatile __PRG2CON0bits_t PRG2CON0bits
;
11583 #define _PRG2CON0_GO 0x01
11584 #define _PRG2CON0_RG2GO 0x01
11585 #define _PRG2CON0_OS 0x02
11586 #define _PRG2CON0_RG2OS 0x02
11587 #define _PRG2CON0_MODE0 0x04
11588 #define _PRG2CON0_RG2MODE0 0x04
11589 #define _PRG2CON0_MODE1 0x08
11590 #define _PRG2CON0_RG2MODE1 0x08
11591 #define _PRG2CON0_REDG 0x10
11592 #define _PRG2CON0_RG2REDG 0x10
11593 #define _PRG2CON0_FEDG 0x20
11594 #define _PRG2CON0_RG2FEDG 0x20
11595 #define _PRG2CON0_EN 0x80
11596 #define _PRG2CON0_RG2EN 0x80
11598 //==============================================================================
11601 //==============================================================================
11604 extern __at(0x079E) __sfr PRG2CON1
;
11622 unsigned RG2RPOL
: 1;
11623 unsigned RG2FPOL
: 1;
11624 unsigned RG2RDY
: 1;
11631 } __PRG2CON1bits_t
;
11633 extern __at(0x079E) volatile __PRG2CON1bits_t PRG2CON1bits
;
11635 #define _PRG2CON1_RPOL 0x01
11636 #define _PRG2CON1_RG2RPOL 0x01
11637 #define _PRG2CON1_FPOL 0x02
11638 #define _PRG2CON1_RG2FPOL 0x02
11639 #define _PRG2CON1_RDY 0x04
11640 #define _PRG2CON1_RG2RDY 0x04
11642 //==============================================================================
11645 //==============================================================================
11648 extern __at(0x079F) __sfr PRG2CON2
;
11654 unsigned ISET0
: 1;
11655 unsigned ISET1
: 1;
11656 unsigned ISET2
: 1;
11657 unsigned ISET3
: 1;
11658 unsigned ISET4
: 1;
11666 unsigned RG2ISET0
: 1;
11667 unsigned RG2ISET1
: 1;
11668 unsigned RG2ISET2
: 1;
11669 unsigned RG2ISET3
: 1;
11670 unsigned RG2ISET4
: 1;
11678 unsigned RG2ISET
: 5;
11687 } __PRG2CON2bits_t
;
11689 extern __at(0x079F) volatile __PRG2CON2bits_t PRG2CON2bits
;
11691 #define _PRG2CON2_ISET0 0x01
11692 #define _PRG2CON2_RG2ISET0 0x01
11693 #define _PRG2CON2_ISET1 0x02
11694 #define _PRG2CON2_RG2ISET1 0x02
11695 #define _PRG2CON2_ISET2 0x04
11696 #define _PRG2CON2_RG2ISET2 0x04
11697 #define _PRG2CON2_ISET3 0x08
11698 #define _PRG2CON2_RG2ISET3 0x08
11699 #define _PRG2CON2_ISET4 0x10
11700 #define _PRG2CON2_RG2ISET4 0x10
11702 //==============================================================================
11705 //==============================================================================
11708 extern __at(0x0D8E) __sfr PWMEN
;
11716 unsigned MPWM5EN
: 1;
11717 unsigned MPWM6EN
: 1;
11722 extern __at(0x0D8E) volatile __PWMENbits_t PWMENbits
;
11724 #define _MPWM5EN 0x10
11725 #define _MPWM6EN 0x20
11727 //==============================================================================
11730 //==============================================================================
11733 extern __at(0x0D8F) __sfr PWMLD
;
11741 unsigned MPWM5LD
: 1;
11742 unsigned MPWM6LD
: 1;
11747 extern __at(0x0D8F) volatile __PWMLDbits_t PWMLDbits
;
11749 #define _MPWM5LD 0x10
11750 #define _MPWM6LD 0x20
11752 //==============================================================================
11755 //==============================================================================
11758 extern __at(0x0D90) __sfr PWMOUT
;
11766 unsigned MPWM5OUT
: 1;
11767 unsigned MPWM6OUT
: 1;
11772 extern __at(0x0D90) volatile __PWMOUTbits_t PWMOUTbits
;
11774 #define _MPWM5OUT 0x10
11775 #define _MPWM6OUT 0x20
11777 //==============================================================================
11779 extern __at(0x0D91) __sfr PWM5PH
;
11781 //==============================================================================
11784 extern __at(0x0D91) __sfr PWM5PHL
;
11788 unsigned PWM5PHL0
: 1;
11789 unsigned PWM5PHL1
: 1;
11790 unsigned PWM5PHL2
: 1;
11791 unsigned PWM5PHL3
: 1;
11792 unsigned PWM5PHL4
: 1;
11793 unsigned PWM5PHL5
: 1;
11794 unsigned PWM5PHL6
: 1;
11795 unsigned PWM5PHL7
: 1;
11798 extern __at(0x0D91) volatile __PWM5PHLbits_t PWM5PHLbits
;
11800 #define _PWM5PHL0 0x01
11801 #define _PWM5PHL1 0x02
11802 #define _PWM5PHL2 0x04
11803 #define _PWM5PHL3 0x08
11804 #define _PWM5PHL4 0x10
11805 #define _PWM5PHL5 0x20
11806 #define _PWM5PHL6 0x40
11807 #define _PWM5PHL7 0x80
11809 //==============================================================================
11812 //==============================================================================
11815 extern __at(0x0D92) __sfr PWM5PHH
;
11819 unsigned PWM5PHH0
: 1;
11820 unsigned PWM5PHH1
: 1;
11821 unsigned PWM5PHH2
: 1;
11822 unsigned PWM5PHH3
: 1;
11823 unsigned PWM5PHH4
: 1;
11824 unsigned PWM5PHH5
: 1;
11825 unsigned PWM5PHH6
: 1;
11826 unsigned PWM5PHH7
: 1;
11829 extern __at(0x0D92) volatile __PWM5PHHbits_t PWM5PHHbits
;
11831 #define _PWM5PHH0 0x01
11832 #define _PWM5PHH1 0x02
11833 #define _PWM5PHH2 0x04
11834 #define _PWM5PHH3 0x08
11835 #define _PWM5PHH4 0x10
11836 #define _PWM5PHH5 0x20
11837 #define _PWM5PHH6 0x40
11838 #define _PWM5PHH7 0x80
11840 //==============================================================================
11842 extern __at(0x0D93) __sfr PWM5DC
;
11844 //==============================================================================
11847 extern __at(0x0D93) __sfr PWM5DCL
;
11851 unsigned PWM5DCL0
: 1;
11852 unsigned PWM5DCL1
: 1;
11853 unsigned PWM5DCL2
: 1;
11854 unsigned PWM5DCL3
: 1;
11855 unsigned PWM5DCL4
: 1;
11856 unsigned PWM5DCL5
: 1;
11857 unsigned PWM5DCL6
: 1;
11858 unsigned PWM5DCL7
: 1;
11861 extern __at(0x0D93) volatile __PWM5DCLbits_t PWM5DCLbits
;
11863 #define _PWM5DCL0 0x01
11864 #define _PWM5DCL1 0x02
11865 #define _PWM5DCL2 0x04
11866 #define _PWM5DCL3 0x08
11867 #define _PWM5DCL4 0x10
11868 #define _PWM5DCL5 0x20
11869 #define _PWM5DCL6 0x40
11870 #define _PWM5DCL7 0x80
11872 //==============================================================================
11875 //==============================================================================
11878 extern __at(0x0D94) __sfr PWM5DCH
;
11882 unsigned PWM5DCH0
: 1;
11883 unsigned PWM5DCH1
: 1;
11884 unsigned PWM5DCH2
: 1;
11885 unsigned PWM5DCH3
: 1;
11886 unsigned PWM5DCH4
: 1;
11887 unsigned PWM5DCH5
: 1;
11888 unsigned PWM5DCH6
: 1;
11889 unsigned PWM5DCH7
: 1;
11892 extern __at(0x0D94) volatile __PWM5DCHbits_t PWM5DCHbits
;
11894 #define _PWM5DCH0 0x01
11895 #define _PWM5DCH1 0x02
11896 #define _PWM5DCH2 0x04
11897 #define _PWM5DCH3 0x08
11898 #define _PWM5DCH4 0x10
11899 #define _PWM5DCH5 0x20
11900 #define _PWM5DCH6 0x40
11901 #define _PWM5DCH7 0x80
11903 //==============================================================================
11905 extern __at(0x0D95) __sfr PWM5PR
;
11907 //==============================================================================
11910 extern __at(0x0D95) __sfr PWM5PRL
;
11914 unsigned PWM5PRL0
: 1;
11915 unsigned PWM5PRL1
: 1;
11916 unsigned PWM5PRL2
: 1;
11917 unsigned PWM5PRL3
: 1;
11918 unsigned PWM5PRL4
: 1;
11919 unsigned PWM5PRL5
: 1;
11920 unsigned PWM5PRL6
: 1;
11921 unsigned PWM5PRL7
: 1;
11924 extern __at(0x0D95) volatile __PWM5PRLbits_t PWM5PRLbits
;
11926 #define _PWM5PRL0 0x01
11927 #define _PWM5PRL1 0x02
11928 #define _PWM5PRL2 0x04
11929 #define _PWM5PRL3 0x08
11930 #define _PWM5PRL4 0x10
11931 #define _PWM5PRL5 0x20
11932 #define _PWM5PRL6 0x40
11933 #define _PWM5PRL7 0x80
11935 //==============================================================================
11938 //==============================================================================
11941 extern __at(0x0D96) __sfr PWM5PRH
;
11945 unsigned PWM5PRH0
: 1;
11946 unsigned PWM5PRH1
: 1;
11947 unsigned PWM5PRH2
: 1;
11948 unsigned PWM5PRH3
: 1;
11949 unsigned PWM5PRH4
: 1;
11950 unsigned PWM5PRH5
: 1;
11951 unsigned PWM5PRH6
: 1;
11952 unsigned PWM5PRH7
: 1;
11955 extern __at(0x0D96) volatile __PWM5PRHbits_t PWM5PRHbits
;
11957 #define _PWM5PRH0 0x01
11958 #define _PWM5PRH1 0x02
11959 #define _PWM5PRH2 0x04
11960 #define _PWM5PRH3 0x08
11961 #define _PWM5PRH4 0x10
11962 #define _PWM5PRH5 0x20
11963 #define _PWM5PRH6 0x40
11964 #define _PWM5PRH7 0x80
11966 //==============================================================================
11968 extern __at(0x0D97) __sfr PWM5OF
;
11970 //==============================================================================
11973 extern __at(0x0D97) __sfr PWM5OFL
;
11977 unsigned PWM5OFL0
: 1;
11978 unsigned PWM5OFL1
: 1;
11979 unsigned PWM5OFL2
: 1;
11980 unsigned PWM5OFL3
: 1;
11981 unsigned PWM5OFL4
: 1;
11982 unsigned PWM5OFL5
: 1;
11983 unsigned PWM5OFL6
: 1;
11984 unsigned PWM5OFL7
: 1;
11987 extern __at(0x0D97) volatile __PWM5OFLbits_t PWM5OFLbits
;
11989 #define _PWM5OFL0 0x01
11990 #define _PWM5OFL1 0x02
11991 #define _PWM5OFL2 0x04
11992 #define _PWM5OFL3 0x08
11993 #define _PWM5OFL4 0x10
11994 #define _PWM5OFL5 0x20
11995 #define _PWM5OFL6 0x40
11996 #define _PWM5OFL7 0x80
11998 //==============================================================================
12001 //==============================================================================
12004 extern __at(0x0D98) __sfr PWM5OFH
;
12008 unsigned PWM5OFH0
: 1;
12009 unsigned PWM5OFH1
: 1;
12010 unsigned PWM5OFH2
: 1;
12011 unsigned PWM5OFH3
: 1;
12012 unsigned PWM5OFH4
: 1;
12013 unsigned PWM5OFH5
: 1;
12014 unsigned PWM5OFH6
: 1;
12015 unsigned PWM5OFH7
: 1;
12018 extern __at(0x0D98) volatile __PWM5OFHbits_t PWM5OFHbits
;
12020 #define _PWM5OFH0 0x01
12021 #define _PWM5OFH1 0x02
12022 #define _PWM5OFH2 0x04
12023 #define _PWM5OFH3 0x08
12024 #define _PWM5OFH4 0x10
12025 #define _PWM5OFH5 0x20
12026 #define _PWM5OFH6 0x40
12027 #define _PWM5OFH7 0x80
12029 //==============================================================================
12031 extern __at(0x0D99) __sfr PWM5TMR
;
12033 //==============================================================================
12036 extern __at(0x0D99) __sfr PWM5TMRL
;
12040 unsigned PWM5TMRL0
: 1;
12041 unsigned PWM5TMRL1
: 1;
12042 unsigned PWM5TMRL2
: 1;
12043 unsigned PWM5TMRL3
: 1;
12044 unsigned PWM5TMRL4
: 1;
12045 unsigned PWM5TMRL5
: 1;
12046 unsigned PWM5TMRL6
: 1;
12047 unsigned PWM5TMRL7
: 1;
12048 } __PWM5TMRLbits_t
;
12050 extern __at(0x0D99) volatile __PWM5TMRLbits_t PWM5TMRLbits
;
12052 #define _PWM5TMRL0 0x01
12053 #define _PWM5TMRL1 0x02
12054 #define _PWM5TMRL2 0x04
12055 #define _PWM5TMRL3 0x08
12056 #define _PWM5TMRL4 0x10
12057 #define _PWM5TMRL5 0x20
12058 #define _PWM5TMRL6 0x40
12059 #define _PWM5TMRL7 0x80
12061 //==============================================================================
12064 //==============================================================================
12067 extern __at(0x0D9A) __sfr PWM5TMRH
;
12071 unsigned PWM5TMRH0
: 1;
12072 unsigned PWM5TMRH1
: 1;
12073 unsigned PWM5TMRH2
: 1;
12074 unsigned PWM5TMRH3
: 1;
12075 unsigned PWM5TMRH4
: 1;
12076 unsigned PWM5TMRH5
: 1;
12077 unsigned PWM5TMRH6
: 1;
12078 unsigned PWM5TMRH7
: 1;
12079 } __PWM5TMRHbits_t
;
12081 extern __at(0x0D9A) volatile __PWM5TMRHbits_t PWM5TMRHbits
;
12083 #define _PWM5TMRH0 0x01
12084 #define _PWM5TMRH1 0x02
12085 #define _PWM5TMRH2 0x04
12086 #define _PWM5TMRH3 0x08
12087 #define _PWM5TMRH4 0x10
12088 #define _PWM5TMRH5 0x20
12089 #define _PWM5TMRH6 0x40
12090 #define _PWM5TMRH7 0x80
12092 //==============================================================================
12095 //==============================================================================
12098 extern __at(0x0D9B) __sfr PWM5CON
;
12106 unsigned PWM5MODE0
: 1;
12107 unsigned PWM5MODE1
: 1;
12118 unsigned MODE0
: 1;
12119 unsigned MODE1
: 1;
12120 unsigned PWM5POL
: 1;
12121 unsigned PWM5OUT
: 1;
12123 unsigned PWM5EN
: 1;
12136 unsigned PWM5MODE
: 2;
12141 extern __at(0x0D9B) volatile __PWM5CONbits_t PWM5CONbits
;
12143 #define _PWM5CON_PWM5MODE0 0x04
12144 #define _PWM5CON_MODE0 0x04
12145 #define _PWM5CON_PWM5MODE1 0x08
12146 #define _PWM5CON_MODE1 0x08
12147 #define _PWM5CON_POL 0x10
12148 #define _PWM5CON_PWM5POL 0x10
12149 #define _PWM5CON_OUT 0x20
12150 #define _PWM5CON_PWM5OUT 0x20
12151 #define _PWM5CON_EN 0x80
12152 #define _PWM5CON_PWM5EN 0x80
12154 //==============================================================================
12157 //==============================================================================
12160 extern __at(0x0D9C) __sfr PWM5INTCON
;
12178 unsigned PWM5PRIE
: 1;
12179 unsigned PWM5DCIE
: 1;
12180 unsigned PWM5PHIE
: 1;
12181 unsigned PWM5OFIE
: 1;
12187 } __PWM5INTCONbits_t
;
12189 extern __at(0x0D9C) volatile __PWM5INTCONbits_t PWM5INTCONbits
;
12192 #define _PWM5PRIE 0x01
12194 #define _PWM5DCIE 0x02
12196 #define _PWM5PHIE 0x04
12198 #define _PWM5OFIE 0x08
12200 //==============================================================================
12203 //==============================================================================
12206 extern __at(0x0D9C) __sfr PWM5INTE
;
12224 unsigned PWM5PRIE
: 1;
12225 unsigned PWM5DCIE
: 1;
12226 unsigned PWM5PHIE
: 1;
12227 unsigned PWM5OFIE
: 1;
12233 } __PWM5INTEbits_t
;
12235 extern __at(0x0D9C) volatile __PWM5INTEbits_t PWM5INTEbits
;
12237 #define _PWM5INTE_PRIE 0x01
12238 #define _PWM5INTE_PWM5PRIE 0x01
12239 #define _PWM5INTE_DCIE 0x02
12240 #define _PWM5INTE_PWM5DCIE 0x02
12241 #define _PWM5INTE_PHIE 0x04
12242 #define _PWM5INTE_PWM5PHIE 0x04
12243 #define _PWM5INTE_OFIE 0x08
12244 #define _PWM5INTE_PWM5OFIE 0x08
12246 //==============================================================================
12249 //==============================================================================
12252 extern __at(0x0D9D) __sfr PWM5INTF
;
12270 unsigned PWM5PRIF
: 1;
12271 unsigned PWM5DCIF
: 1;
12272 unsigned PWM5PHIF
: 1;
12273 unsigned PWM5OFIF
: 1;
12279 } __PWM5INTFbits_t
;
12281 extern __at(0x0D9D) volatile __PWM5INTFbits_t PWM5INTFbits
;
12284 #define _PWM5PRIF 0x01
12286 #define _PWM5DCIF 0x02
12288 #define _PWM5PHIF 0x04
12290 #define _PWM5OFIF 0x08
12292 //==============================================================================
12295 //==============================================================================
12298 extern __at(0x0D9D) __sfr PWM5INTFLG
;
12316 unsigned PWM5PRIF
: 1;
12317 unsigned PWM5DCIF
: 1;
12318 unsigned PWM5PHIF
: 1;
12319 unsigned PWM5OFIF
: 1;
12325 } __PWM5INTFLGbits_t
;
12327 extern __at(0x0D9D) volatile __PWM5INTFLGbits_t PWM5INTFLGbits
;
12329 #define _PWM5INTFLG_PRIF 0x01
12330 #define _PWM5INTFLG_PWM5PRIF 0x01
12331 #define _PWM5INTFLG_DCIF 0x02
12332 #define _PWM5INTFLG_PWM5DCIF 0x02
12333 #define _PWM5INTFLG_PHIF 0x04
12334 #define _PWM5INTFLG_PWM5PHIF 0x04
12335 #define _PWM5INTFLG_OFIF 0x08
12336 #define _PWM5INTFLG_PWM5OFIF 0x08
12338 //==============================================================================
12341 //==============================================================================
12344 extern __at(0x0D9E) __sfr PWM5CLKCON
;
12350 unsigned PWM5CS0
: 1;
12351 unsigned PWM5CS1
: 1;
12352 unsigned PWM5CS2
: 1;
12354 unsigned PWM5PS0
: 1;
12355 unsigned PWM5PS1
: 1;
12356 unsigned PWM5PS2
: 1;
12374 unsigned PWM5CS
: 3;
12387 unsigned PWM5PS
: 3;
12397 } __PWM5CLKCONbits_t
;
12399 extern __at(0x0D9E) volatile __PWM5CLKCONbits_t PWM5CLKCONbits
;
12401 #define _PWM5CLKCON_PWM5CS0 0x01
12402 #define _PWM5CLKCON_CS0 0x01
12403 #define _PWM5CLKCON_PWM5CS1 0x02
12404 #define _PWM5CLKCON_CS1 0x02
12405 #define _PWM5CLKCON_PWM5CS2 0x04
12406 #define _PWM5CLKCON_CS2 0x04
12407 #define _PWM5CLKCON_PWM5PS0 0x10
12408 #define _PWM5CLKCON_PS0 0x10
12409 #define _PWM5CLKCON_PWM5PS1 0x20
12410 #define _PWM5CLKCON_PS1 0x20
12411 #define _PWM5CLKCON_PWM5PS2 0x40
12412 #define _PWM5CLKCON_PS2 0x40
12414 //==============================================================================
12417 //==============================================================================
12420 extern __at(0x0D9F) __sfr PWM5LDCON
;
12426 unsigned PWM5LDS0
: 1;
12444 unsigned PWM5LDM
: 1;
12445 unsigned PWM5LD
: 1;
12447 } __PWM5LDCONbits_t
;
12449 extern __at(0x0D9F) volatile __PWM5LDCONbits_t PWM5LDCONbits
;
12451 #define _PWM5LDS0 0x01
12454 #define _PWM5LDM 0x40
12456 #define _PWM5LD 0x80
12458 //==============================================================================
12461 //==============================================================================
12464 extern __at(0x0DA0) __sfr PWM5OFCON
;
12470 unsigned PWM5OFS0
: 1;
12475 unsigned PWM5OFM0
: 1;
12476 unsigned PWM5OFM1
: 1;
12486 unsigned PWM5OFMC
: 1;
12502 unsigned PWM5OFM
: 2;
12505 } __PWM5OFCONbits_t
;
12507 extern __at(0x0DA0) volatile __PWM5OFCONbits_t PWM5OFCONbits
;
12509 #define _PWM5OFS0 0x01
12512 #define _PWM5OFMC 0x10
12513 #define _PWM5OFM0 0x20
12515 #define _PWM5OFM1 0x40
12518 //==============================================================================
12520 extern __at(0x0DA1) __sfr PWM6PH
;
12522 //==============================================================================
12525 extern __at(0x0DA1) __sfr PWM6PHL
;
12529 unsigned PWM6PHL0
: 1;
12530 unsigned PWM6PHL1
: 1;
12531 unsigned PWM6PHL2
: 1;
12532 unsigned PWM6PHL3
: 1;
12533 unsigned PWM6PHL4
: 1;
12534 unsigned PWM6PHL5
: 1;
12535 unsigned PWM6PHL6
: 1;
12536 unsigned PWM6PHL7
: 1;
12539 extern __at(0x0DA1) volatile __PWM6PHLbits_t PWM6PHLbits
;
12541 #define _PWM6PHL0 0x01
12542 #define _PWM6PHL1 0x02
12543 #define _PWM6PHL2 0x04
12544 #define _PWM6PHL3 0x08
12545 #define _PWM6PHL4 0x10
12546 #define _PWM6PHL5 0x20
12547 #define _PWM6PHL6 0x40
12548 #define _PWM6PHL7 0x80
12550 //==============================================================================
12553 //==============================================================================
12556 extern __at(0x0DA2) __sfr PWM6PHH
;
12560 unsigned PWM6PHH0
: 1;
12561 unsigned PWM6PHH1
: 1;
12562 unsigned PWM6PHH2
: 1;
12563 unsigned PWM6PHH3
: 1;
12564 unsigned PWM6PHH4
: 1;
12565 unsigned PWM6PHH5
: 1;
12566 unsigned PWM6PHH6
: 1;
12567 unsigned PWM6PHH7
: 1;
12570 extern __at(0x0DA2) volatile __PWM6PHHbits_t PWM6PHHbits
;
12572 #define _PWM6PHH0 0x01
12573 #define _PWM6PHH1 0x02
12574 #define _PWM6PHH2 0x04
12575 #define _PWM6PHH3 0x08
12576 #define _PWM6PHH4 0x10
12577 #define _PWM6PHH5 0x20
12578 #define _PWM6PHH6 0x40
12579 #define _PWM6PHH7 0x80
12581 //==============================================================================
12583 extern __at(0x0DA3) __sfr PWM6DC
;
12585 //==============================================================================
12588 extern __at(0x0DA3) __sfr PWM6DCL
;
12592 unsigned PWM6DCL0
: 1;
12593 unsigned PWM6DCL1
: 1;
12594 unsigned PWM6DCL2
: 1;
12595 unsigned PWM6DCL3
: 1;
12596 unsigned PWM6DCL4
: 1;
12597 unsigned PWM6DCL5
: 1;
12598 unsigned PWM6DCL6
: 1;
12599 unsigned PWM6DCL7
: 1;
12602 extern __at(0x0DA3) volatile __PWM6DCLbits_t PWM6DCLbits
;
12604 #define _PWM6DCL0 0x01
12605 #define _PWM6DCL1 0x02
12606 #define _PWM6DCL2 0x04
12607 #define _PWM6DCL3 0x08
12608 #define _PWM6DCL4 0x10
12609 #define _PWM6DCL5 0x20
12610 #define _PWM6DCL6 0x40
12611 #define _PWM6DCL7 0x80
12613 //==============================================================================
12616 //==============================================================================
12619 extern __at(0x0DA4) __sfr PWM6DCH
;
12623 unsigned PWM6DCH0
: 1;
12624 unsigned PWM6DCH1
: 1;
12625 unsigned PWM6DCH2
: 1;
12626 unsigned PWM6DCH3
: 1;
12627 unsigned PWM6DCH4
: 1;
12628 unsigned PWM6DCH5
: 1;
12629 unsigned PWM6DCH6
: 1;
12630 unsigned PWM6DCH7
: 1;
12633 extern __at(0x0DA4) volatile __PWM6DCHbits_t PWM6DCHbits
;
12635 #define _PWM6DCH0 0x01
12636 #define _PWM6DCH1 0x02
12637 #define _PWM6DCH2 0x04
12638 #define _PWM6DCH3 0x08
12639 #define _PWM6DCH4 0x10
12640 #define _PWM6DCH5 0x20
12641 #define _PWM6DCH6 0x40
12642 #define _PWM6DCH7 0x80
12644 //==============================================================================
12646 extern __at(0x0DA5) __sfr PWM6PR
;
12648 //==============================================================================
12651 extern __at(0x0DA5) __sfr PWM6PRL
;
12655 unsigned PWM6PRL0
: 1;
12656 unsigned PWM6PRL1
: 1;
12657 unsigned PWM6PRL2
: 1;
12658 unsigned PWM6PRL3
: 1;
12659 unsigned PWM6PRL4
: 1;
12660 unsigned PWM6PRL5
: 1;
12661 unsigned PWM6PRL6
: 1;
12662 unsigned PWM6PRL7
: 1;
12665 extern __at(0x0DA5) volatile __PWM6PRLbits_t PWM6PRLbits
;
12667 #define _PWM6PRL0 0x01
12668 #define _PWM6PRL1 0x02
12669 #define _PWM6PRL2 0x04
12670 #define _PWM6PRL3 0x08
12671 #define _PWM6PRL4 0x10
12672 #define _PWM6PRL5 0x20
12673 #define _PWM6PRL6 0x40
12674 #define _PWM6PRL7 0x80
12676 //==============================================================================
12679 //==============================================================================
12682 extern __at(0x0DA6) __sfr PWM6PRH
;
12686 unsigned PWM6PRH0
: 1;
12687 unsigned PWM6PRH1
: 1;
12688 unsigned PWM6PRH2
: 1;
12689 unsigned PWM6PRH3
: 1;
12690 unsigned PWM6PRH4
: 1;
12691 unsigned PWM6PRH5
: 1;
12692 unsigned PWM6PRH6
: 1;
12693 unsigned PWM6PRH7
: 1;
12696 extern __at(0x0DA6) volatile __PWM6PRHbits_t PWM6PRHbits
;
12698 #define _PWM6PRH0 0x01
12699 #define _PWM6PRH1 0x02
12700 #define _PWM6PRH2 0x04
12701 #define _PWM6PRH3 0x08
12702 #define _PWM6PRH4 0x10
12703 #define _PWM6PRH5 0x20
12704 #define _PWM6PRH6 0x40
12705 #define _PWM6PRH7 0x80
12707 //==============================================================================
12709 extern __at(0x0DA7) __sfr PWM6OF
;
12711 //==============================================================================
12714 extern __at(0x0DA7) __sfr PWM6OFL
;
12718 unsigned PWM6OFL0
: 1;
12719 unsigned PWM6OFL1
: 1;
12720 unsigned PWM6OFL2
: 1;
12721 unsigned PWM6OFL3
: 1;
12722 unsigned PWM6OFL4
: 1;
12723 unsigned PWM6OFL5
: 1;
12724 unsigned PWM6OFL6
: 1;
12725 unsigned PWM6OFL7
: 1;
12728 extern __at(0x0DA7) volatile __PWM6OFLbits_t PWM6OFLbits
;
12730 #define _PWM6OFL0 0x01
12731 #define _PWM6OFL1 0x02
12732 #define _PWM6OFL2 0x04
12733 #define _PWM6OFL3 0x08
12734 #define _PWM6OFL4 0x10
12735 #define _PWM6OFL5 0x20
12736 #define _PWM6OFL6 0x40
12737 #define _PWM6OFL7 0x80
12739 //==============================================================================
12742 //==============================================================================
12745 extern __at(0x0DA8) __sfr PWM6OFH
;
12749 unsigned PWM6OFH0
: 1;
12750 unsigned PWM6OFH1
: 1;
12751 unsigned PWM6OFH2
: 1;
12752 unsigned PWM6OFH3
: 1;
12753 unsigned PWM6OFH4
: 1;
12754 unsigned PWM6OFH5
: 1;
12755 unsigned PWM6OFH6
: 1;
12756 unsigned PWM6OFH7
: 1;
12759 extern __at(0x0DA8) volatile __PWM6OFHbits_t PWM6OFHbits
;
12761 #define _PWM6OFH0 0x01
12762 #define _PWM6OFH1 0x02
12763 #define _PWM6OFH2 0x04
12764 #define _PWM6OFH3 0x08
12765 #define _PWM6OFH4 0x10
12766 #define _PWM6OFH5 0x20
12767 #define _PWM6OFH6 0x40
12768 #define _PWM6OFH7 0x80
12770 //==============================================================================
12772 extern __at(0x0DA9) __sfr PWM6TMR
;
12774 //==============================================================================
12777 extern __at(0x0DA9) __sfr PWM6TMRL
;
12781 unsigned PWM6TMRL0
: 1;
12782 unsigned PWM6TMRL1
: 1;
12783 unsigned PWM6TMRL2
: 1;
12784 unsigned PWM6TMRL3
: 1;
12785 unsigned PWM6TMRL4
: 1;
12786 unsigned PWM6TMRL5
: 1;
12787 unsigned PWM6TMRL6
: 1;
12788 unsigned PWM6TMRL7
: 1;
12789 } __PWM6TMRLbits_t
;
12791 extern __at(0x0DA9) volatile __PWM6TMRLbits_t PWM6TMRLbits
;
12793 #define _PWM6TMRL0 0x01
12794 #define _PWM6TMRL1 0x02
12795 #define _PWM6TMRL2 0x04
12796 #define _PWM6TMRL3 0x08
12797 #define _PWM6TMRL4 0x10
12798 #define _PWM6TMRL5 0x20
12799 #define _PWM6TMRL6 0x40
12800 #define _PWM6TMRL7 0x80
12802 //==============================================================================
12805 //==============================================================================
12808 extern __at(0x0DAA) __sfr PWM6TMRH
;
12812 unsigned PWM6TMRH0
: 1;
12813 unsigned PWM6TMRH1
: 1;
12814 unsigned PWM6TMRH2
: 1;
12815 unsigned PWM6TMRH3
: 1;
12816 unsigned PWM6TMRH4
: 1;
12817 unsigned PWM6TMRH5
: 1;
12818 unsigned PWM6TMRH6
: 1;
12819 unsigned PWM6TMRH7
: 1;
12820 } __PWM6TMRHbits_t
;
12822 extern __at(0x0DAA) volatile __PWM6TMRHbits_t PWM6TMRHbits
;
12824 #define _PWM6TMRH0 0x01
12825 #define _PWM6TMRH1 0x02
12826 #define _PWM6TMRH2 0x04
12827 #define _PWM6TMRH3 0x08
12828 #define _PWM6TMRH4 0x10
12829 #define _PWM6TMRH5 0x20
12830 #define _PWM6TMRH6 0x40
12831 #define _PWM6TMRH7 0x80
12833 //==============================================================================
12836 //==============================================================================
12839 extern __at(0x0DAB) __sfr PWM6CON
;
12847 unsigned PWM6MODE0
: 1;
12848 unsigned PWM6MODE1
: 1;
12859 unsigned MODE0
: 1;
12860 unsigned MODE1
: 1;
12861 unsigned PWM6POL
: 1;
12862 unsigned PWM6OUT
: 1;
12864 unsigned PWM6EN
: 1;
12870 unsigned PWM6MODE
: 2;
12882 extern __at(0x0DAB) volatile __PWM6CONbits_t PWM6CONbits
;
12884 #define _PWM6CON_PWM6MODE0 0x04
12885 #define _PWM6CON_MODE0 0x04
12886 #define _PWM6CON_PWM6MODE1 0x08
12887 #define _PWM6CON_MODE1 0x08
12888 #define _PWM6CON_POL 0x10
12889 #define _PWM6CON_PWM6POL 0x10
12890 #define _PWM6CON_OUT 0x20
12891 #define _PWM6CON_PWM6OUT 0x20
12892 #define _PWM6CON_EN 0x80
12893 #define _PWM6CON_PWM6EN 0x80
12895 //==============================================================================
12898 //==============================================================================
12901 extern __at(0x0DAC) __sfr PWM6INTCON
;
12919 unsigned PWM6PRIE
: 1;
12920 unsigned PWM6DCIE
: 1;
12921 unsigned PWM6PHIE
: 1;
12922 unsigned PWM6OFIE
: 1;
12928 } __PWM6INTCONbits_t
;
12930 extern __at(0x0DAC) volatile __PWM6INTCONbits_t PWM6INTCONbits
;
12932 #define _PWM6INTCON_PRIE 0x01
12933 #define _PWM6INTCON_PWM6PRIE 0x01
12934 #define _PWM6INTCON_DCIE 0x02
12935 #define _PWM6INTCON_PWM6DCIE 0x02
12936 #define _PWM6INTCON_PHIE 0x04
12937 #define _PWM6INTCON_PWM6PHIE 0x04
12938 #define _PWM6INTCON_OFIE 0x08
12939 #define _PWM6INTCON_PWM6OFIE 0x08
12941 //==============================================================================
12944 //==============================================================================
12947 extern __at(0x0DAC) __sfr PWM6INTE
;
12965 unsigned PWM6PRIE
: 1;
12966 unsigned PWM6DCIE
: 1;
12967 unsigned PWM6PHIE
: 1;
12968 unsigned PWM6OFIE
: 1;
12974 } __PWM6INTEbits_t
;
12976 extern __at(0x0DAC) volatile __PWM6INTEbits_t PWM6INTEbits
;
12978 #define _PWM6INTE_PRIE 0x01
12979 #define _PWM6INTE_PWM6PRIE 0x01
12980 #define _PWM6INTE_DCIE 0x02
12981 #define _PWM6INTE_PWM6DCIE 0x02
12982 #define _PWM6INTE_PHIE 0x04
12983 #define _PWM6INTE_PWM6PHIE 0x04
12984 #define _PWM6INTE_OFIE 0x08
12985 #define _PWM6INTE_PWM6OFIE 0x08
12987 //==============================================================================
12990 //==============================================================================
12993 extern __at(0x0DAD) __sfr PWM6INTF
;
13011 unsigned PWM6PRIF
: 1;
13012 unsigned PWM6DCIF
: 1;
13013 unsigned PWM6PHIF
: 1;
13014 unsigned PWM6OFIF
: 1;
13020 } __PWM6INTFbits_t
;
13022 extern __at(0x0DAD) volatile __PWM6INTFbits_t PWM6INTFbits
;
13024 #define _PWM6INTF_PRIF 0x01
13025 #define _PWM6INTF_PWM6PRIF 0x01
13026 #define _PWM6INTF_DCIF 0x02
13027 #define _PWM6INTF_PWM6DCIF 0x02
13028 #define _PWM6INTF_PHIF 0x04
13029 #define _PWM6INTF_PWM6PHIF 0x04
13030 #define _PWM6INTF_OFIF 0x08
13031 #define _PWM6INTF_PWM6OFIF 0x08
13033 //==============================================================================
13036 //==============================================================================
13039 extern __at(0x0DAD) __sfr PWM6INTFLG
;
13057 unsigned PWM6PRIF
: 1;
13058 unsigned PWM6DCIF
: 1;
13059 unsigned PWM6PHIF
: 1;
13060 unsigned PWM6OFIF
: 1;
13066 } __PWM6INTFLGbits_t
;
13068 extern __at(0x0DAD) volatile __PWM6INTFLGbits_t PWM6INTFLGbits
;
13070 #define _PWM6INTFLG_PRIF 0x01
13071 #define _PWM6INTFLG_PWM6PRIF 0x01
13072 #define _PWM6INTFLG_DCIF 0x02
13073 #define _PWM6INTFLG_PWM6DCIF 0x02
13074 #define _PWM6INTFLG_PHIF 0x04
13075 #define _PWM6INTFLG_PWM6PHIF 0x04
13076 #define _PWM6INTFLG_OFIF 0x08
13077 #define _PWM6INTFLG_PWM6OFIF 0x08
13079 //==============================================================================
13082 //==============================================================================
13085 extern __at(0x0DAE) __sfr PWM6CLKCON
;
13091 unsigned PWM6CS0
: 1;
13092 unsigned PWM6CS1
: 1;
13093 unsigned PWM6CS2
: 1;
13095 unsigned PWM6PS0
: 1;
13096 unsigned PWM6PS1
: 1;
13097 unsigned PWM6PS2
: 1;
13121 unsigned PWM6CS
: 3;
13128 unsigned PWM6PS
: 3;
13138 } __PWM6CLKCONbits_t
;
13140 extern __at(0x0DAE) volatile __PWM6CLKCONbits_t PWM6CLKCONbits
;
13142 #define _PWM6CLKCON_PWM6CS0 0x01
13143 #define _PWM6CLKCON_CS0 0x01
13144 #define _PWM6CLKCON_PWM6CS1 0x02
13145 #define _PWM6CLKCON_CS1 0x02
13146 #define _PWM6CLKCON_PWM6CS2 0x04
13147 #define _PWM6CLKCON_CS2 0x04
13148 #define _PWM6CLKCON_PWM6PS0 0x10
13149 #define _PWM6CLKCON_PS0 0x10
13150 #define _PWM6CLKCON_PWM6PS1 0x20
13151 #define _PWM6CLKCON_PS1 0x20
13152 #define _PWM6CLKCON_PWM6PS2 0x40
13153 #define _PWM6CLKCON_PS2 0x40
13155 //==============================================================================
13158 //==============================================================================
13161 extern __at(0x0DAF) __sfr PWM6LDCON
;
13167 unsigned PWM6LDS0
: 1;
13185 unsigned PWM6LDM
: 1;
13186 unsigned PWM6LD
: 1;
13188 } __PWM6LDCONbits_t
;
13190 extern __at(0x0DAF) volatile __PWM6LDCONbits_t PWM6LDCONbits
;
13192 #define _PWM6LDCON_PWM6LDS0 0x01
13193 #define _PWM6LDCON_LDS0 0x01
13194 #define _PWM6LDCON_LDT 0x40
13195 #define _PWM6LDCON_PWM6LDM 0x40
13196 #define _PWM6LDCON_LDA 0x80
13197 #define _PWM6LDCON_PWM6LD 0x80
13199 //==============================================================================
13202 //==============================================================================
13205 extern __at(0x0DB0) __sfr PWM6OFCON
;
13211 unsigned PWM6OFS0
: 1;
13216 unsigned PWM6OFM0
: 1;
13217 unsigned PWM6OFM1
: 1;
13227 unsigned PWM6OFMC
: 1;
13236 unsigned PWM6OFM
: 2;
13246 } __PWM6OFCONbits_t
;
13248 extern __at(0x0DB0) volatile __PWM6OFCONbits_t PWM6OFCONbits
;
13250 #define _PWM6OFCON_PWM6OFS0 0x01
13251 #define _PWM6OFCON_OFS0 0x01
13252 #define _PWM6OFCON_OFO 0x10
13253 #define _PWM6OFCON_PWM6OFMC 0x10
13254 #define _PWM6OFCON_PWM6OFM0 0x20
13255 #define _PWM6OFCON_OFM0 0x20
13256 #define _PWM6OFCON_PWM6OFM1 0x40
13257 #define _PWM6OFCON_OFM1 0x40
13259 //==============================================================================
13262 //==============================================================================
13265 extern __at(0x0E0F) __sfr PPSLOCK
;
13269 unsigned PPSLOCKED
: 1;
13279 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
13281 #define _PPSLOCKED 0x01
13283 //==============================================================================
13285 extern __at(0x0E10) __sfr INTPPS
;
13286 extern __at(0x0E11) __sfr T0CKIPPS
;
13287 extern __at(0x0E12) __sfr T1CKIPPS
;
13288 extern __at(0x0E13) __sfr T1GPPS
;
13289 extern __at(0x0E14) __sfr CCP1PPS
;
13290 extern __at(0x0E15) __sfr CCP2PPS
;
13291 extern __at(0x0E16) __sfr COG1INPPS
;
13292 extern __at(0x0E17) __sfr COG2INPPS
;
13293 extern __at(0x0E19) __sfr T2CKIPPS
;
13294 extern __at(0x0E1A) __sfr T3CKIPPS
;
13295 extern __at(0x0E1B) __sfr T3GPPS
;
13296 extern __at(0x0E1C) __sfr T4CKIPPS
;
13297 extern __at(0x0E1D) __sfr T5CKIPPS
;
13298 extern __at(0x0E1E) __sfr T5GPPS
;
13299 extern __at(0x0E1F) __sfr T6CKIPPS
;
13300 extern __at(0x0E20) __sfr SSPCLKPPS
;
13301 extern __at(0x0E21) __sfr SSPDATPPS
;
13302 extern __at(0x0E22) __sfr SSPSSPPS
;
13303 extern __at(0x0E24) __sfr RXPPS
;
13304 extern __at(0x0E25) __sfr CKPPS
;
13305 extern __at(0x0E28) __sfr CLCIN0PPS
;
13306 extern __at(0x0E29) __sfr CLCIN1PPS
;
13307 extern __at(0x0E2A) __sfr CLCIN2PPS
;
13308 extern __at(0x0E2B) __sfr CLCIN3PPS
;
13309 extern __at(0x0E2C) __sfr PRG1RPPS
;
13310 extern __at(0x0E2D) __sfr PRG1FPPS
;
13311 extern __at(0x0E2E) __sfr PRG2RPPS
;
13312 extern __at(0x0E2F) __sfr PRG2FPPS
;
13313 extern __at(0x0E30) __sfr MD1CHPPS
;
13314 extern __at(0x0E31) __sfr MD1CLPPS
;
13315 extern __at(0x0E32) __sfr MD1MODPPS
;
13316 extern __at(0x0E33) __sfr MD2CHPPS
;
13317 extern __at(0x0E34) __sfr MD2CLPPS
;
13318 extern __at(0x0E35) __sfr MD2MODPPS
;
13319 extern __at(0x0E90) __sfr RA0PPS
;
13320 extern __at(0x0E91) __sfr RA1PPS
;
13321 extern __at(0x0E92) __sfr RA2PPS
;
13322 extern __at(0x0E94) __sfr RA4PPS
;
13323 extern __at(0x0E95) __sfr RA5PPS
;
13324 extern __at(0x0E9C) __sfr RB4PPS
;
13325 extern __at(0x0E9D) __sfr RB5PPS
;
13326 extern __at(0x0E9E) __sfr RB6PPS
;
13327 extern __at(0x0E9F) __sfr RB7PPS
;
13328 extern __at(0x0EA0) __sfr RC0PPS
;
13329 extern __at(0x0EA1) __sfr RC1PPS
;
13330 extern __at(0x0EA2) __sfr RC2PPS
;
13331 extern __at(0x0EA3) __sfr RC3PPS
;
13332 extern __at(0x0EA4) __sfr RC4PPS
;
13333 extern __at(0x0EA5) __sfr RC5PPS
;
13334 extern __at(0x0EA6) __sfr RC6PPS
;
13335 extern __at(0x0EA7) __sfr RC7PPS
;
13337 //==============================================================================
13340 extern __at(0x0F0F) __sfr CLCDATA
;
13344 unsigned MCLC1OUT
: 1;
13345 unsigned MCLC2OUT
: 1;
13346 unsigned MCLC3OUT
: 1;
13354 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
13356 #define _MCLC1OUT 0x01
13357 #define _MCLC2OUT 0x02
13358 #define _MCLC3OUT 0x04
13360 //==============================================================================
13363 //==============================================================================
13366 extern __at(0x0F10) __sfr CLC1CON
;
13372 unsigned LC1MODE0
: 1;
13373 unsigned LC1MODE1
: 1;
13374 unsigned LC1MODE2
: 1;
13375 unsigned LC1INTN
: 1;
13376 unsigned LC1INTP
: 1;
13377 unsigned LC1OUT
: 1;
13379 unsigned LC1EN
: 1;
13384 unsigned MODE0
: 1;
13385 unsigned MODE1
: 1;
13386 unsigned MODE2
: 1;
13402 unsigned LC1MODE
: 3;
13407 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
13409 #define _CLC1CON_LC1MODE0 0x01
13410 #define _CLC1CON_MODE0 0x01
13411 #define _CLC1CON_LC1MODE1 0x02
13412 #define _CLC1CON_MODE1 0x02
13413 #define _CLC1CON_LC1MODE2 0x04
13414 #define _CLC1CON_MODE2 0x04
13415 #define _CLC1CON_LC1INTN 0x08
13416 #define _CLC1CON_INTN 0x08
13417 #define _CLC1CON_LC1INTP 0x10
13418 #define _CLC1CON_INTP 0x10
13419 #define _CLC1CON_LC1OUT 0x20
13420 #define _CLC1CON_OUT 0x20
13421 #define _CLC1CON_LC1EN 0x80
13422 #define _CLC1CON_EN 0x80
13424 //==============================================================================
13427 //==============================================================================
13430 extern __at(0x0F11) __sfr CLC1POL
;
13436 unsigned LC1G1POL
: 1;
13437 unsigned LC1G2POL
: 1;
13438 unsigned LC1G3POL
: 1;
13439 unsigned LC1G4POL
: 1;
13443 unsigned LC1POL
: 1;
13448 unsigned G1POL
: 1;
13449 unsigned G2POL
: 1;
13450 unsigned G3POL
: 1;
13451 unsigned G4POL
: 1;
13459 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
13461 #define _LC1G1POL 0x01
13462 #define _G1POL 0x01
13463 #define _LC1G2POL 0x02
13464 #define _G2POL 0x02
13465 #define _LC1G3POL 0x04
13466 #define _G3POL 0x04
13467 #define _LC1G4POL 0x08
13468 #define _G4POL 0x08
13469 #define _LC1POL 0x80
13472 //==============================================================================
13475 //==============================================================================
13478 extern __at(0x0F12) __sfr CLC1SEL0
;
13484 unsigned LC1D1S0
: 1;
13485 unsigned LC1D1S1
: 1;
13486 unsigned LC1D1S2
: 1;
13487 unsigned LC1D1S3
: 1;
13488 unsigned LC1D1S4
: 1;
13514 unsigned LC1D1S
: 5;
13517 } __CLC1SEL0bits_t
;
13519 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
13521 #define _LC1D1S0 0x01
13523 #define _LC1D1S1 0x02
13525 #define _LC1D1S2 0x04
13527 #define _LC1D1S3 0x08
13529 #define _LC1D1S4 0x10
13532 //==============================================================================
13535 //==============================================================================
13538 extern __at(0x0F13) __sfr CLC1SEL1
;
13544 unsigned LC1D2S0
: 1;
13545 unsigned LC1D2S1
: 1;
13546 unsigned LC1D2S2
: 1;
13547 unsigned LC1D2S3
: 1;
13548 unsigned LC1D2S4
: 1;
13574 unsigned LC1D2S
: 5;
13577 } __CLC1SEL1bits_t
;
13579 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
13581 #define _LC1D2S0 0x01
13583 #define _LC1D2S1 0x02
13585 #define _LC1D2S2 0x04
13587 #define _LC1D2S3 0x08
13589 #define _LC1D2S4 0x10
13592 //==============================================================================
13595 //==============================================================================
13598 extern __at(0x0F14) __sfr CLC1SEL2
;
13604 unsigned LC1D3S0
: 1;
13605 unsigned LC1D3S1
: 1;
13606 unsigned LC1D3S2
: 1;
13607 unsigned LC1D3S3
: 1;
13608 unsigned LC1D3S4
: 1;
13634 unsigned LC1D3S
: 5;
13637 } __CLC1SEL2bits_t
;
13639 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
13641 #define _LC1D3S0 0x01
13643 #define _LC1D3S1 0x02
13645 #define _LC1D3S2 0x04
13647 #define _LC1D3S3 0x08
13649 #define _LC1D3S4 0x10
13652 //==============================================================================
13655 //==============================================================================
13658 extern __at(0x0F15) __sfr CLC1SEL3
;
13664 unsigned LC1D4S0
: 1;
13665 unsigned LC1D4S1
: 1;
13666 unsigned LC1D4S2
: 1;
13667 unsigned LC1D4S3
: 1;
13668 unsigned LC1D4S4
: 1;
13694 unsigned LC1D4S
: 5;
13697 } __CLC1SEL3bits_t
;
13699 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
13701 #define _LC1D4S0 0x01
13703 #define _LC1D4S1 0x02
13705 #define _LC1D4S2 0x04
13707 #define _LC1D4S3 0x08
13709 #define _LC1D4S4 0x10
13712 //==============================================================================
13715 //==============================================================================
13718 extern __at(0x0F16) __sfr CLC1GLS0
;
13724 unsigned LC1G1D1N
: 1;
13725 unsigned LC1G1D1T
: 1;
13726 unsigned LC1G1D2N
: 1;
13727 unsigned LC1G1D2T
: 1;
13728 unsigned LC1G1D3N
: 1;
13729 unsigned LC1G1D3T
: 1;
13730 unsigned LC1G1D4N
: 1;
13731 unsigned LC1G1D4T
: 1;
13745 } __CLC1GLS0bits_t
;
13747 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
13749 #define _LC1G1D1N 0x01
13751 #define _LC1G1D1T 0x02
13753 #define _LC1G1D2N 0x04
13755 #define _LC1G1D2T 0x08
13757 #define _LC1G1D3N 0x10
13759 #define _LC1G1D3T 0x20
13761 #define _LC1G1D4N 0x40
13763 #define _LC1G1D4T 0x80
13766 //==============================================================================
13769 //==============================================================================
13772 extern __at(0x0F17) __sfr CLC1GLS1
;
13778 unsigned LC1G2D1N
: 1;
13779 unsigned LC1G2D1T
: 1;
13780 unsigned LC1G2D2N
: 1;
13781 unsigned LC1G2D2T
: 1;
13782 unsigned LC1G2D3N
: 1;
13783 unsigned LC1G2D3T
: 1;
13784 unsigned LC1G2D4N
: 1;
13785 unsigned LC1G2D4T
: 1;
13799 } __CLC1GLS1bits_t
;
13801 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
13803 #define _CLC1GLS1_LC1G2D1N 0x01
13804 #define _CLC1GLS1_D1N 0x01
13805 #define _CLC1GLS1_LC1G2D1T 0x02
13806 #define _CLC1GLS1_D1T 0x02
13807 #define _CLC1GLS1_LC1G2D2N 0x04
13808 #define _CLC1GLS1_D2N 0x04
13809 #define _CLC1GLS1_LC1G2D2T 0x08
13810 #define _CLC1GLS1_D2T 0x08
13811 #define _CLC1GLS1_LC1G2D3N 0x10
13812 #define _CLC1GLS1_D3N 0x10
13813 #define _CLC1GLS1_LC1G2D3T 0x20
13814 #define _CLC1GLS1_D3T 0x20
13815 #define _CLC1GLS1_LC1G2D4N 0x40
13816 #define _CLC1GLS1_D4N 0x40
13817 #define _CLC1GLS1_LC1G2D4T 0x80
13818 #define _CLC1GLS1_D4T 0x80
13820 //==============================================================================
13823 //==============================================================================
13826 extern __at(0x0F18) __sfr CLC1GLS2
;
13832 unsigned LC1G3D1N
: 1;
13833 unsigned LC1G3D1T
: 1;
13834 unsigned LC1G3D2N
: 1;
13835 unsigned LC1G3D2T
: 1;
13836 unsigned LC1G3D3N
: 1;
13837 unsigned LC1G3D3T
: 1;
13838 unsigned LC1G3D4N
: 1;
13839 unsigned LC1G3D4T
: 1;
13853 } __CLC1GLS2bits_t
;
13855 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
13857 #define _CLC1GLS2_LC1G3D1N 0x01
13858 #define _CLC1GLS2_D1N 0x01
13859 #define _CLC1GLS2_LC1G3D1T 0x02
13860 #define _CLC1GLS2_D1T 0x02
13861 #define _CLC1GLS2_LC1G3D2N 0x04
13862 #define _CLC1GLS2_D2N 0x04
13863 #define _CLC1GLS2_LC1G3D2T 0x08
13864 #define _CLC1GLS2_D2T 0x08
13865 #define _CLC1GLS2_LC1G3D3N 0x10
13866 #define _CLC1GLS2_D3N 0x10
13867 #define _CLC1GLS2_LC1G3D3T 0x20
13868 #define _CLC1GLS2_D3T 0x20
13869 #define _CLC1GLS2_LC1G3D4N 0x40
13870 #define _CLC1GLS2_D4N 0x40
13871 #define _CLC1GLS2_LC1G3D4T 0x80
13872 #define _CLC1GLS2_D4T 0x80
13874 //==============================================================================
13877 //==============================================================================
13880 extern __at(0x0F19) __sfr CLC1GLS3
;
13886 unsigned LC1G4D1N
: 1;
13887 unsigned LC1G4D1T
: 1;
13888 unsigned LC1G4D2N
: 1;
13889 unsigned LC1G4D2T
: 1;
13890 unsigned LC1G4D3N
: 1;
13891 unsigned LC1G4D3T
: 1;
13892 unsigned LC1G4D4N
: 1;
13893 unsigned LC1G4D4T
: 1;
13898 unsigned G4D1N
: 1;
13899 unsigned G4D1T
: 1;
13900 unsigned G4D2N
: 1;
13901 unsigned G4D2T
: 1;
13902 unsigned G4D3N
: 1;
13903 unsigned G4D3T
: 1;
13904 unsigned G4D4N
: 1;
13905 unsigned G4D4T
: 1;
13907 } __CLC1GLS3bits_t
;
13909 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
13911 #define _LC1G4D1N 0x01
13912 #define _G4D1N 0x01
13913 #define _LC1G4D1T 0x02
13914 #define _G4D1T 0x02
13915 #define _LC1G4D2N 0x04
13916 #define _G4D2N 0x04
13917 #define _LC1G4D2T 0x08
13918 #define _G4D2T 0x08
13919 #define _LC1G4D3N 0x10
13920 #define _G4D3N 0x10
13921 #define _LC1G4D3T 0x20
13922 #define _G4D3T 0x20
13923 #define _LC1G4D4N 0x40
13924 #define _G4D4N 0x40
13925 #define _LC1G4D4T 0x80
13926 #define _G4D4T 0x80
13928 //==============================================================================
13931 //==============================================================================
13934 extern __at(0x0F1A) __sfr CLC2CON
;
13940 unsigned LC2MODE0
: 1;
13941 unsigned LC2MODE1
: 1;
13942 unsigned LC2MODE2
: 1;
13943 unsigned LC2INTN
: 1;
13944 unsigned LC2INTP
: 1;
13945 unsigned LC2OUT
: 1;
13947 unsigned LC2EN
: 1;
13952 unsigned MODE0
: 1;
13953 unsigned MODE1
: 1;
13954 unsigned MODE2
: 1;
13970 unsigned LC2MODE
: 3;
13975 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
13977 #define _CLC2CON_LC2MODE0 0x01
13978 #define _CLC2CON_MODE0 0x01
13979 #define _CLC2CON_LC2MODE1 0x02
13980 #define _CLC2CON_MODE1 0x02
13981 #define _CLC2CON_LC2MODE2 0x04
13982 #define _CLC2CON_MODE2 0x04
13983 #define _CLC2CON_LC2INTN 0x08
13984 #define _CLC2CON_INTN 0x08
13985 #define _CLC2CON_LC2INTP 0x10
13986 #define _CLC2CON_INTP 0x10
13987 #define _CLC2CON_LC2OUT 0x20
13988 #define _CLC2CON_OUT 0x20
13989 #define _CLC2CON_LC2EN 0x80
13990 #define _CLC2CON_EN 0x80
13992 //==============================================================================
13995 //==============================================================================
13998 extern __at(0x0F1B) __sfr CLC2POL
;
14004 unsigned LC2G1POL
: 1;
14005 unsigned LC2G2POL
: 1;
14006 unsigned LC2G3POL
: 1;
14007 unsigned LC2G4POL
: 1;
14011 unsigned LC2POL
: 1;
14016 unsigned G1POL
: 1;
14017 unsigned G2POL
: 1;
14018 unsigned G3POL
: 1;
14019 unsigned G4POL
: 1;
14027 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
14029 #define _CLC2POL_LC2G1POL 0x01
14030 #define _CLC2POL_G1POL 0x01
14031 #define _CLC2POL_LC2G2POL 0x02
14032 #define _CLC2POL_G2POL 0x02
14033 #define _CLC2POL_LC2G3POL 0x04
14034 #define _CLC2POL_G3POL 0x04
14035 #define _CLC2POL_LC2G4POL 0x08
14036 #define _CLC2POL_G4POL 0x08
14037 #define _CLC2POL_LC2POL 0x80
14038 #define _CLC2POL_POL 0x80
14040 //==============================================================================
14043 //==============================================================================
14046 extern __at(0x0F1C) __sfr CLC2SEL0
;
14052 unsigned LC2D1S0
: 1;
14053 unsigned LC2D1S1
: 1;
14054 unsigned LC2D1S2
: 1;
14055 unsigned LC2D1S3
: 1;
14056 unsigned LC2D1S4
: 1;
14082 unsigned LC2D1S
: 5;
14085 } __CLC2SEL0bits_t
;
14087 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
14089 #define _CLC2SEL0_LC2D1S0 0x01
14090 #define _CLC2SEL0_D1S0 0x01
14091 #define _CLC2SEL0_LC2D1S1 0x02
14092 #define _CLC2SEL0_D1S1 0x02
14093 #define _CLC2SEL0_LC2D1S2 0x04
14094 #define _CLC2SEL0_D1S2 0x04
14095 #define _CLC2SEL0_LC2D1S3 0x08
14096 #define _CLC2SEL0_D1S3 0x08
14097 #define _CLC2SEL0_LC2D1S4 0x10
14098 #define _CLC2SEL0_D1S4 0x10
14100 //==============================================================================
14103 //==============================================================================
14106 extern __at(0x0F1D) __sfr CLC2SEL1
;
14112 unsigned LC2D2S0
: 1;
14113 unsigned LC2D2S1
: 1;
14114 unsigned LC2D2S2
: 1;
14115 unsigned LC2D2S3
: 1;
14116 unsigned LC2D2S4
: 1;
14136 unsigned LC2D2S
: 5;
14145 } __CLC2SEL1bits_t
;
14147 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
14149 #define _CLC2SEL1_LC2D2S0 0x01
14150 #define _CLC2SEL1_D2S0 0x01
14151 #define _CLC2SEL1_LC2D2S1 0x02
14152 #define _CLC2SEL1_D2S1 0x02
14153 #define _CLC2SEL1_LC2D2S2 0x04
14154 #define _CLC2SEL1_D2S2 0x04
14155 #define _CLC2SEL1_LC2D2S3 0x08
14156 #define _CLC2SEL1_D2S3 0x08
14157 #define _CLC2SEL1_LC2D2S4 0x10
14158 #define _CLC2SEL1_D2S4 0x10
14160 //==============================================================================
14163 //==============================================================================
14166 extern __at(0x0F1E) __sfr CLC2SEL2
;
14172 unsigned LC2D3S0
: 1;
14173 unsigned LC2D3S1
: 1;
14174 unsigned LC2D3S2
: 1;
14175 unsigned LC2D3S3
: 1;
14176 unsigned LC2D3S4
: 1;
14196 unsigned LC2D3S
: 5;
14205 } __CLC2SEL2bits_t
;
14207 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
14209 #define _CLC2SEL2_LC2D3S0 0x01
14210 #define _CLC2SEL2_D3S0 0x01
14211 #define _CLC2SEL2_LC2D3S1 0x02
14212 #define _CLC2SEL2_D3S1 0x02
14213 #define _CLC2SEL2_LC2D3S2 0x04
14214 #define _CLC2SEL2_D3S2 0x04
14215 #define _CLC2SEL2_LC2D3S3 0x08
14216 #define _CLC2SEL2_D3S3 0x08
14217 #define _CLC2SEL2_LC2D3S4 0x10
14218 #define _CLC2SEL2_D3S4 0x10
14220 //==============================================================================
14223 //==============================================================================
14226 extern __at(0x0F1F) __sfr CLC2SEL3
;
14232 unsigned LC2D4S0
: 1;
14233 unsigned LC2D4S1
: 1;
14234 unsigned LC2D4S2
: 1;
14235 unsigned LC2D4S3
: 1;
14236 unsigned LC2D4S4
: 1;
14262 unsigned LC2D4S
: 5;
14265 } __CLC2SEL3bits_t
;
14267 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
14269 #define _CLC2SEL3_LC2D4S0 0x01
14270 #define _CLC2SEL3_D4S0 0x01
14271 #define _CLC2SEL3_LC2D4S1 0x02
14272 #define _CLC2SEL3_D4S1 0x02
14273 #define _CLC2SEL3_LC2D4S2 0x04
14274 #define _CLC2SEL3_D4S2 0x04
14275 #define _CLC2SEL3_LC2D4S3 0x08
14276 #define _CLC2SEL3_D4S3 0x08
14277 #define _CLC2SEL3_LC2D4S4 0x10
14278 #define _CLC2SEL3_D4S4 0x10
14280 //==============================================================================
14283 //==============================================================================
14286 extern __at(0x0F20) __sfr CLC2GLS0
;
14292 unsigned LC2G1D1N
: 1;
14293 unsigned LC2G1D1T
: 1;
14294 unsigned LC2G1D2N
: 1;
14295 unsigned LC2G1D2T
: 1;
14296 unsigned LC2G1D3N
: 1;
14297 unsigned LC2G1D3T
: 1;
14298 unsigned LC2G1D4N
: 1;
14299 unsigned LC2G1D4T
: 1;
14313 } __CLC2GLS0bits_t
;
14315 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
14317 #define _CLC2GLS0_LC2G1D1N 0x01
14318 #define _CLC2GLS0_D1N 0x01
14319 #define _CLC2GLS0_LC2G1D1T 0x02
14320 #define _CLC2GLS0_D1T 0x02
14321 #define _CLC2GLS0_LC2G1D2N 0x04
14322 #define _CLC2GLS0_D2N 0x04
14323 #define _CLC2GLS0_LC2G1D2T 0x08
14324 #define _CLC2GLS0_D2T 0x08
14325 #define _CLC2GLS0_LC2G1D3N 0x10
14326 #define _CLC2GLS0_D3N 0x10
14327 #define _CLC2GLS0_LC2G1D3T 0x20
14328 #define _CLC2GLS0_D3T 0x20
14329 #define _CLC2GLS0_LC2G1D4N 0x40
14330 #define _CLC2GLS0_D4N 0x40
14331 #define _CLC2GLS0_LC2G1D4T 0x80
14332 #define _CLC2GLS0_D4T 0x80
14334 //==============================================================================
14337 //==============================================================================
14340 extern __at(0x0F21) __sfr CLC2GLS1
;
14346 unsigned LC2G2D1N
: 1;
14347 unsigned LC2G2D1T
: 1;
14348 unsigned LC2G2D2N
: 1;
14349 unsigned LC2G2D2T
: 1;
14350 unsigned LC2G2D3N
: 1;
14351 unsigned LC2G2D3T
: 1;
14352 unsigned LC2G2D4N
: 1;
14353 unsigned LC2G2D4T
: 1;
14367 } __CLC2GLS1bits_t
;
14369 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
14371 #define _CLC2GLS1_LC2G2D1N 0x01
14372 #define _CLC2GLS1_D1N 0x01
14373 #define _CLC2GLS1_LC2G2D1T 0x02
14374 #define _CLC2GLS1_D1T 0x02
14375 #define _CLC2GLS1_LC2G2D2N 0x04
14376 #define _CLC2GLS1_D2N 0x04
14377 #define _CLC2GLS1_LC2G2D2T 0x08
14378 #define _CLC2GLS1_D2T 0x08
14379 #define _CLC2GLS1_LC2G2D3N 0x10
14380 #define _CLC2GLS1_D3N 0x10
14381 #define _CLC2GLS1_LC2G2D3T 0x20
14382 #define _CLC2GLS1_D3T 0x20
14383 #define _CLC2GLS1_LC2G2D4N 0x40
14384 #define _CLC2GLS1_D4N 0x40
14385 #define _CLC2GLS1_LC2G2D4T 0x80
14386 #define _CLC2GLS1_D4T 0x80
14388 //==============================================================================
14391 //==============================================================================
14394 extern __at(0x0F22) __sfr CLC2GLS2
;
14400 unsigned LC2G3D1N
: 1;
14401 unsigned LC2G3D1T
: 1;
14402 unsigned LC2G3D2N
: 1;
14403 unsigned LC2G3D2T
: 1;
14404 unsigned LC2G3D3N
: 1;
14405 unsigned LC2G3D3T
: 1;
14406 unsigned LC2G3D4N
: 1;
14407 unsigned LC2G3D4T
: 1;
14421 } __CLC2GLS2bits_t
;
14423 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
14425 #define _CLC2GLS2_LC2G3D1N 0x01
14426 #define _CLC2GLS2_D1N 0x01
14427 #define _CLC2GLS2_LC2G3D1T 0x02
14428 #define _CLC2GLS2_D1T 0x02
14429 #define _CLC2GLS2_LC2G3D2N 0x04
14430 #define _CLC2GLS2_D2N 0x04
14431 #define _CLC2GLS2_LC2G3D2T 0x08
14432 #define _CLC2GLS2_D2T 0x08
14433 #define _CLC2GLS2_LC2G3D3N 0x10
14434 #define _CLC2GLS2_D3N 0x10
14435 #define _CLC2GLS2_LC2G3D3T 0x20
14436 #define _CLC2GLS2_D3T 0x20
14437 #define _CLC2GLS2_LC2G3D4N 0x40
14438 #define _CLC2GLS2_D4N 0x40
14439 #define _CLC2GLS2_LC2G3D4T 0x80
14440 #define _CLC2GLS2_D4T 0x80
14442 //==============================================================================
14445 //==============================================================================
14448 extern __at(0x0F23) __sfr CLC2GLS3
;
14454 unsigned LC2G4D1N
: 1;
14455 unsigned LC2G4D1T
: 1;
14456 unsigned LC2G4D2N
: 1;
14457 unsigned LC2G4D2T
: 1;
14458 unsigned LC2G4D3N
: 1;
14459 unsigned LC2G4D3T
: 1;
14460 unsigned LC2G4D4N
: 1;
14461 unsigned LC2G4D4T
: 1;
14466 unsigned G4D1N
: 1;
14467 unsigned G4D1T
: 1;
14468 unsigned G4D2N
: 1;
14469 unsigned G4D2T
: 1;
14470 unsigned G4D3N
: 1;
14471 unsigned G4D3T
: 1;
14472 unsigned G4D4N
: 1;
14473 unsigned G4D4T
: 1;
14475 } __CLC2GLS3bits_t
;
14477 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
14479 #define _CLC2GLS3_LC2G4D1N 0x01
14480 #define _CLC2GLS3_G4D1N 0x01
14481 #define _CLC2GLS3_LC2G4D1T 0x02
14482 #define _CLC2GLS3_G4D1T 0x02
14483 #define _CLC2GLS3_LC2G4D2N 0x04
14484 #define _CLC2GLS3_G4D2N 0x04
14485 #define _CLC2GLS3_LC2G4D2T 0x08
14486 #define _CLC2GLS3_G4D2T 0x08
14487 #define _CLC2GLS3_LC2G4D3N 0x10
14488 #define _CLC2GLS3_G4D3N 0x10
14489 #define _CLC2GLS3_LC2G4D3T 0x20
14490 #define _CLC2GLS3_G4D3T 0x20
14491 #define _CLC2GLS3_LC2G4D4N 0x40
14492 #define _CLC2GLS3_G4D4N 0x40
14493 #define _CLC2GLS3_LC2G4D4T 0x80
14494 #define _CLC2GLS3_G4D4T 0x80
14496 //==============================================================================
14499 //==============================================================================
14502 extern __at(0x0F24) __sfr CLC3CON
;
14508 unsigned LC3MODE0
: 1;
14509 unsigned LC3MODE1
: 1;
14510 unsigned LC3MODE2
: 1;
14511 unsigned LC3INTN
: 1;
14512 unsigned LC3INTP
: 1;
14513 unsigned LC3OUT
: 1;
14515 unsigned LC3EN
: 1;
14520 unsigned MODE0
: 1;
14521 unsigned MODE1
: 1;
14522 unsigned MODE2
: 1;
14538 unsigned LC3MODE
: 3;
14543 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
14545 #define _CLC3CON_LC3MODE0 0x01
14546 #define _CLC3CON_MODE0 0x01
14547 #define _CLC3CON_LC3MODE1 0x02
14548 #define _CLC3CON_MODE1 0x02
14549 #define _CLC3CON_LC3MODE2 0x04
14550 #define _CLC3CON_MODE2 0x04
14551 #define _CLC3CON_LC3INTN 0x08
14552 #define _CLC3CON_INTN 0x08
14553 #define _CLC3CON_LC3INTP 0x10
14554 #define _CLC3CON_INTP 0x10
14555 #define _CLC3CON_LC3OUT 0x20
14556 #define _CLC3CON_OUT 0x20
14557 #define _CLC3CON_LC3EN 0x80
14558 #define _CLC3CON_EN 0x80
14560 //==============================================================================
14563 //==============================================================================
14566 extern __at(0x0F25) __sfr CLC3POL
;
14572 unsigned LC3G1POL
: 1;
14573 unsigned LC3G2POL
: 1;
14574 unsigned LC3G3POL
: 1;
14575 unsigned LC3G4POL
: 1;
14579 unsigned LC3POL
: 1;
14584 unsigned G1POL
: 1;
14585 unsigned G2POL
: 1;
14586 unsigned G3POL
: 1;
14587 unsigned G4POL
: 1;
14595 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
14597 #define _CLC3POL_LC3G1POL 0x01
14598 #define _CLC3POL_G1POL 0x01
14599 #define _CLC3POL_LC3G2POL 0x02
14600 #define _CLC3POL_G2POL 0x02
14601 #define _CLC3POL_LC3G3POL 0x04
14602 #define _CLC3POL_G3POL 0x04
14603 #define _CLC3POL_LC3G4POL 0x08
14604 #define _CLC3POL_G4POL 0x08
14605 #define _CLC3POL_LC3POL 0x80
14606 #define _CLC3POL_POL 0x80
14608 //==============================================================================
14611 //==============================================================================
14614 extern __at(0x0F26) __sfr CLC3SEL0
;
14620 unsigned LC3D1S0
: 1;
14621 unsigned LC3D1S1
: 1;
14622 unsigned LC3D1S2
: 1;
14623 unsigned LC3D1S3
: 1;
14624 unsigned LC3D1S4
: 1;
14650 unsigned LC3D1S
: 5;
14653 } __CLC3SEL0bits_t
;
14655 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
14657 #define _CLC3SEL0_LC3D1S0 0x01
14658 #define _CLC3SEL0_D1S0 0x01
14659 #define _CLC3SEL0_LC3D1S1 0x02
14660 #define _CLC3SEL0_D1S1 0x02
14661 #define _CLC3SEL0_LC3D1S2 0x04
14662 #define _CLC3SEL0_D1S2 0x04
14663 #define _CLC3SEL0_LC3D1S3 0x08
14664 #define _CLC3SEL0_D1S3 0x08
14665 #define _CLC3SEL0_LC3D1S4 0x10
14666 #define _CLC3SEL0_D1S4 0x10
14668 //==============================================================================
14671 //==============================================================================
14674 extern __at(0x0F27) __sfr CLC3SEL1
;
14680 unsigned LC3D2S0
: 1;
14681 unsigned LC3D2S1
: 1;
14682 unsigned LC3D2S2
: 1;
14683 unsigned LC3D2S3
: 1;
14684 unsigned LC3D2S4
: 1;
14704 unsigned LC3D2S
: 5;
14713 } __CLC3SEL1bits_t
;
14715 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
14717 #define _CLC3SEL1_LC3D2S0 0x01
14718 #define _CLC3SEL1_D2S0 0x01
14719 #define _CLC3SEL1_LC3D2S1 0x02
14720 #define _CLC3SEL1_D2S1 0x02
14721 #define _CLC3SEL1_LC3D2S2 0x04
14722 #define _CLC3SEL1_D2S2 0x04
14723 #define _CLC3SEL1_LC3D2S3 0x08
14724 #define _CLC3SEL1_D2S3 0x08
14725 #define _CLC3SEL1_LC3D2S4 0x10
14726 #define _CLC3SEL1_D2S4 0x10
14728 //==============================================================================
14731 //==============================================================================
14734 extern __at(0x0F28) __sfr CLC3SEL2
;
14740 unsigned LC3D3S0
: 1;
14741 unsigned LC3D3S1
: 1;
14742 unsigned LC3D3S2
: 1;
14743 unsigned LC3D3S3
: 1;
14744 unsigned LC3D3S4
: 1;
14764 unsigned LC3D3S
: 5;
14773 } __CLC3SEL2bits_t
;
14775 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
14777 #define _CLC3SEL2_LC3D3S0 0x01
14778 #define _CLC3SEL2_D3S0 0x01
14779 #define _CLC3SEL2_LC3D3S1 0x02
14780 #define _CLC3SEL2_D3S1 0x02
14781 #define _CLC3SEL2_LC3D3S2 0x04
14782 #define _CLC3SEL2_D3S2 0x04
14783 #define _CLC3SEL2_LC3D3S3 0x08
14784 #define _CLC3SEL2_D3S3 0x08
14785 #define _CLC3SEL2_LC3D3S4 0x10
14786 #define _CLC3SEL2_D3S4 0x10
14788 //==============================================================================
14791 //==============================================================================
14794 extern __at(0x0F29) __sfr CLC3SEL3
;
14800 unsigned LC3D4S0
: 1;
14801 unsigned LC3D4S1
: 1;
14802 unsigned LC3D4S2
: 1;
14803 unsigned LC3D4S3
: 1;
14804 unsigned LC3D4S4
: 1;
14830 unsigned LC3D4S
: 5;
14833 } __CLC3SEL3bits_t
;
14835 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
14837 #define _CLC3SEL3_LC3D4S0 0x01
14838 #define _CLC3SEL3_D4S0 0x01
14839 #define _CLC3SEL3_LC3D4S1 0x02
14840 #define _CLC3SEL3_D4S1 0x02
14841 #define _CLC3SEL3_LC3D4S2 0x04
14842 #define _CLC3SEL3_D4S2 0x04
14843 #define _CLC3SEL3_LC3D4S3 0x08
14844 #define _CLC3SEL3_D4S3 0x08
14845 #define _CLC3SEL3_LC3D4S4 0x10
14846 #define _CLC3SEL3_D4S4 0x10
14848 //==============================================================================
14851 //==============================================================================
14854 extern __at(0x0F2A) __sfr CLC3GLS0
;
14860 unsigned LC3G1D1N
: 1;
14861 unsigned LC3G1D1T
: 1;
14862 unsigned LC3G1D2N
: 1;
14863 unsigned LC3G1D2T
: 1;
14864 unsigned LC3G1D3N
: 1;
14865 unsigned LC3G1D3T
: 1;
14866 unsigned LC3G1D4N
: 1;
14867 unsigned LC3G1D4T
: 1;
14881 } __CLC3GLS0bits_t
;
14883 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
14885 #define _CLC3GLS0_LC3G1D1N 0x01
14886 #define _CLC3GLS0_D1N 0x01
14887 #define _CLC3GLS0_LC3G1D1T 0x02
14888 #define _CLC3GLS0_D1T 0x02
14889 #define _CLC3GLS0_LC3G1D2N 0x04
14890 #define _CLC3GLS0_D2N 0x04
14891 #define _CLC3GLS0_LC3G1D2T 0x08
14892 #define _CLC3GLS0_D2T 0x08
14893 #define _CLC3GLS0_LC3G1D3N 0x10
14894 #define _CLC3GLS0_D3N 0x10
14895 #define _CLC3GLS0_LC3G1D3T 0x20
14896 #define _CLC3GLS0_D3T 0x20
14897 #define _CLC3GLS0_LC3G1D4N 0x40
14898 #define _CLC3GLS0_D4N 0x40
14899 #define _CLC3GLS0_LC3G1D4T 0x80
14900 #define _CLC3GLS0_D4T 0x80
14902 //==============================================================================
14905 //==============================================================================
14908 extern __at(0x0F2B) __sfr CLC3GLS1
;
14914 unsigned LC3G2D1N
: 1;
14915 unsigned LC3G2D1T
: 1;
14916 unsigned LC3G2D2N
: 1;
14917 unsigned LC3G2D2T
: 1;
14918 unsigned LC3G2D3N
: 1;
14919 unsigned LC3G2D3T
: 1;
14920 unsigned LC3G2D4N
: 1;
14921 unsigned LC3G2D4T
: 1;
14935 } __CLC3GLS1bits_t
;
14937 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
14939 #define _CLC3GLS1_LC3G2D1N 0x01
14940 #define _CLC3GLS1_D1N 0x01
14941 #define _CLC3GLS1_LC3G2D1T 0x02
14942 #define _CLC3GLS1_D1T 0x02
14943 #define _CLC3GLS1_LC3G2D2N 0x04
14944 #define _CLC3GLS1_D2N 0x04
14945 #define _CLC3GLS1_LC3G2D2T 0x08
14946 #define _CLC3GLS1_D2T 0x08
14947 #define _CLC3GLS1_LC3G2D3N 0x10
14948 #define _CLC3GLS1_D3N 0x10
14949 #define _CLC3GLS1_LC3G2D3T 0x20
14950 #define _CLC3GLS1_D3T 0x20
14951 #define _CLC3GLS1_LC3G2D4N 0x40
14952 #define _CLC3GLS1_D4N 0x40
14953 #define _CLC3GLS1_LC3G2D4T 0x80
14954 #define _CLC3GLS1_D4T 0x80
14956 //==============================================================================
14959 //==============================================================================
14962 extern __at(0x0F2C) __sfr CLC3GLS2
;
14968 unsigned LC3G3D1N
: 1;
14969 unsigned LC3G3D1T
: 1;
14970 unsigned LC3G3D2N
: 1;
14971 unsigned LC3G3D2T
: 1;
14972 unsigned LC3G3D3N
: 1;
14973 unsigned LC3G3D3T
: 1;
14974 unsigned LC3G3D4N
: 1;
14975 unsigned LC3G3D4T
: 1;
14989 } __CLC3GLS2bits_t
;
14991 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
14993 #define _CLC3GLS2_LC3G3D1N 0x01
14994 #define _CLC3GLS2_D1N 0x01
14995 #define _CLC3GLS2_LC3G3D1T 0x02
14996 #define _CLC3GLS2_D1T 0x02
14997 #define _CLC3GLS2_LC3G3D2N 0x04
14998 #define _CLC3GLS2_D2N 0x04
14999 #define _CLC3GLS2_LC3G3D2T 0x08
15000 #define _CLC3GLS2_D2T 0x08
15001 #define _CLC3GLS2_LC3G3D3N 0x10
15002 #define _CLC3GLS2_D3N 0x10
15003 #define _CLC3GLS2_LC3G3D3T 0x20
15004 #define _CLC3GLS2_D3T 0x20
15005 #define _CLC3GLS2_LC3G3D4N 0x40
15006 #define _CLC3GLS2_D4N 0x40
15007 #define _CLC3GLS2_LC3G3D4T 0x80
15008 #define _CLC3GLS2_D4T 0x80
15010 //==============================================================================
15013 //==============================================================================
15016 extern __at(0x0F2D) __sfr CLC3GLS3
;
15022 unsigned LC3G4D1N
: 1;
15023 unsigned LC3G4D1T
: 1;
15024 unsigned LC3G4D2N
: 1;
15025 unsigned LC3G4D2T
: 1;
15026 unsigned LC3G4D3N
: 1;
15027 unsigned LC3G4D3T
: 1;
15028 unsigned LC3G4D4N
: 1;
15029 unsigned LC3G4D4T
: 1;
15034 unsigned G4D1N
: 1;
15035 unsigned G4D1T
: 1;
15036 unsigned G4D2N
: 1;
15037 unsigned G4D2T
: 1;
15038 unsigned G4D3N
: 1;
15039 unsigned G4D3T
: 1;
15040 unsigned G4D4N
: 1;
15041 unsigned G4D4T
: 1;
15043 } __CLC3GLS3bits_t
;
15045 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
15047 #define _CLC3GLS3_LC3G4D1N 0x01
15048 #define _CLC3GLS3_G4D1N 0x01
15049 #define _CLC3GLS3_LC3G4D1T 0x02
15050 #define _CLC3GLS3_G4D1T 0x02
15051 #define _CLC3GLS3_LC3G4D2N 0x04
15052 #define _CLC3GLS3_G4D2N 0x04
15053 #define _CLC3GLS3_LC3G4D2T 0x08
15054 #define _CLC3GLS3_G4D2T 0x08
15055 #define _CLC3GLS3_LC3G4D3N 0x10
15056 #define _CLC3GLS3_G4D3N 0x10
15057 #define _CLC3GLS3_LC3G4D3T 0x20
15058 #define _CLC3GLS3_G4D3T 0x20
15059 #define _CLC3GLS3_LC3G4D4N 0x40
15060 #define _CLC3GLS3_G4D4N 0x40
15061 #define _CLC3GLS3_LC3G4D4T 0x80
15062 #define _CLC3GLS3_G4D4T 0x80
15064 //==============================================================================
15067 //==============================================================================
15068 // STATUS_SHAD Bits
15070 extern __at(0x0FE4) __sfr STATUS_SHAD
;
15074 unsigned C_SHAD
: 1;
15075 unsigned DC_SHAD
: 1;
15076 unsigned Z_SHAD
: 1;
15082 } __STATUS_SHADbits_t
;
15084 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
15086 #define _C_SHAD 0x01
15087 #define _DC_SHAD 0x02
15088 #define _Z_SHAD 0x04
15090 //==============================================================================
15092 extern __at(0x0FE5) __sfr WREG_SHAD
;
15093 extern __at(0x0FE6) __sfr BSR_SHAD
;
15094 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
15095 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
15096 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
15097 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
15098 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
15099 extern __at(0x0FED) __sfr STKPTR
;
15100 extern __at(0x0FEE) __sfr TOSL
;
15101 extern __at(0x0FEF) __sfr TOSH
;
15103 //==============================================================================
15105 // Configuration Bits
15107 //==============================================================================
15109 #define _CONFIG1 0x8007
15110 #define _CONFIG2 0x8008
15112 //----------------------------- CONFIG1 Options -------------------------------
15114 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
15115 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
15116 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
15117 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
15118 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
15119 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
15120 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
15121 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
15122 #define _WDTE_OFF 0x3FE7 // WDT disabled.
15123 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
15124 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
15125 #define _WDTE_ON 0x3FFF // WDT enabled.
15126 #define _PWRTE_ON 0x3FDF // PWRT enabled.
15127 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
15128 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
15129 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
15130 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
15131 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
15132 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
15133 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
15134 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
15135 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
15136 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
15137 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
15138 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
15139 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
15140 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
15141 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
15143 //----------------------------- CONFIG2 Options -------------------------------
15145 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
15146 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
15147 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
15148 #define _WRT_OFF 0x3FFF // Write protection off.
15149 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
15150 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
15151 #define _ZCD_ON 0x3F7F // Zero-cross detect circuit is enabled at POR.
15152 #define _ZCD_OFF 0x3FFF // Zero-cross detect circuit is disabled at POR.
15153 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
15154 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
15155 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
15156 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
15157 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
15158 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
15159 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
15160 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
15161 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
15162 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
15163 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
15164 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
15166 //==============================================================================
15168 #define _DEVID1 0x8006
15170 #define _IDLOC0 0x8000
15171 #define _IDLOC1 0x8001
15172 #define _IDLOC2 0x8002
15173 #define _IDLOC3 0x8003
15175 //==============================================================================
15177 #ifndef NO_BIT_DEFINES
15179 #define ADON ADCON0bits.ADON // bit 0
15180 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
15181 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
15182 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
15183 #define CHS0 ADCON0bits.CHS0 // bit 2
15184 #define CHS1 ADCON0bits.CHS1 // bit 3
15185 #define CHS2 ADCON0bits.CHS2 // bit 4
15186 #define CHS3 ADCON0bits.CHS3 // bit 5
15187 #define CHS4 ADCON0bits.CHS4 // bit 6
15189 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
15190 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
15191 #define ADNREF ADCON1bits.ADNREF // bit 2
15192 #define ADFM ADCON1bits.ADFM // bit 7
15194 #define TRIGSEL0 ADCON2bits.TRIGSEL0 // bit 3
15195 #define TRIGSEL1 ADCON2bits.TRIGSEL1 // bit 4
15196 #define TRIGSEL2 ADCON2bits.TRIGSEL2 // bit 5
15197 #define TRIGSEL3 ADCON2bits.TRIGSEL3 // bit 6
15198 #define TRIGSEL4 ADCON2bits.TRIGSEL4 // bit 7
15200 #define ANSA0 ANSELAbits.ANSA0 // bit 0
15201 #define ANSA1 ANSELAbits.ANSA1 // bit 1
15202 #define ANSA2 ANSELAbits.ANSA2 // bit 2
15203 #define ANSA4 ANSELAbits.ANSA4 // bit 4
15205 #define ANSB4 ANSELBbits.ANSB4 // bit 4
15206 #define ANSB5 ANSELBbits.ANSB5 // bit 5
15207 #define ANSB6 ANSELBbits.ANSB6 // bit 6
15208 #define ANSB7 ANSELBbits.ANSB7 // bit 7
15210 #define ANSC0 ANSELCbits.ANSC0 // bit 0
15211 #define ANSC1 ANSELCbits.ANSC1 // bit 1
15212 #define ANSC2 ANSELCbits.ANSC2 // bit 2
15213 #define ANSC3 ANSELCbits.ANSC3 // bit 3
15214 #define ANSC6 ANSELCbits.ANSC6 // bit 6
15215 #define ANSC7 ANSELCbits.ANSC7 // bit 7
15217 #define ABDEN BAUD1CONbits.ABDEN // bit 0
15218 #define WUE BAUD1CONbits.WUE // bit 1
15219 #define BRG16 BAUD1CONbits.BRG16 // bit 3
15220 #define SCKP BAUD1CONbits.SCKP // bit 4
15221 #define RCIDL BAUD1CONbits.RCIDL // bit 6
15222 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
15224 #define BORRDY BORCONbits.BORRDY // bit 0
15225 #define BORFS BORCONbits.BORFS // bit 6
15226 #define SBOREN BORCONbits.SBOREN // bit 7
15228 #define BSR0 BSRbits.BSR0 // bit 0
15229 #define BSR1 BSRbits.BSR1 // bit 1
15230 #define BSR2 BSRbits.BSR2 // bit 2
15231 #define BSR3 BSRbits.BSR3 // bit 3
15232 #define BSR4 BSRbits.BSR4 // bit 4
15234 #define CTS0 CCP1CAPbits.CTS0 // bit 0, shadows bit in CCP1CAPbits
15235 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0, shadows bit in CCP1CAPbits
15236 #define CTS1 CCP1CAPbits.CTS1 // bit 1, shadows bit in CCP1CAPbits
15237 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1, shadows bit in CCP1CAPbits
15238 #define CTS2 CCP1CAPbits.CTS2 // bit 2, shadows bit in CCP1CAPbits
15239 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2, shadows bit in CCP1CAPbits
15241 #define MODE0 CCP1CONbits.MODE0 // bit 0, shadows bit in CCP1CONbits
15242 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0, shadows bit in CCP1CONbits
15243 #define MODE1 CCP1CONbits.MODE1 // bit 1, shadows bit in CCP1CONbits
15244 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1, shadows bit in CCP1CONbits
15245 #define MODE2 CCP1CONbits.MODE2 // bit 2, shadows bit in CCP1CONbits
15246 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2, shadows bit in CCP1CONbits
15247 #define MODE3 CCP1CONbits.MODE3 // bit 3, shadows bit in CCP1CONbits
15248 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3, shadows bit in CCP1CONbits
15249 #define FMT CCP1CONbits.FMT // bit 4, shadows bit in CCP1CONbits
15250 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4, shadows bit in CCP1CONbits
15251 #define OUT CCP1CONbits.OUT // bit 5, shadows bit in CCP1CONbits
15252 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5, shadows bit in CCP1CONbits
15253 #define EN CCP1CONbits.EN // bit 7, shadows bit in CCP1CONbits
15254 #define CCP1EN CCP1CONbits.CCP1EN // bit 7, shadows bit in CCP1CONbits
15256 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
15257 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
15258 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
15259 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
15260 #define P3TSEL0 CCPTMRSbits.P3TSEL0 // bit 4
15261 #define P3TSEL1 CCPTMRSbits.P3TSEL1 // bit 5
15262 #define P4TSEL0 CCPTMRSbits.P4TSEL0 // bit 6
15263 #define P4TSEL1 CCPTMRSbits.P4TSEL1 // bit 7
15265 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
15266 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
15267 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
15268 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
15269 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
15270 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
15271 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
15272 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
15273 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
15274 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
15275 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
15276 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
15277 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
15278 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
15279 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
15280 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
15282 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
15283 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
15284 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
15285 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
15286 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
15287 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
15288 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
15289 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
15290 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
15291 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
15292 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
15293 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
15294 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
15295 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
15296 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
15297 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
15299 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
15300 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
15301 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
15302 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
15303 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
15304 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
15305 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
15306 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
15307 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
15308 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
15310 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
15311 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
15312 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
15313 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
15314 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
15315 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
15316 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
15317 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
15318 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
15319 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
15321 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
15322 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
15323 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
15324 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
15325 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
15326 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
15327 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
15328 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
15329 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
15330 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
15332 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
15333 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
15334 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
15335 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
15336 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
15337 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
15338 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
15339 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
15340 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
15341 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
15343 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
15344 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
15345 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
15346 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
15347 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
15348 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
15349 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
15350 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
15351 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
15352 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
15354 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
15355 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
15356 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
15358 #define NCH0 CM1NSELbits.NCH0 // bit 0, shadows bit in CM1NSELbits
15359 #define C1NCH0 CM1NSELbits.C1NCH0 // bit 0, shadows bit in CM1NSELbits
15360 #define NCH1 CM1NSELbits.NCH1 // bit 1, shadows bit in CM1NSELbits
15361 #define C1NCH1 CM1NSELbits.C1NCH1 // bit 1, shadows bit in CM1NSELbits
15362 #define NCH2 CM1NSELbits.NCH2 // bit 2, shadows bit in CM1NSELbits
15363 #define C1NCH2 CM1NSELbits.C1NCH2 // bit 2, shadows bit in CM1NSELbits
15365 #define PCH0 CM1PSELbits.PCH0 // bit 0, shadows bit in CM1PSELbits
15366 #define C1PCH0 CM1PSELbits.C1PCH0 // bit 0, shadows bit in CM1PSELbits
15367 #define PCH1 CM1PSELbits.PCH1 // bit 1, shadows bit in CM1PSELbits
15368 #define C1PCH1 CM1PSELbits.C1PCH1 // bit 1, shadows bit in CM1PSELbits
15369 #define PCH2 CM1PSELbits.PCH2 // bit 2, shadows bit in CM1PSELbits
15370 #define C1PCH2 CM1PSELbits.C1PCH2 // bit 2, shadows bit in CM1PSELbits
15371 #define PCH3 CM1PSELbits.PCH3 // bit 3, shadows bit in CM1PSELbits
15372 #define C1PCH3 CM1PSELbits.C1PCH3 // bit 3, shadows bit in CM1PSELbits
15374 #define MC1OUT CMOUTbits.MC1OUT // bit 0
15375 #define MC2OUT CMOUTbits.MC2OUT // bit 1
15376 #define MC3OUT CMOUTbits.MC3OUT // bit 2
15377 #define MC4OUT CMOUTbits.MC4OUT // bit 3
15379 #define ASDAC0 COG1ASD0bits.ASDAC0 // bit 2, shadows bit in COG1ASD0bits
15380 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2, shadows bit in COG1ASD0bits
15381 #define ASDAC1 COG1ASD0bits.ASDAC1 // bit 3, shadows bit in COG1ASD0bits
15382 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3, shadows bit in COG1ASD0bits
15383 #define ASDBD0 COG1ASD0bits.ASDBD0 // bit 4, shadows bit in COG1ASD0bits
15384 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4, shadows bit in COG1ASD0bits
15385 #define ASDBD1 COG1ASD0bits.ASDBD1 // bit 5, shadows bit in COG1ASD0bits
15386 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5, shadows bit in COG1ASD0bits
15387 #define ASREN COG1ASD0bits.ASREN // bit 6, shadows bit in COG1ASD0bits
15388 #define ARSEN COG1ASD0bits.ARSEN // bit 6, shadows bit in COG1ASD0bits
15389 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6, shadows bit in COG1ASD0bits
15390 #define G1ASREN COG1ASD0bits.G1ASREN // bit 6, shadows bit in COG1ASD0bits
15391 #define ASE COG1ASD0bits.ASE // bit 7, shadows bit in COG1ASD0bits
15392 #define G1ASE COG1ASD0bits.G1ASE // bit 7, shadows bit in COG1ASD0bits
15394 #define AS0E COG1ASD1bits.AS0E // bit 0, shadows bit in COG1ASD1bits
15395 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0, shadows bit in COG1ASD1bits
15396 #define AS1E COG1ASD1bits.AS1E // bit 1, shadows bit in COG1ASD1bits
15397 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1, shadows bit in COG1ASD1bits
15398 #define AS2E COG1ASD1bits.AS2E // bit 2, shadows bit in COG1ASD1bits
15399 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2, shadows bit in COG1ASD1bits
15400 #define AS3E COG1ASD1bits.AS3E // bit 3, shadows bit in COG1ASD1bits
15401 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3, shadows bit in COG1ASD1bits
15402 #define AS4E COG1ASD1bits.AS4E // bit 4, shadows bit in COG1ASD1bits
15403 #define G1AS4E COG1ASD1bits.G1AS4E // bit 4, shadows bit in COG1ASD1bits
15404 #define AS5E COG1ASD1bits.AS5E // bit 5, shadows bit in COG1ASD1bits
15405 #define G1AS5E COG1ASD1bits.G1AS5E // bit 5, shadows bit in COG1ASD1bits
15406 #define AS6E COG1ASD1bits.AS6E // bit 6, shadows bit in COG1ASD1bits
15407 #define G1AS6E COG1ASD1bits.G1AS6E // bit 6, shadows bit in COG1ASD1bits
15408 #define AS7E COG1ASD1bits.AS7E // bit 7, shadows bit in COG1ASD1bits
15409 #define G1AS7E COG1ASD1bits.G1AS7E // bit 7, shadows bit in COG1ASD1bits
15411 #define BLKF0 COG1BLKFbits.BLKF0 // bit 0, shadows bit in COG1BLKFbits
15412 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0, shadows bit in COG1BLKFbits
15413 #define BLKF1 COG1BLKFbits.BLKF1 // bit 1, shadows bit in COG1BLKFbits
15414 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1, shadows bit in COG1BLKFbits
15415 #define BLKF2 COG1BLKFbits.BLKF2 // bit 2, shadows bit in COG1BLKFbits
15416 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2, shadows bit in COG1BLKFbits
15417 #define BLKF3 COG1BLKFbits.BLKF3 // bit 3, shadows bit in COG1BLKFbits
15418 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3, shadows bit in COG1BLKFbits
15419 #define BLKF4 COG1BLKFbits.BLKF4 // bit 4, shadows bit in COG1BLKFbits
15420 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4, shadows bit in COG1BLKFbits
15421 #define BLKF5 COG1BLKFbits.BLKF5 // bit 5, shadows bit in COG1BLKFbits
15422 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5, shadows bit in COG1BLKFbits
15424 #define BLKR0 COG1BLKRbits.BLKR0 // bit 0, shadows bit in COG1BLKRbits
15425 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0, shadows bit in COG1BLKRbits
15426 #define BLKR1 COG1BLKRbits.BLKR1 // bit 1, shadows bit in COG1BLKRbits
15427 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1, shadows bit in COG1BLKRbits
15428 #define BLKR2 COG1BLKRbits.BLKR2 // bit 2, shadows bit in COG1BLKRbits
15429 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2, shadows bit in COG1BLKRbits
15430 #define BLKR3 COG1BLKRbits.BLKR3 // bit 3, shadows bit in COG1BLKRbits
15431 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3, shadows bit in COG1BLKRbits
15432 #define BLKR4 COG1BLKRbits.BLKR4 // bit 4, shadows bit in COG1BLKRbits
15433 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4, shadows bit in COG1BLKRbits
15434 #define BLKR5 COG1BLKRbits.BLKR5 // bit 5, shadows bit in COG1BLKRbits
15435 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5, shadows bit in COG1BLKRbits
15437 #define POLA COG1CON1bits.POLA // bit 0, shadows bit in COG1CON1bits
15438 #define G1POLA COG1CON1bits.G1POLA // bit 0, shadows bit in COG1CON1bits
15439 #define POLB COG1CON1bits.POLB // bit 1, shadows bit in COG1CON1bits
15440 #define G1POLB COG1CON1bits.G1POLB // bit 1, shadows bit in COG1CON1bits
15441 #define POLC COG1CON1bits.POLC // bit 2, shadows bit in COG1CON1bits
15442 #define G1POLC COG1CON1bits.G1POLC // bit 2, shadows bit in COG1CON1bits
15443 #define POLD COG1CON1bits.POLD // bit 3, shadows bit in COG1CON1bits
15444 #define G1POLD COG1CON1bits.G1POLD // bit 3, shadows bit in COG1CON1bits
15445 #define FDBS COG1CON1bits.FDBS // bit 6, shadows bit in COG1CON1bits
15446 #define G1FDBS COG1CON1bits.G1FDBS // bit 6, shadows bit in COG1CON1bits
15447 #define RDBS COG1CON1bits.RDBS // bit 7, shadows bit in COG1CON1bits
15448 #define G1RDBS COG1CON1bits.G1RDBS // bit 7, shadows bit in COG1CON1bits
15450 #define DBF0 COG1DBFbits.DBF0 // bit 0, shadows bit in COG1DBFbits
15451 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0, shadows bit in COG1DBFbits
15452 #define DBF1 COG1DBFbits.DBF1 // bit 1, shadows bit in COG1DBFbits
15453 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1, shadows bit in COG1DBFbits
15454 #define DBF2 COG1DBFbits.DBF2 // bit 2, shadows bit in COG1DBFbits
15455 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2, shadows bit in COG1DBFbits
15456 #define DBF3 COG1DBFbits.DBF3 // bit 3, shadows bit in COG1DBFbits
15457 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3, shadows bit in COG1DBFbits
15458 #define DBF4 COG1DBFbits.DBF4 // bit 4, shadows bit in COG1DBFbits
15459 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4, shadows bit in COG1DBFbits
15460 #define DBF5 COG1DBFbits.DBF5 // bit 5, shadows bit in COG1DBFbits
15461 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5, shadows bit in COG1DBFbits
15463 #define DBR0 COG1DBRbits.DBR0 // bit 0, shadows bit in COG1DBRbits
15464 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0, shadows bit in COG1DBRbits
15465 #define DBR1 COG1DBRbits.DBR1 // bit 1, shadows bit in COG1DBRbits
15466 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1, shadows bit in COG1DBRbits
15467 #define DBR2 COG1DBRbits.DBR2 // bit 2, shadows bit in COG1DBRbits
15468 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2, shadows bit in COG1DBRbits
15469 #define DBR3 COG1DBRbits.DBR3 // bit 3, shadows bit in COG1DBRbits
15470 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3, shadows bit in COG1DBRbits
15471 #define DBR4 COG1DBRbits.DBR4 // bit 4, shadows bit in COG1DBRbits
15472 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4, shadows bit in COG1DBRbits
15473 #define DBR5 COG1DBRbits.DBR5 // bit 5, shadows bit in COG1DBRbits
15474 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5, shadows bit in COG1DBRbits
15476 #define FIS0 COG1FIS0bits.FIS0 // bit 0, shadows bit in COG1FIS0bits
15477 #define G1FIS0 COG1FIS0bits.G1FIS0 // bit 0, shadows bit in COG1FIS0bits
15478 #define FIS1 COG1FIS0bits.FIS1 // bit 1, shadows bit in COG1FIS0bits
15479 #define G1FIS1 COG1FIS0bits.G1FIS1 // bit 1, shadows bit in COG1FIS0bits
15480 #define FIS2 COG1FIS0bits.FIS2 // bit 2, shadows bit in COG1FIS0bits
15481 #define G1FIS2 COG1FIS0bits.G1FIS2 // bit 2, shadows bit in COG1FIS0bits
15482 #define FIS3 COG1FIS0bits.FIS3 // bit 3, shadows bit in COG1FIS0bits
15483 #define G1FIS3 COG1FIS0bits.G1FIS3 // bit 3, shadows bit in COG1FIS0bits
15484 #define FIS4 COG1FIS0bits.FIS4 // bit 4, shadows bit in COG1FIS0bits
15485 #define G1FIS4 COG1FIS0bits.G1FIS4 // bit 4, shadows bit in COG1FIS0bits
15486 #define FIS5 COG1FIS0bits.FIS5 // bit 5, shadows bit in COG1FIS0bits
15487 #define G1FIS5 COG1FIS0bits.G1FIS5 // bit 5, shadows bit in COG1FIS0bits
15488 #define FIS6 COG1FIS0bits.FIS6 // bit 6, shadows bit in COG1FIS0bits
15489 #define G1FIS6 COG1FIS0bits.G1FIS6 // bit 6, shadows bit in COG1FIS0bits
15490 #define FIS7 COG1FIS0bits.FIS7 // bit 7, shadows bit in COG1FIS0bits
15491 #define G1FIS7 COG1FIS0bits.G1FIS7 // bit 7, shadows bit in COG1FIS0bits
15493 #define FIS8 COG1FIS1bits.FIS8 // bit 0, shadows bit in COG1FIS1bits
15494 #define G1FIS8 COG1FIS1bits.G1FIS8 // bit 0, shadows bit in COG1FIS1bits
15495 #define FIS9 COG1FIS1bits.FIS9 // bit 1, shadows bit in COG1FIS1bits
15496 #define G1FIS9 COG1FIS1bits.G1FIS9 // bit 1, shadows bit in COG1FIS1bits
15497 #define FIS10 COG1FIS1bits.FIS10 // bit 2, shadows bit in COG1FIS1bits
15498 #define G1FIS10 COG1FIS1bits.G1FIS10 // bit 2, shadows bit in COG1FIS1bits
15499 #define FIS11 COG1FIS1bits.FIS11 // bit 3, shadows bit in COG1FIS1bits
15500 #define G1FIS11 COG1FIS1bits.G1FIS11 // bit 3, shadows bit in COG1FIS1bits
15501 #define FIS12 COG1FIS1bits.FIS12 // bit 4, shadows bit in COG1FIS1bits
15502 #define G1FIS12 COG1FIS1bits.G1FIS12 // bit 4, shadows bit in COG1FIS1bits
15503 #define FIS13 COG1FIS1bits.FIS13 // bit 5, shadows bit in COG1FIS1bits
15504 #define G1FIS13 COG1FIS1bits.G1FIS13 // bit 5, shadows bit in COG1FIS1bits
15505 #define FIS14 COG1FIS1bits.FIS14 // bit 6, shadows bit in COG1FIS1bits
15506 #define G1FIS14 COG1FIS1bits.G1FIS14 // bit 6, shadows bit in COG1FIS1bits
15507 #define FIS15 COG1FIS1bits.FIS15 // bit 7, shadows bit in COG1FIS1bits
15508 #define G1FIS15 COG1FIS1bits.G1FIS15 // bit 7, shadows bit in COG1FIS1bits
15510 #define FSIM0 COG1FSIM0bits.FSIM0 // bit 0, shadows bit in COG1FSIM0bits
15511 #define G1FSIM0 COG1FSIM0bits.G1FSIM0 // bit 0, shadows bit in COG1FSIM0bits
15512 #define FSIM1 COG1FSIM0bits.FSIM1 // bit 1, shadows bit in COG1FSIM0bits
15513 #define G1FSIM1 COG1FSIM0bits.G1FSIM1 // bit 1, shadows bit in COG1FSIM0bits
15514 #define FSIM2 COG1FSIM0bits.FSIM2 // bit 2, shadows bit in COG1FSIM0bits
15515 #define G1FSIM2 COG1FSIM0bits.G1FSIM2 // bit 2, shadows bit in COG1FSIM0bits
15516 #define FSIM3 COG1FSIM0bits.FSIM3 // bit 3, shadows bit in COG1FSIM0bits
15517 #define G1FSIM3 COG1FSIM0bits.G1FSIM3 // bit 3, shadows bit in COG1FSIM0bits
15518 #define FSIM4 COG1FSIM0bits.FSIM4 // bit 4, shadows bit in COG1FSIM0bits
15519 #define G1FSIM4 COG1FSIM0bits.G1FSIM4 // bit 4, shadows bit in COG1FSIM0bits
15520 #define FSIM5 COG1FSIM0bits.FSIM5 // bit 5, shadows bit in COG1FSIM0bits
15521 #define G1FSIM5 COG1FSIM0bits.G1FSIM5 // bit 5, shadows bit in COG1FSIM0bits
15522 #define FSIM6 COG1FSIM0bits.FSIM6 // bit 6, shadows bit in COG1FSIM0bits
15523 #define G1FSIM6 COG1FSIM0bits.G1FSIM6 // bit 6, shadows bit in COG1FSIM0bits
15524 #define FSIM7 COG1FSIM0bits.FSIM7 // bit 7, shadows bit in COG1FSIM0bits
15525 #define G1FSIM7 COG1FSIM0bits.G1FSIM7 // bit 7, shadows bit in COG1FSIM0bits
15527 #define FSIM8 COG1FSIM1bits.FSIM8 // bit 0, shadows bit in COG1FSIM1bits
15528 #define G1FSIM8 COG1FSIM1bits.G1FSIM8 // bit 0, shadows bit in COG1FSIM1bits
15529 #define FSIM9 COG1FSIM1bits.FSIM9 // bit 1, shadows bit in COG1FSIM1bits
15530 #define G1FSIM9 COG1FSIM1bits.G1FSIM9 // bit 1, shadows bit in COG1FSIM1bits
15531 #define FSIM10 COG1FSIM1bits.FSIM10 // bit 2, shadows bit in COG1FSIM1bits
15532 #define G1FSIM10 COG1FSIM1bits.G1FSIM10 // bit 2, shadows bit in COG1FSIM1bits
15533 #define FSIM11 COG1FSIM1bits.FSIM11 // bit 3, shadows bit in COG1FSIM1bits
15534 #define G1FSIM11 COG1FSIM1bits.G1FSIM11 // bit 3, shadows bit in COG1FSIM1bits
15535 #define FSIM12 COG1FSIM1bits.FSIM12 // bit 4, shadows bit in COG1FSIM1bits
15536 #define G1FSIM12 COG1FSIM1bits.G1FSIM12 // bit 4, shadows bit in COG1FSIM1bits
15537 #define FSIM13 COG1FSIM1bits.FSIM13 // bit 5, shadows bit in COG1FSIM1bits
15538 #define G1FSIM13 COG1FSIM1bits.G1FSIM13 // bit 5, shadows bit in COG1FSIM1bits
15539 #define FSIM14 COG1FSIM1bits.FSIM14 // bit 6, shadows bit in COG1FSIM1bits
15540 #define G1FSIM14 COG1FSIM1bits.G1FSIM14 // bit 6, shadows bit in COG1FSIM1bits
15541 #define FSIM15 COG1FSIM1bits.FSIM15 // bit 7, shadows bit in COG1FSIM1bits
15542 #define G1FSIM15 COG1FSIM1bits.G1FSIM15 // bit 7, shadows bit in COG1FSIM1bits
15544 #define PHF0 COG1PHFbits.PHF0 // bit 0, shadows bit in COG1PHFbits
15545 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0, shadows bit in COG1PHFbits
15546 #define PHF1 COG1PHFbits.PHF1 // bit 1, shadows bit in COG1PHFbits
15547 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1, shadows bit in COG1PHFbits
15548 #define PHF2 COG1PHFbits.PHF2 // bit 2, shadows bit in COG1PHFbits
15549 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2, shadows bit in COG1PHFbits
15550 #define PHF3 COG1PHFbits.PHF3 // bit 3, shadows bit in COG1PHFbits
15551 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3, shadows bit in COG1PHFbits
15552 #define PHF4 COG1PHFbits.PHF4 // bit 4, shadows bit in COG1PHFbits
15553 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4, shadows bit in COG1PHFbits
15554 #define PHF5 COG1PHFbits.PHF5 // bit 5, shadows bit in COG1PHFbits
15555 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5, shadows bit in COG1PHFbits
15557 #define PHR0 COG1PHRbits.PHR0 // bit 0, shadows bit in COG1PHRbits
15558 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0, shadows bit in COG1PHRbits
15559 #define PHR1 COG1PHRbits.PHR1 // bit 1, shadows bit in COG1PHRbits
15560 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1, shadows bit in COG1PHRbits
15561 #define PHR2 COG1PHRbits.PHR2 // bit 2, shadows bit in COG1PHRbits
15562 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2, shadows bit in COG1PHRbits
15563 #define PHR3 COG1PHRbits.PHR3 // bit 3, shadows bit in COG1PHRbits
15564 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3, shadows bit in COG1PHRbits
15565 #define PHR4 COG1PHRbits.PHR4 // bit 4, shadows bit in COG1PHRbits
15566 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4, shadows bit in COG1PHRbits
15567 #define PHR5 COG1PHRbits.PHR5 // bit 5, shadows bit in COG1PHRbits
15568 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5, shadows bit in COG1PHRbits
15570 #define RIS0 COG1RIS0bits.RIS0 // bit 0, shadows bit in COG1RIS0bits
15571 #define G1RIS0 COG1RIS0bits.G1RIS0 // bit 0, shadows bit in COG1RIS0bits
15572 #define RIS1 COG1RIS0bits.RIS1 // bit 1, shadows bit in COG1RIS0bits
15573 #define G1RIS1 COG1RIS0bits.G1RIS1 // bit 1, shadows bit in COG1RIS0bits
15574 #define RIS2 COG1RIS0bits.RIS2 // bit 2, shadows bit in COG1RIS0bits
15575 #define G1RIS2 COG1RIS0bits.G1RIS2 // bit 2, shadows bit in COG1RIS0bits
15576 #define RIS3 COG1RIS0bits.RIS3 // bit 3, shadows bit in COG1RIS0bits
15577 #define G1RIS3 COG1RIS0bits.G1RIS3 // bit 3, shadows bit in COG1RIS0bits
15578 #define RIS4 COG1RIS0bits.RIS4 // bit 4, shadows bit in COG1RIS0bits
15579 #define G1RIS4 COG1RIS0bits.G1RIS4 // bit 4, shadows bit in COG1RIS0bits
15580 #define RIS5 COG1RIS0bits.RIS5 // bit 5, shadows bit in COG1RIS0bits
15581 #define G1RIS5 COG1RIS0bits.G1RIS5 // bit 5, shadows bit in COG1RIS0bits
15582 #define RIS6 COG1RIS0bits.RIS6 // bit 6, shadows bit in COG1RIS0bits
15583 #define G1RIS6 COG1RIS0bits.G1RIS6 // bit 6, shadows bit in COG1RIS0bits
15584 #define RIS7 COG1RIS0bits.RIS7 // bit 7, shadows bit in COG1RIS0bits
15585 #define G1RIS7 COG1RIS0bits.G1RIS7 // bit 7, shadows bit in COG1RIS0bits
15587 #define RIS8 COG1RIS1bits.RIS8 // bit 0, shadows bit in COG1RIS1bits
15588 #define G1RIS8 COG1RIS1bits.G1RIS8 // bit 0, shadows bit in COG1RIS1bits
15589 #define RIS9 COG1RIS1bits.RIS9 // bit 1, shadows bit in COG1RIS1bits
15590 #define G1RIS9 COG1RIS1bits.G1RIS9 // bit 1, shadows bit in COG1RIS1bits
15591 #define RIS10 COG1RIS1bits.RIS10 // bit 2, shadows bit in COG1RIS1bits
15592 #define G1RIS10 COG1RIS1bits.G1RIS10 // bit 2, shadows bit in COG1RIS1bits
15593 #define RIS11 COG1RIS1bits.RIS11 // bit 3, shadows bit in COG1RIS1bits
15594 #define G1RIS11 COG1RIS1bits.G1RIS11 // bit 3, shadows bit in COG1RIS1bits
15595 #define RIS12 COG1RIS1bits.RIS12 // bit 4, shadows bit in COG1RIS1bits
15596 #define G1RIS12 COG1RIS1bits.G1RIS12 // bit 4, shadows bit in COG1RIS1bits
15597 #define RIS13 COG1RIS1bits.RIS13 // bit 5, shadows bit in COG1RIS1bits
15598 #define G1RIS13 COG1RIS1bits.G1RIS13 // bit 5, shadows bit in COG1RIS1bits
15599 #define RIS14 COG1RIS1bits.RIS14 // bit 6, shadows bit in COG1RIS1bits
15600 #define G1RIS14 COG1RIS1bits.G1RIS14 // bit 6, shadows bit in COG1RIS1bits
15601 #define RIS15 COG1RIS1bits.RIS15 // bit 7, shadows bit in COG1RIS1bits
15602 #define G1RIS15 COG1RIS1bits.G1RIS15 // bit 7, shadows bit in COG1RIS1bits
15604 #define RSIM0 COG1RSIM0bits.RSIM0 // bit 0, shadows bit in COG1RSIM0bits
15605 #define G1RSIM0 COG1RSIM0bits.G1RSIM0 // bit 0, shadows bit in COG1RSIM0bits
15606 #define RSIM1 COG1RSIM0bits.RSIM1 // bit 1, shadows bit in COG1RSIM0bits
15607 #define G1RSIM1 COG1RSIM0bits.G1RSIM1 // bit 1, shadows bit in COG1RSIM0bits
15608 #define RSIM2 COG1RSIM0bits.RSIM2 // bit 2, shadows bit in COG1RSIM0bits
15609 #define G1RSIM2 COG1RSIM0bits.G1RSIM2 // bit 2, shadows bit in COG1RSIM0bits
15610 #define RSIM3 COG1RSIM0bits.RSIM3 // bit 3, shadows bit in COG1RSIM0bits
15611 #define G1RSIM3 COG1RSIM0bits.G1RSIM3 // bit 3, shadows bit in COG1RSIM0bits
15612 #define RSIM4 COG1RSIM0bits.RSIM4 // bit 4, shadows bit in COG1RSIM0bits
15613 #define G1RSIM4 COG1RSIM0bits.G1RSIM4 // bit 4, shadows bit in COG1RSIM0bits
15614 #define RSIM5 COG1RSIM0bits.RSIM5 // bit 5, shadows bit in COG1RSIM0bits
15615 #define G1RSIM5 COG1RSIM0bits.G1RSIM5 // bit 5, shadows bit in COG1RSIM0bits
15616 #define RSIM6 COG1RSIM0bits.RSIM6 // bit 6, shadows bit in COG1RSIM0bits
15617 #define G1RSIM6 COG1RSIM0bits.G1RSIM6 // bit 6, shadows bit in COG1RSIM0bits
15618 #define RSIM7 COG1RSIM0bits.RSIM7 // bit 7, shadows bit in COG1RSIM0bits
15619 #define G1RSIM7 COG1RSIM0bits.G1RSIM7 // bit 7, shadows bit in COG1RSIM0bits
15621 #define RSIM8 COG1RSIM1bits.RSIM8 // bit 0, shadows bit in COG1RSIM1bits
15622 #define G1RSIM8 COG1RSIM1bits.G1RSIM8 // bit 0, shadows bit in COG1RSIM1bits
15623 #define RSIM9 COG1RSIM1bits.RSIM9 // bit 1, shadows bit in COG1RSIM1bits
15624 #define G1RSIM9 COG1RSIM1bits.G1RSIM9 // bit 1, shadows bit in COG1RSIM1bits
15625 #define RSIM10 COG1RSIM1bits.RSIM10 // bit 2, shadows bit in COG1RSIM1bits
15626 #define G1RSIM10 COG1RSIM1bits.G1RSIM10 // bit 2, shadows bit in COG1RSIM1bits
15627 #define RSIM11 COG1RSIM1bits.RSIM11 // bit 3, shadows bit in COG1RSIM1bits
15628 #define G1RSIM11 COG1RSIM1bits.G1RSIM11 // bit 3, shadows bit in COG1RSIM1bits
15629 #define RSIM12 COG1RSIM1bits.RSIM12 // bit 4, shadows bit in COG1RSIM1bits
15630 #define G1RSIM12 COG1RSIM1bits.G1RSIM12 // bit 4, shadows bit in COG1RSIM1bits
15631 #define RSIM13 COG1RSIM1bits.RSIM13 // bit 5, shadows bit in COG1RSIM1bits
15632 #define G1RSIM13 COG1RSIM1bits.G1RSIM13 // bit 5, shadows bit in COG1RSIM1bits
15633 #define RSIM14 COG1RSIM1bits.RSIM14 // bit 6, shadows bit in COG1RSIM1bits
15634 #define G1RSIM14 COG1RSIM1bits.G1RSIM14 // bit 6, shadows bit in COG1RSIM1bits
15635 #define RSIM15 COG1RSIM1bits.RSIM15 // bit 7, shadows bit in COG1RSIM1bits
15636 #define G1RSIM15 COG1RSIM1bits.G1RSIM15 // bit 7, shadows bit in COG1RSIM1bits
15638 #define STRA COG1STRbits.STRA // bit 0, shadows bit in COG1STRbits
15639 #define G1STRA COG1STRbits.G1STRA // bit 0, shadows bit in COG1STRbits
15640 #define STRB COG1STRbits.STRB // bit 1, shadows bit in COG1STRbits
15641 #define G1STRB COG1STRbits.G1STRB // bit 1, shadows bit in COG1STRbits
15642 #define STRC COG1STRbits.STRC // bit 2, shadows bit in COG1STRbits
15643 #define G1STRC COG1STRbits.G1STRC // bit 2, shadows bit in COG1STRbits
15644 #define STRD COG1STRbits.STRD // bit 3, shadows bit in COG1STRbits
15645 #define G1STRD COG1STRbits.G1STRD // bit 3, shadows bit in COG1STRbits
15646 #define SDATA COG1STRbits.SDATA // bit 4, shadows bit in COG1STRbits
15647 #define G1SDATA COG1STRbits.G1SDATA // bit 4, shadows bit in COG1STRbits
15648 #define SDATB COG1STRbits.SDATB // bit 5, shadows bit in COG1STRbits
15649 #define G1SDATB COG1STRbits.G1SDATB // bit 5, shadows bit in COG1STRbits
15650 #define SDATC COG1STRbits.SDATC // bit 6, shadows bit in COG1STRbits
15651 #define G1SDATC COG1STRbits.G1SDATC // bit 6, shadows bit in COG1STRbits
15652 #define SDATD COG1STRbits.SDATD // bit 7, shadows bit in COG1STRbits
15653 #define G1SDATD COG1STRbits.G1SDATD // bit 7, shadows bit in COG1STRbits
15655 #define REF0 DAC1CON1bits.REF0 // bit 0, shadows bit in DAC1CON1bits
15656 #define DAC1REF0 DAC1CON1bits.DAC1REF0 // bit 0, shadows bit in DAC1CON1bits
15657 #define R0 DAC1CON1bits.R0 // bit 0, shadows bit in DAC1CON1bits
15658 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
15659 #define REF1 DAC1CON1bits.REF1 // bit 1, shadows bit in DAC1CON1bits
15660 #define DAC1REF1 DAC1CON1bits.DAC1REF1 // bit 1, shadows bit in DAC1CON1bits
15661 #define R1 DAC1CON1bits.R1 // bit 1, shadows bit in DAC1CON1bits
15662 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
15663 #define REF2 DAC1CON1bits.REF2 // bit 2, shadows bit in DAC1CON1bits
15664 #define DAC1REF2 DAC1CON1bits.DAC1REF2 // bit 2, shadows bit in DAC1CON1bits
15665 #define R2 DAC1CON1bits.R2 // bit 2, shadows bit in DAC1CON1bits
15666 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
15667 #define REF3 DAC1CON1bits.REF3 // bit 3, shadows bit in DAC1CON1bits
15668 #define DAC1REF3 DAC1CON1bits.DAC1REF3 // bit 3, shadows bit in DAC1CON1bits
15669 #define R3 DAC1CON1bits.R3 // bit 3, shadows bit in DAC1CON1bits
15670 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
15671 #define REF4 DAC1CON1bits.REF4 // bit 4, shadows bit in DAC1CON1bits
15672 #define DAC1REF4 DAC1CON1bits.DAC1REF4 // bit 4, shadows bit in DAC1CON1bits
15673 #define R4 DAC1CON1bits.R4 // bit 4, shadows bit in DAC1CON1bits
15674 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
15675 #define REF5 DAC1CON1bits.REF5 // bit 5, shadows bit in DAC1CON1bits
15676 #define DAC1REF5 DAC1CON1bits.DAC1REF5 // bit 5, shadows bit in DAC1CON1bits
15677 #define R5 DAC1CON1bits.R5 // bit 5, shadows bit in DAC1CON1bits
15678 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
15679 #define REF6 DAC1CON1bits.REF6 // bit 6, shadows bit in DAC1CON1bits
15680 #define DAC1REF6 DAC1CON1bits.DAC1REF6 // bit 6, shadows bit in DAC1CON1bits
15681 #define R6 DAC1CON1bits.R6 // bit 6, shadows bit in DAC1CON1bits
15682 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
15683 #define REF7 DAC1CON1bits.REF7 // bit 7, shadows bit in DAC1CON1bits
15684 #define DAC1REF7 DAC1CON1bits.DAC1REF7 // bit 7, shadows bit in DAC1CON1bits
15685 #define R7 DAC1CON1bits.R7 // bit 7, shadows bit in DAC1CON1bits
15686 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
15688 #define REF8 DAC1CON2bits.REF8 // bit 0, shadows bit in DAC1CON2bits
15689 #define DAC1REF8 DAC1CON2bits.DAC1REF8 // bit 0, shadows bit in DAC1CON2bits
15690 #define R8 DAC1CON2bits.R8 // bit 0, shadows bit in DAC1CON2bits
15691 #define DAC1R8 DAC1CON2bits.DAC1R8 // bit 0, shadows bit in DAC1CON2bits
15692 #define REF9 DAC1CON2bits.REF9 // bit 1, shadows bit in DAC1CON2bits
15693 #define DAC1REF9 DAC1CON2bits.DAC1REF9 // bit 1, shadows bit in DAC1CON2bits
15694 #define R9 DAC1CON2bits.R9 // bit 1, shadows bit in DAC1CON2bits
15695 #define DAC1R9 DAC1CON2bits.DAC1R9 // bit 1, shadows bit in DAC1CON2bits
15696 #define REF10 DAC1CON2bits.REF10 // bit 2, shadows bit in DAC1CON2bits
15697 #define DAC1REF10 DAC1CON2bits.DAC1REF10 // bit 2, shadows bit in DAC1CON2bits
15698 #define R10 DAC1CON2bits.R10 // bit 2, shadows bit in DAC1CON2bits
15699 #define DAC1R10 DAC1CON2bits.DAC1R10 // bit 2, shadows bit in DAC1CON2bits
15700 #define REF11 DAC1CON2bits.REF11 // bit 3, shadows bit in DAC1CON2bits
15701 #define DAC1REF11 DAC1CON2bits.DAC1REF11 // bit 3, shadows bit in DAC1CON2bits
15702 #define R11 DAC1CON2bits.R11 // bit 3, shadows bit in DAC1CON2bits
15703 #define DAC1R11 DAC1CON2bits.DAC1R11 // bit 3, shadows bit in DAC1CON2bits
15704 #define REF12 DAC1CON2bits.REF12 // bit 4, shadows bit in DAC1CON2bits
15705 #define DAC1REF12 DAC1CON2bits.DAC1REF12 // bit 4, shadows bit in DAC1CON2bits
15706 #define R12 DAC1CON2bits.R12 // bit 4, shadows bit in DAC1CON2bits
15707 #define DAC1R12 DAC1CON2bits.DAC1R12 // bit 4, shadows bit in DAC1CON2bits
15708 #define REF13 DAC1CON2bits.REF13 // bit 5, shadows bit in DAC1CON2bits
15709 #define DAC1REF13 DAC1CON2bits.DAC1REF13 // bit 5, shadows bit in DAC1CON2bits
15710 #define R13 DAC1CON2bits.R13 // bit 5, shadows bit in DAC1CON2bits
15711 #define DAC1R13 DAC1CON2bits.DAC1R13 // bit 5, shadows bit in DAC1CON2bits
15712 #define REF14 DAC1CON2bits.REF14 // bit 6, shadows bit in DAC1CON2bits
15713 #define DAC1REF14 DAC1CON2bits.DAC1REF14 // bit 6, shadows bit in DAC1CON2bits
15714 #define R14 DAC1CON2bits.R14 // bit 6, shadows bit in DAC1CON2bits
15715 #define DAC1R14 DAC1CON2bits.DAC1R14 // bit 6, shadows bit in DAC1CON2bits
15716 #define REF15 DAC1CON2bits.REF15 // bit 7, shadows bit in DAC1CON2bits
15717 #define DAC1REF15 DAC1CON2bits.DAC1REF15 // bit 7, shadows bit in DAC1CON2bits
15718 #define R15 DAC1CON2bits.R15 // bit 7, shadows bit in DAC1CON2bits
15719 #define DAC1R15 DAC1CON2bits.DAC1R15 // bit 7, shadows bit in DAC1CON2bits
15721 #define DAC1LD DACLDbits.DAC1LD // bit 0
15722 #define DAC2LD DACLDbits.DAC2LD // bit 1
15724 #define TSRNG FVRCONbits.TSRNG // bit 4
15725 #define TSEN FVRCONbits.TSEN // bit 5
15726 #define FVRRDY FVRCONbits.FVRRDY // bit 6
15727 #define FVREN FVRCONbits.FVREN // bit 7
15729 #define HIDC4 HIDRVCbits.HIDC4 // bit 4
15730 #define HIDC5 HIDRVCbits.HIDC5 // bit 5
15732 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
15733 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
15734 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
15735 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
15736 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
15737 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
15739 #define INLVLB4 INLVLBbits.INLVLB4 // bit 4
15740 #define INLVLB5 INLVLBbits.INLVLB5 // bit 5
15741 #define INLVLB6 INLVLBbits.INLVLB6 // bit 6
15742 #define INLVLB7 INLVLBbits.INLVLB7 // bit 7
15744 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
15745 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
15746 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
15747 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
15748 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
15749 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
15750 #define INLVLC6 INLVLCbits.INLVLC6 // bit 6
15751 #define INLVLC7 INLVLCbits.INLVLC7 // bit 7
15753 #define IOCIF INTCONbits.IOCIF // bit 0
15754 #define INTF INTCONbits.INTF // bit 1
15755 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
15756 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
15757 #define IOCIE INTCONbits.IOCIE // bit 3
15758 #define INTE INTCONbits.INTE // bit 4
15759 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
15760 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
15761 #define PEIE INTCONbits.PEIE // bit 6
15762 #define GIE INTCONbits.GIE // bit 7
15764 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
15765 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
15766 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
15767 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
15768 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
15769 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
15771 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
15772 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
15773 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
15774 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
15775 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
15776 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
15778 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
15779 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
15780 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
15781 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
15782 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
15783 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
15785 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
15786 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
15787 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
15788 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
15790 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
15791 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
15792 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
15793 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
15795 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
15796 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
15797 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
15798 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
15800 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
15801 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
15802 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
15803 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
15804 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
15805 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
15806 #define IOCCF6 IOCCFbits.IOCCF6 // bit 6
15807 #define IOCCF7 IOCCFbits.IOCCF7 // bit 7
15809 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
15810 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
15811 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
15812 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
15813 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
15814 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
15815 #define IOCCN6 IOCCNbits.IOCCN6 // bit 6
15816 #define IOCCN7 IOCCNbits.IOCCN7 // bit 7
15818 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
15819 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
15820 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
15821 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
15822 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
15823 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
15824 #define IOCCP6 IOCCPbits.IOCCP6 // bit 6
15825 #define IOCCP7 IOCCPbits.IOCCP7 // bit 7
15827 #define LATA0 LATAbits.LATA0 // bit 0
15828 #define LATA1 LATAbits.LATA1 // bit 1
15829 #define LATA2 LATAbits.LATA2 // bit 2
15830 #define LATA4 LATAbits.LATA4 // bit 4
15831 #define LATA5 LATAbits.LATA5 // bit 5
15833 #define LATB4 LATBbits.LATB4 // bit 4
15834 #define LATB5 LATBbits.LATB5 // bit 5
15835 #define LATB6 LATBbits.LATB6 // bit 6
15836 #define LATB7 LATBbits.LATB7 // bit 7
15838 #define LATC0 LATCbits.LATC0 // bit 0
15839 #define LATC1 LATCbits.LATC1 // bit 1
15840 #define LATC2 LATCbits.LATC2 // bit 2
15841 #define LATC3 LATCbits.LATC3 // bit 3
15842 #define LATC4 LATCbits.LATC4 // bit 4
15843 #define LATC5 LATCbits.LATC5 // bit 5
15844 #define LATC6 LATCbits.LATC6 // bit 6
15845 #define LATC7 LATCbits.LATC7 // bit 7
15847 #define CH0 MD1CARHbits.CH0 // bit 0, shadows bit in MD1CARHbits
15848 #define MD1CH0 MD1CARHbits.MD1CH0 // bit 0, shadows bit in MD1CARHbits
15849 #define CH1 MD1CARHbits.CH1 // bit 1, shadows bit in MD1CARHbits
15850 #define MD1CH1 MD1CARHbits.MD1CH1 // bit 1, shadows bit in MD1CARHbits
15851 #define CH2 MD1CARHbits.CH2 // bit 2, shadows bit in MD1CARHbits
15852 #define MD1CH2 MD1CARHbits.MD1CH2 // bit 2, shadows bit in MD1CARHbits
15853 #define CH3 MD1CARHbits.CH3 // bit 3, shadows bit in MD1CARHbits
15854 #define MD1CH3 MD1CARHbits.MD1CH3 // bit 3, shadows bit in MD1CARHbits
15856 #define CL0 MD1CARLbits.CL0 // bit 0, shadows bit in MD1CARLbits
15857 #define MD1CL0 MD1CARLbits.MD1CL0 // bit 0, shadows bit in MD1CARLbits
15858 #define CL1 MD1CARLbits.CL1 // bit 1, shadows bit in MD1CARLbits
15859 #define MD1CL1 MD1CARLbits.MD1CL1 // bit 1, shadows bit in MD1CARLbits
15860 #define CL2 MD1CARLbits.CL2 // bit 2, shadows bit in MD1CARLbits
15861 #define MD1CL2 MD1CARLbits.MD1CL2 // bit 2, shadows bit in MD1CARLbits
15862 #define CL3 MD1CARLbits.CL3 // bit 3, shadows bit in MD1CARLbits
15863 #define MD1CL3 MD1CARLbits.MD1CL3 // bit 3, shadows bit in MD1CARLbits
15865 #define CLSYNC MD1CON1bits.CLSYNC // bit 0, shadows bit in MD1CON1bits
15866 #define MD1CLSYNC MD1CON1bits.MD1CLSYNC // bit 0, shadows bit in MD1CON1bits
15867 #define CLPOL MD1CON1bits.CLPOL // bit 1, shadows bit in MD1CON1bits
15868 #define MD1CLPOL MD1CON1bits.MD1CLPOL // bit 1, shadows bit in MD1CON1bits
15869 #define CHSYNC MD1CON1bits.CHSYNC // bit 4, shadows bit in MD1CON1bits
15870 #define MD1CHSYNC MD1CON1bits.MD1CHSYNC // bit 4, shadows bit in MD1CON1bits
15871 #define CHPOL MD1CON1bits.CHPOL // bit 5, shadows bit in MD1CON1bits
15872 #define MD1CHPOL MD1CON1bits.MD1CHPOL // bit 5, shadows bit in MD1CON1bits
15874 #define MS0 MD1SRCbits.MS0 // bit 0, shadows bit in MD1SRCbits
15875 #define MD1MS0 MD1SRCbits.MD1MS0 // bit 0, shadows bit in MD1SRCbits
15876 #define MS1 MD1SRCbits.MS1 // bit 1, shadows bit in MD1SRCbits
15877 #define MD1MS1 MD1SRCbits.MD1MS1 // bit 1, shadows bit in MD1SRCbits
15878 #define MS2 MD1SRCbits.MS2 // bit 2, shadows bit in MD1SRCbits
15879 #define MD1MS2 MD1SRCbits.MD1MS2 // bit 2, shadows bit in MD1SRCbits
15880 #define MS3 MD1SRCbits.MS3 // bit 3, shadows bit in MD1SRCbits
15881 #define MD1MS3 MD1SRCbits.MD1MS3 // bit 3, shadows bit in MD1SRCbits
15882 #define MS4 MD1SRCbits.MS4 // bit 4, shadows bit in MD1SRCbits
15883 #define MD1MS4 MD1SRCbits.MD1MS4 // bit 4, shadows bit in MD1SRCbits
15885 #define ODA0 ODCONAbits.ODA0 // bit 0
15886 #define ODA1 ODCONAbits.ODA1 // bit 1
15887 #define ODA2 ODCONAbits.ODA2 // bit 2
15888 #define ODA4 ODCONAbits.ODA4 // bit 4
15889 #define ODA5 ODCONAbits.ODA5 // bit 5
15891 #define ODB4 ODCONBbits.ODB4 // bit 4
15892 #define ODB5 ODCONBbits.ODB5 // bit 5
15893 #define ODB6 ODCONBbits.ODB6 // bit 6
15894 #define ODB7 ODCONBbits.ODB7 // bit 7
15896 #define ODC0 ODCONCbits.ODC0 // bit 0
15897 #define ODC1 ODCONCbits.ODC1 // bit 1
15898 #define ODC2 ODCONCbits.ODC2 // bit 2
15899 #define ODC3 ODCONCbits.ODC3 // bit 3
15900 #define ODC4 ODCONCbits.ODC4 // bit 4
15901 #define ODC5 ODCONCbits.ODC5 // bit 5
15902 #define ODC6 ODCONCbits.ODC6 // bit 6
15903 #define ODC7 ODCONCbits.ODC7 // bit 7
15905 #define PS0 OPTION_REGbits.PS0 // bit 0
15906 #define PS1 OPTION_REGbits.PS1 // bit 1
15907 #define PS2 OPTION_REGbits.PS2 // bit 2
15908 #define PSA OPTION_REGbits.PSA // bit 3
15909 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
15910 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
15911 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
15912 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
15913 #define INTEDG OPTION_REGbits.INTEDG // bit 6
15914 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
15916 #define SCS0 OSCCONbits.SCS0 // bit 0
15917 #define SCS1 OSCCONbits.SCS1 // bit 1
15918 #define IRCF0 OSCCONbits.IRCF0 // bit 3
15919 #define IRCF1 OSCCONbits.IRCF1 // bit 4
15920 #define IRCF2 OSCCONbits.IRCF2 // bit 5
15921 #define IRCF3 OSCCONbits.IRCF3 // bit 6
15922 #define SPLLEN OSCCONbits.SPLLEN // bit 7
15924 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
15925 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
15926 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
15927 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
15928 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
15929 #define OSTS OSCSTATbits.OSTS // bit 5
15930 #define PLLR OSCSTATbits.PLLR // bit 6
15931 #define SOSCR OSCSTATbits.SOSCR // bit 7
15933 #define TUN0 OSCTUNEbits.TUN0 // bit 0
15934 #define TUN1 OSCTUNEbits.TUN1 // bit 1
15935 #define TUN2 OSCTUNEbits.TUN2 // bit 2
15936 #define TUN3 OSCTUNEbits.TUN3 // bit 3
15937 #define TUN4 OSCTUNEbits.TUN4 // bit 4
15938 #define TUN5 OSCTUNEbits.TUN5 // bit 5
15940 #define NOT_BOR PCONbits.NOT_BOR // bit 0
15941 #define NOT_POR PCONbits.NOT_POR // bit 1
15942 #define NOT_RI PCONbits.NOT_RI // bit 2
15943 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
15944 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
15945 #define STKUNF PCONbits.STKUNF // bit 6
15946 #define STKOVF PCONbits.STKOVF // bit 7
15948 #define TMR1IE PIE1bits.TMR1IE // bit 0
15949 #define TMR2IE PIE1bits.TMR2IE // bit 1
15950 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
15951 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
15952 #define SSP1IE PIE1bits.SSP1IE // bit 3
15953 #define TXIE PIE1bits.TXIE // bit 4
15954 #define RCIE PIE1bits.RCIE // bit 5
15955 #define ADIE PIE1bits.ADIE // bit 6
15956 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
15958 #define CCP2IE PIE2bits.CCP2IE // bit 0
15959 #define C3IE PIE2bits.C3IE // bit 1
15960 #define C4IE PIE2bits.C4IE // bit 2
15961 #define BCL1IE PIE2bits.BCL1IE // bit 3
15962 #define C1IE PIE2bits.C1IE // bit 5
15963 #define C2IE PIE2bits.C2IE // bit 6
15964 #define OSFIE PIE2bits.OSFIE // bit 7
15966 #define CLC1IE PIE3bits.CLC1IE // bit 0
15967 #define CLC2IE PIE3bits.CLC2IE // bit 1
15968 #define CLC3IE PIE3bits.CLC3IE // bit 2
15969 #define COG2IE PIE3bits.COG2IE // bit 3
15970 #define ZCDIE PIE3bits.ZCDIE // bit 4
15971 #define COGIE PIE3bits.COGIE // bit 5
15972 #define PWM5IE PIE3bits.PWM5IE // bit 6
15973 #define PWM6IE PIE3bits.PWM6IE // bit 7
15975 #define TMR4IE PIE4bits.TMR4IE // bit 0
15976 #define TMR6IE PIE4bits.TMR6IE // bit 1
15977 #define TMR3IE PIE4bits.TMR3IE // bit 2
15978 #define TMR3GIE PIE4bits.TMR3GIE // bit 3
15979 #define TMR5IE PIE4bits.TMR5IE // bit 4
15980 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
15982 #define TMR1IF PIR1bits.TMR1IF // bit 0
15983 #define TMR2IF PIR1bits.TMR2IF // bit 1
15984 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
15985 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
15986 #define SSP1IF PIR1bits.SSP1IF // bit 3
15987 #define TXIF PIR1bits.TXIF // bit 4
15988 #define RCIF PIR1bits.RCIF // bit 5
15989 #define ADIF PIR1bits.ADIF // bit 6
15990 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
15992 #define CCP2IF PIR2bits.CCP2IF // bit 0
15993 #define C3IF PIR2bits.C3IF // bit 1
15994 #define C4IF PIR2bits.C4IF // bit 2
15995 #define BCL1IF PIR2bits.BCL1IF // bit 3
15996 #define C1IF PIR2bits.C1IF // bit 5
15997 #define C2IF PIR2bits.C2IF // bit 6
15998 #define OSFIF PIR2bits.OSFIF // bit 7
16000 #define CLC1IF PIR3bits.CLC1IF // bit 0
16001 #define CLC2IF PIR3bits.CLC2IF // bit 1
16002 #define CLC3IF PIR3bits.CLC3IF // bit 2
16003 #define COG2IF PIR3bits.COG2IF // bit 3
16004 #define ZCDIF PIR3bits.ZCDIF // bit 4
16005 #define COG1IF PIR3bits.COG1IF // bit 5
16006 #define PWM5IF PIR3bits.PWM5IF // bit 6
16007 #define PWM6IF PIR3bits.PWM6IF // bit 7
16009 #define TMR4IF PIR4bits.TMR4IF // bit 0
16010 #define TMR6IF PIR4bits.TMR6IF // bit 1
16011 #define TMR3IF PIR4bits.TMR3IF // bit 2
16012 #define TMR3GIF PIR4bits.TMR3GIF // bit 3
16013 #define TMR5IF PIR4bits.TMR5IF // bit 4
16014 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
16016 #define RD PMCON1bits.RD // bit 0
16017 #define WR PMCON1bits.WR // bit 1
16018 #define WREN PMCON1bits.WREN // bit 2
16019 #define WRERR PMCON1bits.WRERR // bit 3
16020 #define FREE PMCON1bits.FREE // bit 4
16021 #define LWLO PMCON1bits.LWLO // bit 5
16022 #define CFGS PMCON1bits.CFGS // bit 6
16024 #define RA0 PORTAbits.RA0 // bit 0
16025 #define RA1 PORTAbits.RA1 // bit 1
16026 #define RA2 PORTAbits.RA2 // bit 2
16027 #define RA3 PORTAbits.RA3 // bit 3
16028 #define RA4 PORTAbits.RA4 // bit 4
16029 #define RA5 PORTAbits.RA5 // bit 5
16031 #define RB4 PORTBbits.RB4 // bit 4
16032 #define RB5 PORTBbits.RB5 // bit 5
16033 #define RB6 PORTBbits.RB6 // bit 6
16034 #define RB7 PORTBbits.RB7 // bit 7
16036 #define RC0 PORTCbits.RC0 // bit 0
16037 #define RC1 PORTCbits.RC1 // bit 1
16038 #define RC2 PORTCbits.RC2 // bit 2
16039 #define RC3 PORTCbits.RC3 // bit 3
16040 #define RC4 PORTCbits.RC4 // bit 4
16041 #define RC5 PORTCbits.RC5 // bit 5
16042 #define RC6 PORTCbits.RC6 // bit 6
16043 #define RC7 PORTCbits.RC7 // bit 7
16045 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
16047 #define RPOL PRG1CON1bits.RPOL // bit 0, shadows bit in PRG1CON1bits
16048 #define RG1RPOL PRG1CON1bits.RG1RPOL // bit 0, shadows bit in PRG1CON1bits
16049 #define FPOL PRG1CON1bits.FPOL // bit 1, shadows bit in PRG1CON1bits
16050 #define RG1FPOL PRG1CON1bits.RG1FPOL // bit 1, shadows bit in PRG1CON1bits
16051 #define RDY PRG1CON1bits.RDY // bit 2, shadows bit in PRG1CON1bits
16052 #define RG1RDY PRG1CON1bits.RG1RDY // bit 2, shadows bit in PRG1CON1bits
16054 #define ISET0 PRG1CON2bits.ISET0 // bit 0, shadows bit in PRG1CON2bits
16055 #define RG1ISET0 PRG1CON2bits.RG1ISET0 // bit 0, shadows bit in PRG1CON2bits
16056 #define ISET1 PRG1CON2bits.ISET1 // bit 1, shadows bit in PRG1CON2bits
16057 #define RG1ISET1 PRG1CON2bits.RG1ISET1 // bit 1, shadows bit in PRG1CON2bits
16058 #define ISET2 PRG1CON2bits.ISET2 // bit 2, shadows bit in PRG1CON2bits
16059 #define RG1ISET2 PRG1CON2bits.RG1ISET2 // bit 2, shadows bit in PRG1CON2bits
16060 #define ISET3 PRG1CON2bits.ISET3 // bit 3, shadows bit in PRG1CON2bits
16061 #define RG1ISET3 PRG1CON2bits.RG1ISET3 // bit 3, shadows bit in PRG1CON2bits
16062 #define ISET4 PRG1CON2bits.ISET4 // bit 4, shadows bit in PRG1CON2bits
16063 #define RG1ISET4 PRG1CON2bits.RG1ISET4 // bit 4, shadows bit in PRG1CON2bits
16065 #define FTSS0 PRG1FTSSbits.FTSS0 // bit 0, shadows bit in PRG1FTSSbits
16066 #define RG1FTSS0 PRG1FTSSbits.RG1FTSS0 // bit 0, shadows bit in PRG1FTSSbits
16067 #define FTSS1 PRG1FTSSbits.FTSS1 // bit 1, shadows bit in PRG1FTSSbits
16068 #define RG1FTSS1 PRG1FTSSbits.RG1FTSS1 // bit 1, shadows bit in PRG1FTSSbits
16069 #define FTSS2 PRG1FTSSbits.FTSS2 // bit 2, shadows bit in PRG1FTSSbits
16070 #define RG1FTSS2 PRG1FTSSbits.RG1FTSS2 // bit 2, shadows bit in PRG1FTSSbits
16071 #define FTSS3 PRG1FTSSbits.FTSS3 // bit 3, shadows bit in PRG1FTSSbits
16072 #define RG1FTSS3 PRG1FTSSbits.RG1FTSS3 // bit 3, shadows bit in PRG1FTSSbits
16074 #define INS0 PRG1INSbits.INS0 // bit 0, shadows bit in PRG1INSbits
16075 #define RG1INS0 PRG1INSbits.RG1INS0 // bit 0, shadows bit in PRG1INSbits
16076 #define INS1 PRG1INSbits.INS1 // bit 1, shadows bit in PRG1INSbits
16077 #define RG1INS1 PRG1INSbits.RG1INS1 // bit 1, shadows bit in PRG1INSbits
16078 #define INS2 PRG1INSbits.INS2 // bit 2, shadows bit in PRG1INSbits
16079 #define RG1INS2 PRG1INSbits.RG1INS2 // bit 2, shadows bit in PRG1INSbits
16080 #define INS3 PRG1INSbits.INS3 // bit 3, shadows bit in PRG1INSbits
16081 #define RG1INS3 PRG1INSbits.RG1INS3 // bit 3, shadows bit in PRG1INSbits
16083 #define RTSS0 PRG1RTSSbits.RTSS0 // bit 0, shadows bit in PRG1RTSSbits
16084 #define RG1RTSS0 PRG1RTSSbits.RG1RTSS0 // bit 0, shadows bit in PRG1RTSSbits
16085 #define RTSS1 PRG1RTSSbits.RTSS1 // bit 1, shadows bit in PRG1RTSSbits
16086 #define RG1RTSS1 PRG1RTSSbits.RG1RTSS1 // bit 1, shadows bit in PRG1RTSSbits
16087 #define RTSS2 PRG1RTSSbits.RTSS2 // bit 2, shadows bit in PRG1RTSSbits
16088 #define RG1RTSS2 PRG1RTSSbits.RG1RTSS2 // bit 2, shadows bit in PRG1RTSSbits
16089 #define RTSS3 PRG1RTSSbits.RTSS3 // bit 3, shadows bit in PRG1RTSSbits
16090 #define RG1RTSS3 PRG1RTSSbits.RG1RTSS3 // bit 3, shadows bit in PRG1RTSSbits
16092 #define DC2 PWM3DCHbits.DC2 // bit 0, shadows bit in PWM3DCHbits
16093 #define PWM3DC2 PWM3DCHbits.PWM3DC2 // bit 0, shadows bit in PWM3DCHbits
16094 #define PWMPW2 PWM3DCHbits.PWMPW2 // bit 0, shadows bit in PWM3DCHbits
16095 #define DC3 PWM3DCHbits.DC3 // bit 1, shadows bit in PWM3DCHbits
16096 #define PWM3DC3 PWM3DCHbits.PWM3DC3 // bit 1, shadows bit in PWM3DCHbits
16097 #define PWMPW3 PWM3DCHbits.PWMPW3 // bit 1, shadows bit in PWM3DCHbits
16098 #define DC4 PWM3DCHbits.DC4 // bit 2, shadows bit in PWM3DCHbits
16099 #define PWM3DC4 PWM3DCHbits.PWM3DC4 // bit 2, shadows bit in PWM3DCHbits
16100 #define PWMPW4 PWM3DCHbits.PWMPW4 // bit 2, shadows bit in PWM3DCHbits
16101 #define DC5 PWM3DCHbits.DC5 // bit 3, shadows bit in PWM3DCHbits
16102 #define PWM3DC5 PWM3DCHbits.PWM3DC5 // bit 3, shadows bit in PWM3DCHbits
16103 #define PWMPW5 PWM3DCHbits.PWMPW5 // bit 3, shadows bit in PWM3DCHbits
16104 #define DC6 PWM3DCHbits.DC6 // bit 4, shadows bit in PWM3DCHbits
16105 #define PWM3DC6 PWM3DCHbits.PWM3DC6 // bit 4, shadows bit in PWM3DCHbits
16106 #define PWMPW6 PWM3DCHbits.PWMPW6 // bit 4, shadows bit in PWM3DCHbits
16107 #define DC7 PWM3DCHbits.DC7 // bit 5, shadows bit in PWM3DCHbits
16108 #define PWM3DC7 PWM3DCHbits.PWM3DC7 // bit 5, shadows bit in PWM3DCHbits
16109 #define PWMPW7 PWM3DCHbits.PWMPW7 // bit 5, shadows bit in PWM3DCHbits
16110 #define DC8 PWM3DCHbits.DC8 // bit 6, shadows bit in PWM3DCHbits
16111 #define PWM3DC8 PWM3DCHbits.PWM3DC8 // bit 6, shadows bit in PWM3DCHbits
16112 #define PWMPW8 PWM3DCHbits.PWMPW8 // bit 6, shadows bit in PWM3DCHbits
16113 #define DC9 PWM3DCHbits.DC9 // bit 7, shadows bit in PWM3DCHbits
16114 #define PWM3DC9 PWM3DCHbits.PWM3DC9 // bit 7, shadows bit in PWM3DCHbits
16115 #define PWMPW9 PWM3DCHbits.PWMPW9 // bit 7, shadows bit in PWM3DCHbits
16117 #define DC0 PWM3DCLbits.DC0 // bit 6, shadows bit in PWM3DCLbits
16118 #define PWM3DC0 PWM3DCLbits.PWM3DC0 // bit 6, shadows bit in PWM3DCLbits
16119 #define PWMPW0 PWM3DCLbits.PWMPW0 // bit 6, shadows bit in PWM3DCLbits
16120 #define DC1 PWM3DCLbits.DC1 // bit 7, shadows bit in PWM3DCLbits
16121 #define PWM3DC1 PWM3DCLbits.PWM3DC1 // bit 7, shadows bit in PWM3DCLbits
16122 #define PWMPW1 PWM3DCLbits.PWMPW1 // bit 7, shadows bit in PWM3DCLbits
16124 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
16125 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
16126 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
16127 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
16128 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
16129 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
16130 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
16131 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
16133 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 0
16134 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 1
16135 #define PWM5DCL2 PWM5DCLbits.PWM5DCL2 // bit 2
16136 #define PWM5DCL3 PWM5DCLbits.PWM5DCL3 // bit 3
16137 #define PWM5DCL4 PWM5DCLbits.PWM5DCL4 // bit 4
16138 #define PWM5DCL5 PWM5DCLbits.PWM5DCL5 // bit 5
16139 #define PWM5DCL6 PWM5DCLbits.PWM5DCL6 // bit 6
16140 #define PWM5DCL7 PWM5DCLbits.PWM5DCL7 // bit 7
16142 #define PRIE PWM5INTCONbits.PRIE // bit 0, shadows bit in PWM5INTCONbits
16143 #define PWM5PRIE PWM5INTCONbits.PWM5PRIE // bit 0, shadows bit in PWM5INTCONbits
16144 #define DCIE PWM5INTCONbits.DCIE // bit 1, shadows bit in PWM5INTCONbits
16145 #define PWM5DCIE PWM5INTCONbits.PWM5DCIE // bit 1, shadows bit in PWM5INTCONbits
16146 #define PHIE PWM5INTCONbits.PHIE // bit 2, shadows bit in PWM5INTCONbits
16147 #define PWM5PHIE PWM5INTCONbits.PWM5PHIE // bit 2, shadows bit in PWM5INTCONbits
16148 #define OFIE PWM5INTCONbits.OFIE // bit 3, shadows bit in PWM5INTCONbits
16149 #define PWM5OFIE PWM5INTCONbits.PWM5OFIE // bit 3, shadows bit in PWM5INTCONbits
16151 #define PRIF PWM5INTFbits.PRIF // bit 0, shadows bit in PWM5INTFbits
16152 #define PWM5PRIF PWM5INTFbits.PWM5PRIF // bit 0, shadows bit in PWM5INTFbits
16153 #define DCIF PWM5INTFbits.DCIF // bit 1, shadows bit in PWM5INTFbits
16154 #define PWM5DCIF PWM5INTFbits.PWM5DCIF // bit 1, shadows bit in PWM5INTFbits
16155 #define PHIF PWM5INTFbits.PHIF // bit 2, shadows bit in PWM5INTFbits
16156 #define PWM5PHIF PWM5INTFbits.PWM5PHIF // bit 2, shadows bit in PWM5INTFbits
16157 #define OFIF PWM5INTFbits.OFIF // bit 3, shadows bit in PWM5INTFbits
16158 #define PWM5OFIF PWM5INTFbits.PWM5OFIF // bit 3, shadows bit in PWM5INTFbits
16160 #define PWM5LDS0 PWM5LDCONbits.PWM5LDS0 // bit 0, shadows bit in PWM5LDCONbits
16161 #define LDS0 PWM5LDCONbits.LDS0 // bit 0, shadows bit in PWM5LDCONbits
16162 #define LDT PWM5LDCONbits.LDT // bit 6, shadows bit in PWM5LDCONbits
16163 #define PWM5LDM PWM5LDCONbits.PWM5LDM // bit 6, shadows bit in PWM5LDCONbits
16164 #define LDA PWM5LDCONbits.LDA // bit 7, shadows bit in PWM5LDCONbits
16165 #define PWM5LD PWM5LDCONbits.PWM5LD // bit 7, shadows bit in PWM5LDCONbits
16167 #define PWM5OFS0 PWM5OFCONbits.PWM5OFS0 // bit 0, shadows bit in PWM5OFCONbits
16168 #define OFS0 PWM5OFCONbits.OFS0 // bit 0, shadows bit in PWM5OFCONbits
16169 #define OFO PWM5OFCONbits.OFO // bit 4, shadows bit in PWM5OFCONbits
16170 #define PWM5OFMC PWM5OFCONbits.PWM5OFMC // bit 4, shadows bit in PWM5OFCONbits
16171 #define PWM5OFM0 PWM5OFCONbits.PWM5OFM0 // bit 5, shadows bit in PWM5OFCONbits
16172 #define OFM0 PWM5OFCONbits.OFM0 // bit 5, shadows bit in PWM5OFCONbits
16173 #define PWM5OFM1 PWM5OFCONbits.PWM5OFM1 // bit 6, shadows bit in PWM5OFCONbits
16174 #define OFM1 PWM5OFCONbits.OFM1 // bit 6, shadows bit in PWM5OFCONbits
16176 #define PWM5OFH0 PWM5OFHbits.PWM5OFH0 // bit 0
16177 #define PWM5OFH1 PWM5OFHbits.PWM5OFH1 // bit 1
16178 #define PWM5OFH2 PWM5OFHbits.PWM5OFH2 // bit 2
16179 #define PWM5OFH3 PWM5OFHbits.PWM5OFH3 // bit 3
16180 #define PWM5OFH4 PWM5OFHbits.PWM5OFH4 // bit 4
16181 #define PWM5OFH5 PWM5OFHbits.PWM5OFH5 // bit 5
16182 #define PWM5OFH6 PWM5OFHbits.PWM5OFH6 // bit 6
16183 #define PWM5OFH7 PWM5OFHbits.PWM5OFH7 // bit 7
16185 #define PWM5OFL0 PWM5OFLbits.PWM5OFL0 // bit 0
16186 #define PWM5OFL1 PWM5OFLbits.PWM5OFL1 // bit 1
16187 #define PWM5OFL2 PWM5OFLbits.PWM5OFL2 // bit 2
16188 #define PWM5OFL3 PWM5OFLbits.PWM5OFL3 // bit 3
16189 #define PWM5OFL4 PWM5OFLbits.PWM5OFL4 // bit 4
16190 #define PWM5OFL5 PWM5OFLbits.PWM5OFL5 // bit 5
16191 #define PWM5OFL6 PWM5OFLbits.PWM5OFL6 // bit 6
16192 #define PWM5OFL7 PWM5OFLbits.PWM5OFL7 // bit 7
16194 #define PWM5PHH0 PWM5PHHbits.PWM5PHH0 // bit 0
16195 #define PWM5PHH1 PWM5PHHbits.PWM5PHH1 // bit 1
16196 #define PWM5PHH2 PWM5PHHbits.PWM5PHH2 // bit 2
16197 #define PWM5PHH3 PWM5PHHbits.PWM5PHH3 // bit 3
16198 #define PWM5PHH4 PWM5PHHbits.PWM5PHH4 // bit 4
16199 #define PWM5PHH5 PWM5PHHbits.PWM5PHH5 // bit 5
16200 #define PWM5PHH6 PWM5PHHbits.PWM5PHH6 // bit 6
16201 #define PWM5PHH7 PWM5PHHbits.PWM5PHH7 // bit 7
16203 #define PWM5PHL0 PWM5PHLbits.PWM5PHL0 // bit 0
16204 #define PWM5PHL1 PWM5PHLbits.PWM5PHL1 // bit 1
16205 #define PWM5PHL2 PWM5PHLbits.PWM5PHL2 // bit 2
16206 #define PWM5PHL3 PWM5PHLbits.PWM5PHL3 // bit 3
16207 #define PWM5PHL4 PWM5PHLbits.PWM5PHL4 // bit 4
16208 #define PWM5PHL5 PWM5PHLbits.PWM5PHL5 // bit 5
16209 #define PWM5PHL6 PWM5PHLbits.PWM5PHL6 // bit 6
16210 #define PWM5PHL7 PWM5PHLbits.PWM5PHL7 // bit 7
16212 #define PWM5PRH0 PWM5PRHbits.PWM5PRH0 // bit 0
16213 #define PWM5PRH1 PWM5PRHbits.PWM5PRH1 // bit 1
16214 #define PWM5PRH2 PWM5PRHbits.PWM5PRH2 // bit 2
16215 #define PWM5PRH3 PWM5PRHbits.PWM5PRH3 // bit 3
16216 #define PWM5PRH4 PWM5PRHbits.PWM5PRH4 // bit 4
16217 #define PWM5PRH5 PWM5PRHbits.PWM5PRH5 // bit 5
16218 #define PWM5PRH6 PWM5PRHbits.PWM5PRH6 // bit 6
16219 #define PWM5PRH7 PWM5PRHbits.PWM5PRH7 // bit 7
16221 #define PWM5PRL0 PWM5PRLbits.PWM5PRL0 // bit 0
16222 #define PWM5PRL1 PWM5PRLbits.PWM5PRL1 // bit 1
16223 #define PWM5PRL2 PWM5PRLbits.PWM5PRL2 // bit 2
16224 #define PWM5PRL3 PWM5PRLbits.PWM5PRL3 // bit 3
16225 #define PWM5PRL4 PWM5PRLbits.PWM5PRL4 // bit 4
16226 #define PWM5PRL5 PWM5PRLbits.PWM5PRL5 // bit 5
16227 #define PWM5PRL6 PWM5PRLbits.PWM5PRL6 // bit 6
16228 #define PWM5PRL7 PWM5PRLbits.PWM5PRL7 // bit 7
16230 #define PWM5TMRH0 PWM5TMRHbits.PWM5TMRH0 // bit 0
16231 #define PWM5TMRH1 PWM5TMRHbits.PWM5TMRH1 // bit 1
16232 #define PWM5TMRH2 PWM5TMRHbits.PWM5TMRH2 // bit 2
16233 #define PWM5TMRH3 PWM5TMRHbits.PWM5TMRH3 // bit 3
16234 #define PWM5TMRH4 PWM5TMRHbits.PWM5TMRH4 // bit 4
16235 #define PWM5TMRH5 PWM5TMRHbits.PWM5TMRH5 // bit 5
16236 #define PWM5TMRH6 PWM5TMRHbits.PWM5TMRH6 // bit 6
16237 #define PWM5TMRH7 PWM5TMRHbits.PWM5TMRH7 // bit 7
16239 #define PWM5TMRL0 PWM5TMRLbits.PWM5TMRL0 // bit 0
16240 #define PWM5TMRL1 PWM5TMRLbits.PWM5TMRL1 // bit 1
16241 #define PWM5TMRL2 PWM5TMRLbits.PWM5TMRL2 // bit 2
16242 #define PWM5TMRL3 PWM5TMRLbits.PWM5TMRL3 // bit 3
16243 #define PWM5TMRL4 PWM5TMRLbits.PWM5TMRL4 // bit 4
16244 #define PWM5TMRL5 PWM5TMRLbits.PWM5TMRL5 // bit 5
16245 #define PWM5TMRL6 PWM5TMRLbits.PWM5TMRL6 // bit 6
16246 #define PWM5TMRL7 PWM5TMRLbits.PWM5TMRL7 // bit 7
16248 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
16249 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
16250 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
16251 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
16252 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
16253 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
16254 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
16255 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
16257 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 0
16258 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 1
16259 #define PWM6DCL2 PWM6DCLbits.PWM6DCL2 // bit 2
16260 #define PWM6DCL3 PWM6DCLbits.PWM6DCL3 // bit 3
16261 #define PWM6DCL4 PWM6DCLbits.PWM6DCL4 // bit 4
16262 #define PWM6DCL5 PWM6DCLbits.PWM6DCL5 // bit 5
16263 #define PWM6DCL6 PWM6DCLbits.PWM6DCL6 // bit 6
16264 #define PWM6DCL7 PWM6DCLbits.PWM6DCL7 // bit 7
16266 #define PWM6OFH0 PWM6OFHbits.PWM6OFH0 // bit 0
16267 #define PWM6OFH1 PWM6OFHbits.PWM6OFH1 // bit 1
16268 #define PWM6OFH2 PWM6OFHbits.PWM6OFH2 // bit 2
16269 #define PWM6OFH3 PWM6OFHbits.PWM6OFH3 // bit 3
16270 #define PWM6OFH4 PWM6OFHbits.PWM6OFH4 // bit 4
16271 #define PWM6OFH5 PWM6OFHbits.PWM6OFH5 // bit 5
16272 #define PWM6OFH6 PWM6OFHbits.PWM6OFH6 // bit 6
16273 #define PWM6OFH7 PWM6OFHbits.PWM6OFH7 // bit 7
16275 #define PWM6OFL0 PWM6OFLbits.PWM6OFL0 // bit 0
16276 #define PWM6OFL1 PWM6OFLbits.PWM6OFL1 // bit 1
16277 #define PWM6OFL2 PWM6OFLbits.PWM6OFL2 // bit 2
16278 #define PWM6OFL3 PWM6OFLbits.PWM6OFL3 // bit 3
16279 #define PWM6OFL4 PWM6OFLbits.PWM6OFL4 // bit 4
16280 #define PWM6OFL5 PWM6OFLbits.PWM6OFL5 // bit 5
16281 #define PWM6OFL6 PWM6OFLbits.PWM6OFL6 // bit 6
16282 #define PWM6OFL7 PWM6OFLbits.PWM6OFL7 // bit 7
16284 #define PWM6PHH0 PWM6PHHbits.PWM6PHH0 // bit 0
16285 #define PWM6PHH1 PWM6PHHbits.PWM6PHH1 // bit 1
16286 #define PWM6PHH2 PWM6PHHbits.PWM6PHH2 // bit 2
16287 #define PWM6PHH3 PWM6PHHbits.PWM6PHH3 // bit 3
16288 #define PWM6PHH4 PWM6PHHbits.PWM6PHH4 // bit 4
16289 #define PWM6PHH5 PWM6PHHbits.PWM6PHH5 // bit 5
16290 #define PWM6PHH6 PWM6PHHbits.PWM6PHH6 // bit 6
16291 #define PWM6PHH7 PWM6PHHbits.PWM6PHH7 // bit 7
16293 #define PWM6PHL0 PWM6PHLbits.PWM6PHL0 // bit 0
16294 #define PWM6PHL1 PWM6PHLbits.PWM6PHL1 // bit 1
16295 #define PWM6PHL2 PWM6PHLbits.PWM6PHL2 // bit 2
16296 #define PWM6PHL3 PWM6PHLbits.PWM6PHL3 // bit 3
16297 #define PWM6PHL4 PWM6PHLbits.PWM6PHL4 // bit 4
16298 #define PWM6PHL5 PWM6PHLbits.PWM6PHL5 // bit 5
16299 #define PWM6PHL6 PWM6PHLbits.PWM6PHL6 // bit 6
16300 #define PWM6PHL7 PWM6PHLbits.PWM6PHL7 // bit 7
16302 #define PWM6PRH0 PWM6PRHbits.PWM6PRH0 // bit 0
16303 #define PWM6PRH1 PWM6PRHbits.PWM6PRH1 // bit 1
16304 #define PWM6PRH2 PWM6PRHbits.PWM6PRH2 // bit 2
16305 #define PWM6PRH3 PWM6PRHbits.PWM6PRH3 // bit 3
16306 #define PWM6PRH4 PWM6PRHbits.PWM6PRH4 // bit 4
16307 #define PWM6PRH5 PWM6PRHbits.PWM6PRH5 // bit 5
16308 #define PWM6PRH6 PWM6PRHbits.PWM6PRH6 // bit 6
16309 #define PWM6PRH7 PWM6PRHbits.PWM6PRH7 // bit 7
16311 #define PWM6PRL0 PWM6PRLbits.PWM6PRL0 // bit 0
16312 #define PWM6PRL1 PWM6PRLbits.PWM6PRL1 // bit 1
16313 #define PWM6PRL2 PWM6PRLbits.PWM6PRL2 // bit 2
16314 #define PWM6PRL3 PWM6PRLbits.PWM6PRL3 // bit 3
16315 #define PWM6PRL4 PWM6PRLbits.PWM6PRL4 // bit 4
16316 #define PWM6PRL5 PWM6PRLbits.PWM6PRL5 // bit 5
16317 #define PWM6PRL6 PWM6PRLbits.PWM6PRL6 // bit 6
16318 #define PWM6PRL7 PWM6PRLbits.PWM6PRL7 // bit 7
16320 #define PWM6TMRH0 PWM6TMRHbits.PWM6TMRH0 // bit 0
16321 #define PWM6TMRH1 PWM6TMRHbits.PWM6TMRH1 // bit 1
16322 #define PWM6TMRH2 PWM6TMRHbits.PWM6TMRH2 // bit 2
16323 #define PWM6TMRH3 PWM6TMRHbits.PWM6TMRH3 // bit 3
16324 #define PWM6TMRH4 PWM6TMRHbits.PWM6TMRH4 // bit 4
16325 #define PWM6TMRH5 PWM6TMRHbits.PWM6TMRH5 // bit 5
16326 #define PWM6TMRH6 PWM6TMRHbits.PWM6TMRH6 // bit 6
16327 #define PWM6TMRH7 PWM6TMRHbits.PWM6TMRH7 // bit 7
16329 #define PWM6TMRL0 PWM6TMRLbits.PWM6TMRL0 // bit 0
16330 #define PWM6TMRL1 PWM6TMRLbits.PWM6TMRL1 // bit 1
16331 #define PWM6TMRL2 PWM6TMRLbits.PWM6TMRL2 // bit 2
16332 #define PWM6TMRL3 PWM6TMRLbits.PWM6TMRL3 // bit 3
16333 #define PWM6TMRL4 PWM6TMRLbits.PWM6TMRL4 // bit 4
16334 #define PWM6TMRL5 PWM6TMRLbits.PWM6TMRL5 // bit 5
16335 #define PWM6TMRL6 PWM6TMRLbits.PWM6TMRL6 // bit 6
16336 #define PWM6TMRL7 PWM6TMRLbits.PWM6TMRL7 // bit 7
16338 #define MPWM5EN PWMENbits.MPWM5EN // bit 4
16339 #define MPWM6EN PWMENbits.MPWM6EN // bit 5
16341 #define MPWM5LD PWMLDbits.MPWM5LD // bit 4
16342 #define MPWM6LD PWMLDbits.MPWM6LD // bit 5
16344 #define MPWM5OUT PWMOUTbits.MPWM5OUT // bit 4
16345 #define MPWM6OUT PWMOUTbits.MPWM6OUT // bit 5
16347 #define RX9D RC1STAbits.RX9D // bit 0
16348 #define OERR RC1STAbits.OERR // bit 1
16349 #define FERR RC1STAbits.FERR // bit 2
16350 #define ADDEN RC1STAbits.ADDEN // bit 3
16351 #define CREN RC1STAbits.CREN // bit 4
16352 #define SREN RC1STAbits.SREN // bit 5
16353 #define RX9 RC1STAbits.RX9 // bit 6
16354 #define SPEN RC1STAbits.SPEN // bit 7
16356 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
16357 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
16358 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
16359 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
16360 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
16362 #define SLRB4 SLRCONBbits.SLRB4 // bit 4
16363 #define SLRB5 SLRCONBbits.SLRB5 // bit 5
16364 #define SLRB6 SLRCONBbits.SLRB6 // bit 6
16365 #define SLRB7 SLRCONBbits.SLRB7 // bit 7
16367 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
16368 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
16369 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
16370 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
16371 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
16372 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
16373 #define SLRC6 SLRCONCbits.SLRC6 // bit 6
16374 #define SLRC7 SLRCONCbits.SLRC7 // bit 7
16376 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
16377 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
16378 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
16379 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
16380 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
16381 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
16382 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
16383 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
16384 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
16385 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
16386 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
16387 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
16388 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
16389 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
16390 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
16391 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
16393 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
16394 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
16395 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
16396 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
16397 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
16398 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
16399 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
16400 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
16401 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
16402 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
16403 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
16404 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
16405 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
16406 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
16407 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
16408 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
16410 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
16411 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
16412 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
16413 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
16414 #define CKP SSP1CONbits.CKP // bit 4
16415 #define SSPEN SSP1CONbits.SSPEN // bit 5
16416 #define SSPOV SSP1CONbits.SSPOV // bit 6
16417 #define WCOL SSP1CONbits.WCOL // bit 7
16419 #define SEN SSP1CON2bits.SEN // bit 0
16420 #define RSEN SSP1CON2bits.RSEN // bit 1
16421 #define PEN SSP1CON2bits.PEN // bit 2
16422 #define RCEN SSP1CON2bits.RCEN // bit 3
16423 #define ACKEN SSP1CON2bits.ACKEN // bit 4
16424 #define ACKDT SSP1CON2bits.ACKDT // bit 5
16425 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
16426 #define GCEN SSP1CON2bits.GCEN // bit 7
16428 #define DHEN SSP1CON3bits.DHEN // bit 0
16429 #define AHEN SSP1CON3bits.AHEN // bit 1
16430 #define SBCDE SSP1CON3bits.SBCDE // bit 2
16431 #define SDAHT SSP1CON3bits.SDAHT // bit 3
16432 #define BOEN SSP1CON3bits.BOEN // bit 4
16433 #define SCIE SSP1CON3bits.SCIE // bit 5
16434 #define PCIE SSP1CON3bits.PCIE // bit 6
16435 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
16437 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
16438 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
16439 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
16440 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
16441 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
16442 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
16443 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
16444 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
16445 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
16446 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
16447 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
16448 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
16449 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
16450 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
16451 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
16452 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
16454 #define BF SSP1STATbits.BF // bit 0
16455 #define UA SSP1STATbits.UA // bit 1
16456 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
16457 #define S SSP1STATbits.S // bit 3
16458 #define P SSP1STATbits.P // bit 4
16459 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
16460 #define CKE SSP1STATbits.CKE // bit 6
16461 #define SMP SSP1STATbits.SMP // bit 7
16463 #define C STATUSbits.C // bit 0
16464 #define DC STATUSbits.DC // bit 1
16465 #define Z STATUSbits.Z // bit 2
16466 #define NOT_PD STATUSbits.NOT_PD // bit 3
16467 #define NOT_TO STATUSbits.NOT_TO // bit 4
16469 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
16470 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
16471 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
16473 #define GSS0 T1GCONbits.GSS0 // bit 0, shadows bit in T1GCONbits
16474 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0, shadows bit in T1GCONbits
16475 #define GSS1 T1GCONbits.GSS1 // bit 1, shadows bit in T1GCONbits
16476 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1, shadows bit in T1GCONbits
16477 #define GVAL T1GCONbits.GVAL // bit 2, shadows bit in T1GCONbits
16478 #define T1GVAL T1GCONbits.T1GVAL // bit 2, shadows bit in T1GCONbits
16479 #define GGO_NOT_DONE T1GCONbits.GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
16480 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
16481 #define GSPM T1GCONbits.GSPM // bit 4, shadows bit in T1GCONbits
16482 #define T1GSPM T1GCONbits.T1GSPM // bit 4, shadows bit in T1GCONbits
16483 #define GTM T1GCONbits.GTM // bit 5, shadows bit in T1GCONbits
16484 #define T1GTM T1GCONbits.T1GTM // bit 5, shadows bit in T1GCONbits
16485 #define GPOL T1GCONbits.GPOL // bit 6, shadows bit in T1GCONbits
16486 #define T1GPOL T1GCONbits.T1GPOL // bit 6, shadows bit in T1GCONbits
16487 #define GE T1GCONbits.GE // bit 7, shadows bit in T1GCONbits
16488 #define T1GE T1GCONbits.T1GE // bit 7, shadows bit in T1GCONbits
16489 #define TMR1GE T1GCONbits.TMR1GE // bit 7, shadows bit in T1GCONbits
16491 #define RSEL0 T2RSTbits.RSEL0 // bit 0, shadows bit in T2RSTbits
16492 #define T2RSEL0 T2RSTbits.T2RSEL0 // bit 0, shadows bit in T2RSTbits
16493 #define RSEL1 T2RSTbits.RSEL1 // bit 1, shadows bit in T2RSTbits
16494 #define T2RSEL1 T2RSTbits.T2RSEL1 // bit 1, shadows bit in T2RSTbits
16495 #define RSEL2 T2RSTbits.RSEL2 // bit 2, shadows bit in T2RSTbits
16496 #define T2RSEL2 T2RSTbits.T2RSEL2 // bit 2, shadows bit in T2RSTbits
16497 #define RSEL3 T2RSTbits.RSEL3 // bit 3, shadows bit in T2RSTbits
16498 #define T2RSEL3 T2RSTbits.T2RSEL3 // bit 3, shadows bit in T2RSTbits
16500 #define TRISA0 TRISAbits.TRISA0 // bit 0
16501 #define TRISA1 TRISAbits.TRISA1 // bit 1
16502 #define TRISA2 TRISAbits.TRISA2 // bit 2
16503 #define TRISA4 TRISAbits.TRISA4 // bit 4
16504 #define TRISA5 TRISAbits.TRISA5 // bit 5
16506 #define TRISB4 TRISBbits.TRISB4 // bit 4
16507 #define TRISB5 TRISBbits.TRISB5 // bit 5
16508 #define TRISB6 TRISBbits.TRISB6 // bit 6
16509 #define TRISB7 TRISBbits.TRISB7 // bit 7
16511 #define TRISC0 TRISCbits.TRISC0 // bit 0
16512 #define TRISC1 TRISCbits.TRISC1 // bit 1
16513 #define TRISC2 TRISCbits.TRISC2 // bit 2
16514 #define TRISC3 TRISCbits.TRISC3 // bit 3
16515 #define TRISC4 TRISCbits.TRISC4 // bit 4
16516 #define TRISC5 TRISCbits.TRISC5 // bit 5
16517 #define TRISC6 TRISCbits.TRISC6 // bit 6
16518 #define TRISC7 TRISCbits.TRISC7 // bit 7
16520 #define SWDTEN WDTCONbits.SWDTEN // bit 0
16521 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
16522 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
16523 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
16524 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
16525 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
16527 #define WPUA0 WPUAbits.WPUA0 // bit 0
16528 #define WPUA1 WPUAbits.WPUA1 // bit 1
16529 #define WPUA2 WPUAbits.WPUA2 // bit 2
16530 #define WPUA3 WPUAbits.WPUA3 // bit 3
16531 #define WPUA4 WPUAbits.WPUA4 // bit 4
16532 #define WPUA5 WPUAbits.WPUA5 // bit 5
16534 #define WPUB4 WPUBbits.WPUB4 // bit 4
16535 #define WPUB5 WPUBbits.WPUB5 // bit 5
16536 #define WPUB6 WPUBbits.WPUB6 // bit 6
16537 #define WPUB7 WPUBbits.WPUB7 // bit 7
16539 #define WPUC0 WPUCbits.WPUC0 // bit 0
16540 #define WPUC1 WPUCbits.WPUC1 // bit 1
16541 #define WPUC2 WPUCbits.WPUC2 // bit 2
16542 #define WPUC3 WPUCbits.WPUC3 // bit 3
16543 #define WPUC4 WPUCbits.WPUC4 // bit 4
16544 #define WPUC5 WPUCbits.WPUC5 // bit 5
16545 #define WPUC6 WPUCbits.WPUC6 // bit 6
16546 #define WPUC7 WPUCbits.WPUC7 // bit 7
16548 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
16549 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
16550 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
16551 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
16552 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
16554 #endif // #ifndef NO_BIT_DEFINES
16556 #endif // #ifndef __PIC16LF1769_H__