2 * This declarations of the PIC16LF18323 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:23 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF18323_H__
26 #define __PIC16LF18323_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTC_ADDR 0x000E
52 #define PIR0_ADDR 0x0010
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define PIR4_ADDR 0x0014
57 #define TMR0L_ADDR 0x0015
58 #define TMR0H_ADDR 0x0016
59 #define T0CON0_ADDR 0x0017
60 #define T0CON1_ADDR 0x0018
61 #define TMR1_ADDR 0x0019
62 #define TMR1L_ADDR 0x0019
63 #define TMR1H_ADDR 0x001A
64 #define T1CON_ADDR 0x001B
65 #define T1GCON_ADDR 0x001C
66 #define TMR2_ADDR 0x001D
67 #define PR2_ADDR 0x001E
68 #define T2CON_ADDR 0x001F
69 #define TRISA_ADDR 0x008C
70 #define TRISC_ADDR 0x008E
71 #define PIE0_ADDR 0x0090
72 #define PIE1_ADDR 0x0091
73 #define PIE2_ADDR 0x0092
74 #define PIE3_ADDR 0x0093
75 #define PIE4_ADDR 0x0094
76 #define WDTCON_ADDR 0x0097
77 #define ADRES_ADDR 0x009B
78 #define ADRESL_ADDR 0x009B
79 #define ADRESH_ADDR 0x009C
80 #define ADCON0_ADDR 0x009D
81 #define ADCON1_ADDR 0x009E
82 #define ADACT_ADDR 0x009F
83 #define LATA_ADDR 0x010C
84 #define LATC_ADDR 0x010E
85 #define CM1CON0_ADDR 0x0111
86 #define CM1CON1_ADDR 0x0112
87 #define CM2CON0_ADDR 0x0113
88 #define CM2CON1_ADDR 0x0114
89 #define CMOUT_ADDR 0x0115
90 #define BORCON_ADDR 0x0116
91 #define FVRCON_ADDR 0x0117
92 #define DACCON0_ADDR 0x0118
93 #define DACCON1_ADDR 0x0119
94 #define ANSELA_ADDR 0x018C
95 #define ANSELC_ADDR 0x018E
96 #define RC1REG_ADDR 0x0199
97 #define RCREG_ADDR 0x0199
98 #define RCREG1_ADDR 0x0199
99 #define TX1REG_ADDR 0x019A
100 #define TXREG_ADDR 0x019A
101 #define TXREG1_ADDR 0x019A
102 #define SP1BRG_ADDR 0x019B
103 #define SP1BRGL_ADDR 0x019B
104 #define SPBRG_ADDR 0x019B
105 #define SPBRG1_ADDR 0x019B
106 #define SPBRGL_ADDR 0x019B
107 #define SP1BRGH_ADDR 0x019C
108 #define SPBRGH_ADDR 0x019C
109 #define SPBRGH1_ADDR 0x019C
110 #define RC1STA_ADDR 0x019D
111 #define RCSTA_ADDR 0x019D
112 #define RCSTA1_ADDR 0x019D
113 #define TX1STA_ADDR 0x019E
114 #define TXSTA_ADDR 0x019E
115 #define TXSTA1_ADDR 0x019E
116 #define BAUD1CON_ADDR 0x019F
117 #define BAUDCON_ADDR 0x019F
118 #define BAUDCON1_ADDR 0x019F
119 #define BAUDCTL_ADDR 0x019F
120 #define BAUDCTL1_ADDR 0x019F
121 #define WPUA_ADDR 0x020C
122 #define WPUC_ADDR 0x020E
123 #define SSP1BUF_ADDR 0x0211
124 #define SSPBUF_ADDR 0x0211
125 #define SSP1ADD_ADDR 0x0212
126 #define SSPADD_ADDR 0x0212
127 #define SSP1MSK_ADDR 0x0213
128 #define SSPMSK_ADDR 0x0213
129 #define SSP1STAT_ADDR 0x0214
130 #define SSPSTAT_ADDR 0x0214
131 #define SSP1CON_ADDR 0x0215
132 #define SSP1CON1_ADDR 0x0215
133 #define SSPCON_ADDR 0x0215
134 #define SSPCON1_ADDR 0x0215
135 #define SSP1CON2_ADDR 0x0216
136 #define SSPCON2_ADDR 0x0216
137 #define SSP1CON3_ADDR 0x0217
138 #define SSPCON3_ADDR 0x0217
139 #define ODCONA_ADDR 0x028C
140 #define ODCONC_ADDR 0x028E
141 #define CCPR1_ADDR 0x0291
142 #define CCPR1L_ADDR 0x0291
143 #define CCPR1H_ADDR 0x0292
144 #define CCP1CON_ADDR 0x0293
145 #define CCP1CAP_ADDR 0x0294
146 #define CCPR2_ADDR 0x0295
147 #define CCPR2L_ADDR 0x0295
148 #define CCPR2H_ADDR 0x0296
149 #define CCP2CON_ADDR 0x0297
150 #define CCP2CAP_ADDR 0x0298
151 #define CCPTMRS_ADDR 0x029F
152 #define SLRCONA_ADDR 0x030C
153 #define SLRCONC_ADDR 0x030E
154 #define INLVLA_ADDR 0x038C
155 #define INLVLC_ADDR 0x038E
156 #define IOCAP_ADDR 0x0391
157 #define IOCAN_ADDR 0x0392
158 #define IOCAF_ADDR 0x0393
159 #define IOCCP_ADDR 0x0397
160 #define IOCCN_ADDR 0x0398
161 #define IOCCF_ADDR 0x0399
162 #define CLKRCON_ADDR 0x039A
163 #define MDCON_ADDR 0x039C
164 #define MDSRC_ADDR 0x039D
165 #define MDCARH_ADDR 0x039E
166 #define MDCARL_ADDR 0x039F
167 #define CCDNA_ADDR 0x040C
168 #define CCDNC_ADDR 0x040E
169 #define CCDCON_ADDR 0x041F
170 #define CCDPA_ADDR 0x048C
171 #define CCDPC_ADDR 0x048E
172 #define NCO1ACC_ADDR 0x0498
173 #define NCO1ACCL_ADDR 0x0498
174 #define NCO1ACCH_ADDR 0x0499
175 #define NCO1ACCU_ADDR 0x049A
176 #define NCO1INC_ADDR 0x049B
177 #define NCO1INCL_ADDR 0x049B
178 #define NCO1INCH_ADDR 0x049C
179 #define NCO1INCU_ADDR 0x049D
180 #define NCO1CON_ADDR 0x049E
181 #define NCO1CLK_ADDR 0x049F
182 #define PWM5DCL_ADDR 0x0617
183 #define PWM5DCH_ADDR 0x0618
184 #define PWM5CON_ADDR 0x0619
185 #define PWM5CON0_ADDR 0x0619
186 #define PWM6DCL_ADDR 0x061A
187 #define PWM6DCH_ADDR 0x061B
188 #define PWM6CON_ADDR 0x061C
189 #define PWM6CON0_ADDR 0x061C
190 #define CWG1CLKCON_ADDR 0x0691
191 #define CWG1DAT_ADDR 0x0692
192 #define CWG1DBR_ADDR 0x0693
193 #define CWG1DBF_ADDR 0x0694
194 #define CWG1CON0_ADDR 0x0695
195 #define CWG1CON1_ADDR 0x0696
196 #define CWG1AS0_ADDR 0x0697
197 #define CWG1AS1_ADDR 0x0698
198 #define CWG1STR_ADDR 0x0699
199 #define NVMADR_ADDR 0x0891
200 #define NVMADRL_ADDR 0x0891
201 #define NVMADRH_ADDR 0x0892
202 #define NVMDAT_ADDR 0x0893
203 #define NVMDATL_ADDR 0x0893
204 #define NVMDATH_ADDR 0x0894
205 #define NVMCON1_ADDR 0x0895
206 #define NVMCON2_ADDR 0x0896
207 #define PCON0_ADDR 0x089B
208 #define PMD0_ADDR 0x0911
209 #define PMD1_ADDR 0x0912
210 #define PMD2_ADDR 0x0913
211 #define PMD3_ADDR 0x0914
212 #define PMD4_ADDR 0x0915
213 #define PMD5_ADDR 0x0916
214 #define CPUDOZE_ADDR 0x0918
215 #define OSCCON1_ADDR 0x0919
216 #define OSCCON2_ADDR 0x091A
217 #define OSCCON3_ADDR 0x091B
218 #define OSCSTAT1_ADDR 0x091C
219 #define OSCEN_ADDR 0x091D
220 #define OSCTUNE_ADDR 0x091E
221 #define OSCFRQ_ADDR 0x091F
222 #define PPSLOCK_ADDR 0x0E0F
223 #define INTPPS_ADDR 0x0E10
224 #define T0CKIPPS_ADDR 0x0E11
225 #define T1CKIPPS_ADDR 0x0E12
226 #define T1GPPS_ADDR 0x0E13
227 #define CCP1PPS_ADDR 0x0E14
228 #define CCP2PPS_ADDR 0x0E15
229 #define CWG1PPS_ADDR 0x0E18
230 #define MDCIN1PPS_ADDR 0x0E1A
231 #define MDCIN2PPS_ADDR 0x0E1B
232 #define MDMINPPS_ADDR 0x0E1C
233 #define SSP1CLKPPS_ADDR 0x0E20
234 #define SSP1DATPPS_ADDR 0x0E21
235 #define SSP1SSPPS_ADDR 0x0E22
236 #define RXPPS_ADDR 0x0E24
237 #define TXPPS_ADDR 0x0E25
238 #define CLCIN0PPS_ADDR 0x0E28
239 #define CLCIN1PPS_ADDR 0x0E29
240 #define CLCIN2PPS_ADDR 0x0E2A
241 #define CLCIN3PPS_ADDR 0x0E2B
242 #define RA0PPS_ADDR 0x0E90
243 #define RA1PPS_ADDR 0x0E91
244 #define RA2PPS_ADDR 0x0E92
245 #define RA4PPS_ADDR 0x0E94
246 #define RA5PPS_ADDR 0x0E95
247 #define RC0PPS_ADDR 0x0EA0
248 #define RC1PPS_ADDR 0x0EA1
249 #define RC2PPS_ADDR 0x0EA2
250 #define RC3PPS_ADDR 0x0EA3
251 #define RC4PPS_ADDR 0x0EA4
252 #define RC5PPS_ADDR 0x0EA5
253 #define CLCDATA_ADDR 0x0F0F
254 #define CLC1CON_ADDR 0x0F10
255 #define CLC1POL_ADDR 0x0F11
256 #define CLC1SEL0_ADDR 0x0F12
257 #define CLC1SEL1_ADDR 0x0F13
258 #define CLC1SEL2_ADDR 0x0F14
259 #define CLC1SEL3_ADDR 0x0F15
260 #define CLC1GLS0_ADDR 0x0F16
261 #define CLC1GLS1_ADDR 0x0F17
262 #define CLC1GLS2_ADDR 0x0F18
263 #define CLC1GLS3_ADDR 0x0F19
264 #define CLC2CON_ADDR 0x0F1A
265 #define CLC2POL_ADDR 0x0F1B
266 #define CLC2SEL0_ADDR 0x0F1C
267 #define CLC2SEL1_ADDR 0x0F1D
268 #define CLC2SEL2_ADDR 0x0F1E
269 #define CLC2SEL3_ADDR 0x0F1F
270 #define CLC2GLS0_ADDR 0x0F20
271 #define CLC2GLS1_ADDR 0x0F21
272 #define CLC2GLS2_ADDR 0x0F22
273 #define CLC2GLS3_ADDR 0x0F23
274 #define STATUS_SHAD_ADDR 0x0FE4
275 #define WREG_SHAD_ADDR 0x0FE5
276 #define BSR_SHAD_ADDR 0x0FE6
277 #define PCLATH_SHAD_ADDR 0x0FE7
278 #define FSR0L_SHAD_ADDR 0x0FE8
279 #define FSR0H_SHAD_ADDR 0x0FE9
280 #define FSR1L_SHAD_ADDR 0x0FEA
281 #define FSR1H_SHAD_ADDR 0x0FEB
282 #define STKPTR_ADDR 0x0FED
283 #define TOSL_ADDR 0x0FEE
284 #define TOSH_ADDR 0x0FEF
286 #endif // #ifndef NO_ADDR_DEFINES
288 //==============================================================================
290 // Register Definitions
292 //==============================================================================
294 extern __at(0x0000) __sfr INDF0
;
295 extern __at(0x0001) __sfr INDF1
;
296 extern __at(0x0002) __sfr PCL
;
298 //==============================================================================
301 extern __at(0x0003) __sfr STATUS
;
315 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
323 //==============================================================================
325 extern __at(0x0004) __sfr FSR0
;
326 extern __at(0x0004) __sfr FSR0L
;
327 extern __at(0x0005) __sfr FSR0H
;
328 extern __at(0x0006) __sfr FSR1
;
329 extern __at(0x0006) __sfr FSR1L
;
330 extern __at(0x0007) __sfr FSR1H
;
332 //==============================================================================
335 extern __at(0x0008) __sfr BSR
;
358 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
366 //==============================================================================
368 extern __at(0x0009) __sfr WREG
;
369 extern __at(0x000A) __sfr PCLATH
;
371 //==============================================================================
374 extern __at(0x000B) __sfr INTCON
;
388 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
394 //==============================================================================
397 //==============================================================================
400 extern __at(0x000C) __sfr PORTA
;
423 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
432 //==============================================================================
435 //==============================================================================
438 extern __at(0x000E) __sfr PORTC
;
461 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
470 //==============================================================================
473 //==============================================================================
476 extern __at(0x0010) __sfr PIR0
;
490 extern __at(0x0010) volatile __PIR0bits_t PIR0bits
;
496 //==============================================================================
499 //==============================================================================
502 extern __at(0x0011) __sfr PIR1
;
513 unsigned TMR1GIF
: 1;
516 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
525 #define _TMR1GIF 0x80
527 //==============================================================================
530 //==============================================================================
533 extern __at(0x0012) __sfr PIR2
;
547 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
554 //==============================================================================
557 //==============================================================================
560 extern __at(0x0013) __sfr PIR3
;
574 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
581 //==============================================================================
584 //==============================================================================
587 extern __at(0x0014) __sfr PIR4
;
601 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
607 //==============================================================================
610 //==============================================================================
613 extern __at(0x0015) __sfr TMR0L
;
627 extern __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits
;
638 //==============================================================================
641 //==============================================================================
644 extern __at(0x0016) __sfr TMR0H
;
658 extern __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits
;
669 //==============================================================================
672 //==============================================================================
675 extern __at(0x0017) __sfr T0CON0
;
681 unsigned T0OUTPS0
: 1;
682 unsigned T0OUTPS1
: 1;
683 unsigned T0OUTPS2
: 1;
684 unsigned T0OUTPS3
: 1;
685 unsigned T016BIT
: 1;
693 unsigned T0OUTPS
: 4;
698 extern __at(0x0017) volatile __T0CON0bits_t T0CON0bits
;
700 #define _T0OUTPS0 0x01
701 #define _T0OUTPS1 0x02
702 #define _T0OUTPS2 0x04
703 #define _T0OUTPS3 0x08
704 #define _T016BIT 0x10
708 //==============================================================================
711 //==============================================================================
714 extern __at(0x0018) __sfr T0CON1
;
720 unsigned T0CKPS0
: 1;
721 unsigned T0CKPS1
: 1;
722 unsigned T0CKPS2
: 1;
723 unsigned T0CKPS3
: 1;
724 unsigned T0ASYNC
: 1;
743 extern __at(0x0018) volatile __T0CON1bits_t T0CON1bits
;
745 #define _T0CKPS0 0x01
746 #define _T0CKPS1 0x02
747 #define _T0CKPS2 0x04
748 #define _T0CKPS3 0x08
749 #define _T0ASYNC 0x10
754 //==============================================================================
756 extern __at(0x0019) __sfr TMR1
;
757 extern __at(0x0019) __sfr TMR1L
;
758 extern __at(0x001A) __sfr TMR1H
;
760 //==============================================================================
763 extern __at(0x001B) __sfr T1CON
;
773 unsigned T1CKPS0
: 1;
774 unsigned T1CKPS1
: 1;
775 unsigned TMR1CS0
: 1;
776 unsigned TMR1CS1
: 1;
793 extern __at(0x001B) volatile __T1CONbits_t T1CONbits
;
798 #define _T1CKPS0 0x10
799 #define _T1CKPS1 0x20
800 #define _TMR1CS0 0x40
801 #define _TMR1CS1 0x80
803 //==============================================================================
806 //==============================================================================
809 extern __at(0x001C) __sfr T1GCON
;
818 unsigned T1GGO_NOT_DONE
: 1;
832 extern __at(0x001C) volatile __T1GCONbits_t T1GCONbits
;
837 #define _T1GGO_NOT_DONE 0x08
843 //==============================================================================
845 extern __at(0x001D) __sfr TMR2
;
846 extern __at(0x001E) __sfr PR2
;
848 //==============================================================================
851 extern __at(0x001F) __sfr T2CON
;
857 unsigned T2CKPS0
: 1;
858 unsigned T2CKPS1
: 1;
860 unsigned T2OUTPS0
: 1;
861 unsigned T2OUTPS1
: 1;
862 unsigned T2OUTPS2
: 1;
863 unsigned T2OUTPS3
: 1;
876 unsigned T2OUTPS
: 4;
881 extern __at(0x001F) volatile __T2CONbits_t T2CONbits
;
883 #define _T2CKPS0 0x01
884 #define _T2CKPS1 0x02
886 #define _T2OUTPS0 0x08
887 #define _T2OUTPS1 0x10
888 #define _T2OUTPS2 0x20
889 #define _T2OUTPS3 0x40
891 //==============================================================================
894 //==============================================================================
897 extern __at(0x008C) __sfr TRISA
;
911 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
919 //==============================================================================
922 //==============================================================================
925 extern __at(0x008E) __sfr TRISC
;
948 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
957 //==============================================================================
960 //==============================================================================
963 extern __at(0x0090) __sfr PIE0
;
977 extern __at(0x0090) volatile __PIE0bits_t PIE0bits
;
983 //==============================================================================
986 //==============================================================================
989 extern __at(0x0091) __sfr PIE1
;
1000 unsigned TMR1GIE
: 1;
1003 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1005 #define _TMR1IE 0x01
1006 #define _TMR2IE 0x02
1007 #define _BCL1IE 0x04
1008 #define _SSP1IE 0x08
1012 #define _TMR1GIE 0x80
1014 //==============================================================================
1017 //==============================================================================
1020 extern __at(0x0092) __sfr PIE2
;
1024 unsigned NCO1IE
: 1;
1034 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1036 #define _NCO1IE 0x01
1041 //==============================================================================
1044 //==============================================================================
1047 extern __at(0x0093) __sfr PIE3
;
1051 unsigned CLC1IE
: 1;
1052 unsigned CLC2IE
: 1;
1061 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1063 #define _CLC1IE 0x01
1064 #define _CLC2IE 0x02
1068 //==============================================================================
1071 //==============================================================================
1074 extern __at(0x0094) __sfr PIE4
;
1078 unsigned CCP1IE
: 1;
1079 unsigned CCP2IE
: 1;
1084 unsigned CWG1IE
: 1;
1088 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1090 #define _CCP1IE 0x01
1091 #define _CCP2IE 0x02
1092 #define _CWG1IE 0x40
1094 //==============================================================================
1097 //==============================================================================
1100 extern __at(0x0097) __sfr WDTCON
;
1106 unsigned SWDTEN
: 1;
1107 unsigned WDTPS0
: 1;
1108 unsigned WDTPS1
: 1;
1109 unsigned WDTPS2
: 1;
1110 unsigned WDTPS3
: 1;
1111 unsigned WDTPS4
: 1;
1124 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1126 #define _SWDTEN 0x01
1127 #define _WDTPS0 0x02
1128 #define _WDTPS1 0x04
1129 #define _WDTPS2 0x08
1130 #define _WDTPS3 0x10
1131 #define _WDTPS4 0x20
1133 //==============================================================================
1135 extern __at(0x009B) __sfr ADRES
;
1136 extern __at(0x009B) __sfr ADRESL
;
1137 extern __at(0x009C) __sfr ADRESH
;
1139 //==============================================================================
1142 extern __at(0x009D) __sfr ADCON0
;
1149 unsigned GO_NOT_DONE
: 1;
1189 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1192 #define _GO_NOT_DONE 0x02
1202 //==============================================================================
1205 //==============================================================================
1208 extern __at(0x009E) __sfr ADCON1
;
1214 unsigned ADPREF0
: 1;
1215 unsigned ADPREF1
: 1;
1216 unsigned ADNREF
: 1;
1226 unsigned ADPREF
: 2;
1238 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1240 #define _ADPREF0 0x01
1241 #define _ADPREF1 0x02
1242 #define _ADNREF 0x04
1248 //==============================================================================
1251 //==============================================================================
1254 extern __at(0x009F) __sfr ADACT
;
1260 unsigned ADACT0
: 1;
1261 unsigned ADACT1
: 1;
1262 unsigned ADACT2
: 1;
1263 unsigned ADACT3
: 1;
1277 extern __at(0x009F) volatile __ADACTbits_t ADACTbits
;
1279 #define _ADACT0 0x01
1280 #define _ADACT1 0x02
1281 #define _ADACT2 0x04
1282 #define _ADACT3 0x08
1284 //==============================================================================
1287 //==============================================================================
1290 extern __at(0x010C) __sfr LATA
;
1304 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1312 //==============================================================================
1315 //==============================================================================
1318 extern __at(0x010E) __sfr LATC
;
1341 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1350 //==============================================================================
1353 //==============================================================================
1356 extern __at(0x0111) __sfr CM1CON0
;
1360 unsigned C1SYNC
: 1;
1370 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1372 #define _C1SYNC 0x01
1379 //==============================================================================
1382 //==============================================================================
1385 extern __at(0x0112) __sfr CM1CON1
;
1391 unsigned C1NCH0
: 1;
1392 unsigned C1NCH1
: 1;
1393 unsigned C1NCH2
: 1;
1394 unsigned C1PCH0
: 1;
1395 unsigned C1PCH1
: 1;
1396 unsigned C1PCH2
: 1;
1397 unsigned C1INTN
: 1;
1398 unsigned C1INTP
: 1;
1415 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1417 #define _C1NCH0 0x01
1418 #define _C1NCH1 0x02
1419 #define _C1NCH2 0x04
1420 #define _C1PCH0 0x08
1421 #define _C1PCH1 0x10
1422 #define _C1PCH2 0x20
1423 #define _C1INTN 0x40
1424 #define _C1INTP 0x80
1426 //==============================================================================
1429 //==============================================================================
1432 extern __at(0x0113) __sfr CM2CON0
;
1436 unsigned C2SYNC
: 1;
1446 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1448 #define _C2SYNC 0x01
1455 //==============================================================================
1458 //==============================================================================
1461 extern __at(0x0114) __sfr CM2CON1
;
1467 unsigned C2NCH0
: 1;
1468 unsigned C2NCH1
: 1;
1469 unsigned C2NCH2
: 1;
1470 unsigned C2PCH0
: 1;
1471 unsigned C2PCH1
: 1;
1472 unsigned C2PCH2
: 1;
1473 unsigned C2INTN
: 1;
1474 unsigned C2INTP
: 1;
1491 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1493 #define _C2NCH0 0x01
1494 #define _C2NCH1 0x02
1495 #define _C2NCH2 0x04
1496 #define _C2PCH0 0x08
1497 #define _C2PCH1 0x10
1498 #define _C2PCH2 0x20
1499 #define _C2INTN 0x40
1500 #define _C2INTP 0x80
1502 //==============================================================================
1505 //==============================================================================
1508 extern __at(0x0115) __sfr CMOUT
;
1512 unsigned MC1OUT
: 1;
1513 unsigned MC2OUT
: 1;
1522 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1524 #define _MC1OUT 0x01
1525 #define _MC2OUT 0x02
1527 //==============================================================================
1530 //==============================================================================
1533 extern __at(0x0116) __sfr BORCON
;
1537 unsigned BORRDY
: 1;
1544 unsigned SBOREN
: 1;
1547 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1549 #define _BORRDY 0x01
1550 #define _SBOREN 0x80
1552 //==============================================================================
1555 //==============================================================================
1558 extern __at(0x0117) __sfr FVRCON
;
1564 unsigned ADFVR0
: 1;
1565 unsigned ADFVR1
: 1;
1566 unsigned CDAFVR0
: 1;
1567 unsigned CDAFVR1
: 1;
1570 unsigned FVRRDY
: 1;
1583 unsigned CDAFVR
: 2;
1588 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1590 #define _ADFVR0 0x01
1591 #define _ADFVR1 0x02
1592 #define _CDAFVR0 0x04
1593 #define _CDAFVR1 0x08
1596 #define _FVRRDY 0x40
1599 //==============================================================================
1602 //==============================================================================
1605 extern __at(0x0118) __sfr DACCON0
;
1611 unsigned DAC1NSS
: 1;
1613 unsigned DAC1PSS0
: 1;
1614 unsigned DAC1PSS1
: 1;
1616 unsigned DAC1OE
: 1;
1618 unsigned DAC1EN
: 1;
1624 unsigned DAC1PSS
: 2;
1629 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1631 #define _DAC1NSS 0x01
1632 #define _DAC1PSS0 0x04
1633 #define _DAC1PSS1 0x08
1634 #define _DAC1OE 0x20
1635 #define _DAC1EN 0x80
1637 //==============================================================================
1640 //==============================================================================
1643 extern __at(0x0119) __sfr DACCON1
;
1649 unsigned DAC1R0
: 1;
1650 unsigned DAC1R1
: 1;
1651 unsigned DAC1R2
: 1;
1652 unsigned DAC1R3
: 1;
1653 unsigned DAC1R4
: 1;
1666 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1668 #define _DAC1R0 0x01
1669 #define _DAC1R1 0x02
1670 #define _DAC1R2 0x04
1671 #define _DAC1R3 0x08
1672 #define _DAC1R4 0x10
1674 //==============================================================================
1677 //==============================================================================
1680 extern __at(0x018C) __sfr ANSELA
;
1694 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1702 //==============================================================================
1705 //==============================================================================
1708 extern __at(0x018E) __sfr ANSELC
;
1731 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1740 //==============================================================================
1742 extern __at(0x0199) __sfr RC1REG
;
1743 extern __at(0x0199) __sfr RCREG
;
1744 extern __at(0x0199) __sfr RCREG1
;
1745 extern __at(0x019A) __sfr TX1REG
;
1746 extern __at(0x019A) __sfr TXREG
;
1747 extern __at(0x019A) __sfr TXREG1
;
1748 extern __at(0x019B) __sfr SP1BRG
;
1749 extern __at(0x019B) __sfr SP1BRGL
;
1750 extern __at(0x019B) __sfr SPBRG
;
1751 extern __at(0x019B) __sfr SPBRG1
;
1752 extern __at(0x019B) __sfr SPBRGL
;
1753 extern __at(0x019C) __sfr SP1BRGH
;
1754 extern __at(0x019C) __sfr SPBRGH
;
1755 extern __at(0x019C) __sfr SPBRGH1
;
1757 //==============================================================================
1760 extern __at(0x019D) __sfr RC1STA
;
1774 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1785 //==============================================================================
1788 //==============================================================================
1791 extern __at(0x019D) __sfr RCSTA
;
1805 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1807 #define _RCSTA_RX9D 0x01
1808 #define _RCSTA_OERR 0x02
1809 #define _RCSTA_FERR 0x04
1810 #define _RCSTA_ADDEN 0x08
1811 #define _RCSTA_CREN 0x10
1812 #define _RCSTA_SREN 0x20
1813 #define _RCSTA_RX9 0x40
1814 #define _RCSTA_SPEN 0x80
1816 //==============================================================================
1819 //==============================================================================
1822 extern __at(0x019D) __sfr RCSTA1
;
1836 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
1838 #define _RCSTA1_RX9D 0x01
1839 #define _RCSTA1_OERR 0x02
1840 #define _RCSTA1_FERR 0x04
1841 #define _RCSTA1_ADDEN 0x08
1842 #define _RCSTA1_CREN 0x10
1843 #define _RCSTA1_SREN 0x20
1844 #define _RCSTA1_RX9 0x40
1845 #define _RCSTA1_SPEN 0x80
1847 //==============================================================================
1850 //==============================================================================
1853 extern __at(0x019E) __sfr TX1STA
;
1867 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
1878 //==============================================================================
1881 //==============================================================================
1884 extern __at(0x019E) __sfr TXSTA
;
1898 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
1900 #define _TXSTA_TX9D 0x01
1901 #define _TXSTA_TRMT 0x02
1902 #define _TXSTA_BRGH 0x04
1903 #define _TXSTA_SENDB 0x08
1904 #define _TXSTA_SYNC 0x10
1905 #define _TXSTA_TXEN 0x20
1906 #define _TXSTA_TX9 0x40
1907 #define _TXSTA_CSRC 0x80
1909 //==============================================================================
1912 //==============================================================================
1915 extern __at(0x019E) __sfr TXSTA1
;
1929 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
1931 #define _TXSTA1_TX9D 0x01
1932 #define _TXSTA1_TRMT 0x02
1933 #define _TXSTA1_BRGH 0x04
1934 #define _TXSTA1_SENDB 0x08
1935 #define _TXSTA1_SYNC 0x10
1936 #define _TXSTA1_TXEN 0x20
1937 #define _TXSTA1_TX9 0x40
1938 #define _TXSTA1_CSRC 0x80
1940 //==============================================================================
1943 //==============================================================================
1946 extern __at(0x019F) __sfr BAUD1CON
;
1957 unsigned ABDOVF
: 1;
1960 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
1967 #define _ABDOVF 0x80
1969 //==============================================================================
1972 //==============================================================================
1975 extern __at(0x019F) __sfr BAUDCON
;
1986 unsigned ABDOVF
: 1;
1989 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
1991 #define _BAUDCON_ABDEN 0x01
1992 #define _BAUDCON_WUE 0x02
1993 #define _BAUDCON_BRG16 0x08
1994 #define _BAUDCON_SCKP 0x10
1995 #define _BAUDCON_RCIDL 0x40
1996 #define _BAUDCON_ABDOVF 0x80
1998 //==============================================================================
2001 //==============================================================================
2004 extern __at(0x019F) __sfr BAUDCON1
;
2015 unsigned ABDOVF
: 1;
2018 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2020 #define _BAUDCON1_ABDEN 0x01
2021 #define _BAUDCON1_WUE 0x02
2022 #define _BAUDCON1_BRG16 0x08
2023 #define _BAUDCON1_SCKP 0x10
2024 #define _BAUDCON1_RCIDL 0x40
2025 #define _BAUDCON1_ABDOVF 0x80
2027 //==============================================================================
2030 //==============================================================================
2033 extern __at(0x019F) __sfr BAUDCTL
;
2044 unsigned ABDOVF
: 1;
2047 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2049 #define _BAUDCTL_ABDEN 0x01
2050 #define _BAUDCTL_WUE 0x02
2051 #define _BAUDCTL_BRG16 0x08
2052 #define _BAUDCTL_SCKP 0x10
2053 #define _BAUDCTL_RCIDL 0x40
2054 #define _BAUDCTL_ABDOVF 0x80
2056 //==============================================================================
2059 //==============================================================================
2062 extern __at(0x019F) __sfr BAUDCTL1
;
2073 unsigned ABDOVF
: 1;
2076 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2078 #define _BAUDCTL1_ABDEN 0x01
2079 #define _BAUDCTL1_WUE 0x02
2080 #define _BAUDCTL1_BRG16 0x08
2081 #define _BAUDCTL1_SCKP 0x10
2082 #define _BAUDCTL1_RCIDL 0x40
2083 #define _BAUDCTL1_ABDOVF 0x80
2085 //==============================================================================
2088 //==============================================================================
2091 extern __at(0x020C) __sfr WPUA
;
2114 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2123 //==============================================================================
2126 //==============================================================================
2129 extern __at(0x020E) __sfr WPUC
;
2152 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2161 //==============================================================================
2164 //==============================================================================
2167 extern __at(0x0211) __sfr SSP1BUF
;
2173 unsigned SSP1BUF0
: 1;
2174 unsigned SSP1BUF1
: 1;
2175 unsigned SSP1BUF2
: 1;
2176 unsigned SSP1BUF3
: 1;
2177 unsigned SSP1BUF4
: 1;
2178 unsigned SSP1BUF5
: 1;
2179 unsigned SSP1BUF6
: 1;
2180 unsigned SSP1BUF7
: 1;
2196 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2198 #define _SSP1BUF0 0x01
2200 #define _SSP1BUF1 0x02
2202 #define _SSP1BUF2 0x04
2204 #define _SSP1BUF3 0x08
2206 #define _SSP1BUF4 0x10
2208 #define _SSP1BUF5 0x20
2210 #define _SSP1BUF6 0x40
2212 #define _SSP1BUF7 0x80
2215 //==============================================================================
2218 //==============================================================================
2221 extern __at(0x0211) __sfr SSPBUF
;
2227 unsigned SSP1BUF0
: 1;
2228 unsigned SSP1BUF1
: 1;
2229 unsigned SSP1BUF2
: 1;
2230 unsigned SSP1BUF3
: 1;
2231 unsigned SSP1BUF4
: 1;
2232 unsigned SSP1BUF5
: 1;
2233 unsigned SSP1BUF6
: 1;
2234 unsigned SSP1BUF7
: 1;
2250 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2252 #define _SSPBUF_SSP1BUF0 0x01
2253 #define _SSPBUF_BUF0 0x01
2254 #define _SSPBUF_SSP1BUF1 0x02
2255 #define _SSPBUF_BUF1 0x02
2256 #define _SSPBUF_SSP1BUF2 0x04
2257 #define _SSPBUF_BUF2 0x04
2258 #define _SSPBUF_SSP1BUF3 0x08
2259 #define _SSPBUF_BUF3 0x08
2260 #define _SSPBUF_SSP1BUF4 0x10
2261 #define _SSPBUF_BUF4 0x10
2262 #define _SSPBUF_SSP1BUF5 0x20
2263 #define _SSPBUF_BUF5 0x20
2264 #define _SSPBUF_SSP1BUF6 0x40
2265 #define _SSPBUF_BUF6 0x40
2266 #define _SSPBUF_SSP1BUF7 0x80
2267 #define _SSPBUF_BUF7 0x80
2269 //==============================================================================
2272 //==============================================================================
2275 extern __at(0x0212) __sfr SSP1ADD
;
2281 unsigned SSP1ADD0
: 1;
2282 unsigned SSP1ADD1
: 1;
2283 unsigned SSP1ADD2
: 1;
2284 unsigned SSP1ADD3
: 1;
2285 unsigned SSP1ADD4
: 1;
2286 unsigned SSP1ADD5
: 1;
2287 unsigned SSP1ADD6
: 1;
2288 unsigned SSP1ADD7
: 1;
2304 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2306 #define _SSP1ADD0 0x01
2308 #define _SSP1ADD1 0x02
2310 #define _SSP1ADD2 0x04
2312 #define _SSP1ADD3 0x08
2314 #define _SSP1ADD4 0x10
2316 #define _SSP1ADD5 0x20
2318 #define _SSP1ADD6 0x40
2320 #define _SSP1ADD7 0x80
2323 //==============================================================================
2326 //==============================================================================
2329 extern __at(0x0212) __sfr SSPADD
;
2335 unsigned SSP1ADD0
: 1;
2336 unsigned SSP1ADD1
: 1;
2337 unsigned SSP1ADD2
: 1;
2338 unsigned SSP1ADD3
: 1;
2339 unsigned SSP1ADD4
: 1;
2340 unsigned SSP1ADD5
: 1;
2341 unsigned SSP1ADD6
: 1;
2342 unsigned SSP1ADD7
: 1;
2358 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2360 #define _SSPADD_SSP1ADD0 0x01
2361 #define _SSPADD_ADD0 0x01
2362 #define _SSPADD_SSP1ADD1 0x02
2363 #define _SSPADD_ADD1 0x02
2364 #define _SSPADD_SSP1ADD2 0x04
2365 #define _SSPADD_ADD2 0x04
2366 #define _SSPADD_SSP1ADD3 0x08
2367 #define _SSPADD_ADD3 0x08
2368 #define _SSPADD_SSP1ADD4 0x10
2369 #define _SSPADD_ADD4 0x10
2370 #define _SSPADD_SSP1ADD5 0x20
2371 #define _SSPADD_ADD5 0x20
2372 #define _SSPADD_SSP1ADD6 0x40
2373 #define _SSPADD_ADD6 0x40
2374 #define _SSPADD_SSP1ADD7 0x80
2375 #define _SSPADD_ADD7 0x80
2377 //==============================================================================
2380 //==============================================================================
2383 extern __at(0x0213) __sfr SSP1MSK
;
2389 unsigned SSP1MSK0
: 1;
2390 unsigned SSP1MSK1
: 1;
2391 unsigned SSP1MSK2
: 1;
2392 unsigned SSP1MSK3
: 1;
2393 unsigned SSP1MSK4
: 1;
2394 unsigned SSP1MSK5
: 1;
2395 unsigned SSP1MSK6
: 1;
2396 unsigned SSP1MSK7
: 1;
2412 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2414 #define _SSP1MSK0 0x01
2416 #define _SSP1MSK1 0x02
2418 #define _SSP1MSK2 0x04
2420 #define _SSP1MSK3 0x08
2422 #define _SSP1MSK4 0x10
2424 #define _SSP1MSK5 0x20
2426 #define _SSP1MSK6 0x40
2428 #define _SSP1MSK7 0x80
2431 //==============================================================================
2434 //==============================================================================
2437 extern __at(0x0213) __sfr SSPMSK
;
2443 unsigned SSP1MSK0
: 1;
2444 unsigned SSP1MSK1
: 1;
2445 unsigned SSP1MSK2
: 1;
2446 unsigned SSP1MSK3
: 1;
2447 unsigned SSP1MSK4
: 1;
2448 unsigned SSP1MSK5
: 1;
2449 unsigned SSP1MSK6
: 1;
2450 unsigned SSP1MSK7
: 1;
2466 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2468 #define _SSPMSK_SSP1MSK0 0x01
2469 #define _SSPMSK_MSK0 0x01
2470 #define _SSPMSK_SSP1MSK1 0x02
2471 #define _SSPMSK_MSK1 0x02
2472 #define _SSPMSK_SSP1MSK2 0x04
2473 #define _SSPMSK_MSK2 0x04
2474 #define _SSPMSK_SSP1MSK3 0x08
2475 #define _SSPMSK_MSK3 0x08
2476 #define _SSPMSK_SSP1MSK4 0x10
2477 #define _SSPMSK_MSK4 0x10
2478 #define _SSPMSK_SSP1MSK5 0x20
2479 #define _SSPMSK_MSK5 0x20
2480 #define _SSPMSK_SSP1MSK6 0x40
2481 #define _SSPMSK_MSK6 0x40
2482 #define _SSPMSK_SSP1MSK7 0x80
2483 #define _SSPMSK_MSK7 0x80
2485 //==============================================================================
2488 //==============================================================================
2491 extern __at(0x0214) __sfr SSP1STAT
;
2497 unsigned R_NOT_W
: 1;
2500 unsigned D_NOT_A
: 1;
2505 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2509 #define _R_NOT_W 0x04
2512 #define _D_NOT_A 0x20
2516 //==============================================================================
2519 //==============================================================================
2522 extern __at(0x0214) __sfr SSPSTAT
;
2528 unsigned R_NOT_W
: 1;
2531 unsigned D_NOT_A
: 1;
2536 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2538 #define _SSPSTAT_BF 0x01
2539 #define _SSPSTAT_UA 0x02
2540 #define _SSPSTAT_R_NOT_W 0x04
2541 #define _SSPSTAT_S 0x08
2542 #define _SSPSTAT_P 0x10
2543 #define _SSPSTAT_D_NOT_A 0x20
2544 #define _SSPSTAT_CKE 0x40
2545 #define _SSPSTAT_SMP 0x80
2547 //==============================================================================
2550 //==============================================================================
2553 extern __at(0x0215) __sfr SSP1CON
;
2576 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2587 //==============================================================================
2590 //==============================================================================
2593 extern __at(0x0215) __sfr SSP1CON1
;
2616 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2618 #define _SSP1CON1_SSPM0 0x01
2619 #define _SSP1CON1_SSPM1 0x02
2620 #define _SSP1CON1_SSPM2 0x04
2621 #define _SSP1CON1_SSPM3 0x08
2622 #define _SSP1CON1_CKP 0x10
2623 #define _SSP1CON1_SSPEN 0x20
2624 #define _SSP1CON1_SSPOV 0x40
2625 #define _SSP1CON1_WCOL 0x80
2627 //==============================================================================
2630 //==============================================================================
2633 extern __at(0x0215) __sfr SSPCON
;
2656 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2658 #define _SSPCON_SSPM0 0x01
2659 #define _SSPCON_SSPM1 0x02
2660 #define _SSPCON_SSPM2 0x04
2661 #define _SSPCON_SSPM3 0x08
2662 #define _SSPCON_CKP 0x10
2663 #define _SSPCON_SSPEN 0x20
2664 #define _SSPCON_SSPOV 0x40
2665 #define _SSPCON_WCOL 0x80
2667 //==============================================================================
2670 //==============================================================================
2673 extern __at(0x0215) __sfr SSPCON1
;
2696 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2698 #define _SSPCON1_SSPM0 0x01
2699 #define _SSPCON1_SSPM1 0x02
2700 #define _SSPCON1_SSPM2 0x04
2701 #define _SSPCON1_SSPM3 0x08
2702 #define _SSPCON1_CKP 0x10
2703 #define _SSPCON1_SSPEN 0x20
2704 #define _SSPCON1_SSPOV 0x40
2705 #define _SSPCON1_WCOL 0x80
2707 //==============================================================================
2710 //==============================================================================
2713 extern __at(0x0216) __sfr SSP1CON2
;
2723 unsigned ACKSTAT
: 1;
2727 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2735 #define _ACKSTAT 0x40
2738 //==============================================================================
2741 //==============================================================================
2744 extern __at(0x0216) __sfr SSPCON2
;
2754 unsigned ACKSTAT
: 1;
2758 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2760 #define _SSPCON2_SEN 0x01
2761 #define _SSPCON2_RSEN 0x02
2762 #define _SSPCON2_PEN 0x04
2763 #define _SSPCON2_RCEN 0x08
2764 #define _SSPCON2_ACKEN 0x10
2765 #define _SSPCON2_ACKDT 0x20
2766 #define _SSPCON2_ACKSTAT 0x40
2767 #define _SSPCON2_GCEN 0x80
2769 //==============================================================================
2772 //==============================================================================
2775 extern __at(0x0217) __sfr SSP1CON3
;
2786 unsigned ACKTIM
: 1;
2789 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
2798 #define _ACKTIM 0x80
2800 //==============================================================================
2803 //==============================================================================
2806 extern __at(0x0217) __sfr SSPCON3
;
2817 unsigned ACKTIM
: 1;
2820 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2822 #define _SSPCON3_DHEN 0x01
2823 #define _SSPCON3_AHEN 0x02
2824 #define _SSPCON3_SBCDE 0x04
2825 #define _SSPCON3_SDAHT 0x08
2826 #define _SSPCON3_BOEN 0x10
2827 #define _SSPCON3_SCIE 0x20
2828 #define _SSPCON3_PCIE 0x40
2829 #define _SSPCON3_ACKTIM 0x80
2831 //==============================================================================
2834 //==============================================================================
2837 extern __at(0x028C) __sfr ODCONA
;
2851 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
2859 //==============================================================================
2862 //==============================================================================
2865 extern __at(0x028E) __sfr ODCONC
;
2888 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
2897 //==============================================================================
2899 extern __at(0x0291) __sfr CCPR1
;
2900 extern __at(0x0291) __sfr CCPR1L
;
2901 extern __at(0x0292) __sfr CCPR1H
;
2903 //==============================================================================
2906 extern __at(0x0293) __sfr CCP1CON
;
2912 unsigned CCP1MODE0
: 1;
2913 unsigned CCP1MODE1
: 1;
2914 unsigned CCP1MODE2
: 1;
2915 unsigned CCP1MODE3
: 1;
2916 unsigned CCP1FMT
: 1;
2917 unsigned CCP1OUT
: 1;
2919 unsigned CCP1EN
: 1;
2924 unsigned CCP1MODE
: 4;
2929 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
2931 #define _CCP1MODE0 0x01
2932 #define _CCP1MODE1 0x02
2933 #define _CCP1MODE2 0x04
2934 #define _CCP1MODE3 0x08
2935 #define _CCP1FMT 0x10
2936 #define _CCP1OUT 0x20
2937 #define _CCP1EN 0x80
2939 //==============================================================================
2942 //==============================================================================
2945 extern __at(0x0294) __sfr CCP1CAP
;
2951 unsigned CCP1CTS0
: 1;
2952 unsigned CCP1CTS1
: 1;
2953 unsigned CCP1CTS2
: 1;
2963 unsigned CCP1CTS
: 3;
2968 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
2970 #define _CCP1CTS0 0x01
2971 #define _CCP1CTS1 0x02
2972 #define _CCP1CTS2 0x04
2974 //==============================================================================
2976 extern __at(0x0295) __sfr CCPR2
;
2977 extern __at(0x0295) __sfr CCPR2L
;
2978 extern __at(0x0296) __sfr CCPR2H
;
2980 //==============================================================================
2983 extern __at(0x0297) __sfr CCP2CON
;
2989 unsigned CCP2MODE0
: 1;
2990 unsigned CCP2MODE1
: 1;
2991 unsigned CCP2MODE2
: 1;
2992 unsigned CCP2MODE3
: 1;
2993 unsigned CCP2FMT
: 1;
2994 unsigned CCP2OUT
: 1;
2996 unsigned CCP2EN
: 1;
3001 unsigned CCP2MODE
: 4;
3006 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
3008 #define _CCP2MODE0 0x01
3009 #define _CCP2MODE1 0x02
3010 #define _CCP2MODE2 0x04
3011 #define _CCP2MODE3 0x08
3012 #define _CCP2FMT 0x10
3013 #define _CCP2OUT 0x20
3014 #define _CCP2EN 0x80
3016 //==============================================================================
3019 //==============================================================================
3022 extern __at(0x0298) __sfr CCP2CAP
;
3028 unsigned CCP2CTS0
: 1;
3029 unsigned CCP2CTS1
: 1;
3030 unsigned CCP2CTS2
: 1;
3040 unsigned CCP2CTS
: 3;
3045 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
3047 #define _CCP2CTS0 0x01
3048 #define _CCP2CTS1 0x02
3049 #define _CCP2CTS2 0x04
3051 //==============================================================================
3054 //==============================================================================
3057 extern __at(0x029F) __sfr CCPTMRS
;
3061 unsigned C1TSEL
: 1;
3063 unsigned C2TSEL
: 1;
3071 extern __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits
;
3073 #define _C1TSEL 0x01
3074 #define _C2TSEL 0x04
3076 //==============================================================================
3079 //==============================================================================
3082 extern __at(0x030C) __sfr SLRCONA
;
3096 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3104 //==============================================================================
3107 //==============================================================================
3110 extern __at(0x030E) __sfr SLRCONC
;
3133 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3142 //==============================================================================
3145 //==============================================================================
3148 extern __at(0x038C) __sfr INLVLA
;
3154 unsigned INLVLA0
: 1;
3155 unsigned INLVLA1
: 1;
3156 unsigned INLVLA2
: 1;
3157 unsigned INLVLA3
: 1;
3158 unsigned INLVLA4
: 1;
3159 unsigned INLVLA5
: 1;
3166 unsigned INLVLA
: 6;
3171 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3173 #define _INLVLA0 0x01
3174 #define _INLVLA1 0x02
3175 #define _INLVLA2 0x04
3176 #define _INLVLA3 0x08
3177 #define _INLVLA4 0x10
3178 #define _INLVLA5 0x20
3180 //==============================================================================
3183 //==============================================================================
3186 extern __at(0x038E) __sfr INLVLC
;
3192 unsigned INLVLC0
: 1;
3193 unsigned INLVLC1
: 1;
3194 unsigned INLVLC2
: 1;
3195 unsigned INLVLC3
: 1;
3196 unsigned INLVLC4
: 1;
3197 unsigned INLVLC5
: 1;
3204 unsigned INLVLC
: 6;
3209 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3211 #define _INLVLC0 0x01
3212 #define _INLVLC1 0x02
3213 #define _INLVLC2 0x04
3214 #define _INLVLC3 0x08
3215 #define _INLVLC4 0x10
3216 #define _INLVLC5 0x20
3218 //==============================================================================
3221 //==============================================================================
3224 extern __at(0x0391) __sfr IOCAP
;
3230 unsigned IOCAP0
: 1;
3231 unsigned IOCAP1
: 1;
3232 unsigned IOCAP2
: 1;
3233 unsigned IOCAP3
: 1;
3234 unsigned IOCAP4
: 1;
3235 unsigned IOCAP5
: 1;
3247 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3249 #define _IOCAP0 0x01
3250 #define _IOCAP1 0x02
3251 #define _IOCAP2 0x04
3252 #define _IOCAP3 0x08
3253 #define _IOCAP4 0x10
3254 #define _IOCAP5 0x20
3256 //==============================================================================
3259 //==============================================================================
3262 extern __at(0x0392) __sfr IOCAN
;
3268 unsigned IOCAN0
: 1;
3269 unsigned IOCAN1
: 1;
3270 unsigned IOCAN2
: 1;
3271 unsigned IOCAN3
: 1;
3272 unsigned IOCAN4
: 1;
3273 unsigned IOCAN5
: 1;
3285 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3287 #define _IOCAN0 0x01
3288 #define _IOCAN1 0x02
3289 #define _IOCAN2 0x04
3290 #define _IOCAN3 0x08
3291 #define _IOCAN4 0x10
3292 #define _IOCAN5 0x20
3294 //==============================================================================
3297 //==============================================================================
3300 extern __at(0x0393) __sfr IOCAF
;
3306 unsigned IOCAF0
: 1;
3307 unsigned IOCAF1
: 1;
3308 unsigned IOCAF2
: 1;
3309 unsigned IOCAF3
: 1;
3310 unsigned IOCAF4
: 1;
3311 unsigned IOCAF5
: 1;
3323 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3325 #define _IOCAF0 0x01
3326 #define _IOCAF1 0x02
3327 #define _IOCAF2 0x04
3328 #define _IOCAF3 0x08
3329 #define _IOCAF4 0x10
3330 #define _IOCAF5 0x20
3332 //==============================================================================
3335 //==============================================================================
3338 extern __at(0x0397) __sfr IOCCP
;
3344 unsigned IOCCP0
: 1;
3345 unsigned IOCCP1
: 1;
3346 unsigned IOCCP2
: 1;
3347 unsigned IOCCP3
: 1;
3348 unsigned IOCCP4
: 1;
3349 unsigned IOCCP5
: 1;
3361 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3363 #define _IOCCP0 0x01
3364 #define _IOCCP1 0x02
3365 #define _IOCCP2 0x04
3366 #define _IOCCP3 0x08
3367 #define _IOCCP4 0x10
3368 #define _IOCCP5 0x20
3370 //==============================================================================
3373 //==============================================================================
3376 extern __at(0x0398) __sfr IOCCN
;
3382 unsigned IOCCN0
: 1;
3383 unsigned IOCCN1
: 1;
3384 unsigned IOCCN2
: 1;
3385 unsigned IOCCN3
: 1;
3386 unsigned IOCCN4
: 1;
3387 unsigned IOCCN5
: 1;
3399 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
3401 #define _IOCCN0 0x01
3402 #define _IOCCN1 0x02
3403 #define _IOCCN2 0x04
3404 #define _IOCCN3 0x08
3405 #define _IOCCN4 0x10
3406 #define _IOCCN5 0x20
3408 //==============================================================================
3411 //==============================================================================
3414 extern __at(0x0399) __sfr IOCCF
;
3420 unsigned IOCCF0
: 1;
3421 unsigned IOCCF1
: 1;
3422 unsigned IOCCF2
: 1;
3423 unsigned IOCCF3
: 1;
3424 unsigned IOCCF4
: 1;
3425 unsigned IOCCF5
: 1;
3437 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
3439 #define _IOCCF0 0x01
3440 #define _IOCCF1 0x02
3441 #define _IOCCF2 0x04
3442 #define _IOCCF3 0x08
3443 #define _IOCCF4 0x10
3444 #define _IOCCF5 0x20
3446 //==============================================================================
3449 //==============================================================================
3452 extern __at(0x039A) __sfr CLKRCON
;
3458 unsigned CLKRDIV0
: 1;
3459 unsigned CLKRDIV1
: 1;
3460 unsigned CLKRDIV2
: 1;
3461 unsigned CLKRDC0
: 1;
3462 unsigned CLKRDC1
: 1;
3465 unsigned CLKREN
: 1;
3470 unsigned CLKRDIV
: 3;
3477 unsigned CLKRDC
: 2;
3482 extern __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits
;
3484 #define _CLKRDIV0 0x01
3485 #define _CLKRDIV1 0x02
3486 #define _CLKRDIV2 0x04
3487 #define _CLKRDC0 0x08
3488 #define _CLKRDC1 0x10
3489 #define _CLKREN 0x80
3491 //==============================================================================
3494 //==============================================================================
3497 extern __at(0x039C) __sfr MDCON
;
3505 unsigned MDOPOL
: 1;
3511 extern __at(0x039C) volatile __MDCONbits_t MDCONbits
;
3515 #define _MDOPOL 0x10
3518 //==============================================================================
3521 //==============================================================================
3524 extern __at(0x039D) __sfr MDSRC
;
3547 extern __at(0x039D) volatile __MDSRCbits_t MDSRCbits
;
3554 //==============================================================================
3557 //==============================================================================
3560 extern __at(0x039E) __sfr MDCARH
;
3571 unsigned MDCHSYNC
: 1;
3572 unsigned MDCHPOL
: 1;
3583 extern __at(0x039E) volatile __MDCARHbits_t MDCARHbits
;
3589 #define _MDCHSYNC 0x20
3590 #define _MDCHPOL 0x40
3592 //==============================================================================
3595 //==============================================================================
3598 extern __at(0x039F) __sfr MDCARL
;
3609 unsigned MDCLSYNC
: 1;
3610 unsigned MDCLPOL
: 1;
3621 extern __at(0x039F) volatile __MDCARLbits_t MDCARLbits
;
3627 #define _MDCLSYNC 0x20
3628 #define _MDCLPOL 0x40
3630 //==============================================================================
3633 //==============================================================================
3636 extern __at(0x040C) __sfr CCDNA
;
3640 unsigned CCDNA0
: 1;
3641 unsigned CCDNA1
: 1;
3642 unsigned CCDNA2
: 1;
3644 unsigned CCDNA4
: 1;
3645 unsigned CCDNA5
: 1;
3650 extern __at(0x040C) volatile __CCDNAbits_t CCDNAbits
;
3652 #define _CCDNA0 0x01
3653 #define _CCDNA1 0x02
3654 #define _CCDNA2 0x04
3655 #define _CCDNA4 0x10
3656 #define _CCDNA5 0x20
3658 //==============================================================================
3661 //==============================================================================
3664 extern __at(0x040E) __sfr CCDNC
;
3670 unsigned CCDNC0
: 1;
3671 unsigned CCDNC1
: 1;
3672 unsigned CCDNC2
: 1;
3673 unsigned CCDNC3
: 1;
3674 unsigned CCDNC4
: 1;
3675 unsigned CCDNC5
: 1;
3687 extern __at(0x040E) volatile __CCDNCbits_t CCDNCbits
;
3689 #define _CCDNC0 0x01
3690 #define _CCDNC1 0x02
3691 #define _CCDNC2 0x04
3692 #define _CCDNC3 0x08
3693 #define _CCDNC4 0x10
3694 #define _CCDNC5 0x20
3696 //==============================================================================
3699 //==============================================================================
3702 extern __at(0x041F) __sfr CCDCON
;
3725 extern __at(0x041F) volatile __CCDCONbits_t CCDCONbits
;
3731 //==============================================================================
3734 //==============================================================================
3737 extern __at(0x048C) __sfr CCDPA
;
3741 unsigned CCDPA0
: 1;
3742 unsigned CCDPA1
: 1;
3743 unsigned CCDPA2
: 1;
3745 unsigned CCDPA4
: 1;
3746 unsigned CCDPA5
: 1;
3751 extern __at(0x048C) volatile __CCDPAbits_t CCDPAbits
;
3753 #define _CCDPA0 0x01
3754 #define _CCDPA1 0x02
3755 #define _CCDPA2 0x04
3756 #define _CCDPA4 0x10
3757 #define _CCDPA5 0x20
3759 //==============================================================================
3762 //==============================================================================
3765 extern __at(0x048E) __sfr CCDPC
;
3771 unsigned CCDPC0
: 1;
3772 unsigned CCDPC1
: 1;
3773 unsigned CCDPC2
: 1;
3774 unsigned CCDPC3
: 1;
3775 unsigned CCDPC4
: 1;
3776 unsigned CCDPC5
: 1;
3788 extern __at(0x048E) volatile __CCDPCbits_t CCDPCbits
;
3790 #define _CCDPC0 0x01
3791 #define _CCDPC1 0x02
3792 #define _CCDPC2 0x04
3793 #define _CCDPC3 0x08
3794 #define _CCDPC4 0x10
3795 #define _CCDPC5 0x20
3797 //==============================================================================
3799 extern __at(0x0498) __sfr NCO1ACC
;
3800 extern __at(0x0498) __sfr NCO1ACCL
;
3801 extern __at(0x0499) __sfr NCO1ACCH
;
3802 extern __at(0x049A) __sfr NCO1ACCU
;
3803 extern __at(0x049B) __sfr NCO1INC
;
3804 extern __at(0x049B) __sfr NCO1INCL
;
3805 extern __at(0x049C) __sfr NCO1INCH
;
3806 extern __at(0x049D) __sfr NCO1INCU
;
3808 //==============================================================================
3811 extern __at(0x049E) __sfr NCO1CON
;
3825 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
3832 //==============================================================================
3834 extern __at(0x049F) __sfr NCO1CLK
;
3836 //==============================================================================
3839 extern __at(0x0617) __sfr PWM5DCL
;
3851 unsigned PWM5DCL0
: 1;
3852 unsigned PWM5DCL1
: 1;
3858 unsigned PWM5DCL
: 2;
3862 extern __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits
;
3864 #define _PWM5DCL0 0x40
3865 #define _PWM5DCL1 0x80
3867 //==============================================================================
3870 //==============================================================================
3873 extern __at(0x0618) __sfr PWM5DCH
;
3877 unsigned PWM5DCH0
: 1;
3878 unsigned PWM5DCH1
: 1;
3879 unsigned PWM5DCH2
: 1;
3880 unsigned PWM5DCH3
: 1;
3881 unsigned PWM5DCH4
: 1;
3882 unsigned PWM5DCH5
: 1;
3883 unsigned PWM5DCH6
: 1;
3884 unsigned PWM5DCH7
: 1;
3887 extern __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits
;
3889 #define _PWM5DCH0 0x01
3890 #define _PWM5DCH1 0x02
3891 #define _PWM5DCH2 0x04
3892 #define _PWM5DCH3 0x08
3893 #define _PWM5DCH4 0x10
3894 #define _PWM5DCH5 0x20
3895 #define _PWM5DCH6 0x40
3896 #define _PWM5DCH7 0x80
3898 //==============================================================================
3901 //==============================================================================
3904 extern __at(0x0619) __sfr PWM5CON
;
3912 unsigned PWM5POL
: 1;
3913 unsigned PWM5OUT
: 1;
3915 unsigned PWM5EN
: 1;
3918 extern __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits
;
3920 #define _PWM5POL 0x10
3921 #define _PWM5OUT 0x20
3922 #define _PWM5EN 0x80
3924 //==============================================================================
3927 //==============================================================================
3930 extern __at(0x0619) __sfr PWM5CON0
;
3938 unsigned PWM5POL
: 1;
3939 unsigned PWM5OUT
: 1;
3941 unsigned PWM5EN
: 1;
3944 extern __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits
;
3946 #define _PWM5CON0_PWM5POL 0x10
3947 #define _PWM5CON0_PWM5OUT 0x20
3948 #define _PWM5CON0_PWM5EN 0x80
3950 //==============================================================================
3953 //==============================================================================
3956 extern __at(0x061A) __sfr PWM6DCL
;
3968 unsigned PWM6DCL0
: 1;
3969 unsigned PWM6DCL1
: 1;
3975 unsigned PWM6DCL
: 2;
3979 extern __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits
;
3981 #define _PWM6DCL0 0x40
3982 #define _PWM6DCL1 0x80
3984 //==============================================================================
3987 //==============================================================================
3990 extern __at(0x061B) __sfr PWM6DCH
;
3994 unsigned PWM6DCH0
: 1;
3995 unsigned PWM6DCH1
: 1;
3996 unsigned PWM6DCH2
: 1;
3997 unsigned PWM6DCH3
: 1;
3998 unsigned PWM6DCH4
: 1;
3999 unsigned PWM6DCH5
: 1;
4000 unsigned PWM6DCH6
: 1;
4001 unsigned PWM6DCH7
: 1;
4004 extern __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits
;
4006 #define _PWM6DCH0 0x01
4007 #define _PWM6DCH1 0x02
4008 #define _PWM6DCH2 0x04
4009 #define _PWM6DCH3 0x08
4010 #define _PWM6DCH4 0x10
4011 #define _PWM6DCH5 0x20
4012 #define _PWM6DCH6 0x40
4013 #define _PWM6DCH7 0x80
4015 //==============================================================================
4018 //==============================================================================
4021 extern __at(0x061C) __sfr PWM6CON
;
4029 unsigned PWM6POL
: 1;
4030 unsigned PWM6OUT
: 1;
4032 unsigned PWM6EN
: 1;
4035 extern __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits
;
4037 #define _PWM6POL 0x10
4038 #define _PWM6OUT 0x20
4039 #define _PWM6EN 0x80
4041 //==============================================================================
4044 //==============================================================================
4047 extern __at(0x061C) __sfr PWM6CON0
;
4055 unsigned PWM6POL
: 1;
4056 unsigned PWM6OUT
: 1;
4058 unsigned PWM6EN
: 1;
4061 extern __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits
;
4063 #define _PWM6CON0_PWM6POL 0x10
4064 #define _PWM6CON0_PWM6OUT 0x20
4065 #define _PWM6CON0_PWM6EN 0x80
4067 //==============================================================================
4070 //==============================================================================
4073 extern __at(0x0691) __sfr CWG1CLKCON
;
4091 unsigned CWG1CS
: 1;
4100 } __CWG1CLKCONbits_t
;
4102 extern __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits
;
4105 #define _CWG1CS 0x01
4107 //==============================================================================
4110 //==============================================================================
4113 extern __at(0x0692) __sfr CWG1DAT
;
4119 unsigned CWG1DAT0
: 1;
4120 unsigned CWG1DAT1
: 1;
4121 unsigned CWG1DAT2
: 1;
4122 unsigned CWG1DAT3
: 1;
4131 unsigned CWG1DAT
: 4;
4136 extern __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits
;
4138 #define _CWG1DAT0 0x01
4139 #define _CWG1DAT1 0x02
4140 #define _CWG1DAT2 0x04
4141 #define _CWG1DAT3 0x08
4143 //==============================================================================
4146 //==============================================================================
4149 extern __at(0x0693) __sfr CWG1DBR
;
4167 unsigned CWG1DBR0
: 1;
4168 unsigned CWG1DBR1
: 1;
4169 unsigned CWG1DBR2
: 1;
4170 unsigned CWG1DBR3
: 1;
4171 unsigned CWG1DBR4
: 1;
4172 unsigned CWG1DBR5
: 1;
4179 unsigned CWG1DBR
: 6;
4190 extern __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits
;
4193 #define _CWG1DBR0 0x01
4195 #define _CWG1DBR1 0x02
4197 #define _CWG1DBR2 0x04
4199 #define _CWG1DBR3 0x08
4201 #define _CWG1DBR4 0x10
4203 #define _CWG1DBR5 0x20
4205 //==============================================================================
4208 //==============================================================================
4211 extern __at(0x0694) __sfr CWG1DBF
;
4229 unsigned CWG1DBF0
: 1;
4230 unsigned CWG1DBF1
: 1;
4231 unsigned CWG1DBF2
: 1;
4232 unsigned CWG1DBF3
: 1;
4233 unsigned CWG1DBF4
: 1;
4234 unsigned CWG1DBF5
: 1;
4241 unsigned CWG1DBF
: 6;
4252 extern __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits
;
4255 #define _CWG1DBF0 0x01
4257 #define _CWG1DBF1 0x02
4259 #define _CWG1DBF2 0x04
4261 #define _CWG1DBF3 0x08
4263 #define _CWG1DBF4 0x10
4265 #define _CWG1DBF5 0x20
4267 //==============================================================================
4270 //==============================================================================
4273 extern __at(0x0695) __sfr CWG1CON0
;
4291 unsigned CWG1MODE0
: 1;
4292 unsigned CWG1MODE1
: 1;
4293 unsigned CWG1MODE2
: 1;
4297 unsigned CWG1LD
: 1;
4310 unsigned CWG1EN
: 1;
4321 unsigned CWG1MODE
: 3;
4326 extern __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits
;
4328 #define _CWG1CON0_MODE0 0x01
4329 #define _CWG1CON0_CWG1MODE0 0x01
4330 #define _CWG1CON0_MODE1 0x02
4331 #define _CWG1CON0_CWG1MODE1 0x02
4332 #define _CWG1CON0_MODE2 0x04
4333 #define _CWG1CON0_CWG1MODE2 0x04
4334 #define _CWG1CON0_LD 0x40
4335 #define _CWG1CON0_CWG1LD 0x40
4336 #define _CWG1CON0_EN 0x80
4337 #define _CWG1CON0_G1EN 0x80
4338 #define _CWG1CON0_CWG1EN 0x80
4340 //==============================================================================
4343 //==============================================================================
4346 extern __at(0x0696) __sfr CWG1CON1
;
4364 unsigned CWG1POLA
: 1;
4365 unsigned CWG1POLB
: 1;
4366 unsigned CWG1POLC
: 1;
4367 unsigned CWG1POLD
: 1;
4369 unsigned CWG1IN
: 1;
4375 extern __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits
;
4378 #define _CWG1POLA 0x01
4380 #define _CWG1POLB 0x02
4382 #define _CWG1POLC 0x04
4384 #define _CWG1POLD 0x08
4386 #define _CWG1IN 0x20
4388 //==============================================================================
4391 //==============================================================================
4394 extern __at(0x0697) __sfr CWG1AS0
;
4407 unsigned SHUTDOWN
: 1;
4414 unsigned CWG1LSAC0
: 1;
4415 unsigned CWG1LSAC1
: 1;
4416 unsigned CWG1LSBD0
: 1;
4417 unsigned CWG1LSBD1
: 1;
4418 unsigned CWG1REN
: 1;
4419 unsigned CWG1SHUTDOWN
: 1;
4425 unsigned CWG1LSAC
: 2;
4439 unsigned CWG1LSBD
: 2;
4451 extern __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits
;
4454 #define _CWG1LSAC0 0x04
4456 #define _CWG1LSAC1 0x08
4458 #define _CWG1LSBD0 0x10
4460 #define _CWG1LSBD1 0x20
4462 #define _CWG1REN 0x40
4463 #define _SHUTDOWN 0x80
4464 #define _CWG1SHUTDOWN 0x80
4466 //==============================================================================
4469 //==============================================================================
4472 extern __at(0x0698) __sfr CWG1AS1
;
4486 extern __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits
;
4493 //==============================================================================
4496 //==============================================================================
4499 extern __at(0x0699) __sfr CWG1STR
;
4517 unsigned CWG1STRA
: 1;
4518 unsigned CWG1STRB
: 1;
4519 unsigned CWG1STRC
: 1;
4520 unsigned CWG1STRD
: 1;
4521 unsigned CWG1OVRA
: 1;
4522 unsigned CWG1OVRB
: 1;
4523 unsigned CWG1OVRC
: 1;
4524 unsigned CWG1OVRD
: 1;
4528 extern __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits
;
4531 #define _CWG1STRA 0x01
4533 #define _CWG1STRB 0x02
4535 #define _CWG1STRC 0x04
4537 #define _CWG1STRD 0x08
4539 #define _CWG1OVRA 0x10
4541 #define _CWG1OVRB 0x20
4543 #define _CWG1OVRC 0x40
4545 #define _CWG1OVRD 0x80
4547 //==============================================================================
4549 extern __at(0x0891) __sfr NVMADR
;
4551 //==============================================================================
4554 extern __at(0x0891) __sfr NVMADRL
;
4558 unsigned NVMADR0
: 1;
4559 unsigned NVMADR1
: 1;
4560 unsigned NVMADR2
: 1;
4561 unsigned NVMADR3
: 1;
4562 unsigned NVMADR4
: 1;
4563 unsigned NVMADR5
: 1;
4564 unsigned NVMADR6
: 1;
4565 unsigned NVMADR7
: 1;
4568 extern __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits
;
4570 #define _NVMADR0 0x01
4571 #define _NVMADR1 0x02
4572 #define _NVMADR2 0x04
4573 #define _NVMADR3 0x08
4574 #define _NVMADR4 0x10
4575 #define _NVMADR5 0x20
4576 #define _NVMADR6 0x40
4577 #define _NVMADR7 0x80
4579 //==============================================================================
4582 //==============================================================================
4585 extern __at(0x0892) __sfr NVMADRH
;
4589 unsigned NVMADR8
: 1;
4590 unsigned NVMADR9
: 1;
4591 unsigned NVMADR10
: 1;
4592 unsigned NVMADR11
: 1;
4593 unsigned NVMADR12
: 1;
4594 unsigned NVMADR13
: 1;
4595 unsigned NVMADR14
: 1;
4599 extern __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits
;
4601 #define _NVMADR8 0x01
4602 #define _NVMADR9 0x02
4603 #define _NVMADR10 0x04
4604 #define _NVMADR11 0x08
4605 #define _NVMADR12 0x10
4606 #define _NVMADR13 0x20
4607 #define _NVMADR14 0x40
4609 //==============================================================================
4611 extern __at(0x0893) __sfr NVMDAT
;
4613 //==============================================================================
4616 extern __at(0x0893) __sfr NVMDATL
;
4620 unsigned NVMDAT0
: 1;
4621 unsigned NVMDAT1
: 1;
4622 unsigned NVMDAT2
: 1;
4623 unsigned NVMDAT3
: 1;
4624 unsigned NVMDAT4
: 1;
4625 unsigned NVMDAT5
: 1;
4626 unsigned NVMDAT6
: 1;
4627 unsigned NVMDAT7
: 1;
4630 extern __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits
;
4632 #define _NVMDAT0 0x01
4633 #define _NVMDAT1 0x02
4634 #define _NVMDAT2 0x04
4635 #define _NVMDAT3 0x08
4636 #define _NVMDAT4 0x10
4637 #define _NVMDAT5 0x20
4638 #define _NVMDAT6 0x40
4639 #define _NVMDAT7 0x80
4641 //==============================================================================
4644 //==============================================================================
4647 extern __at(0x0894) __sfr NVMDATH
;
4651 unsigned NVMDAT8
: 1;
4652 unsigned NVMDAT9
: 1;
4653 unsigned NVMDAT10
: 1;
4654 unsigned NVMDAT11
: 1;
4655 unsigned NVMDAT12
: 1;
4656 unsigned NVMDAT13
: 1;
4661 extern __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits
;
4663 #define _NVMDAT8 0x01
4664 #define _NVMDAT9 0x02
4665 #define _NVMDAT10 0x04
4666 #define _NVMDAT11 0x08
4667 #define _NVMDAT12 0x10
4668 #define _NVMDAT13 0x20
4670 //==============================================================================
4673 //==============================================================================
4676 extern __at(0x0895) __sfr NVMCON1
;
4686 unsigned NVMREGS
: 1;
4690 extern __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits
;
4698 #define _NVMREGS 0x40
4700 //==============================================================================
4702 extern __at(0x0896) __sfr NVMCON2
;
4704 //==============================================================================
4707 extern __at(0x089B) __sfr PCON0
;
4711 unsigned NOT_BOR
: 1;
4712 unsigned NOT_POR
: 1;
4713 unsigned NOT_RI
: 1;
4714 unsigned NOT_RMCLR
: 1;
4715 unsigned NOT_RWDT
: 1;
4717 unsigned STKUNF
: 1;
4718 unsigned STKOVF
: 1;
4721 extern __at(0x089B) volatile __PCON0bits_t PCON0bits
;
4723 #define _NOT_BOR 0x01
4724 #define _NOT_POR 0x02
4725 #define _NOT_RI 0x04
4726 #define _NOT_RMCLR 0x08
4727 #define _NOT_RWDT 0x10
4728 #define _STKUNF 0x40
4729 #define _STKOVF 0x80
4731 //==============================================================================
4734 //==============================================================================
4737 extern __at(0x0911) __sfr PMD0
;
4742 unsigned CLKRMD
: 1;
4748 unsigned SYSCMD
: 1;
4751 extern __at(0x0911) volatile __PMD0bits_t PMD0bits
;
4754 #define _CLKRMD 0x02
4757 #define _SYSCMD 0x80
4759 //==============================================================================
4762 //==============================================================================
4765 extern __at(0x0912) __sfr PMD1
;
4769 unsigned TMR0MD
: 1;
4770 unsigned TMR1MD
: 1;
4771 unsigned TMR2MD
: 1;
4779 extern __at(0x0912) volatile __PMD1bits_t PMD1bits
;
4781 #define _TMR0MD 0x01
4782 #define _TMR1MD 0x02
4783 #define _TMR2MD 0x04
4786 //==============================================================================
4789 //==============================================================================
4792 extern __at(0x0913) __sfr PMD2
;
4797 unsigned CMP1MD
: 1;
4798 unsigned CMP2MD
: 1;
4806 extern __at(0x0913) volatile __PMD2bits_t PMD2bits
;
4808 #define _CMP1MD 0x02
4809 #define _CMP2MD 0x04
4813 //==============================================================================
4816 //==============================================================================
4819 extern __at(0x0914) __sfr PMD3
;
4823 unsigned CCP1MD
: 1;
4824 unsigned CCP2MD
: 1;
4827 unsigned PWM5MD
: 1;
4828 unsigned PWM6MD
: 1;
4829 unsigned CWG1MD
: 1;
4833 extern __at(0x0914) volatile __PMD3bits_t PMD3bits
;
4835 #define _CCP1MD 0x01
4836 #define _CCP2MD 0x02
4837 #define _PWM5MD 0x10
4838 #define _PWM6MD 0x20
4839 #define _CWG1MD 0x40
4841 //==============================================================================
4844 //==============================================================================
4847 extern __at(0x0915) __sfr PMD4
;
4852 unsigned MSSP1MD
: 1;
4856 unsigned UART1MD
: 1;
4861 extern __at(0x0915) volatile __PMD4bits_t PMD4bits
;
4863 #define _MSSP1MD 0x02
4864 #define _UART1MD 0x20
4866 //==============================================================================
4869 //==============================================================================
4872 extern __at(0x0916) __sfr PMD5
;
4877 unsigned CLC1MD
: 1;
4878 unsigned CLC2MD
: 1;
4886 extern __at(0x0916) volatile __PMD5bits_t PMD5bits
;
4889 #define _CLC1MD 0x02
4890 #define _CLC2MD 0x04
4892 //==============================================================================
4895 //==============================================================================
4898 extern __at(0x0918) __sfr CPUDOZE
;
4921 extern __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits
;
4931 //==============================================================================
4934 //==============================================================================
4937 extern __at(0x0919) __sfr OSCCON1
;
4967 extern __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits
;
4977 //==============================================================================
4980 //==============================================================================
4983 extern __at(0x091A) __sfr OSCCON2
;
5013 extern __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits
;
5023 //==============================================================================
5026 //==============================================================================
5029 extern __at(0x091B) __sfr OSCCON3
;
5038 unsigned SOSCBE
: 1;
5039 unsigned SOSCPWR
: 1;
5040 unsigned CSWHOLD
: 1;
5043 extern __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits
;
5047 #define _SOSCBE 0x20
5048 #define _SOSCPWR 0x40
5049 #define _CSWHOLD 0x80
5051 //==============================================================================
5054 //==============================================================================
5057 extern __at(0x091C) __sfr OSCSTAT1
;
5071 extern __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits
;
5080 //==============================================================================
5083 //==============================================================================
5086 extern __at(0x091D) __sfr OSCEN
;
5093 unsigned SOSCEN
: 1;
5097 unsigned EXTOEN
: 1;
5100 extern __at(0x091D) volatile __OSCENbits_t OSCENbits
;
5103 #define _SOSCEN 0x08
5106 #define _EXTOEN 0x80
5108 //==============================================================================
5111 //==============================================================================
5114 extern __at(0x091E) __sfr OSCTUNE
;
5120 unsigned HFTUN0
: 1;
5121 unsigned HFTUN1
: 1;
5122 unsigned HFTUN2
: 1;
5123 unsigned HFTUN3
: 1;
5124 unsigned HFTUN4
: 1;
5125 unsigned HFTUN5
: 1;
5137 extern __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits
;
5139 #define _HFTUN0 0x01
5140 #define _HFTUN1 0x02
5141 #define _HFTUN2 0x04
5142 #define _HFTUN3 0x08
5143 #define _HFTUN4 0x10
5144 #define _HFTUN5 0x20
5146 //==============================================================================
5149 //==============================================================================
5152 extern __at(0x091F) __sfr OSCFRQ
;
5158 unsigned HFFRQ0
: 1;
5159 unsigned HFFRQ1
: 1;
5160 unsigned HFFRQ2
: 1;
5161 unsigned HFFRQ3
: 1;
5175 extern __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits
;
5177 #define _HFFRQ0 0x01
5178 #define _HFFRQ1 0x02
5179 #define _HFFRQ2 0x04
5180 #define _HFFRQ3 0x08
5182 //==============================================================================
5185 //==============================================================================
5188 extern __at(0x0E0F) __sfr PPSLOCK
;
5192 unsigned PPSLOCKED
: 1;
5202 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
5204 #define _PPSLOCKED 0x01
5206 //==============================================================================
5209 //==============================================================================
5212 extern __at(0x0E10) __sfr INTPPS
;
5218 unsigned INTPPS0
: 1;
5219 unsigned INTPPS1
: 1;
5220 unsigned INTPPS2
: 1;
5221 unsigned INTPPS3
: 1;
5222 unsigned INTPPS4
: 1;
5230 unsigned INTPPS
: 5;
5235 extern __at(0x0E10) volatile __INTPPSbits_t INTPPSbits
;
5237 #define _INTPPS0 0x01
5238 #define _INTPPS1 0x02
5239 #define _INTPPS2 0x04
5240 #define _INTPPS3 0x08
5241 #define _INTPPS4 0x10
5243 //==============================================================================
5246 //==============================================================================
5249 extern __at(0x0E11) __sfr T0CKIPPS
;
5255 unsigned T0CKIPPS0
: 1;
5256 unsigned T0CKIPPS1
: 1;
5257 unsigned T0CKIPPS2
: 1;
5258 unsigned T0CKIPPS3
: 1;
5259 unsigned T0CKIPPS4
: 1;
5267 unsigned T0CKIPPS
: 5;
5272 extern __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits
;
5274 #define _T0CKIPPS0 0x01
5275 #define _T0CKIPPS1 0x02
5276 #define _T0CKIPPS2 0x04
5277 #define _T0CKIPPS3 0x08
5278 #define _T0CKIPPS4 0x10
5280 //==============================================================================
5283 //==============================================================================
5286 extern __at(0x0E12) __sfr T1CKIPPS
;
5292 unsigned T1CKIPPS0
: 1;
5293 unsigned T1CKIPPS1
: 1;
5294 unsigned T1CKIPPS2
: 1;
5295 unsigned T1CKIPPS3
: 1;
5296 unsigned T1CKIPPS4
: 1;
5304 unsigned T1CKIPPS
: 5;
5309 extern __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits
;
5311 #define _T1CKIPPS0 0x01
5312 #define _T1CKIPPS1 0x02
5313 #define _T1CKIPPS2 0x04
5314 #define _T1CKIPPS3 0x08
5315 #define _T1CKIPPS4 0x10
5317 //==============================================================================
5320 //==============================================================================
5323 extern __at(0x0E13) __sfr T1GPPS
;
5329 unsigned T1GPPS0
: 1;
5330 unsigned T1GPPS1
: 1;
5331 unsigned T1GPPS2
: 1;
5332 unsigned T1GPPS3
: 1;
5333 unsigned T1GPPS4
: 1;
5341 unsigned T1GPPS
: 5;
5346 extern __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits
;
5348 #define _T1GPPS0 0x01
5349 #define _T1GPPS1 0x02
5350 #define _T1GPPS2 0x04
5351 #define _T1GPPS3 0x08
5352 #define _T1GPPS4 0x10
5354 //==============================================================================
5357 //==============================================================================
5360 extern __at(0x0E14) __sfr CCP1PPS
;
5366 unsigned CCP1PPS0
: 1;
5367 unsigned CCP1PPS1
: 1;
5368 unsigned CCP1PPS2
: 1;
5369 unsigned CCP1PPS3
: 1;
5370 unsigned CCP1PPS4
: 1;
5378 unsigned CCP1PPS
: 5;
5383 extern __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits
;
5385 #define _CCP1PPS0 0x01
5386 #define _CCP1PPS1 0x02
5387 #define _CCP1PPS2 0x04
5388 #define _CCP1PPS3 0x08
5389 #define _CCP1PPS4 0x10
5391 //==============================================================================
5394 //==============================================================================
5397 extern __at(0x0E15) __sfr CCP2PPS
;
5403 unsigned CCP2PPS0
: 1;
5404 unsigned CCP2PPS1
: 1;
5405 unsigned CCP2PPS2
: 1;
5406 unsigned CCP2PPS3
: 1;
5407 unsigned CCP2PPS4
: 1;
5415 unsigned CCP2PPS
: 5;
5420 extern __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits
;
5422 #define _CCP2PPS0 0x01
5423 #define _CCP2PPS1 0x02
5424 #define _CCP2PPS2 0x04
5425 #define _CCP2PPS3 0x08
5426 #define _CCP2PPS4 0x10
5428 //==============================================================================
5431 //==============================================================================
5434 extern __at(0x0E18) __sfr CWG1PPS
;
5440 unsigned CWG1PPS0
: 1;
5441 unsigned CWG1PPS1
: 1;
5442 unsigned CWG1PPS2
: 1;
5443 unsigned CWG1PPS3
: 1;
5444 unsigned CWG1PPS4
: 1;
5452 unsigned CWG1PPS
: 5;
5457 extern __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits
;
5459 #define _CWG1PPS0 0x01
5460 #define _CWG1PPS1 0x02
5461 #define _CWG1PPS2 0x04
5462 #define _CWG1PPS3 0x08
5463 #define _CWG1PPS4 0x10
5465 //==============================================================================
5468 //==============================================================================
5471 extern __at(0x0E1A) __sfr MDCIN1PPS
;
5477 unsigned MDCIN1PPS0
: 1;
5478 unsigned MDCIN1PPS1
: 1;
5479 unsigned MDCIN1PPS2
: 1;
5480 unsigned MDCIN1PPS3
: 1;
5481 unsigned MDCIN1PPS4
: 1;
5489 unsigned MDCIN1PPS
: 5;
5492 } __MDCIN1PPSbits_t
;
5494 extern __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits
;
5496 #define _MDCIN1PPS0 0x01
5497 #define _MDCIN1PPS1 0x02
5498 #define _MDCIN1PPS2 0x04
5499 #define _MDCIN1PPS3 0x08
5500 #define _MDCIN1PPS4 0x10
5502 //==============================================================================
5505 //==============================================================================
5508 extern __at(0x0E1B) __sfr MDCIN2PPS
;
5514 unsigned MDCIN2PPS0
: 1;
5515 unsigned MDCIN2PPS1
: 1;
5516 unsigned MDCIN2PPS2
: 1;
5517 unsigned MDCIN2PPS3
: 1;
5518 unsigned MDCIN2PPS4
: 1;
5526 unsigned MDCIN2PPS
: 5;
5529 } __MDCIN2PPSbits_t
;
5531 extern __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits
;
5533 #define _MDCIN2PPS0 0x01
5534 #define _MDCIN2PPS1 0x02
5535 #define _MDCIN2PPS2 0x04
5536 #define _MDCIN2PPS3 0x08
5537 #define _MDCIN2PPS4 0x10
5539 //==============================================================================
5542 //==============================================================================
5545 extern __at(0x0E1C) __sfr MDMINPPS
;
5551 unsigned MDMINPPS0
: 1;
5552 unsigned MDMINPPS1
: 1;
5553 unsigned MDMINPPS2
: 1;
5554 unsigned MDMINPPS3
: 1;
5555 unsigned MDMINPPS4
: 1;
5563 unsigned MDMINPPS
: 5;
5568 extern __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits
;
5570 #define _MDMINPPS0 0x01
5571 #define _MDMINPPS1 0x02
5572 #define _MDMINPPS2 0x04
5573 #define _MDMINPPS3 0x08
5574 #define _MDMINPPS4 0x10
5576 //==============================================================================
5579 //==============================================================================
5582 extern __at(0x0E20) __sfr SSP1CLKPPS
;
5588 unsigned SSP1CLKPPS0
: 1;
5589 unsigned SSP1CLKPPS1
: 1;
5590 unsigned SSP1CLKPPS2
: 1;
5591 unsigned SSP1CLKPPS3
: 1;
5592 unsigned SSP1CLKPPS4
: 1;
5600 unsigned SSP1CLKPPS
: 5;
5603 } __SSP1CLKPPSbits_t
;
5605 extern __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits
;
5607 #define _SSP1CLKPPS0 0x01
5608 #define _SSP1CLKPPS1 0x02
5609 #define _SSP1CLKPPS2 0x04
5610 #define _SSP1CLKPPS3 0x08
5611 #define _SSP1CLKPPS4 0x10
5613 //==============================================================================
5616 //==============================================================================
5619 extern __at(0x0E21) __sfr SSP1DATPPS
;
5625 unsigned SSP1DATPPS0
: 1;
5626 unsigned SSP1DATPPS1
: 1;
5627 unsigned SSP1DATPPS2
: 1;
5628 unsigned SSP1DATPPS3
: 1;
5629 unsigned SSP1DATPPS4
: 1;
5637 unsigned SSP1DATPPS
: 5;
5640 } __SSP1DATPPSbits_t
;
5642 extern __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits
;
5644 #define _SSP1DATPPS0 0x01
5645 #define _SSP1DATPPS1 0x02
5646 #define _SSP1DATPPS2 0x04
5647 #define _SSP1DATPPS3 0x08
5648 #define _SSP1DATPPS4 0x10
5650 //==============================================================================
5653 //==============================================================================
5656 extern __at(0x0E22) __sfr SSP1SSPPS
;
5662 unsigned SSP1SSPPS0
: 1;
5663 unsigned SSP1SSPPS1
: 1;
5664 unsigned SSP1SSPPS2
: 1;
5665 unsigned SSP1SSPPS3
: 1;
5666 unsigned SSP1SSPPS4
: 1;
5674 unsigned SSP1SSPPS
: 5;
5677 } __SSP1SSPPSbits_t
;
5679 extern __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits
;
5681 #define _SSP1SSPPS0 0x01
5682 #define _SSP1SSPPS1 0x02
5683 #define _SSP1SSPPS2 0x04
5684 #define _SSP1SSPPS3 0x08
5685 #define _SSP1SSPPS4 0x10
5687 //==============================================================================
5690 //==============================================================================
5693 extern __at(0x0E24) __sfr RXPPS
;
5699 unsigned RXPPS0
: 1;
5700 unsigned RXPPS1
: 1;
5701 unsigned RXPPS2
: 1;
5702 unsigned RXPPS3
: 1;
5703 unsigned RXPPS4
: 1;
5716 extern __at(0x0E24) volatile __RXPPSbits_t RXPPSbits
;
5718 #define _RXPPS0 0x01
5719 #define _RXPPS1 0x02
5720 #define _RXPPS2 0x04
5721 #define _RXPPS3 0x08
5722 #define _RXPPS4 0x10
5724 //==============================================================================
5727 //==============================================================================
5730 extern __at(0x0E25) __sfr TXPPS
;
5736 unsigned TXPPS0
: 1;
5737 unsigned TXPPS1
: 1;
5738 unsigned TXPPS2
: 1;
5739 unsigned TXPPS3
: 1;
5740 unsigned TXPPS4
: 1;
5753 extern __at(0x0E25) volatile __TXPPSbits_t TXPPSbits
;
5755 #define _TXPPS0 0x01
5756 #define _TXPPS1 0x02
5757 #define _TXPPS2 0x04
5758 #define _TXPPS3 0x08
5759 #define _TXPPS4 0x10
5761 //==============================================================================
5764 //==============================================================================
5767 extern __at(0x0E28) __sfr CLCIN0PPS
;
5773 unsigned CLCIN0PPS0
: 1;
5774 unsigned CLCIN0PPS1
: 1;
5775 unsigned CLCIN0PPS2
: 1;
5776 unsigned CLCIN0PPS3
: 1;
5777 unsigned CLCIN0PPS4
: 1;
5785 unsigned CLCIN0PPS
: 5;
5788 } __CLCIN0PPSbits_t
;
5790 extern __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits
;
5792 #define _CLCIN0PPS0 0x01
5793 #define _CLCIN0PPS1 0x02
5794 #define _CLCIN0PPS2 0x04
5795 #define _CLCIN0PPS3 0x08
5796 #define _CLCIN0PPS4 0x10
5798 //==============================================================================
5801 //==============================================================================
5804 extern __at(0x0E29) __sfr CLCIN1PPS
;
5810 unsigned CLCIN1PPS0
: 1;
5811 unsigned CLCIN1PPS1
: 1;
5812 unsigned CLCIN1PPS2
: 1;
5813 unsigned CLCIN1PPS3
: 1;
5814 unsigned CLCIN1PPS4
: 1;
5822 unsigned CLCIN1PPS
: 5;
5825 } __CLCIN1PPSbits_t
;
5827 extern __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits
;
5829 #define _CLCIN1PPS0 0x01
5830 #define _CLCIN1PPS1 0x02
5831 #define _CLCIN1PPS2 0x04
5832 #define _CLCIN1PPS3 0x08
5833 #define _CLCIN1PPS4 0x10
5835 //==============================================================================
5838 //==============================================================================
5841 extern __at(0x0E2A) __sfr CLCIN2PPS
;
5847 unsigned CLCIN2PPS0
: 1;
5848 unsigned CLCIN2PPS1
: 1;
5849 unsigned CLCIN2PPS2
: 1;
5850 unsigned CLCIN2PPS3
: 1;
5851 unsigned CLCIN2PPS4
: 1;
5859 unsigned CLCIN2PPS
: 5;
5862 } __CLCIN2PPSbits_t
;
5864 extern __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits
;
5866 #define _CLCIN2PPS0 0x01
5867 #define _CLCIN2PPS1 0x02
5868 #define _CLCIN2PPS2 0x04
5869 #define _CLCIN2PPS3 0x08
5870 #define _CLCIN2PPS4 0x10
5872 //==============================================================================
5875 //==============================================================================
5878 extern __at(0x0E2B) __sfr CLCIN3PPS
;
5884 unsigned CLCIN3PPS0
: 1;
5885 unsigned CLCIN3PPS1
: 1;
5886 unsigned CLCIN3PPS2
: 1;
5887 unsigned CLCIN3PPS3
: 1;
5888 unsigned CLCIN3PPS4
: 1;
5896 unsigned CLCIN3PPS
: 5;
5899 } __CLCIN3PPSbits_t
;
5901 extern __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits
;
5903 #define _CLCIN3PPS0 0x01
5904 #define _CLCIN3PPS1 0x02
5905 #define _CLCIN3PPS2 0x04
5906 #define _CLCIN3PPS3 0x08
5907 #define _CLCIN3PPS4 0x10
5909 //==============================================================================
5912 //==============================================================================
5915 extern __at(0x0E90) __sfr RA0PPS
;
5921 unsigned RA0PPS0
: 1;
5922 unsigned RA0PPS1
: 1;
5923 unsigned RA0PPS2
: 1;
5924 unsigned RA0PPS3
: 1;
5925 unsigned RA0PPS4
: 1;
5933 unsigned RA0PPS
: 5;
5938 extern __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits
;
5940 #define _RA0PPS0 0x01
5941 #define _RA0PPS1 0x02
5942 #define _RA0PPS2 0x04
5943 #define _RA0PPS3 0x08
5944 #define _RA0PPS4 0x10
5946 //==============================================================================
5949 //==============================================================================
5952 extern __at(0x0E91) __sfr RA1PPS
;
5958 unsigned RA1PPS0
: 1;
5959 unsigned RA1PPS1
: 1;
5960 unsigned RA1PPS2
: 1;
5961 unsigned RA1PPS3
: 1;
5962 unsigned RA1PPS4
: 1;
5970 unsigned RA1PPS
: 5;
5975 extern __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits
;
5977 #define _RA1PPS0 0x01
5978 #define _RA1PPS1 0x02
5979 #define _RA1PPS2 0x04
5980 #define _RA1PPS3 0x08
5981 #define _RA1PPS4 0x10
5983 //==============================================================================
5986 //==============================================================================
5989 extern __at(0x0E92) __sfr RA2PPS
;
5995 unsigned RA2PPS0
: 1;
5996 unsigned RA2PPS1
: 1;
5997 unsigned RA2PPS2
: 1;
5998 unsigned RA2PPS3
: 1;
5999 unsigned RA2PPS4
: 1;
6007 unsigned RA2PPS
: 5;
6012 extern __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits
;
6014 #define _RA2PPS0 0x01
6015 #define _RA2PPS1 0x02
6016 #define _RA2PPS2 0x04
6017 #define _RA2PPS3 0x08
6018 #define _RA2PPS4 0x10
6020 //==============================================================================
6023 //==============================================================================
6026 extern __at(0x0E94) __sfr RA4PPS
;
6032 unsigned RA4PPS0
: 1;
6033 unsigned RA4PPS1
: 1;
6034 unsigned RA4PPS2
: 1;
6035 unsigned RA4PPS3
: 1;
6036 unsigned RA4PPS4
: 1;
6044 unsigned RA4PPS
: 5;
6049 extern __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits
;
6051 #define _RA4PPS0 0x01
6052 #define _RA4PPS1 0x02
6053 #define _RA4PPS2 0x04
6054 #define _RA4PPS3 0x08
6055 #define _RA4PPS4 0x10
6057 //==============================================================================
6060 //==============================================================================
6063 extern __at(0x0E95) __sfr RA5PPS
;
6069 unsigned RA5PPS0
: 1;
6070 unsigned RA5PPS1
: 1;
6071 unsigned RA5PPS2
: 1;
6072 unsigned RA5PPS3
: 1;
6073 unsigned RA5PPS4
: 1;
6081 unsigned RA5PPS
: 5;
6086 extern __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits
;
6088 #define _RA5PPS0 0x01
6089 #define _RA5PPS1 0x02
6090 #define _RA5PPS2 0x04
6091 #define _RA5PPS3 0x08
6092 #define _RA5PPS4 0x10
6094 //==============================================================================
6097 //==============================================================================
6100 extern __at(0x0EA0) __sfr RC0PPS
;
6106 unsigned RC0PPS0
: 1;
6107 unsigned RC0PPS1
: 1;
6108 unsigned RC0PPS2
: 1;
6109 unsigned RC0PPS3
: 1;
6110 unsigned RC0PPS4
: 1;
6118 unsigned RC0PPS
: 5;
6123 extern __at(0x0EA0) volatile __RC0PPSbits_t RC0PPSbits
;
6125 #define _RC0PPS0 0x01
6126 #define _RC0PPS1 0x02
6127 #define _RC0PPS2 0x04
6128 #define _RC0PPS3 0x08
6129 #define _RC0PPS4 0x10
6131 //==============================================================================
6134 //==============================================================================
6137 extern __at(0x0EA1) __sfr RC1PPS
;
6143 unsigned RC1PPS0
: 1;
6144 unsigned RC1PPS1
: 1;
6145 unsigned RC1PPS2
: 1;
6146 unsigned RC1PPS3
: 1;
6147 unsigned RC1PPS4
: 1;
6155 unsigned RC1PPS
: 5;
6160 extern __at(0x0EA1) volatile __RC1PPSbits_t RC1PPSbits
;
6162 #define _RC1PPS0 0x01
6163 #define _RC1PPS1 0x02
6164 #define _RC1PPS2 0x04
6165 #define _RC1PPS3 0x08
6166 #define _RC1PPS4 0x10
6168 //==============================================================================
6171 //==============================================================================
6174 extern __at(0x0EA2) __sfr RC2PPS
;
6180 unsigned RC2PPS0
: 1;
6181 unsigned RC2PPS1
: 1;
6182 unsigned RC2PPS2
: 1;
6183 unsigned RC2PPS3
: 1;
6184 unsigned RC2PPS4
: 1;
6192 unsigned RC2PPS
: 5;
6197 extern __at(0x0EA2) volatile __RC2PPSbits_t RC2PPSbits
;
6199 #define _RC2PPS0 0x01
6200 #define _RC2PPS1 0x02
6201 #define _RC2PPS2 0x04
6202 #define _RC2PPS3 0x08
6203 #define _RC2PPS4 0x10
6205 //==============================================================================
6208 //==============================================================================
6211 extern __at(0x0EA3) __sfr RC3PPS
;
6217 unsigned RC3PPS0
: 1;
6218 unsigned RC3PPS1
: 1;
6219 unsigned RC3PPS2
: 1;
6220 unsigned RC3PPS3
: 1;
6221 unsigned RC3PPS4
: 1;
6229 unsigned RC3PPS
: 5;
6234 extern __at(0x0EA3) volatile __RC3PPSbits_t RC3PPSbits
;
6236 #define _RC3PPS0 0x01
6237 #define _RC3PPS1 0x02
6238 #define _RC3PPS2 0x04
6239 #define _RC3PPS3 0x08
6240 #define _RC3PPS4 0x10
6242 //==============================================================================
6245 //==============================================================================
6248 extern __at(0x0EA4) __sfr RC4PPS
;
6254 unsigned RC4PPS0
: 1;
6255 unsigned RC4PPS1
: 1;
6256 unsigned RC4PPS2
: 1;
6257 unsigned RC4PPS3
: 1;
6258 unsigned RC4PPS4
: 1;
6266 unsigned RC4PPS
: 5;
6271 extern __at(0x0EA4) volatile __RC4PPSbits_t RC4PPSbits
;
6273 #define _RC4PPS0 0x01
6274 #define _RC4PPS1 0x02
6275 #define _RC4PPS2 0x04
6276 #define _RC4PPS3 0x08
6277 #define _RC4PPS4 0x10
6279 //==============================================================================
6282 //==============================================================================
6285 extern __at(0x0EA5) __sfr RC5PPS
;
6291 unsigned RC5PPS0
: 1;
6292 unsigned RC5PPS1
: 1;
6293 unsigned RC5PPS2
: 1;
6294 unsigned RC5PPS3
: 1;
6295 unsigned RC5PPS4
: 1;
6303 unsigned RC5PPS
: 5;
6308 extern __at(0x0EA5) volatile __RC5PPSbits_t RC5PPSbits
;
6310 #define _RC5PPS0 0x01
6311 #define _RC5PPS1 0x02
6312 #define _RC5PPS2 0x04
6313 #define _RC5PPS3 0x08
6314 #define _RC5PPS4 0x10
6316 //==============================================================================
6319 //==============================================================================
6322 extern __at(0x0F0F) __sfr CLCDATA
;
6326 unsigned MLC1OUT
: 1;
6327 unsigned MLC2OUT
: 1;
6336 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
6338 #define _MLC1OUT 0x01
6339 #define _MLC2OUT 0x02
6341 //==============================================================================
6344 //==============================================================================
6347 extern __at(0x0F10) __sfr CLC1CON
;
6353 unsigned LC1MODE0
: 1;
6354 unsigned LC1MODE1
: 1;
6355 unsigned LC1MODE2
: 1;
6356 unsigned LC1INTN
: 1;
6357 unsigned LC1INTP
: 1;
6358 unsigned LC1OUT
: 1;
6383 unsigned LC1MODE
: 3;
6388 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
6390 #define _LC1MODE0 0x01
6392 #define _LC1MODE1 0x02
6394 #define _LC1MODE2 0x04
6396 #define _LC1INTN 0x08
6398 #define _LC1INTP 0x10
6400 #define _LC1OUT 0x20
6405 //==============================================================================
6408 //==============================================================================
6411 extern __at(0x0F11) __sfr CLC1POL
;
6417 unsigned LC1G1POL
: 1;
6418 unsigned LC1G2POL
: 1;
6419 unsigned LC1G3POL
: 1;
6420 unsigned LC1G4POL
: 1;
6424 unsigned LC1POL
: 1;
6440 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
6442 #define _LC1G1POL 0x01
6444 #define _LC1G2POL 0x02
6446 #define _LC1G3POL 0x04
6448 #define _LC1G4POL 0x08
6450 #define _LC1POL 0x80
6453 //==============================================================================
6456 //==============================================================================
6459 extern __at(0x0F12) __sfr CLC1SEL0
;
6465 unsigned LC1D1S0
: 1;
6466 unsigned LC1D1S1
: 1;
6467 unsigned LC1D1S2
: 1;
6468 unsigned LC1D1S3
: 1;
6469 unsigned LC1D1S4
: 1;
6495 unsigned LC1D1S
: 5;
6500 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
6502 #define _LC1D1S0 0x01
6504 #define _LC1D1S1 0x02
6506 #define _LC1D1S2 0x04
6508 #define _LC1D1S3 0x08
6510 #define _LC1D1S4 0x10
6513 //==============================================================================
6516 //==============================================================================
6519 extern __at(0x0F13) __sfr CLC1SEL1
;
6525 unsigned LC1D2S0
: 1;
6526 unsigned LC1D2S1
: 1;
6527 unsigned LC1D2S2
: 1;
6528 unsigned LC1D2S3
: 1;
6529 unsigned LC1D2S4
: 1;
6549 unsigned LC1D2S
: 5;
6560 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
6562 #define _LC1D2S0 0x01
6564 #define _LC1D2S1 0x02
6566 #define _LC1D2S2 0x04
6568 #define _LC1D2S3 0x08
6570 #define _LC1D2S4 0x10
6573 //==============================================================================
6576 //==============================================================================
6579 extern __at(0x0F14) __sfr CLC1SEL2
;
6585 unsigned LC1D3S0
: 1;
6586 unsigned LC1D3S1
: 1;
6587 unsigned LC1D3S2
: 1;
6588 unsigned LC1D3S3
: 1;
6589 unsigned LC1D3S4
: 1;
6609 unsigned LC1D3S
: 5;
6620 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
6622 #define _LC1D3S0 0x01
6624 #define _LC1D3S1 0x02
6626 #define _LC1D3S2 0x04
6628 #define _LC1D3S3 0x08
6630 #define _LC1D3S4 0x10
6633 //==============================================================================
6636 //==============================================================================
6639 extern __at(0x0F15) __sfr CLC1SEL3
;
6645 unsigned LC1D4S0
: 1;
6646 unsigned LC1D4S1
: 1;
6647 unsigned LC1D4S2
: 1;
6648 unsigned LC1D4S3
: 1;
6649 unsigned LC1D4S4
: 1;
6675 unsigned LC1D4S
: 5;
6680 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
6682 #define _LC1D4S0 0x01
6684 #define _LC1D4S1 0x02
6686 #define _LC1D4S2 0x04
6688 #define _LC1D4S3 0x08
6690 #define _LC1D4S4 0x10
6693 //==============================================================================
6696 //==============================================================================
6699 extern __at(0x0F16) __sfr CLC1GLS0
;
6705 unsigned LC1G1D1N
: 1;
6706 unsigned LC1G1D1T
: 1;
6707 unsigned LC1G1D2N
: 1;
6708 unsigned LC1G1D2T
: 1;
6709 unsigned LC1G1D3N
: 1;
6710 unsigned LC1G1D3T
: 1;
6711 unsigned LC1G1D4N
: 1;
6712 unsigned LC1G1D4T
: 1;
6728 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
6730 #define _LC1G1D1N 0x01
6732 #define _LC1G1D1T 0x02
6734 #define _LC1G1D2N 0x04
6736 #define _LC1G1D2T 0x08
6738 #define _LC1G1D3N 0x10
6740 #define _LC1G1D3T 0x20
6742 #define _LC1G1D4N 0x40
6744 #define _LC1G1D4T 0x80
6747 //==============================================================================
6750 //==============================================================================
6753 extern __at(0x0F17) __sfr CLC1GLS1
;
6759 unsigned LC1G2D1N
: 1;
6760 unsigned LC1G2D1T
: 1;
6761 unsigned LC1G2D2N
: 1;
6762 unsigned LC1G2D2T
: 1;
6763 unsigned LC1G2D3N
: 1;
6764 unsigned LC1G2D3T
: 1;
6765 unsigned LC1G2D4N
: 1;
6766 unsigned LC1G2D4T
: 1;
6782 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
6784 #define _CLC1GLS1_LC1G2D1N 0x01
6785 #define _CLC1GLS1_D1N 0x01
6786 #define _CLC1GLS1_LC1G2D1T 0x02
6787 #define _CLC1GLS1_D1T 0x02
6788 #define _CLC1GLS1_LC1G2D2N 0x04
6789 #define _CLC1GLS1_D2N 0x04
6790 #define _CLC1GLS1_LC1G2D2T 0x08
6791 #define _CLC1GLS1_D2T 0x08
6792 #define _CLC1GLS1_LC1G2D3N 0x10
6793 #define _CLC1GLS1_D3N 0x10
6794 #define _CLC1GLS1_LC1G2D3T 0x20
6795 #define _CLC1GLS1_D3T 0x20
6796 #define _CLC1GLS1_LC1G2D4N 0x40
6797 #define _CLC1GLS1_D4N 0x40
6798 #define _CLC1GLS1_LC1G2D4T 0x80
6799 #define _CLC1GLS1_D4T 0x80
6801 //==============================================================================
6804 //==============================================================================
6807 extern __at(0x0F18) __sfr CLC1GLS2
;
6813 unsigned LC1G3D1N
: 1;
6814 unsigned LC1G3D1T
: 1;
6815 unsigned LC1G3D2N
: 1;
6816 unsigned LC1G3D2T
: 1;
6817 unsigned LC1G3D3N
: 1;
6818 unsigned LC1G3D3T
: 1;
6819 unsigned LC1G3D4N
: 1;
6820 unsigned LC1G3D4T
: 1;
6836 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
6838 #define _CLC1GLS2_LC1G3D1N 0x01
6839 #define _CLC1GLS2_D1N 0x01
6840 #define _CLC1GLS2_LC1G3D1T 0x02
6841 #define _CLC1GLS2_D1T 0x02
6842 #define _CLC1GLS2_LC1G3D2N 0x04
6843 #define _CLC1GLS2_D2N 0x04
6844 #define _CLC1GLS2_LC1G3D2T 0x08
6845 #define _CLC1GLS2_D2T 0x08
6846 #define _CLC1GLS2_LC1G3D3N 0x10
6847 #define _CLC1GLS2_D3N 0x10
6848 #define _CLC1GLS2_LC1G3D3T 0x20
6849 #define _CLC1GLS2_D3T 0x20
6850 #define _CLC1GLS2_LC1G3D4N 0x40
6851 #define _CLC1GLS2_D4N 0x40
6852 #define _CLC1GLS2_LC1G3D4T 0x80
6853 #define _CLC1GLS2_D4T 0x80
6855 //==============================================================================
6858 //==============================================================================
6861 extern __at(0x0F19) __sfr CLC1GLS3
;
6867 unsigned LC1G4D1N
: 1;
6868 unsigned LC1G4D1T
: 1;
6869 unsigned LC1G4D2N
: 1;
6870 unsigned LC1G4D2T
: 1;
6871 unsigned LC1G4D3N
: 1;
6872 unsigned LC1G4D3T
: 1;
6873 unsigned LC1G4D4N
: 1;
6874 unsigned LC1G4D4T
: 1;
6890 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
6892 #define _LC1G4D1N 0x01
6894 #define _LC1G4D1T 0x02
6896 #define _LC1G4D2N 0x04
6898 #define _LC1G4D2T 0x08
6900 #define _LC1G4D3N 0x10
6902 #define _LC1G4D3T 0x20
6904 #define _LC1G4D4N 0x40
6906 #define _LC1G4D4T 0x80
6909 //==============================================================================
6912 //==============================================================================
6915 extern __at(0x0F1A) __sfr CLC2CON
;
6921 unsigned LC2MODE0
: 1;
6922 unsigned LC2MODE1
: 1;
6923 unsigned LC2MODE2
: 1;
6924 unsigned LC2INTN
: 1;
6925 unsigned LC2INTP
: 1;
6926 unsigned LC2OUT
: 1;
6951 unsigned LC2MODE
: 3;
6956 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
6958 #define _CLC2CON_LC2MODE0 0x01
6959 #define _CLC2CON_MODE0 0x01
6960 #define _CLC2CON_LC2MODE1 0x02
6961 #define _CLC2CON_MODE1 0x02
6962 #define _CLC2CON_LC2MODE2 0x04
6963 #define _CLC2CON_MODE2 0x04
6964 #define _CLC2CON_LC2INTN 0x08
6965 #define _CLC2CON_INTN 0x08
6966 #define _CLC2CON_LC2INTP 0x10
6967 #define _CLC2CON_INTP 0x10
6968 #define _CLC2CON_LC2OUT 0x20
6969 #define _CLC2CON_OUT 0x20
6970 #define _CLC2CON_LC2EN 0x80
6971 #define _CLC2CON_EN 0x80
6973 //==============================================================================
6976 //==============================================================================
6979 extern __at(0x0F1B) __sfr CLC2POL
;
6985 unsigned LC2G1POL
: 1;
6986 unsigned LC2G2POL
: 1;
6987 unsigned LC2G3POL
: 1;
6988 unsigned LC2G4POL
: 1;
6992 unsigned LC2POL
: 1;
7008 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
7010 #define _CLC2POL_LC2G1POL 0x01
7011 #define _CLC2POL_G1POL 0x01
7012 #define _CLC2POL_LC2G2POL 0x02
7013 #define _CLC2POL_G2POL 0x02
7014 #define _CLC2POL_LC2G3POL 0x04
7015 #define _CLC2POL_G3POL 0x04
7016 #define _CLC2POL_LC2G4POL 0x08
7017 #define _CLC2POL_G4POL 0x08
7018 #define _CLC2POL_LC2POL 0x80
7019 #define _CLC2POL_POL 0x80
7021 //==============================================================================
7024 //==============================================================================
7027 extern __at(0x0F1C) __sfr CLC2SEL0
;
7033 unsigned LC2D1S0
: 1;
7034 unsigned LC2D1S1
: 1;
7035 unsigned LC2D1S2
: 1;
7036 unsigned LC2D1S3
: 1;
7037 unsigned LC2D1S4
: 1;
7057 unsigned LC2D1S
: 5;
7068 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
7070 #define _CLC2SEL0_LC2D1S0 0x01
7071 #define _CLC2SEL0_D1S0 0x01
7072 #define _CLC2SEL0_LC2D1S1 0x02
7073 #define _CLC2SEL0_D1S1 0x02
7074 #define _CLC2SEL0_LC2D1S2 0x04
7075 #define _CLC2SEL0_D1S2 0x04
7076 #define _CLC2SEL0_LC2D1S3 0x08
7077 #define _CLC2SEL0_D1S3 0x08
7078 #define _CLC2SEL0_LC2D1S4 0x10
7079 #define _CLC2SEL0_D1S4 0x10
7081 //==============================================================================
7084 //==============================================================================
7087 extern __at(0x0F1D) __sfr CLC2SEL1
;
7093 unsigned LC2D2S0
: 1;
7094 unsigned LC2D2S1
: 1;
7095 unsigned LC2D2S2
: 1;
7096 unsigned LC2D2S3
: 1;
7097 unsigned LC2D2S4
: 1;
7117 unsigned LC2D2S
: 5;
7128 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
7130 #define _CLC2SEL1_LC2D2S0 0x01
7131 #define _CLC2SEL1_D2S0 0x01
7132 #define _CLC2SEL1_LC2D2S1 0x02
7133 #define _CLC2SEL1_D2S1 0x02
7134 #define _CLC2SEL1_LC2D2S2 0x04
7135 #define _CLC2SEL1_D2S2 0x04
7136 #define _CLC2SEL1_LC2D2S3 0x08
7137 #define _CLC2SEL1_D2S3 0x08
7138 #define _CLC2SEL1_LC2D2S4 0x10
7139 #define _CLC2SEL1_D2S4 0x10
7141 //==============================================================================
7144 //==============================================================================
7147 extern __at(0x0F1E) __sfr CLC2SEL2
;
7153 unsigned LC2D3S0
: 1;
7154 unsigned LC2D3S1
: 1;
7155 unsigned LC2D3S2
: 1;
7156 unsigned LC2D3S3
: 1;
7157 unsigned LC2D3S4
: 1;
7177 unsigned LC2D3S
: 5;
7188 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
7190 #define _CLC2SEL2_LC2D3S0 0x01
7191 #define _CLC2SEL2_D3S0 0x01
7192 #define _CLC2SEL2_LC2D3S1 0x02
7193 #define _CLC2SEL2_D3S1 0x02
7194 #define _CLC2SEL2_LC2D3S2 0x04
7195 #define _CLC2SEL2_D3S2 0x04
7196 #define _CLC2SEL2_LC2D3S3 0x08
7197 #define _CLC2SEL2_D3S3 0x08
7198 #define _CLC2SEL2_LC2D3S4 0x10
7199 #define _CLC2SEL2_D3S4 0x10
7201 //==============================================================================
7204 //==============================================================================
7207 extern __at(0x0F1F) __sfr CLC2SEL3
;
7213 unsigned LC2D4S0
: 1;
7214 unsigned LC2D4S1
: 1;
7215 unsigned LC2D4S2
: 1;
7216 unsigned LC2D4S3
: 1;
7217 unsigned LC2D4S4
: 1;
7237 unsigned LC2D4S
: 5;
7248 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
7250 #define _CLC2SEL3_LC2D4S0 0x01
7251 #define _CLC2SEL3_D4S0 0x01
7252 #define _CLC2SEL3_LC2D4S1 0x02
7253 #define _CLC2SEL3_D4S1 0x02
7254 #define _CLC2SEL3_LC2D4S2 0x04
7255 #define _CLC2SEL3_D4S2 0x04
7256 #define _CLC2SEL3_LC2D4S3 0x08
7257 #define _CLC2SEL3_D4S3 0x08
7258 #define _CLC2SEL3_LC2D4S4 0x10
7259 #define _CLC2SEL3_D4S4 0x10
7261 //==============================================================================
7264 //==============================================================================
7267 extern __at(0x0F20) __sfr CLC2GLS0
;
7273 unsigned LC2G1D1N
: 1;
7274 unsigned LC2G1D1T
: 1;
7275 unsigned LC2G1D2N
: 1;
7276 unsigned LC2G1D2T
: 1;
7277 unsigned LC2G1D3N
: 1;
7278 unsigned LC2G1D3T
: 1;
7279 unsigned LC2G1D4N
: 1;
7280 unsigned LC2G1D4T
: 1;
7296 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
7298 #define _CLC2GLS0_LC2G1D1N 0x01
7299 #define _CLC2GLS0_D1N 0x01
7300 #define _CLC2GLS0_LC2G1D1T 0x02
7301 #define _CLC2GLS0_D1T 0x02
7302 #define _CLC2GLS0_LC2G1D2N 0x04
7303 #define _CLC2GLS0_D2N 0x04
7304 #define _CLC2GLS0_LC2G1D2T 0x08
7305 #define _CLC2GLS0_D2T 0x08
7306 #define _CLC2GLS0_LC2G1D3N 0x10
7307 #define _CLC2GLS0_D3N 0x10
7308 #define _CLC2GLS0_LC2G1D3T 0x20
7309 #define _CLC2GLS0_D3T 0x20
7310 #define _CLC2GLS0_LC2G1D4N 0x40
7311 #define _CLC2GLS0_D4N 0x40
7312 #define _CLC2GLS0_LC2G1D4T 0x80
7313 #define _CLC2GLS0_D4T 0x80
7315 //==============================================================================
7318 //==============================================================================
7321 extern __at(0x0F21) __sfr CLC2GLS1
;
7327 unsigned LC2G2D1N
: 1;
7328 unsigned LC2G2D1T
: 1;
7329 unsigned LC2G2D2N
: 1;
7330 unsigned LC2G2D2T
: 1;
7331 unsigned LC2G2D3N
: 1;
7332 unsigned LC2G2D3T
: 1;
7333 unsigned LC2G2D4N
: 1;
7334 unsigned LC2G2D4T
: 1;
7350 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
7352 #define _CLC2GLS1_LC2G2D1N 0x01
7353 #define _CLC2GLS1_D1N 0x01
7354 #define _CLC2GLS1_LC2G2D1T 0x02
7355 #define _CLC2GLS1_D1T 0x02
7356 #define _CLC2GLS1_LC2G2D2N 0x04
7357 #define _CLC2GLS1_D2N 0x04
7358 #define _CLC2GLS1_LC2G2D2T 0x08
7359 #define _CLC2GLS1_D2T 0x08
7360 #define _CLC2GLS1_LC2G2D3N 0x10
7361 #define _CLC2GLS1_D3N 0x10
7362 #define _CLC2GLS1_LC2G2D3T 0x20
7363 #define _CLC2GLS1_D3T 0x20
7364 #define _CLC2GLS1_LC2G2D4N 0x40
7365 #define _CLC2GLS1_D4N 0x40
7366 #define _CLC2GLS1_LC2G2D4T 0x80
7367 #define _CLC2GLS1_D4T 0x80
7369 //==============================================================================
7372 //==============================================================================
7375 extern __at(0x0F22) __sfr CLC2GLS2
;
7381 unsigned LC2G3D1N
: 1;
7382 unsigned LC2G3D1T
: 1;
7383 unsigned LC2G3D2N
: 1;
7384 unsigned LC2G3D2T
: 1;
7385 unsigned LC2G3D3N
: 1;
7386 unsigned LC2G3D3T
: 1;
7387 unsigned LC2G3D4N
: 1;
7388 unsigned LC2G3D4T
: 1;
7404 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
7406 #define _CLC2GLS2_LC2G3D1N 0x01
7407 #define _CLC2GLS2_D1N 0x01
7408 #define _CLC2GLS2_LC2G3D1T 0x02
7409 #define _CLC2GLS2_D1T 0x02
7410 #define _CLC2GLS2_LC2G3D2N 0x04
7411 #define _CLC2GLS2_D2N 0x04
7412 #define _CLC2GLS2_LC2G3D2T 0x08
7413 #define _CLC2GLS2_D2T 0x08
7414 #define _CLC2GLS2_LC2G3D3N 0x10
7415 #define _CLC2GLS2_D3N 0x10
7416 #define _CLC2GLS2_LC2G3D3T 0x20
7417 #define _CLC2GLS2_D3T 0x20
7418 #define _CLC2GLS2_LC2G3D4N 0x40
7419 #define _CLC2GLS2_D4N 0x40
7420 #define _CLC2GLS2_LC2G3D4T 0x80
7421 #define _CLC2GLS2_D4T 0x80
7423 //==============================================================================
7426 //==============================================================================
7429 extern __at(0x0F23) __sfr CLC2GLS3
;
7435 unsigned LC2G4D1N
: 1;
7436 unsigned LC2G4D1T
: 1;
7437 unsigned LC2G4D2N
: 1;
7438 unsigned LC2G4D2T
: 1;
7439 unsigned LC2G4D3N
: 1;
7440 unsigned LC2G4D3T
: 1;
7441 unsigned LC2G4D4N
: 1;
7442 unsigned LC2G4D4T
: 1;
7458 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
7460 #define _CLC2GLS3_LC2G4D1N 0x01
7461 #define _CLC2GLS3_G4D1N 0x01
7462 #define _CLC2GLS3_LC2G4D1T 0x02
7463 #define _CLC2GLS3_G4D1T 0x02
7464 #define _CLC2GLS3_LC2G4D2N 0x04
7465 #define _CLC2GLS3_G4D2N 0x04
7466 #define _CLC2GLS3_LC2G4D2T 0x08
7467 #define _CLC2GLS3_G4D2T 0x08
7468 #define _CLC2GLS3_LC2G4D3N 0x10
7469 #define _CLC2GLS3_G4D3N 0x10
7470 #define _CLC2GLS3_LC2G4D3T 0x20
7471 #define _CLC2GLS3_G4D3T 0x20
7472 #define _CLC2GLS3_LC2G4D4N 0x40
7473 #define _CLC2GLS3_G4D4N 0x40
7474 #define _CLC2GLS3_LC2G4D4T 0x80
7475 #define _CLC2GLS3_G4D4T 0x80
7477 //==============================================================================
7480 //==============================================================================
7483 extern __at(0x0FE4) __sfr STATUS_SHAD
;
7487 unsigned C_SHAD
: 1;
7488 unsigned DC_SHAD
: 1;
7489 unsigned Z_SHAD
: 1;
7495 } __STATUS_SHADbits_t
;
7497 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
7499 #define _C_SHAD 0x01
7500 #define _DC_SHAD 0x02
7501 #define _Z_SHAD 0x04
7503 //==============================================================================
7505 extern __at(0x0FE5) __sfr WREG_SHAD
;
7506 extern __at(0x0FE6) __sfr BSR_SHAD
;
7507 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
7508 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
7509 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
7510 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
7511 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
7512 extern __at(0x0FED) __sfr STKPTR
;
7513 extern __at(0x0FEE) __sfr TOSL
;
7514 extern __at(0x0FEF) __sfr TOSH
;
7516 //==============================================================================
7518 // Configuration Bits
7520 //==============================================================================
7522 #define _CONFIG1 0x8007
7523 #define _CONFIG2 0x8008
7524 #define _CONFIG3 0x8009
7525 #define _CONFIG4 0x800A
7527 //----------------------------- CONFIG1 Options -------------------------------
7529 #define _FEXTOSC_LP 0x3FF8 // LP (crystal oscillator) optimized for 32.768 kHz.
7530 #define _FEXTOSC_XT 0x3FF9 // XT (crystal oscillator) from 100 kHz to 4 MHz.
7531 #define _FEXTOSC_HS 0x3FFA // HS (crystal oscillator) above 4 MHz.
7532 #define _FEXTOSC_OFF 0x3FFC // Oscillator not enabled.
7533 #define _FEXTOSC_ECL 0x3FFD // EC (external clock) below 100 kHz.
7534 #define _FEXTOSC_ECM 0x3FFE // EC (external clock) for 100 kHz to 8 MHz.
7535 #define _FEXTOSC_ECH 0x3FFF // EC (external clock) above 8 MHz.
7536 #define _RSTOSC_HFINT32 0x3F8F // HFINTOSC with 2x PLL (32MHz).
7537 #define _RSTOSC_EXT4X 0x3F9F // EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
7538 #define _RSTOSC_SOSC 0x3FBF // SOSC (31kHz).
7539 #define _RSTOSC_LFINT 0x3FCF // LFINTOSC (31kHz).
7540 #define _RSTOSC_HFINT1 0x3FEF // HFINTOSC (1MHz).
7541 #define _RSTOSC_EXT1X 0x3FFF // EXTOSC operating per FEXTOSC bits.
7542 #define _CLKOUTEN_ON 0x3EFF // CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
7543 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled; I/O or oscillator function on OSC2.
7544 #define _CSWEN_OFF 0x37FF // The NOSC and NDIV bits cannot be changed by user software.
7545 #define _CSWEN_ON 0x3FFF // Writing to NOSC and NDIV is allowed.
7546 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
7547 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
7549 //----------------------------- CONFIG2 Options -------------------------------
7551 #define _MCLRE_OFF 0x3FFE // MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
7552 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR; Weak pull-up enabled.
7553 #define _PWRTE_ON 0x3FFD // PWRT enabled.
7554 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
7555 #define _WDTE_OFF 0x3FF3 // WDT disabled; SWDTEN is ignored.
7556 #define _WDTE_SWDTEN 0x3FF7 // WDT controlled by the SWDTEN bit in the WDTCON register.
7557 #define _WDTE_SLEEP 0x3FFB // WDT enabled while running and disabled in SLEEP/IDLE; SWDTEN is ignored.
7558 #define _WDTE_ON 0x3FFF // WDT enabled, SWDTEN is ignored.
7559 #define _LPBOREN_ON 0x3FDF // ULPBOR enabled.
7560 #define _LPBOREN_OFF 0x3FFF // ULPBOR disabled.
7561 #define _BOREN_OFF 0x3F3F // Brown-out Reset disabled.
7562 #define _BOREN_SBOREN 0x3F7F // Brown-out Reset enabled according to SBOREN.
7563 #define _BOREN_SLEEP 0x3FBF // Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
7564 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled, SBOREN bit ignored.
7565 #define _BORV_HIGH 0x3DFF // Brown-out voltage (Vbor) set to 2.7V.
7566 #define _BORV_LOW 0x3FFF // Brown-out voltage (Vbor) set to 2.45V.
7567 #define _PPS1WAY_OFF 0x37FF // The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
7568 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
7569 #define _STVREN_OFF 0x2FFF // Stack Overflow or Underflow will not cause a Reset.
7570 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
7571 #define _DEBUG_ON 0x1FFF // Background debugger enabled.
7572 #define _DEBUG_OFF 0x3FFF // Background debugger disabled.
7574 //----------------------------- CONFIG3 Options -------------------------------
7576 #define _WRT_ALL 0x3FFC // 0000h to 07FFh write protected, no addresses may be modified.
7577 #define _WRT_HALF 0x3FFD // 0000h to 03FFh write-protected, 0400h to 07FFh may be modified.
7578 #define _WRT_BOOT 0x3FFE // 0000h to 01FFh write-protected, 0200h to 07FFh may be modified.
7579 #define _WRT_OFF 0x3FFF // Write protection off.
7580 #define _LVP_OFF 0x1FFF // High Voltage on MCLR/VPP must be used for programming.
7581 #define _LVP_ON 0x3FFF // Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
7583 //----------------------------- CONFIG4 Options -------------------------------
7585 #define _CP_ON 0x3FFE // User NVM code protection enabled.
7586 #define _CP_OFF 0x3FFF // User NVM code protection disabled.
7587 #define _CPD_ON 0x3FFD // Data NVM code protection enabled.
7588 #define _CPD_OFF 0x3FFF // Data NVM code protection disabled.
7590 //==============================================================================
7592 #define _DEVID1 0x8006
7594 #define _IDLOC0 0x8000
7595 #define _IDLOC1 0x8001
7596 #define _IDLOC2 0x8002
7597 #define _IDLOC3 0x8003
7599 //==============================================================================
7601 #ifndef NO_BIT_DEFINES
7603 #define ADACT0 ADACTbits.ADACT0 // bit 0
7604 #define ADACT1 ADACTbits.ADACT1 // bit 1
7605 #define ADACT2 ADACTbits.ADACT2 // bit 2
7606 #define ADACT3 ADACTbits.ADACT3 // bit 3
7608 #define ADON ADCON0bits.ADON // bit 0
7609 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
7610 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
7611 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
7612 #define CHS0 ADCON0bits.CHS0 // bit 2
7613 #define CHS1 ADCON0bits.CHS1 // bit 3
7614 #define CHS2 ADCON0bits.CHS2 // bit 4
7615 #define CHS3 ADCON0bits.CHS3 // bit 5
7616 #define CHS4 ADCON0bits.CHS4 // bit 6
7617 #define CHS5 ADCON0bits.CHS5 // bit 7
7619 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
7620 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
7621 #define ADNREF ADCON1bits.ADNREF // bit 2
7622 #define ADCS0 ADCON1bits.ADCS0 // bit 4
7623 #define ADCS1 ADCON1bits.ADCS1 // bit 5
7624 #define ADCS2 ADCON1bits.ADCS2 // bit 6
7625 #define ADFM ADCON1bits.ADFM // bit 7
7627 #define ANSA0 ANSELAbits.ANSA0 // bit 0
7628 #define ANSA1 ANSELAbits.ANSA1 // bit 1
7629 #define ANSA2 ANSELAbits.ANSA2 // bit 2
7630 #define ANSA4 ANSELAbits.ANSA4 // bit 4
7631 #define ANSA5 ANSELAbits.ANSA5 // bit 5
7633 #define ANSC0 ANSELCbits.ANSC0 // bit 0
7634 #define ANSC1 ANSELCbits.ANSC1 // bit 1
7635 #define ANSC2 ANSELCbits.ANSC2 // bit 2
7636 #define ANSC3 ANSELCbits.ANSC3 // bit 3
7637 #define ANSC4 ANSELCbits.ANSC4 // bit 4
7638 #define ANSC5 ANSELCbits.ANSC5 // bit 5
7640 #define ABDEN BAUD1CONbits.ABDEN // bit 0
7641 #define WUE BAUD1CONbits.WUE // bit 1
7642 #define BRG16 BAUD1CONbits.BRG16 // bit 3
7643 #define SCKP BAUD1CONbits.SCKP // bit 4
7644 #define RCIDL BAUD1CONbits.RCIDL // bit 6
7645 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
7647 #define BORRDY BORCONbits.BORRDY // bit 0
7648 #define SBOREN BORCONbits.SBOREN // bit 7
7650 #define BSR0 BSRbits.BSR0 // bit 0
7651 #define BSR1 BSRbits.BSR1 // bit 1
7652 #define BSR2 BSRbits.BSR2 // bit 2
7653 #define BSR3 BSRbits.BSR3 // bit 3
7654 #define BSR4 BSRbits.BSR4 // bit 4
7656 #define CCDS0 CCDCONbits.CCDS0 // bit 0
7657 #define CCDS1 CCDCONbits.CCDS1 // bit 1
7658 #define CCDEN CCDCONbits.CCDEN // bit 7
7660 #define CCDNA0 CCDNAbits.CCDNA0 // bit 0
7661 #define CCDNA1 CCDNAbits.CCDNA1 // bit 1
7662 #define CCDNA2 CCDNAbits.CCDNA2 // bit 2
7663 #define CCDNA4 CCDNAbits.CCDNA4 // bit 4
7664 #define CCDNA5 CCDNAbits.CCDNA5 // bit 5
7666 #define CCDNC0 CCDNCbits.CCDNC0 // bit 0
7667 #define CCDNC1 CCDNCbits.CCDNC1 // bit 1
7668 #define CCDNC2 CCDNCbits.CCDNC2 // bit 2
7669 #define CCDNC3 CCDNCbits.CCDNC3 // bit 3
7670 #define CCDNC4 CCDNCbits.CCDNC4 // bit 4
7671 #define CCDNC5 CCDNCbits.CCDNC5 // bit 5
7673 #define CCDPA0 CCDPAbits.CCDPA0 // bit 0
7674 #define CCDPA1 CCDPAbits.CCDPA1 // bit 1
7675 #define CCDPA2 CCDPAbits.CCDPA2 // bit 2
7676 #define CCDPA4 CCDPAbits.CCDPA4 // bit 4
7677 #define CCDPA5 CCDPAbits.CCDPA5 // bit 5
7679 #define CCDPC0 CCDPCbits.CCDPC0 // bit 0
7680 #define CCDPC1 CCDPCbits.CCDPC1 // bit 1
7681 #define CCDPC2 CCDPCbits.CCDPC2 // bit 2
7682 #define CCDPC3 CCDPCbits.CCDPC3 // bit 3
7683 #define CCDPC4 CCDPCbits.CCDPC4 // bit 4
7684 #define CCDPC5 CCDPCbits.CCDPC5 // bit 5
7686 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0
7687 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1
7688 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2
7690 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0
7691 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1
7692 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2
7693 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3
7694 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4
7695 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5
7696 #define CCP1EN CCP1CONbits.CCP1EN // bit 7
7698 #define CCP1PPS0 CCP1PPSbits.CCP1PPS0 // bit 0
7699 #define CCP1PPS1 CCP1PPSbits.CCP1PPS1 // bit 1
7700 #define CCP1PPS2 CCP1PPSbits.CCP1PPS2 // bit 2
7701 #define CCP1PPS3 CCP1PPSbits.CCP1PPS3 // bit 3
7702 #define CCP1PPS4 CCP1PPSbits.CCP1PPS4 // bit 4
7704 #define CCP2CTS0 CCP2CAPbits.CCP2CTS0 // bit 0
7705 #define CCP2CTS1 CCP2CAPbits.CCP2CTS1 // bit 1
7706 #define CCP2CTS2 CCP2CAPbits.CCP2CTS2 // bit 2
7708 #define CCP2MODE0 CCP2CONbits.CCP2MODE0 // bit 0
7709 #define CCP2MODE1 CCP2CONbits.CCP2MODE1 // bit 1
7710 #define CCP2MODE2 CCP2CONbits.CCP2MODE2 // bit 2
7711 #define CCP2MODE3 CCP2CONbits.CCP2MODE3 // bit 3
7712 #define CCP2FMT CCP2CONbits.CCP2FMT // bit 4
7713 #define CCP2OUT CCP2CONbits.CCP2OUT // bit 5
7714 #define CCP2EN CCP2CONbits.CCP2EN // bit 7
7716 #define CCP2PPS0 CCP2PPSbits.CCP2PPS0 // bit 0
7717 #define CCP2PPS1 CCP2PPSbits.CCP2PPS1 // bit 1
7718 #define CCP2PPS2 CCP2PPSbits.CCP2PPS2 // bit 2
7719 #define CCP2PPS3 CCP2PPSbits.CCP2PPS3 // bit 3
7720 #define CCP2PPS4 CCP2PPSbits.CCP2PPS4 // bit 4
7722 #define C1TSEL CCPTMRSbits.C1TSEL // bit 0
7723 #define C2TSEL CCPTMRSbits.C2TSEL // bit 2
7725 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
7726 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
7727 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
7728 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
7729 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
7730 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
7731 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
7732 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
7733 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
7734 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
7735 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
7736 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
7737 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
7738 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
7740 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
7741 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
7742 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
7743 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
7744 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
7745 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
7746 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
7747 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
7748 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
7749 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
7750 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
7751 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
7752 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
7753 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
7754 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
7755 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
7757 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
7758 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
7759 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
7760 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
7761 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
7762 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
7763 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
7764 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
7765 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
7766 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
7767 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
7768 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
7769 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
7770 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
7771 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
7772 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
7774 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
7775 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
7776 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
7777 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
7778 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
7779 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
7780 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
7781 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
7782 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
7783 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
7785 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
7786 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
7787 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
7788 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
7789 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
7790 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
7791 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
7792 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
7793 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
7794 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
7796 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
7797 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
7798 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
7799 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
7800 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
7801 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
7802 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
7803 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
7804 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
7805 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
7807 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
7808 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
7809 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
7810 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
7811 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
7812 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
7813 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
7814 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
7815 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
7816 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
7818 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
7819 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
7820 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
7821 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
7822 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
7823 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
7824 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
7825 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
7826 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
7827 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
7829 #define MLC1OUT CLCDATAbits.MLC1OUT // bit 0
7830 #define MLC2OUT CLCDATAbits.MLC2OUT // bit 1
7832 #define CLCIN0PPS0 CLCIN0PPSbits.CLCIN0PPS0 // bit 0
7833 #define CLCIN0PPS1 CLCIN0PPSbits.CLCIN0PPS1 // bit 1
7834 #define CLCIN0PPS2 CLCIN0PPSbits.CLCIN0PPS2 // bit 2
7835 #define CLCIN0PPS3 CLCIN0PPSbits.CLCIN0PPS3 // bit 3
7836 #define CLCIN0PPS4 CLCIN0PPSbits.CLCIN0PPS4 // bit 4
7838 #define CLCIN1PPS0 CLCIN1PPSbits.CLCIN1PPS0 // bit 0
7839 #define CLCIN1PPS1 CLCIN1PPSbits.CLCIN1PPS1 // bit 1
7840 #define CLCIN1PPS2 CLCIN1PPSbits.CLCIN1PPS2 // bit 2
7841 #define CLCIN1PPS3 CLCIN1PPSbits.CLCIN1PPS3 // bit 3
7842 #define CLCIN1PPS4 CLCIN1PPSbits.CLCIN1PPS4 // bit 4
7844 #define CLCIN2PPS0 CLCIN2PPSbits.CLCIN2PPS0 // bit 0
7845 #define CLCIN2PPS1 CLCIN2PPSbits.CLCIN2PPS1 // bit 1
7846 #define CLCIN2PPS2 CLCIN2PPSbits.CLCIN2PPS2 // bit 2
7847 #define CLCIN2PPS3 CLCIN2PPSbits.CLCIN2PPS3 // bit 3
7848 #define CLCIN2PPS4 CLCIN2PPSbits.CLCIN2PPS4 // bit 4
7850 #define CLCIN3PPS0 CLCIN3PPSbits.CLCIN3PPS0 // bit 0
7851 #define CLCIN3PPS1 CLCIN3PPSbits.CLCIN3PPS1 // bit 1
7852 #define CLCIN3PPS2 CLCIN3PPSbits.CLCIN3PPS2 // bit 2
7853 #define CLCIN3PPS3 CLCIN3PPSbits.CLCIN3PPS3 // bit 3
7854 #define CLCIN3PPS4 CLCIN3PPSbits.CLCIN3PPS4 // bit 4
7856 #define CLKRDIV0 CLKRCONbits.CLKRDIV0 // bit 0
7857 #define CLKRDIV1 CLKRCONbits.CLKRDIV1 // bit 1
7858 #define CLKRDIV2 CLKRCONbits.CLKRDIV2 // bit 2
7859 #define CLKRDC0 CLKRCONbits.CLKRDC0 // bit 3
7860 #define CLKRDC1 CLKRCONbits.CLKRDC1 // bit 4
7861 #define CLKREN CLKRCONbits.CLKREN // bit 7
7863 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
7864 #define C1HYS CM1CON0bits.C1HYS // bit 1
7865 #define C1SP CM1CON0bits.C1SP // bit 2
7866 #define C1POL CM1CON0bits.C1POL // bit 4
7867 #define C1OUT CM1CON0bits.C1OUT // bit 6
7868 #define C1ON CM1CON0bits.C1ON // bit 7
7870 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
7871 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
7872 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
7873 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
7874 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
7875 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
7876 #define C1INTN CM1CON1bits.C1INTN // bit 6
7877 #define C1INTP CM1CON1bits.C1INTP // bit 7
7879 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
7880 #define C2HYS CM2CON0bits.C2HYS // bit 1
7881 #define C2SP CM2CON0bits.C2SP // bit 2
7882 #define C2POL CM2CON0bits.C2POL // bit 4
7883 #define C2OUT CM2CON0bits.C2OUT // bit 6
7884 #define C2ON CM2CON0bits.C2ON // bit 7
7886 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
7887 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
7888 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
7889 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
7890 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
7891 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
7892 #define C2INTN CM2CON1bits.C2INTN // bit 6
7893 #define C2INTP CM2CON1bits.C2INTP // bit 7
7895 #define MC1OUT CMOUTbits.MC1OUT // bit 0
7896 #define MC2OUT CMOUTbits.MC2OUT // bit 1
7898 #define DOZE0 CPUDOZEbits.DOZE0 // bit 0
7899 #define DOZE1 CPUDOZEbits.DOZE1 // bit 1
7900 #define DOZE2 CPUDOZEbits.DOZE2 // bit 2
7901 #define DOE CPUDOZEbits.DOE // bit 4
7902 #define ROI CPUDOZEbits.ROI // bit 5
7903 #define DOZEN CPUDOZEbits.DOZEN // bit 6
7904 #define IDLEN CPUDOZEbits.IDLEN // bit 7
7906 #define LSAC0 CWG1AS0bits.LSAC0 // bit 2, shadows bit in CWG1AS0bits
7907 #define CWG1LSAC0 CWG1AS0bits.CWG1LSAC0 // bit 2, shadows bit in CWG1AS0bits
7908 #define LSAC1 CWG1AS0bits.LSAC1 // bit 3, shadows bit in CWG1AS0bits
7909 #define CWG1LSAC1 CWG1AS0bits.CWG1LSAC1 // bit 3, shadows bit in CWG1AS0bits
7910 #define LSBD0 CWG1AS0bits.LSBD0 // bit 4, shadows bit in CWG1AS0bits
7911 #define CWG1LSBD0 CWG1AS0bits.CWG1LSBD0 // bit 4, shadows bit in CWG1AS0bits
7912 #define LSBD1 CWG1AS0bits.LSBD1 // bit 5, shadows bit in CWG1AS0bits
7913 #define CWG1LSBD1 CWG1AS0bits.CWG1LSBD1 // bit 5, shadows bit in CWG1AS0bits
7914 #define REN CWG1AS0bits.REN // bit 6, shadows bit in CWG1AS0bits
7915 #define CWG1REN CWG1AS0bits.CWG1REN // bit 6, shadows bit in CWG1AS0bits
7916 #define SHUTDOWN CWG1AS0bits.SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
7917 #define CWG1SHUTDOWN CWG1AS0bits.CWG1SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
7919 #define AS0E CWG1AS1bits.AS0E // bit 0
7920 #define AS1E CWG1AS1bits.AS1E // bit 1
7921 #define AS2E CWG1AS1bits.AS2E // bit 2
7922 #define AS3E CWG1AS1bits.AS3E // bit 3
7924 #define CS CWG1CLKCONbits.CS // bit 0, shadows bit in CWG1CLKCONbits
7925 #define CWG1CS CWG1CLKCONbits.CWG1CS // bit 0, shadows bit in CWG1CLKCONbits
7927 #define POLA CWG1CON1bits.POLA // bit 0, shadows bit in CWG1CON1bits
7928 #define CWG1POLA CWG1CON1bits.CWG1POLA // bit 0, shadows bit in CWG1CON1bits
7929 #define POLB CWG1CON1bits.POLB // bit 1, shadows bit in CWG1CON1bits
7930 #define CWG1POLB CWG1CON1bits.CWG1POLB // bit 1, shadows bit in CWG1CON1bits
7931 #define POLC CWG1CON1bits.POLC // bit 2, shadows bit in CWG1CON1bits
7932 #define CWG1POLC CWG1CON1bits.CWG1POLC // bit 2, shadows bit in CWG1CON1bits
7933 #define POLD CWG1CON1bits.POLD // bit 3, shadows bit in CWG1CON1bits
7934 #define CWG1POLD CWG1CON1bits.CWG1POLD // bit 3, shadows bit in CWG1CON1bits
7935 #define IN CWG1CON1bits.IN // bit 5, shadows bit in CWG1CON1bits
7936 #define CWG1IN CWG1CON1bits.CWG1IN // bit 5, shadows bit in CWG1CON1bits
7938 #define CWG1DAT0 CWG1DATbits.CWG1DAT0 // bit 0
7939 #define CWG1DAT1 CWG1DATbits.CWG1DAT1 // bit 1
7940 #define CWG1DAT2 CWG1DATbits.CWG1DAT2 // bit 2
7941 #define CWG1DAT3 CWG1DATbits.CWG1DAT3 // bit 3
7943 #define DBF0 CWG1DBFbits.DBF0 // bit 0, shadows bit in CWG1DBFbits
7944 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0, shadows bit in CWG1DBFbits
7945 #define DBF1 CWG1DBFbits.DBF1 // bit 1, shadows bit in CWG1DBFbits
7946 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1, shadows bit in CWG1DBFbits
7947 #define DBF2 CWG1DBFbits.DBF2 // bit 2, shadows bit in CWG1DBFbits
7948 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2, shadows bit in CWG1DBFbits
7949 #define DBF3 CWG1DBFbits.DBF3 // bit 3, shadows bit in CWG1DBFbits
7950 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3, shadows bit in CWG1DBFbits
7951 #define DBF4 CWG1DBFbits.DBF4 // bit 4, shadows bit in CWG1DBFbits
7952 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4, shadows bit in CWG1DBFbits
7953 #define DBF5 CWG1DBFbits.DBF5 // bit 5, shadows bit in CWG1DBFbits
7954 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5, shadows bit in CWG1DBFbits
7956 #define DBR0 CWG1DBRbits.DBR0 // bit 0, shadows bit in CWG1DBRbits
7957 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0, shadows bit in CWG1DBRbits
7958 #define DBR1 CWG1DBRbits.DBR1 // bit 1, shadows bit in CWG1DBRbits
7959 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1, shadows bit in CWG1DBRbits
7960 #define DBR2 CWG1DBRbits.DBR2 // bit 2, shadows bit in CWG1DBRbits
7961 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2, shadows bit in CWG1DBRbits
7962 #define DBR3 CWG1DBRbits.DBR3 // bit 3, shadows bit in CWG1DBRbits
7963 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3, shadows bit in CWG1DBRbits
7964 #define DBR4 CWG1DBRbits.DBR4 // bit 4, shadows bit in CWG1DBRbits
7965 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4, shadows bit in CWG1DBRbits
7966 #define DBR5 CWG1DBRbits.DBR5 // bit 5, shadows bit in CWG1DBRbits
7967 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5, shadows bit in CWG1DBRbits
7969 #define CWG1PPS0 CWG1PPSbits.CWG1PPS0 // bit 0
7970 #define CWG1PPS1 CWG1PPSbits.CWG1PPS1 // bit 1
7971 #define CWG1PPS2 CWG1PPSbits.CWG1PPS2 // bit 2
7972 #define CWG1PPS3 CWG1PPSbits.CWG1PPS3 // bit 3
7973 #define CWG1PPS4 CWG1PPSbits.CWG1PPS4 // bit 4
7975 #define STRA CWG1STRbits.STRA // bit 0, shadows bit in CWG1STRbits
7976 #define CWG1STRA CWG1STRbits.CWG1STRA // bit 0, shadows bit in CWG1STRbits
7977 #define STRB CWG1STRbits.STRB // bit 1, shadows bit in CWG1STRbits
7978 #define CWG1STRB CWG1STRbits.CWG1STRB // bit 1, shadows bit in CWG1STRbits
7979 #define STRC CWG1STRbits.STRC // bit 2, shadows bit in CWG1STRbits
7980 #define CWG1STRC CWG1STRbits.CWG1STRC // bit 2, shadows bit in CWG1STRbits
7981 #define STRD CWG1STRbits.STRD // bit 3, shadows bit in CWG1STRbits
7982 #define CWG1STRD CWG1STRbits.CWG1STRD // bit 3, shadows bit in CWG1STRbits
7983 #define OVRA CWG1STRbits.OVRA // bit 4, shadows bit in CWG1STRbits
7984 #define CWG1OVRA CWG1STRbits.CWG1OVRA // bit 4, shadows bit in CWG1STRbits
7985 #define OVRB CWG1STRbits.OVRB // bit 5, shadows bit in CWG1STRbits
7986 #define CWG1OVRB CWG1STRbits.CWG1OVRB // bit 5, shadows bit in CWG1STRbits
7987 #define OVRC CWG1STRbits.OVRC // bit 6, shadows bit in CWG1STRbits
7988 #define CWG1OVRC CWG1STRbits.CWG1OVRC // bit 6, shadows bit in CWG1STRbits
7989 #define OVRD CWG1STRbits.OVRD // bit 7, shadows bit in CWG1STRbits
7990 #define CWG1OVRD CWG1STRbits.CWG1OVRD // bit 7, shadows bit in CWG1STRbits
7992 #define DAC1NSS DACCON0bits.DAC1NSS // bit 0
7993 #define DAC1PSS0 DACCON0bits.DAC1PSS0 // bit 2
7994 #define DAC1PSS1 DACCON0bits.DAC1PSS1 // bit 3
7995 #define DAC1OE DACCON0bits.DAC1OE // bit 5
7996 #define DAC1EN DACCON0bits.DAC1EN // bit 7
7998 #define DAC1R0 DACCON1bits.DAC1R0 // bit 0
7999 #define DAC1R1 DACCON1bits.DAC1R1 // bit 1
8000 #define DAC1R2 DACCON1bits.DAC1R2 // bit 2
8001 #define DAC1R3 DACCON1bits.DAC1R3 // bit 3
8002 #define DAC1R4 DACCON1bits.DAC1R4 // bit 4
8004 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
8005 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
8006 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
8007 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
8008 #define TSRNG FVRCONbits.TSRNG // bit 4
8009 #define TSEN FVRCONbits.TSEN // bit 5
8010 #define FVRRDY FVRCONbits.FVRRDY // bit 6
8011 #define FVREN FVRCONbits.FVREN // bit 7
8013 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
8014 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
8015 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
8016 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
8017 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
8018 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
8020 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
8021 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
8022 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
8023 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
8024 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
8025 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
8027 #define INTEDG INTCONbits.INTEDG // bit 0
8028 #define PEIE INTCONbits.PEIE // bit 6
8029 #define GIE INTCONbits.GIE // bit 7
8031 #define INTPPS0 INTPPSbits.INTPPS0 // bit 0
8032 #define INTPPS1 INTPPSbits.INTPPS1 // bit 1
8033 #define INTPPS2 INTPPSbits.INTPPS2 // bit 2
8034 #define INTPPS3 INTPPSbits.INTPPS3 // bit 3
8035 #define INTPPS4 INTPPSbits.INTPPS4 // bit 4
8037 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
8038 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
8039 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
8040 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
8041 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
8042 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
8044 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
8045 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
8046 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
8047 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
8048 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
8049 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
8051 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
8052 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
8053 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
8054 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
8055 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
8056 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
8058 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
8059 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
8060 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
8061 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
8062 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
8063 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
8065 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
8066 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
8067 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
8068 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
8069 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
8070 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
8072 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
8073 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
8074 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
8075 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
8076 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
8077 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
8079 #define LATA0 LATAbits.LATA0 // bit 0
8080 #define LATA1 LATAbits.LATA1 // bit 1
8081 #define LATA2 LATAbits.LATA2 // bit 2
8082 #define LATA4 LATAbits.LATA4 // bit 4
8083 #define LATA5 LATAbits.LATA5 // bit 5
8085 #define LATC0 LATCbits.LATC0 // bit 0
8086 #define LATC1 LATCbits.LATC1 // bit 1
8087 #define LATC2 LATCbits.LATC2 // bit 2
8088 #define LATC3 LATCbits.LATC3 // bit 3
8089 #define LATC4 LATCbits.LATC4 // bit 4
8090 #define LATC5 LATCbits.LATC5 // bit 5
8092 #define MDCH0 MDCARHbits.MDCH0 // bit 0
8093 #define MDCH1 MDCARHbits.MDCH1 // bit 1
8094 #define MDCH2 MDCARHbits.MDCH2 // bit 2
8095 #define MDCH3 MDCARHbits.MDCH3 // bit 3
8096 #define MDCHSYNC MDCARHbits.MDCHSYNC // bit 5
8097 #define MDCHPOL MDCARHbits.MDCHPOL // bit 6
8099 #define MDCL0 MDCARLbits.MDCL0 // bit 0
8100 #define MDCL1 MDCARLbits.MDCL1 // bit 1
8101 #define MDCL2 MDCARLbits.MDCL2 // bit 2
8102 #define MDCL3 MDCARLbits.MDCL3 // bit 3
8103 #define MDCLSYNC MDCARLbits.MDCLSYNC // bit 5
8104 #define MDCLPOL MDCARLbits.MDCLPOL // bit 6
8106 #define MDCIN1PPS0 MDCIN1PPSbits.MDCIN1PPS0 // bit 0
8107 #define MDCIN1PPS1 MDCIN1PPSbits.MDCIN1PPS1 // bit 1
8108 #define MDCIN1PPS2 MDCIN1PPSbits.MDCIN1PPS2 // bit 2
8109 #define MDCIN1PPS3 MDCIN1PPSbits.MDCIN1PPS3 // bit 3
8110 #define MDCIN1PPS4 MDCIN1PPSbits.MDCIN1PPS4 // bit 4
8112 #define MDCIN2PPS0 MDCIN2PPSbits.MDCIN2PPS0 // bit 0
8113 #define MDCIN2PPS1 MDCIN2PPSbits.MDCIN2PPS1 // bit 1
8114 #define MDCIN2PPS2 MDCIN2PPSbits.MDCIN2PPS2 // bit 2
8115 #define MDCIN2PPS3 MDCIN2PPSbits.MDCIN2PPS3 // bit 3
8116 #define MDCIN2PPS4 MDCIN2PPSbits.MDCIN2PPS4 // bit 4
8118 #define MDBIT MDCONbits.MDBIT // bit 0
8119 #define MDOUT MDCONbits.MDOUT // bit 3
8120 #define MDOPOL MDCONbits.MDOPOL // bit 4
8121 #define MDEN MDCONbits.MDEN // bit 7
8123 #define MDMINPPS0 MDMINPPSbits.MDMINPPS0 // bit 0
8124 #define MDMINPPS1 MDMINPPSbits.MDMINPPS1 // bit 1
8125 #define MDMINPPS2 MDMINPPSbits.MDMINPPS2 // bit 2
8126 #define MDMINPPS3 MDMINPPSbits.MDMINPPS3 // bit 3
8127 #define MDMINPPS4 MDMINPPSbits.MDMINPPS4 // bit 4
8129 #define MDMS0 MDSRCbits.MDMS0 // bit 0
8130 #define MDMS1 MDSRCbits.MDMS1 // bit 1
8131 #define MDMS2 MDSRCbits.MDMS2 // bit 2
8132 #define MDMS3 MDSRCbits.MDMS3 // bit 3
8134 #define N1PFM NCO1CONbits.N1PFM // bit 0
8135 #define N1POL NCO1CONbits.N1POL // bit 4
8136 #define N1OUT NCO1CONbits.N1OUT // bit 5
8137 #define N1EN NCO1CONbits.N1EN // bit 7
8139 #define NVMADR8 NVMADRHbits.NVMADR8 // bit 0
8140 #define NVMADR9 NVMADRHbits.NVMADR9 // bit 1
8141 #define NVMADR10 NVMADRHbits.NVMADR10 // bit 2
8142 #define NVMADR11 NVMADRHbits.NVMADR11 // bit 3
8143 #define NVMADR12 NVMADRHbits.NVMADR12 // bit 4
8144 #define NVMADR13 NVMADRHbits.NVMADR13 // bit 5
8145 #define NVMADR14 NVMADRHbits.NVMADR14 // bit 6
8147 #define NVMADR0 NVMADRLbits.NVMADR0 // bit 0
8148 #define NVMADR1 NVMADRLbits.NVMADR1 // bit 1
8149 #define NVMADR2 NVMADRLbits.NVMADR2 // bit 2
8150 #define NVMADR3 NVMADRLbits.NVMADR3 // bit 3
8151 #define NVMADR4 NVMADRLbits.NVMADR4 // bit 4
8152 #define NVMADR5 NVMADRLbits.NVMADR5 // bit 5
8153 #define NVMADR6 NVMADRLbits.NVMADR6 // bit 6
8154 #define NVMADR7 NVMADRLbits.NVMADR7 // bit 7
8156 #define RD NVMCON1bits.RD // bit 0
8157 #define WR NVMCON1bits.WR // bit 1
8158 #define WREN NVMCON1bits.WREN // bit 2
8159 #define WRERR NVMCON1bits.WRERR // bit 3
8160 #define FREE NVMCON1bits.FREE // bit 4
8161 #define LWLO NVMCON1bits.LWLO // bit 5
8162 #define NVMREGS NVMCON1bits.NVMREGS // bit 6
8164 #define NVMDAT8 NVMDATHbits.NVMDAT8 // bit 0
8165 #define NVMDAT9 NVMDATHbits.NVMDAT9 // bit 1
8166 #define NVMDAT10 NVMDATHbits.NVMDAT10 // bit 2
8167 #define NVMDAT11 NVMDATHbits.NVMDAT11 // bit 3
8168 #define NVMDAT12 NVMDATHbits.NVMDAT12 // bit 4
8169 #define NVMDAT13 NVMDATHbits.NVMDAT13 // bit 5
8171 #define NVMDAT0 NVMDATLbits.NVMDAT0 // bit 0
8172 #define NVMDAT1 NVMDATLbits.NVMDAT1 // bit 1
8173 #define NVMDAT2 NVMDATLbits.NVMDAT2 // bit 2
8174 #define NVMDAT3 NVMDATLbits.NVMDAT3 // bit 3
8175 #define NVMDAT4 NVMDATLbits.NVMDAT4 // bit 4
8176 #define NVMDAT5 NVMDATLbits.NVMDAT5 // bit 5
8177 #define NVMDAT6 NVMDATLbits.NVMDAT6 // bit 6
8178 #define NVMDAT7 NVMDATLbits.NVMDAT7 // bit 7
8180 #define ODCA0 ODCONAbits.ODCA0 // bit 0
8181 #define ODCA1 ODCONAbits.ODCA1 // bit 1
8182 #define ODCA2 ODCONAbits.ODCA2 // bit 2
8183 #define ODCA4 ODCONAbits.ODCA4 // bit 4
8184 #define ODCA5 ODCONAbits.ODCA5 // bit 5
8186 #define ODCC0 ODCONCbits.ODCC0 // bit 0
8187 #define ODCC1 ODCONCbits.ODCC1 // bit 1
8188 #define ODCC2 ODCONCbits.ODCC2 // bit 2
8189 #define ODCC3 ODCONCbits.ODCC3 // bit 3
8190 #define ODCC4 ODCONCbits.ODCC4 // bit 4
8191 #define ODCC5 ODCONCbits.ODCC5 // bit 5
8193 #define NDIV0 OSCCON1bits.NDIV0 // bit 0
8194 #define NDIV1 OSCCON1bits.NDIV1 // bit 1
8195 #define NDIV2 OSCCON1bits.NDIV2 // bit 2
8196 #define NDIV3 OSCCON1bits.NDIV3 // bit 3
8197 #define NOSC0 OSCCON1bits.NOSC0 // bit 4
8198 #define NOSC1 OSCCON1bits.NOSC1 // bit 5
8199 #define NOSC2 OSCCON1bits.NOSC2 // bit 6
8201 #define CDIV0 OSCCON2bits.CDIV0 // bit 0
8202 #define CDIV1 OSCCON2bits.CDIV1 // bit 1
8203 #define CDIV2 OSCCON2bits.CDIV2 // bit 2
8204 #define CDIV3 OSCCON2bits.CDIV3 // bit 3
8205 #define COSC0 OSCCON2bits.COSC0 // bit 4
8206 #define COSC1 OSCCON2bits.COSC1 // bit 5
8207 #define COSC2 OSCCON2bits.COSC2 // bit 6
8209 #define NOSCR OSCCON3bits.NOSCR // bit 3
8210 #define ORDY OSCCON3bits.ORDY // bit 4
8211 #define SOSCBE OSCCON3bits.SOSCBE // bit 5
8212 #define SOSCPWR OSCCON3bits.SOSCPWR // bit 6
8213 #define CSWHOLD OSCCON3bits.CSWHOLD // bit 7
8215 #define ADOEN OSCENbits.ADOEN // bit 2
8216 #define SOSCEN OSCENbits.SOSCEN // bit 3
8217 #define LFOEN OSCENbits.LFOEN // bit 4
8218 #define HFOEN OSCENbits.HFOEN // bit 6
8219 #define EXTOEN OSCENbits.EXTOEN // bit 7
8221 #define HFFRQ0 OSCFRQbits.HFFRQ0 // bit 0
8222 #define HFFRQ1 OSCFRQbits.HFFRQ1 // bit 1
8223 #define HFFRQ2 OSCFRQbits.HFFRQ2 // bit 2
8224 #define HFFRQ3 OSCFRQbits.HFFRQ3 // bit 3
8226 #define PLLR OSCSTAT1bits.PLLR // bit 0
8227 #define ADOR OSCSTAT1bits.ADOR // bit 2
8228 #define SOR OSCSTAT1bits.SOR // bit 3
8229 #define LFOR OSCSTAT1bits.LFOR // bit 4
8230 #define HFOR OSCSTAT1bits.HFOR // bit 6
8231 #define EXTOR OSCSTAT1bits.EXTOR // bit 7
8233 #define HFTUN0 OSCTUNEbits.HFTUN0 // bit 0
8234 #define HFTUN1 OSCTUNEbits.HFTUN1 // bit 1
8235 #define HFTUN2 OSCTUNEbits.HFTUN2 // bit 2
8236 #define HFTUN3 OSCTUNEbits.HFTUN3 // bit 3
8237 #define HFTUN4 OSCTUNEbits.HFTUN4 // bit 4
8238 #define HFTUN5 OSCTUNEbits.HFTUN5 // bit 5
8240 #define NOT_BOR PCON0bits.NOT_BOR // bit 0
8241 #define NOT_POR PCON0bits.NOT_POR // bit 1
8242 #define NOT_RI PCON0bits.NOT_RI // bit 2
8243 #define NOT_RMCLR PCON0bits.NOT_RMCLR // bit 3
8244 #define NOT_RWDT PCON0bits.NOT_RWDT // bit 4
8245 #define STKUNF PCON0bits.STKUNF // bit 6
8246 #define STKOVF PCON0bits.STKOVF // bit 7
8248 #define INTE PIE0bits.INTE // bit 0
8249 #define IOCIE PIE0bits.IOCIE // bit 4
8250 #define TMR0IE PIE0bits.TMR0IE // bit 5
8252 #define TMR1IE PIE1bits.TMR1IE // bit 0
8253 #define TMR2IE PIE1bits.TMR2IE // bit 1
8254 #define BCL1IE PIE1bits.BCL1IE // bit 2
8255 #define SSP1IE PIE1bits.SSP1IE // bit 3
8256 #define TXIE PIE1bits.TXIE // bit 4
8257 #define RCIE PIE1bits.RCIE // bit 5
8258 #define ADIE PIE1bits.ADIE // bit 6
8259 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
8261 #define NCO1IE PIE2bits.NCO1IE // bit 0
8262 #define NVMIE PIE2bits.NVMIE // bit 4
8263 #define C1IE PIE2bits.C1IE // bit 5
8264 #define C2IE PIE2bits.C2IE // bit 6
8266 #define CLC1IE PIE3bits.CLC1IE // bit 0
8267 #define CLC2IE PIE3bits.CLC2IE // bit 1
8268 #define CSWIE PIE3bits.CSWIE // bit 6
8269 #define OSFIE PIE3bits.OSFIE // bit 7
8271 #define CCP1IE PIE4bits.CCP1IE // bit 0
8272 #define CCP2IE PIE4bits.CCP2IE // bit 1
8273 #define CWG1IE PIE4bits.CWG1IE // bit 6
8275 #define INTF PIR0bits.INTF // bit 0
8276 #define IOCIF PIR0bits.IOCIF // bit 4
8277 #define TMR0IF PIR0bits.TMR0IF // bit 5
8279 #define TMR1IF PIR1bits.TMR1IF // bit 0
8280 #define TMR2IF PIR1bits.TMR2IF // bit 1
8281 #define BCL1IF PIR1bits.BCL1IF // bit 2
8282 #define SSP1IF PIR1bits.SSP1IF // bit 3
8283 #define TXIF PIR1bits.TXIF // bit 4
8284 #define RCIF PIR1bits.RCIF // bit 5
8285 #define ADIF PIR1bits.ADIF // bit 6
8286 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
8288 #define NCO1IF PIR2bits.NCO1IF // bit 0
8289 #define NVMIF PIR2bits.NVMIF // bit 4
8290 #define C1IF PIR2bits.C1IF // bit 5
8291 #define C2IF PIR2bits.C2IF // bit 6
8293 #define CLC1IF PIR3bits.CLC1IF // bit 0
8294 #define CLC2IF PIR3bits.CLC2IF // bit 1
8295 #define CSWIF PIR3bits.CSWIF // bit 6
8296 #define OSFIF PIR3bits.OSFIF // bit 7
8298 #define CCP1IF PIR4bits.CCP1IF // bit 0
8299 #define CCP2IF PIR4bits.CCP2IF // bit 1
8300 #define CWG1IF PIR4bits.CWG1IF // bit 6
8302 #define IOCMD PMD0bits.IOCMD // bit 0
8303 #define CLKRMD PMD0bits.CLKRMD // bit 1
8304 #define NVMMD PMD0bits.NVMMD // bit 2
8305 #define FVRMD PMD0bits.FVRMD // bit 6
8306 #define SYSCMD PMD0bits.SYSCMD // bit 7
8308 #define TMR0MD PMD1bits.TMR0MD // bit 0
8309 #define TMR1MD PMD1bits.TMR1MD // bit 1
8310 #define TMR2MD PMD1bits.TMR2MD // bit 2
8311 #define NCOMD PMD1bits.NCOMD // bit 7
8313 #define CMP1MD PMD2bits.CMP1MD // bit 1
8314 #define CMP2MD PMD2bits.CMP2MD // bit 2
8315 #define ADCMD PMD2bits.ADCMD // bit 5
8316 #define DACMD PMD2bits.DACMD // bit 6
8318 #define CCP1MD PMD3bits.CCP1MD // bit 0
8319 #define CCP2MD PMD3bits.CCP2MD // bit 1
8320 #define PWM5MD PMD3bits.PWM5MD // bit 4
8321 #define PWM6MD PMD3bits.PWM6MD // bit 5
8322 #define CWG1MD PMD3bits.CWG1MD // bit 6
8324 #define MSSP1MD PMD4bits.MSSP1MD // bit 1
8325 #define UART1MD PMD4bits.UART1MD // bit 5
8327 #define DSMMD PMD5bits.DSMMD // bit 0
8328 #define CLC1MD PMD5bits.CLC1MD // bit 1
8329 #define CLC2MD PMD5bits.CLC2MD // bit 2
8331 #define RA0 PORTAbits.RA0 // bit 0
8332 #define RA1 PORTAbits.RA1 // bit 1
8333 #define RA2 PORTAbits.RA2 // bit 2
8334 #define RA3 PORTAbits.RA3 // bit 3
8335 #define RA4 PORTAbits.RA4 // bit 4
8336 #define RA5 PORTAbits.RA5 // bit 5
8338 #define RC0 PORTCbits.RC0 // bit 0
8339 #define RC1 PORTCbits.RC1 // bit 1
8340 #define RC2 PORTCbits.RC2 // bit 2
8341 #define RC3 PORTCbits.RC3 // bit 3
8342 #define RC4 PORTCbits.RC4 // bit 4
8343 #define RC5 PORTCbits.RC5 // bit 5
8345 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
8347 #define PWM5POL PWM5CONbits.PWM5POL // bit 4
8348 #define PWM5OUT PWM5CONbits.PWM5OUT // bit 5
8349 #define PWM5EN PWM5CONbits.PWM5EN // bit 7
8351 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
8352 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
8353 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
8354 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
8355 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
8356 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
8357 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
8358 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
8360 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 6
8361 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 7
8363 #define PWM6POL PWM6CONbits.PWM6POL // bit 4
8364 #define PWM6OUT PWM6CONbits.PWM6OUT // bit 5
8365 #define PWM6EN PWM6CONbits.PWM6EN // bit 7
8367 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
8368 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
8369 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
8370 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
8371 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
8372 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
8373 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
8374 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
8376 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 6
8377 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 7
8379 #define RA0PPS0 RA0PPSbits.RA0PPS0 // bit 0
8380 #define RA0PPS1 RA0PPSbits.RA0PPS1 // bit 1
8381 #define RA0PPS2 RA0PPSbits.RA0PPS2 // bit 2
8382 #define RA0PPS3 RA0PPSbits.RA0PPS3 // bit 3
8383 #define RA0PPS4 RA0PPSbits.RA0PPS4 // bit 4
8385 #define RA1PPS0 RA1PPSbits.RA1PPS0 // bit 0
8386 #define RA1PPS1 RA1PPSbits.RA1PPS1 // bit 1
8387 #define RA1PPS2 RA1PPSbits.RA1PPS2 // bit 2
8388 #define RA1PPS3 RA1PPSbits.RA1PPS3 // bit 3
8389 #define RA1PPS4 RA1PPSbits.RA1PPS4 // bit 4
8391 #define RA2PPS0 RA2PPSbits.RA2PPS0 // bit 0
8392 #define RA2PPS1 RA2PPSbits.RA2PPS1 // bit 1
8393 #define RA2PPS2 RA2PPSbits.RA2PPS2 // bit 2
8394 #define RA2PPS3 RA2PPSbits.RA2PPS3 // bit 3
8395 #define RA2PPS4 RA2PPSbits.RA2PPS4 // bit 4
8397 #define RA4PPS0 RA4PPSbits.RA4PPS0 // bit 0
8398 #define RA4PPS1 RA4PPSbits.RA4PPS1 // bit 1
8399 #define RA4PPS2 RA4PPSbits.RA4PPS2 // bit 2
8400 #define RA4PPS3 RA4PPSbits.RA4PPS3 // bit 3
8401 #define RA4PPS4 RA4PPSbits.RA4PPS4 // bit 4
8403 #define RA5PPS0 RA5PPSbits.RA5PPS0 // bit 0
8404 #define RA5PPS1 RA5PPSbits.RA5PPS1 // bit 1
8405 #define RA5PPS2 RA5PPSbits.RA5PPS2 // bit 2
8406 #define RA5PPS3 RA5PPSbits.RA5PPS3 // bit 3
8407 #define RA5PPS4 RA5PPSbits.RA5PPS4 // bit 4
8409 #define RC0PPS0 RC0PPSbits.RC0PPS0 // bit 0
8410 #define RC0PPS1 RC0PPSbits.RC0PPS1 // bit 1
8411 #define RC0PPS2 RC0PPSbits.RC0PPS2 // bit 2
8412 #define RC0PPS3 RC0PPSbits.RC0PPS3 // bit 3
8413 #define RC0PPS4 RC0PPSbits.RC0PPS4 // bit 4
8415 #define RC1PPS0 RC1PPSbits.RC1PPS0 // bit 0
8416 #define RC1PPS1 RC1PPSbits.RC1PPS1 // bit 1
8417 #define RC1PPS2 RC1PPSbits.RC1PPS2 // bit 2
8418 #define RC1PPS3 RC1PPSbits.RC1PPS3 // bit 3
8419 #define RC1PPS4 RC1PPSbits.RC1PPS4 // bit 4
8421 #define RX9D RC1STAbits.RX9D // bit 0
8422 #define OERR RC1STAbits.OERR // bit 1
8423 #define FERR RC1STAbits.FERR // bit 2
8424 #define ADDEN RC1STAbits.ADDEN // bit 3
8425 #define CREN RC1STAbits.CREN // bit 4
8426 #define SREN RC1STAbits.SREN // bit 5
8427 #define RX9 RC1STAbits.RX9 // bit 6
8428 #define SPEN RC1STAbits.SPEN // bit 7
8430 #define RC2PPS0 RC2PPSbits.RC2PPS0 // bit 0
8431 #define RC2PPS1 RC2PPSbits.RC2PPS1 // bit 1
8432 #define RC2PPS2 RC2PPSbits.RC2PPS2 // bit 2
8433 #define RC2PPS3 RC2PPSbits.RC2PPS3 // bit 3
8434 #define RC2PPS4 RC2PPSbits.RC2PPS4 // bit 4
8436 #define RC3PPS0 RC3PPSbits.RC3PPS0 // bit 0
8437 #define RC3PPS1 RC3PPSbits.RC3PPS1 // bit 1
8438 #define RC3PPS2 RC3PPSbits.RC3PPS2 // bit 2
8439 #define RC3PPS3 RC3PPSbits.RC3PPS3 // bit 3
8440 #define RC3PPS4 RC3PPSbits.RC3PPS4 // bit 4
8442 #define RC4PPS0 RC4PPSbits.RC4PPS0 // bit 0
8443 #define RC4PPS1 RC4PPSbits.RC4PPS1 // bit 1
8444 #define RC4PPS2 RC4PPSbits.RC4PPS2 // bit 2
8445 #define RC4PPS3 RC4PPSbits.RC4PPS3 // bit 3
8446 #define RC4PPS4 RC4PPSbits.RC4PPS4 // bit 4
8448 #define RC5PPS0 RC5PPSbits.RC5PPS0 // bit 0
8449 #define RC5PPS1 RC5PPSbits.RC5PPS1 // bit 1
8450 #define RC5PPS2 RC5PPSbits.RC5PPS2 // bit 2
8451 #define RC5PPS3 RC5PPSbits.RC5PPS3 // bit 3
8452 #define RC5PPS4 RC5PPSbits.RC5PPS4 // bit 4
8454 #define RXPPS0 RXPPSbits.RXPPS0 // bit 0
8455 #define RXPPS1 RXPPSbits.RXPPS1 // bit 1
8456 #define RXPPS2 RXPPSbits.RXPPS2 // bit 2
8457 #define RXPPS3 RXPPSbits.RXPPS3 // bit 3
8458 #define RXPPS4 RXPPSbits.RXPPS4 // bit 4
8460 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
8461 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
8462 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
8463 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
8464 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
8466 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
8467 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
8468 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
8469 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
8470 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
8471 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
8473 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
8474 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
8475 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
8476 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
8477 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
8478 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
8479 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
8480 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
8481 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
8482 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
8483 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
8484 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
8485 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
8486 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
8487 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
8488 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
8490 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
8491 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
8492 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
8493 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
8494 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
8495 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
8496 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
8497 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
8498 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
8499 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
8500 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
8501 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
8502 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
8503 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
8504 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
8505 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
8507 #define SSP1CLKPPS0 SSP1CLKPPSbits.SSP1CLKPPS0 // bit 0
8508 #define SSP1CLKPPS1 SSP1CLKPPSbits.SSP1CLKPPS1 // bit 1
8509 #define SSP1CLKPPS2 SSP1CLKPPSbits.SSP1CLKPPS2 // bit 2
8510 #define SSP1CLKPPS3 SSP1CLKPPSbits.SSP1CLKPPS3 // bit 3
8511 #define SSP1CLKPPS4 SSP1CLKPPSbits.SSP1CLKPPS4 // bit 4
8513 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
8514 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
8515 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
8516 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
8517 #define CKP SSP1CONbits.CKP // bit 4
8518 #define SSPEN SSP1CONbits.SSPEN // bit 5
8519 #define SSPOV SSP1CONbits.SSPOV // bit 6
8520 #define WCOL SSP1CONbits.WCOL // bit 7
8522 #define SEN SSP1CON2bits.SEN // bit 0
8523 #define RSEN SSP1CON2bits.RSEN // bit 1
8524 #define PEN SSP1CON2bits.PEN // bit 2
8525 #define RCEN SSP1CON2bits.RCEN // bit 3
8526 #define ACKEN SSP1CON2bits.ACKEN // bit 4
8527 #define ACKDT SSP1CON2bits.ACKDT // bit 5
8528 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
8529 #define GCEN SSP1CON2bits.GCEN // bit 7
8531 #define DHEN SSP1CON3bits.DHEN // bit 0
8532 #define AHEN SSP1CON3bits.AHEN // bit 1
8533 #define SBCDE SSP1CON3bits.SBCDE // bit 2
8534 #define SDAHT SSP1CON3bits.SDAHT // bit 3
8535 #define BOEN SSP1CON3bits.BOEN // bit 4
8536 #define SCIE SSP1CON3bits.SCIE // bit 5
8537 #define PCIE SSP1CON3bits.PCIE // bit 6
8538 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
8540 #define SSP1DATPPS0 SSP1DATPPSbits.SSP1DATPPS0 // bit 0
8541 #define SSP1DATPPS1 SSP1DATPPSbits.SSP1DATPPS1 // bit 1
8542 #define SSP1DATPPS2 SSP1DATPPSbits.SSP1DATPPS2 // bit 2
8543 #define SSP1DATPPS3 SSP1DATPPSbits.SSP1DATPPS3 // bit 3
8544 #define SSP1DATPPS4 SSP1DATPPSbits.SSP1DATPPS4 // bit 4
8546 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
8547 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
8548 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
8549 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
8550 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
8551 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
8552 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
8553 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
8554 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
8555 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
8556 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
8557 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
8558 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
8559 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
8560 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
8561 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
8563 #define SSP1SSPPS0 SSP1SSPPSbits.SSP1SSPPS0 // bit 0
8564 #define SSP1SSPPS1 SSP1SSPPSbits.SSP1SSPPS1 // bit 1
8565 #define SSP1SSPPS2 SSP1SSPPSbits.SSP1SSPPS2 // bit 2
8566 #define SSP1SSPPS3 SSP1SSPPSbits.SSP1SSPPS3 // bit 3
8567 #define SSP1SSPPS4 SSP1SSPPSbits.SSP1SSPPS4 // bit 4
8569 #define BF SSP1STATbits.BF // bit 0
8570 #define UA SSP1STATbits.UA // bit 1
8571 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
8572 #define S SSP1STATbits.S // bit 3
8573 #define P SSP1STATbits.P // bit 4
8574 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
8575 #define CKE SSP1STATbits.CKE // bit 6
8576 #define SMP SSP1STATbits.SMP // bit 7
8578 #define C STATUSbits.C // bit 0
8579 #define DC STATUSbits.DC // bit 1
8580 #define Z STATUSbits.Z // bit 2
8581 #define NOT_PD STATUSbits.NOT_PD // bit 3
8582 #define NOT_TO STATUSbits.NOT_TO // bit 4
8584 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
8585 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
8586 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
8588 #define T0CKIPPS0 T0CKIPPSbits.T0CKIPPS0 // bit 0
8589 #define T0CKIPPS1 T0CKIPPSbits.T0CKIPPS1 // bit 1
8590 #define T0CKIPPS2 T0CKIPPSbits.T0CKIPPS2 // bit 2
8591 #define T0CKIPPS3 T0CKIPPSbits.T0CKIPPS3 // bit 3
8592 #define T0CKIPPS4 T0CKIPPSbits.T0CKIPPS4 // bit 4
8594 #define T0OUTPS0 T0CON0bits.T0OUTPS0 // bit 0
8595 #define T0OUTPS1 T0CON0bits.T0OUTPS1 // bit 1
8596 #define T0OUTPS2 T0CON0bits.T0OUTPS2 // bit 2
8597 #define T0OUTPS3 T0CON0bits.T0OUTPS3 // bit 3
8598 #define T016BIT T0CON0bits.T016BIT // bit 4
8599 #define T0OUT T0CON0bits.T0OUT // bit 5
8600 #define T0EN T0CON0bits.T0EN // bit 7
8602 #define T0CKPS0 T0CON1bits.T0CKPS0 // bit 0
8603 #define T0CKPS1 T0CON1bits.T0CKPS1 // bit 1
8604 #define T0CKPS2 T0CON1bits.T0CKPS2 // bit 2
8605 #define T0CKPS3 T0CON1bits.T0CKPS3 // bit 3
8606 #define T0ASYNC T0CON1bits.T0ASYNC // bit 4
8607 #define T0CS0 T0CON1bits.T0CS0 // bit 5
8608 #define T0CS1 T0CON1bits.T0CS1 // bit 6
8609 #define T0CS2 T0CON1bits.T0CS2 // bit 7
8611 #define T1CKIPPS0 T1CKIPPSbits.T1CKIPPS0 // bit 0
8612 #define T1CKIPPS1 T1CKIPPSbits.T1CKIPPS1 // bit 1
8613 #define T1CKIPPS2 T1CKIPPSbits.T1CKIPPS2 // bit 2
8614 #define T1CKIPPS3 T1CKIPPSbits.T1CKIPPS3 // bit 3
8615 #define T1CKIPPS4 T1CKIPPSbits.T1CKIPPS4 // bit 4
8617 #define TMR1ON T1CONbits.TMR1ON // bit 0
8618 #define T1SYNC T1CONbits.T1SYNC // bit 2
8619 #define T1SOSC T1CONbits.T1SOSC // bit 3
8620 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
8621 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
8622 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
8623 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
8625 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
8626 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
8627 #define T1GVAL T1GCONbits.T1GVAL // bit 2
8628 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
8629 #define T1GSPM T1GCONbits.T1GSPM // bit 4
8630 #define T1GTM T1GCONbits.T1GTM // bit 5
8631 #define T1GPOL T1GCONbits.T1GPOL // bit 6
8632 #define TMR1GE T1GCONbits.TMR1GE // bit 7
8634 #define T1GPPS0 T1GPPSbits.T1GPPS0 // bit 0
8635 #define T1GPPS1 T1GPPSbits.T1GPPS1 // bit 1
8636 #define T1GPPS2 T1GPPSbits.T1GPPS2 // bit 2
8637 #define T1GPPS3 T1GPPSbits.T1GPPS3 // bit 3
8638 #define T1GPPS4 T1GPPSbits.T1GPPS4 // bit 4
8640 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
8641 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
8642 #define TMR2ON T2CONbits.TMR2ON // bit 2
8643 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
8644 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
8645 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
8646 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
8648 #define TMR08 TMR0Hbits.TMR08 // bit 0
8649 #define TMR09 TMR0Hbits.TMR09 // bit 1
8650 #define TMR010 TMR0Hbits.TMR010 // bit 2
8651 #define TMR011 TMR0Hbits.TMR011 // bit 3
8652 #define TMR012 TMR0Hbits.TMR012 // bit 4
8653 #define TMR013 TMR0Hbits.TMR013 // bit 5
8654 #define TMR014 TMR0Hbits.TMR014 // bit 6
8655 #define TMR015 TMR0Hbits.TMR015 // bit 7
8657 #define TMR00 TMR0Lbits.TMR00 // bit 0
8658 #define TMR01 TMR0Lbits.TMR01 // bit 1
8659 #define TMR02 TMR0Lbits.TMR02 // bit 2
8660 #define TMR03 TMR0Lbits.TMR03 // bit 3
8661 #define TMR04 TMR0Lbits.TMR04 // bit 4
8662 #define TMR05 TMR0Lbits.TMR05 // bit 5
8663 #define TMR06 TMR0Lbits.TMR06 // bit 6
8664 #define TMR07 TMR0Lbits.TMR07 // bit 7
8666 #define TRISA0 TRISAbits.TRISA0 // bit 0
8667 #define TRISA1 TRISAbits.TRISA1 // bit 1
8668 #define TRISA2 TRISAbits.TRISA2 // bit 2
8669 #define TRISA4 TRISAbits.TRISA4 // bit 4
8670 #define TRISA5 TRISAbits.TRISA5 // bit 5
8672 #define TRISC0 TRISCbits.TRISC0 // bit 0
8673 #define TRISC1 TRISCbits.TRISC1 // bit 1
8674 #define TRISC2 TRISCbits.TRISC2 // bit 2
8675 #define TRISC3 TRISCbits.TRISC3 // bit 3
8676 #define TRISC4 TRISCbits.TRISC4 // bit 4
8677 #define TRISC5 TRISCbits.TRISC5 // bit 5
8679 #define TX9D TX1STAbits.TX9D // bit 0
8680 #define TRMT TX1STAbits.TRMT // bit 1
8681 #define BRGH TX1STAbits.BRGH // bit 2
8682 #define SENDB TX1STAbits.SENDB // bit 3
8683 #define SYNC TX1STAbits.SYNC // bit 4
8684 #define TXEN TX1STAbits.TXEN // bit 5
8685 #define TX9 TX1STAbits.TX9 // bit 6
8686 #define CSRC TX1STAbits.CSRC // bit 7
8688 #define TXPPS0 TXPPSbits.TXPPS0 // bit 0
8689 #define TXPPS1 TXPPSbits.TXPPS1 // bit 1
8690 #define TXPPS2 TXPPSbits.TXPPS2 // bit 2
8691 #define TXPPS3 TXPPSbits.TXPPS3 // bit 3
8692 #define TXPPS4 TXPPSbits.TXPPS4 // bit 4
8694 #define SWDTEN WDTCONbits.SWDTEN // bit 0
8695 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
8696 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
8697 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
8698 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
8699 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
8701 #define WPUA0 WPUAbits.WPUA0 // bit 0
8702 #define WPUA1 WPUAbits.WPUA1 // bit 1
8703 #define WPUA2 WPUAbits.WPUA2 // bit 2
8704 #define WPUA3 WPUAbits.WPUA3 // bit 3
8705 #define WPUA4 WPUAbits.WPUA4 // bit 4
8706 #define WPUA5 WPUAbits.WPUA5 // bit 5
8708 #define WPUC0 WPUCbits.WPUC0 // bit 0
8709 #define WPUC1 WPUCbits.WPUC1 // bit 1
8710 #define WPUC2 WPUCbits.WPUC2 // bit 2
8711 #define WPUC3 WPUCbits.WPUC3 // bit 3
8712 #define WPUC4 WPUCbits.WPUC4 // bit 4
8713 #define WPUC5 WPUCbits.WPUC5 // bit 5
8715 #endif // #ifndef NO_BIT_DEFINES
8717 #endif // #ifndef __PIC16LF18323_H__