2 * This declarations of the PIC16LF18344 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:24 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF18344_H__
26 #define __PIC16LF18344_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PIR0_ADDR 0x0010
54 #define PIR1_ADDR 0x0011
55 #define PIR2_ADDR 0x0012
56 #define PIR3_ADDR 0x0013
57 #define PIR4_ADDR 0x0014
58 #define TMR0L_ADDR 0x0015
59 #define TMR0H_ADDR 0x0016
60 #define T0CON0_ADDR 0x0017
61 #define T0CON1_ADDR 0x0018
62 #define TMR1_ADDR 0x0019
63 #define TMR1L_ADDR 0x0019
64 #define TMR1H_ADDR 0x001A
65 #define T1CON_ADDR 0x001B
66 #define T1GCON_ADDR 0x001C
67 #define TMR2_ADDR 0x001D
68 #define PR2_ADDR 0x001E
69 #define T2CON_ADDR 0x001F
70 #define TRISA_ADDR 0x008C
71 #define TRISB_ADDR 0x008D
72 #define TRISC_ADDR 0x008E
73 #define PIE0_ADDR 0x0090
74 #define PIE1_ADDR 0x0091
75 #define PIE2_ADDR 0x0092
76 #define PIE3_ADDR 0x0093
77 #define PIE4_ADDR 0x0094
78 #define WDTCON_ADDR 0x0097
79 #define ADRES_ADDR 0x009B
80 #define ADRESL_ADDR 0x009B
81 #define ADRESH_ADDR 0x009C
82 #define ADCON0_ADDR 0x009D
83 #define ADCON1_ADDR 0x009E
84 #define ADACT_ADDR 0x009F
85 #define LATA_ADDR 0x010C
86 #define LATB_ADDR 0x010D
87 #define LATC_ADDR 0x010E
88 #define CM1CON0_ADDR 0x0111
89 #define CM1CON1_ADDR 0x0112
90 #define CM2CON0_ADDR 0x0113
91 #define CM2CON1_ADDR 0x0114
92 #define CMOUT_ADDR 0x0115
93 #define BORCON_ADDR 0x0116
94 #define FVRCON_ADDR 0x0117
95 #define DACCON0_ADDR 0x0118
96 #define DACCON1_ADDR 0x0119
97 #define ANSELA_ADDR 0x018C
98 #define ANSELB_ADDR 0x018D
99 #define ANSELC_ADDR 0x018E
100 #define RC1REG_ADDR 0x0199
101 #define RCREG_ADDR 0x0199
102 #define RCREG1_ADDR 0x0199
103 #define TX1REG_ADDR 0x019A
104 #define TXREG_ADDR 0x019A
105 #define TXREG1_ADDR 0x019A
106 #define SP1BRG_ADDR 0x019B
107 #define SP1BRGL_ADDR 0x019B
108 #define SPBRG_ADDR 0x019B
109 #define SPBRG1_ADDR 0x019B
110 #define SPBRGL_ADDR 0x019B
111 #define SP1BRGH_ADDR 0x019C
112 #define SPBRGH_ADDR 0x019C
113 #define SPBRGH1_ADDR 0x019C
114 #define RC1STA_ADDR 0x019D
115 #define RCSTA_ADDR 0x019D
116 #define RCSTA1_ADDR 0x019D
117 #define TX1STA_ADDR 0x019E
118 #define TXSTA_ADDR 0x019E
119 #define TXSTA1_ADDR 0x019E
120 #define BAUD1CON_ADDR 0x019F
121 #define BAUDCON_ADDR 0x019F
122 #define BAUDCON1_ADDR 0x019F
123 #define BAUDCTL_ADDR 0x019F
124 #define BAUDCTL1_ADDR 0x019F
125 #define WPUA_ADDR 0x020C
126 #define WPUB_ADDR 0x020D
127 #define WPUC_ADDR 0x020E
128 #define SSP1BUF_ADDR 0x0211
129 #define SSPBUF_ADDR 0x0211
130 #define SSP1ADD_ADDR 0x0212
131 #define SSPADD_ADDR 0x0212
132 #define SSP1MSK_ADDR 0x0213
133 #define SSPMSK_ADDR 0x0213
134 #define SSP1STAT_ADDR 0x0214
135 #define SSPSTAT_ADDR 0x0214
136 #define SSP1CON_ADDR 0x0215
137 #define SSP1CON1_ADDR 0x0215
138 #define SSPCON_ADDR 0x0215
139 #define SSPCON1_ADDR 0x0215
140 #define SSP1CON2_ADDR 0x0216
141 #define SSPCON2_ADDR 0x0216
142 #define SSP1CON3_ADDR 0x0217
143 #define SSPCON3_ADDR 0x0217
144 #define ODCONA_ADDR 0x028C
145 #define ODCONB_ADDR 0x028D
146 #define ODCONC_ADDR 0x028E
147 #define CCPR1_ADDR 0x0291
148 #define CCPR1L_ADDR 0x0291
149 #define CCPR1H_ADDR 0x0292
150 #define CCP1CON_ADDR 0x0293
151 #define CCP1CAP_ADDR 0x0294
152 #define CCPR2_ADDR 0x0295
153 #define CCPR2L_ADDR 0x0295
154 #define CCPR2H_ADDR 0x0296
155 #define CCP2CON_ADDR 0x0297
156 #define CCP2CAP_ADDR 0x0298
157 #define CCPTMRS_ADDR 0x029F
158 #define SLRCONA_ADDR 0x030C
159 #define SLRCONB_ADDR 0x030D
160 #define SLRCONC_ADDR 0x030E
161 #define CCPR3_ADDR 0x0311
162 #define CCPR3L_ADDR 0x0311
163 #define CCPR3H_ADDR 0x0312
164 #define CCP3CON_ADDR 0x0313
165 #define CCP3CAP_ADDR 0x0314
166 #define CCPR4_ADDR 0x0315
167 #define CCPR4L_ADDR 0x0315
168 #define CCPR4H_ADDR 0x0316
169 #define CCP4CON_ADDR 0x0317
170 #define CCP4CAP_ADDR 0x0318
171 #define INLVLA_ADDR 0x038C
172 #define INLVLB_ADDR 0x038D
173 #define INLVLC_ADDR 0x038E
174 #define IOCAP_ADDR 0x0391
175 #define IOCAN_ADDR 0x0392
176 #define IOCAF_ADDR 0x0393
177 #define IOCBP_ADDR 0x0394
178 #define IOCBN_ADDR 0x0395
179 #define IOCBF_ADDR 0x0396
180 #define IOCCP_ADDR 0x0397
181 #define IOCCN_ADDR 0x0398
182 #define IOCCF_ADDR 0x0399
183 #define CLKRCON_ADDR 0x039A
184 #define MDCON_ADDR 0x039C
185 #define MDSRC_ADDR 0x039D
186 #define MDCARH_ADDR 0x039E
187 #define MDCARL_ADDR 0x039F
188 #define CCDNA_ADDR 0x040C
189 #define CCDNB_ADDR 0x040D
190 #define CCDNC_ADDR 0x040E
191 #define TMR3_ADDR 0x0411
192 #define TMR3L_ADDR 0x0411
193 #define TMR3H_ADDR 0x0412
194 #define T3CON_ADDR 0x0413
195 #define T3GCON_ADDR 0x0414
196 #define TMR4_ADDR 0x0415
197 #define PR4_ADDR 0x0416
198 #define T4CON_ADDR 0x0417
199 #define TMR5_ADDR 0x0418
200 #define TMR5L_ADDR 0x0418
201 #define TMR5H_ADDR 0x0419
202 #define T5CON_ADDR 0x041A
203 #define T5GCON_ADDR 0x041B
204 #define TMR6_ADDR 0x041C
205 #define PR6_ADDR 0x041D
206 #define T6CON_ADDR 0x041E
207 #define CCDCON_ADDR 0x041F
208 #define CCDPA_ADDR 0x048C
209 #define CCDPB_ADDR 0x048D
210 #define CCDPC_ADDR 0x048E
211 #define NCO1ACC_ADDR 0x0498
212 #define NCO1ACCL_ADDR 0x0498
213 #define NCO1ACCH_ADDR 0x0499
214 #define NCO1ACCU_ADDR 0x049A
215 #define NCO1INC_ADDR 0x049B
216 #define NCO1INCL_ADDR 0x049B
217 #define NCO1INCH_ADDR 0x049C
218 #define NCO1INCU_ADDR 0x049D
219 #define NCO1CON_ADDR 0x049E
220 #define NCO1CLK_ADDR 0x049F
221 #define PWM5DCL_ADDR 0x0617
222 #define PWM5DCH_ADDR 0x0618
223 #define PWM5CON_ADDR 0x0619
224 #define PWM5CON0_ADDR 0x0619
225 #define PWM6DCL_ADDR 0x061A
226 #define PWM6DCH_ADDR 0x061B
227 #define PWM6CON_ADDR 0x061C
228 #define PWM6CON0_ADDR 0x061C
229 #define PWMTMRS_ADDR 0x061F
230 #define CWG1CLKCON_ADDR 0x0691
231 #define CWG1DAT_ADDR 0x0692
232 #define CWG1DBR_ADDR 0x0693
233 #define CWG1DBF_ADDR 0x0694
234 #define CWG1CON0_ADDR 0x0695
235 #define CWG1CON1_ADDR 0x0696
236 #define CWG1AS0_ADDR 0x0697
237 #define CWG1AS1_ADDR 0x0698
238 #define CWG1STR_ADDR 0x0699
239 #define CWG2CLKCON_ADDR 0x0711
240 #define CWG2DAT_ADDR 0x0712
241 #define CWG2DBR_ADDR 0x0713
242 #define CWG2DBF_ADDR 0x0714
243 #define CWG2CON0_ADDR 0x0715
244 #define CWG2CON1_ADDR 0x0716
245 #define CWG2AS0_ADDR 0x0717
246 #define CWG2AS1_ADDR 0x0718
247 #define CWG2STR_ADDR 0x0719
248 #define NVMADR_ADDR 0x0891
249 #define NVMADRL_ADDR 0x0891
250 #define NVMADRH_ADDR 0x0892
251 #define NVMDAT_ADDR 0x0893
252 #define NVMDATL_ADDR 0x0893
253 #define NVMDATH_ADDR 0x0894
254 #define NVMCON1_ADDR 0x0895
255 #define NVMCON2_ADDR 0x0896
256 #define PCON0_ADDR 0x089B
257 #define PMD0_ADDR 0x0911
258 #define PMD1_ADDR 0x0912
259 #define PMD2_ADDR 0x0913
260 #define PMD3_ADDR 0x0914
261 #define PMD4_ADDR 0x0915
262 #define PMD5_ADDR 0x0916
263 #define CPUDOZE_ADDR 0x0918
264 #define OSCCON1_ADDR 0x0919
265 #define OSCCON2_ADDR 0x091A
266 #define OSCCON3_ADDR 0x091B
267 #define OSCSTAT1_ADDR 0x091C
268 #define OSCEN_ADDR 0x091D
269 #define OSCTUNE_ADDR 0x091E
270 #define OSCFRQ_ADDR 0x091F
271 #define PPSLOCK_ADDR 0x0E0F
272 #define INTPPS_ADDR 0x0E10
273 #define T0CKIPPS_ADDR 0x0E11
274 #define T1CKIPPS_ADDR 0x0E12
275 #define T1GPPS_ADDR 0x0E13
276 #define CCP1PPS_ADDR 0x0E14
277 #define CCP2PPS_ADDR 0x0E15
278 #define CCP3PPS_ADDR 0x0E16
279 #define CCP4PPS_ADDR 0x0E17
280 #define CWG1PPS_ADDR 0x0E18
281 #define CWG2PPS_ADDR 0x0E19
282 #define MDCIN1PPS_ADDR 0x0E1A
283 #define MDCIN2PPS_ADDR 0x0E1B
284 #define MDMINPPS_ADDR 0x0E1C
285 #define SSP1CLKPPS_ADDR 0x0E20
286 #define SSP1DATPPS_ADDR 0x0E21
287 #define SSP1SSPPS_ADDR 0x0E22
288 #define RXPPS_ADDR 0x0E24
289 #define TXPPS_ADDR 0x0E25
290 #define CLCIN0PPS_ADDR 0x0E28
291 #define CLCIN1PPS_ADDR 0x0E29
292 #define CLCIN2PPS_ADDR 0x0E2A
293 #define CLCIN3PPS_ADDR 0x0E2B
294 #define T3CKIPPS_ADDR 0x0E2C
295 #define T3GPPS_ADDR 0x0E2D
296 #define T5CKIPPS_ADDR 0x0E2E
297 #define T5GPPS_ADDR 0x0E2F
298 #define RA0PPS_ADDR 0x0E90
299 #define RA1PPS_ADDR 0x0E91
300 #define RA2PPS_ADDR 0x0E92
301 #define RA4PPS_ADDR 0x0E94
302 #define RA5PPS_ADDR 0x0E95
303 #define RB4PPS_ADDR 0x0E9C
304 #define RB5PPS_ADDR 0x0E9D
305 #define RB6PPS_ADDR 0x0E9E
306 #define RB7PPS_ADDR 0x0E9F
307 #define RC0PPS_ADDR 0x0EA0
308 #define RC1PPS_ADDR 0x0EA1
309 #define RC2PPS_ADDR 0x0EA2
310 #define RC3PPS_ADDR 0x0EA3
311 #define RC4PPS_ADDR 0x0EA4
312 #define RC5PPS_ADDR 0x0EA5
313 #define RC6PPS_ADDR 0x0EA6
314 #define RC7PPS_ADDR 0x0EA7
315 #define CLCDATA_ADDR 0x0F0F
316 #define CLC1CON_ADDR 0x0F10
317 #define CLC1POL_ADDR 0x0F11
318 #define CLC1SEL0_ADDR 0x0F12
319 #define CLC1SEL1_ADDR 0x0F13
320 #define CLC1SEL2_ADDR 0x0F14
321 #define CLC1SEL3_ADDR 0x0F15
322 #define CLC1GLS0_ADDR 0x0F16
323 #define CLC1GLS1_ADDR 0x0F17
324 #define CLC1GLS2_ADDR 0x0F18
325 #define CLC1GLS3_ADDR 0x0F19
326 #define CLC2CON_ADDR 0x0F1A
327 #define CLC2POL_ADDR 0x0F1B
328 #define CLC2SEL0_ADDR 0x0F1C
329 #define CLC2SEL1_ADDR 0x0F1D
330 #define CLC2SEL2_ADDR 0x0F1E
331 #define CLC2SEL3_ADDR 0x0F1F
332 #define CLC2GLS0_ADDR 0x0F20
333 #define CLC2GLS1_ADDR 0x0F21
334 #define CLC2GLS2_ADDR 0x0F22
335 #define CLC2GLS3_ADDR 0x0F23
336 #define CLC3CON_ADDR 0x0F24
337 #define CLC3POL_ADDR 0x0F25
338 #define CLC3SEL0_ADDR 0x0F26
339 #define CLC3SEL1_ADDR 0x0F27
340 #define CLC3SEL2_ADDR 0x0F28
341 #define CLC3SEL3_ADDR 0x0F29
342 #define CLC3GLS0_ADDR 0x0F2A
343 #define CLC3GLS1_ADDR 0x0F2B
344 #define CLC3GLS2_ADDR 0x0F2C
345 #define CLC3GLS3_ADDR 0x0F2D
346 #define CLC4CON_ADDR 0x0F2E
347 #define CLC4POL_ADDR 0x0F2F
348 #define CLC4SEL0_ADDR 0x0F30
349 #define CLC4SEL1_ADDR 0x0F31
350 #define CLC4SEL2_ADDR 0x0F32
351 #define CLC4SEL3_ADDR 0x0F33
352 #define CLC4GLS0_ADDR 0x0F34
353 #define CLC4GLS1_ADDR 0x0F35
354 #define CLC4GLS2_ADDR 0x0F36
355 #define CLC4GLS3_ADDR 0x0F37
356 #define STATUS_SHAD_ADDR 0x0FE4
357 #define WREG_SHAD_ADDR 0x0FE5
358 #define BSR_SHAD_ADDR 0x0FE6
359 #define PCLATH_SHAD_ADDR 0x0FE7
360 #define FSR0L_SHAD_ADDR 0x0FE8
361 #define FSR0H_SHAD_ADDR 0x0FE9
362 #define FSR1L_SHAD_ADDR 0x0FEA
363 #define FSR1H_SHAD_ADDR 0x0FEB
364 #define STKPTR_ADDR 0x0FED
365 #define TOSL_ADDR 0x0FEE
366 #define TOSH_ADDR 0x0FEF
368 #endif // #ifndef NO_ADDR_DEFINES
370 //==============================================================================
372 // Register Definitions
374 //==============================================================================
376 extern __at(0x0000) __sfr INDF0
;
377 extern __at(0x0001) __sfr INDF1
;
378 extern __at(0x0002) __sfr PCL
;
380 //==============================================================================
383 extern __at(0x0003) __sfr STATUS
;
397 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
405 //==============================================================================
407 extern __at(0x0004) __sfr FSR0
;
408 extern __at(0x0004) __sfr FSR0L
;
409 extern __at(0x0005) __sfr FSR0H
;
410 extern __at(0x0006) __sfr FSR1
;
411 extern __at(0x0006) __sfr FSR1L
;
412 extern __at(0x0007) __sfr FSR1H
;
414 //==============================================================================
417 extern __at(0x0008) __sfr BSR
;
440 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
448 //==============================================================================
450 extern __at(0x0009) __sfr WREG
;
451 extern __at(0x000A) __sfr PCLATH
;
453 //==============================================================================
456 extern __at(0x000B) __sfr INTCON
;
470 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
476 //==============================================================================
479 //==============================================================================
482 extern __at(0x000C) __sfr PORTA
;
505 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
514 //==============================================================================
517 //==============================================================================
520 extern __at(0x000D) __sfr PORTB
;
534 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
541 //==============================================================================
544 //==============================================================================
547 extern __at(0x000E) __sfr PORTC
;
561 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
572 //==============================================================================
575 //==============================================================================
578 extern __at(0x0010) __sfr PIR0
;
592 extern __at(0x0010) volatile __PIR0bits_t PIR0bits
;
598 //==============================================================================
601 //==============================================================================
604 extern __at(0x0011) __sfr PIR1
;
615 unsigned TMR1GIF
: 1;
618 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
627 #define _TMR1GIF 0x80
629 //==============================================================================
632 //==============================================================================
635 extern __at(0x0012) __sfr PIR2
;
649 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
658 //==============================================================================
661 //==============================================================================
664 extern __at(0x0013) __sfr PIR3
;
673 unsigned TMR3GIF
: 1;
678 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
685 #define _TMR3GIF 0x20
689 //==============================================================================
692 //==============================================================================
695 extern __at(0x0014) __sfr PIR4
;
704 unsigned TMR5GIF
: 1;
709 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
716 #define _TMR5GIF 0x20
720 //==============================================================================
723 //==============================================================================
726 extern __at(0x0015) __sfr TMR0L
;
740 extern __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits
;
751 //==============================================================================
754 //==============================================================================
757 extern __at(0x0016) __sfr TMR0H
;
771 extern __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits
;
782 //==============================================================================
785 //==============================================================================
788 extern __at(0x0017) __sfr T0CON0
;
794 unsigned T0OUTPS0
: 1;
795 unsigned T0OUTPS1
: 1;
796 unsigned T0OUTPS2
: 1;
797 unsigned T0OUTPS3
: 1;
798 unsigned T016BIT
: 1;
806 unsigned T0OUTPS
: 4;
811 extern __at(0x0017) volatile __T0CON0bits_t T0CON0bits
;
813 #define _T0OUTPS0 0x01
814 #define _T0OUTPS1 0x02
815 #define _T0OUTPS2 0x04
816 #define _T0OUTPS3 0x08
817 #define _T016BIT 0x10
821 //==============================================================================
824 //==============================================================================
827 extern __at(0x0018) __sfr T0CON1
;
833 unsigned T0CKPS0
: 1;
834 unsigned T0CKPS1
: 1;
835 unsigned T0CKPS2
: 1;
836 unsigned T0CKPS3
: 1;
837 unsigned T0ASYNC
: 1;
856 extern __at(0x0018) volatile __T0CON1bits_t T0CON1bits
;
858 #define _T0CKPS0 0x01
859 #define _T0CKPS1 0x02
860 #define _T0CKPS2 0x04
861 #define _T0CKPS3 0x08
862 #define _T0ASYNC 0x10
867 //==============================================================================
869 extern __at(0x0019) __sfr TMR1
;
870 extern __at(0x0019) __sfr TMR1L
;
871 extern __at(0x001A) __sfr TMR1H
;
873 //==============================================================================
876 extern __at(0x001B) __sfr T1CON
;
886 unsigned T1CKPS0
: 1;
887 unsigned T1CKPS1
: 1;
888 unsigned TMR1CS0
: 1;
889 unsigned TMR1CS1
: 1;
906 extern __at(0x001B) volatile __T1CONbits_t T1CONbits
;
911 #define _T1CKPS0 0x10
912 #define _T1CKPS1 0x20
913 #define _TMR1CS0 0x40
914 #define _TMR1CS1 0x80
916 //==============================================================================
919 //==============================================================================
922 extern __at(0x001C) __sfr T1GCON
;
931 unsigned T1GGO_NOT_DONE
: 1;
945 extern __at(0x001C) volatile __T1GCONbits_t T1GCONbits
;
950 #define _T1GGO_NOT_DONE 0x08
956 //==============================================================================
958 extern __at(0x001D) __sfr TMR2
;
959 extern __at(0x001E) __sfr PR2
;
961 //==============================================================================
964 extern __at(0x001F) __sfr T2CON
;
970 unsigned T2CKPS0
: 1;
971 unsigned T2CKPS1
: 1;
973 unsigned T2OUTPS0
: 1;
974 unsigned T2OUTPS1
: 1;
975 unsigned T2OUTPS2
: 1;
976 unsigned T2OUTPS3
: 1;
989 unsigned T2OUTPS
: 4;
994 extern __at(0x001F) volatile __T2CONbits_t T2CONbits
;
996 #define _T2CKPS0 0x01
997 #define _T2CKPS1 0x02
999 #define _T2OUTPS0 0x08
1000 #define _T2OUTPS1 0x10
1001 #define _T2OUTPS2 0x20
1002 #define _T2OUTPS3 0x40
1004 //==============================================================================
1007 //==============================================================================
1010 extern __at(0x008C) __sfr TRISA
;
1014 unsigned TRISA0
: 1;
1015 unsigned TRISA1
: 1;
1016 unsigned TRISA2
: 1;
1018 unsigned TRISA4
: 1;
1019 unsigned TRISA5
: 1;
1024 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1026 #define _TRISA0 0x01
1027 #define _TRISA1 0x02
1028 #define _TRISA2 0x04
1029 #define _TRISA4 0x10
1030 #define _TRISA5 0x20
1032 //==============================================================================
1035 //==============================================================================
1038 extern __at(0x008D) __sfr TRISB
;
1046 unsigned TRISB4
: 1;
1047 unsigned TRISB5
: 1;
1048 unsigned TRISB6
: 1;
1049 unsigned TRISB7
: 1;
1052 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
1054 #define _TRISB4 0x10
1055 #define _TRISB5 0x20
1056 #define _TRISB6 0x40
1057 #define _TRISB7 0x80
1059 //==============================================================================
1062 //==============================================================================
1065 extern __at(0x008E) __sfr TRISC
;
1069 unsigned TRISC0
: 1;
1070 unsigned TRISC1
: 1;
1071 unsigned TRISC2
: 1;
1072 unsigned TRISC3
: 1;
1073 unsigned TRISC4
: 1;
1074 unsigned TRISC5
: 1;
1075 unsigned TRISC6
: 1;
1076 unsigned TRISC7
: 1;
1079 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1081 #define _TRISC0 0x01
1082 #define _TRISC1 0x02
1083 #define _TRISC2 0x04
1084 #define _TRISC3 0x08
1085 #define _TRISC4 0x10
1086 #define _TRISC5 0x20
1087 #define _TRISC6 0x40
1088 #define _TRISC7 0x80
1090 //==============================================================================
1093 //==============================================================================
1096 extern __at(0x0090) __sfr PIE0
;
1105 unsigned TMR0IE
: 1;
1110 extern __at(0x0090) volatile __PIE0bits_t PIE0bits
;
1114 #define _TMR0IE 0x20
1116 //==============================================================================
1119 //==============================================================================
1122 extern __at(0x0091) __sfr PIE1
;
1126 unsigned TMR1IE
: 1;
1127 unsigned TMR2IE
: 1;
1128 unsigned BCL1IE
: 1;
1129 unsigned SSP1IE
: 1;
1133 unsigned TMR1GIE
: 1;
1136 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1138 #define _TMR1IE 0x01
1139 #define _TMR2IE 0x02
1140 #define _BCL1IE 0x04
1141 #define _SSP1IE 0x08
1145 #define _TMR1GIE 0x80
1147 //==============================================================================
1150 //==============================================================================
1153 extern __at(0x0092) __sfr PIE2
;
1157 unsigned NCO1IE
: 1;
1158 unsigned TMR4IE
: 1;
1164 unsigned TMR6IE
: 1;
1167 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1169 #define _NCO1IE 0x01
1170 #define _TMR4IE 0x02
1174 #define _TMR6IE 0x80
1176 //==============================================================================
1179 //==============================================================================
1182 extern __at(0x0093) __sfr PIE3
;
1186 unsigned CLC1IE
: 1;
1187 unsigned CLC2IE
: 1;
1188 unsigned CLC3IE
: 1;
1189 unsigned CLC4IE
: 1;
1190 unsigned TMR3IE
: 1;
1191 unsigned TMR3GIE
: 1;
1196 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1198 #define _CLC1IE 0x01
1199 #define _CLC2IE 0x02
1200 #define _CLC3IE 0x04
1201 #define _CLC4IE 0x08
1202 #define _TMR3IE 0x10
1203 #define _TMR3GIE 0x20
1207 //==============================================================================
1210 //==============================================================================
1213 extern __at(0x0094) __sfr PIE4
;
1217 unsigned CCP1IE
: 1;
1218 unsigned CCP2IE
: 1;
1219 unsigned CCP3IE
: 1;
1220 unsigned CCP4IE
: 1;
1221 unsigned TMR5IE
: 1;
1222 unsigned TMR5GIE
: 1;
1223 unsigned CWG1IE
: 1;
1224 unsigned CWG2IE
: 1;
1227 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1229 #define _CCP1IE 0x01
1230 #define _CCP2IE 0x02
1231 #define _CCP3IE 0x04
1232 #define _CCP4IE 0x08
1233 #define _TMR5IE 0x10
1234 #define _TMR5GIE 0x20
1235 #define _CWG1IE 0x40
1236 #define _CWG2IE 0x80
1238 //==============================================================================
1241 //==============================================================================
1244 extern __at(0x0097) __sfr WDTCON
;
1250 unsigned SWDTEN
: 1;
1251 unsigned WDTPS0
: 1;
1252 unsigned WDTPS1
: 1;
1253 unsigned WDTPS2
: 1;
1254 unsigned WDTPS3
: 1;
1255 unsigned WDTPS4
: 1;
1268 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1270 #define _SWDTEN 0x01
1271 #define _WDTPS0 0x02
1272 #define _WDTPS1 0x04
1273 #define _WDTPS2 0x08
1274 #define _WDTPS3 0x10
1275 #define _WDTPS4 0x20
1277 //==============================================================================
1279 extern __at(0x009B) __sfr ADRES
;
1280 extern __at(0x009B) __sfr ADRESL
;
1281 extern __at(0x009C) __sfr ADRESH
;
1283 //==============================================================================
1286 extern __at(0x009D) __sfr ADCON0
;
1293 unsigned GO_NOT_DONE
: 1;
1333 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1336 #define _GO_NOT_DONE 0x02
1346 //==============================================================================
1349 //==============================================================================
1352 extern __at(0x009E) __sfr ADCON1
;
1358 unsigned ADPREF0
: 1;
1359 unsigned ADPREF1
: 1;
1360 unsigned ADNREF
: 1;
1370 unsigned ADPREF
: 2;
1382 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1384 #define _ADPREF0 0x01
1385 #define _ADPREF1 0x02
1386 #define _ADNREF 0x04
1392 //==============================================================================
1395 //==============================================================================
1398 extern __at(0x009F) __sfr ADACT
;
1404 unsigned ADACT0
: 1;
1405 unsigned ADACT1
: 1;
1406 unsigned ADACT2
: 1;
1407 unsigned ADACT3
: 1;
1408 unsigned ADACT4
: 1;
1421 extern __at(0x009F) volatile __ADACTbits_t ADACTbits
;
1423 #define _ADACT0 0x01
1424 #define _ADACT1 0x02
1425 #define _ADACT2 0x04
1426 #define _ADACT3 0x08
1427 #define _ADACT4 0x10
1429 //==============================================================================
1432 //==============================================================================
1435 extern __at(0x010C) __sfr LATA
;
1449 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1457 //==============================================================================
1460 //==============================================================================
1463 extern __at(0x010D) __sfr LATB
;
1477 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
1484 //==============================================================================
1487 //==============================================================================
1490 extern __at(0x010E) __sfr LATC
;
1504 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1515 //==============================================================================
1518 //==============================================================================
1521 extern __at(0x0111) __sfr CM1CON0
;
1525 unsigned C1SYNC
: 1;
1535 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1537 #define _C1SYNC 0x01
1544 //==============================================================================
1547 //==============================================================================
1550 extern __at(0x0112) __sfr CM1CON1
;
1556 unsigned C1NCH0
: 1;
1557 unsigned C1NCH1
: 1;
1558 unsigned C1NCH2
: 1;
1559 unsigned C1PCH0
: 1;
1560 unsigned C1PCH1
: 1;
1561 unsigned C1PCH2
: 1;
1562 unsigned C1INTN
: 1;
1563 unsigned C1INTP
: 1;
1580 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1582 #define _C1NCH0 0x01
1583 #define _C1NCH1 0x02
1584 #define _C1NCH2 0x04
1585 #define _C1PCH0 0x08
1586 #define _C1PCH1 0x10
1587 #define _C1PCH2 0x20
1588 #define _C1INTN 0x40
1589 #define _C1INTP 0x80
1591 //==============================================================================
1594 //==============================================================================
1597 extern __at(0x0113) __sfr CM2CON0
;
1601 unsigned C2SYNC
: 1;
1611 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1613 #define _C2SYNC 0x01
1620 //==============================================================================
1623 //==============================================================================
1626 extern __at(0x0114) __sfr CM2CON1
;
1632 unsigned C2NCH0
: 1;
1633 unsigned C2NCH1
: 1;
1634 unsigned C2NCH2
: 1;
1635 unsigned C2PCH0
: 1;
1636 unsigned C2PCH1
: 1;
1637 unsigned C2PCH2
: 1;
1638 unsigned C2INTN
: 1;
1639 unsigned C2INTP
: 1;
1656 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1658 #define _C2NCH0 0x01
1659 #define _C2NCH1 0x02
1660 #define _C2NCH2 0x04
1661 #define _C2PCH0 0x08
1662 #define _C2PCH1 0x10
1663 #define _C2PCH2 0x20
1664 #define _C2INTN 0x40
1665 #define _C2INTP 0x80
1667 //==============================================================================
1670 //==============================================================================
1673 extern __at(0x0115) __sfr CMOUT
;
1677 unsigned MC1OUT
: 1;
1678 unsigned MC2OUT
: 1;
1687 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1689 #define _MC1OUT 0x01
1690 #define _MC2OUT 0x02
1692 //==============================================================================
1695 //==============================================================================
1698 extern __at(0x0116) __sfr BORCON
;
1702 unsigned BORRDY
: 1;
1709 unsigned SBOREN
: 1;
1712 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1714 #define _BORRDY 0x01
1715 #define _SBOREN 0x80
1717 //==============================================================================
1720 //==============================================================================
1723 extern __at(0x0117) __sfr FVRCON
;
1729 unsigned ADFVR0
: 1;
1730 unsigned ADFVR1
: 1;
1731 unsigned CDAFVR0
: 1;
1732 unsigned CDAFVR1
: 1;
1735 unsigned FVRRDY
: 1;
1748 unsigned CDAFVR
: 2;
1753 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1755 #define _ADFVR0 0x01
1756 #define _ADFVR1 0x02
1757 #define _CDAFVR0 0x04
1758 #define _CDAFVR1 0x08
1761 #define _FVRRDY 0x40
1764 //==============================================================================
1767 //==============================================================================
1770 extern __at(0x0118) __sfr DACCON0
;
1776 unsigned DAC1NSS
: 1;
1778 unsigned DAC1PSS0
: 1;
1779 unsigned DAC1PSS1
: 1;
1781 unsigned DAC1OE
: 1;
1783 unsigned DAC1EN
: 1;
1789 unsigned DAC1PSS
: 2;
1794 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1796 #define _DAC1NSS 0x01
1797 #define _DAC1PSS0 0x04
1798 #define _DAC1PSS1 0x08
1799 #define _DAC1OE 0x20
1800 #define _DAC1EN 0x80
1802 //==============================================================================
1805 //==============================================================================
1808 extern __at(0x0119) __sfr DACCON1
;
1814 unsigned DAC1R0
: 1;
1815 unsigned DAC1R1
: 1;
1816 unsigned DAC1R2
: 1;
1817 unsigned DAC1R3
: 1;
1818 unsigned DAC1R4
: 1;
1831 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1833 #define _DAC1R0 0x01
1834 #define _DAC1R1 0x02
1835 #define _DAC1R2 0x04
1836 #define _DAC1R3 0x08
1837 #define _DAC1R4 0x10
1839 //==============================================================================
1842 //==============================================================================
1845 extern __at(0x018C) __sfr ANSELA
;
1859 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1867 //==============================================================================
1870 //==============================================================================
1873 extern __at(0x018D) __sfr ANSELB
;
1887 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
1894 //==============================================================================
1897 //==============================================================================
1900 extern __at(0x018E) __sfr ANSELC
;
1914 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1925 //==============================================================================
1927 extern __at(0x0199) __sfr RC1REG
;
1928 extern __at(0x0199) __sfr RCREG
;
1929 extern __at(0x0199) __sfr RCREG1
;
1930 extern __at(0x019A) __sfr TX1REG
;
1931 extern __at(0x019A) __sfr TXREG
;
1932 extern __at(0x019A) __sfr TXREG1
;
1933 extern __at(0x019B) __sfr SP1BRG
;
1934 extern __at(0x019B) __sfr SP1BRGL
;
1935 extern __at(0x019B) __sfr SPBRG
;
1936 extern __at(0x019B) __sfr SPBRG1
;
1937 extern __at(0x019B) __sfr SPBRGL
;
1938 extern __at(0x019C) __sfr SP1BRGH
;
1939 extern __at(0x019C) __sfr SPBRGH
;
1940 extern __at(0x019C) __sfr SPBRGH1
;
1942 //==============================================================================
1945 extern __at(0x019D) __sfr RC1STA
;
1959 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1970 //==============================================================================
1973 //==============================================================================
1976 extern __at(0x019D) __sfr RCSTA
;
1990 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1992 #define _RCSTA_RX9D 0x01
1993 #define _RCSTA_OERR 0x02
1994 #define _RCSTA_FERR 0x04
1995 #define _RCSTA_ADDEN 0x08
1996 #define _RCSTA_CREN 0x10
1997 #define _RCSTA_SREN 0x20
1998 #define _RCSTA_RX9 0x40
1999 #define _RCSTA_SPEN 0x80
2001 //==============================================================================
2004 //==============================================================================
2007 extern __at(0x019D) __sfr RCSTA1
;
2021 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
2023 #define _RCSTA1_RX9D 0x01
2024 #define _RCSTA1_OERR 0x02
2025 #define _RCSTA1_FERR 0x04
2026 #define _RCSTA1_ADDEN 0x08
2027 #define _RCSTA1_CREN 0x10
2028 #define _RCSTA1_SREN 0x20
2029 #define _RCSTA1_RX9 0x40
2030 #define _RCSTA1_SPEN 0x80
2032 //==============================================================================
2035 //==============================================================================
2038 extern __at(0x019E) __sfr TX1STA
;
2052 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
2063 //==============================================================================
2066 //==============================================================================
2069 extern __at(0x019E) __sfr TXSTA
;
2083 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2085 #define _TXSTA_TX9D 0x01
2086 #define _TXSTA_TRMT 0x02
2087 #define _TXSTA_BRGH 0x04
2088 #define _TXSTA_SENDB 0x08
2089 #define _TXSTA_SYNC 0x10
2090 #define _TXSTA_TXEN 0x20
2091 #define _TXSTA_TX9 0x40
2092 #define _TXSTA_CSRC 0x80
2094 //==============================================================================
2097 //==============================================================================
2100 extern __at(0x019E) __sfr TXSTA1
;
2114 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2116 #define _TXSTA1_TX9D 0x01
2117 #define _TXSTA1_TRMT 0x02
2118 #define _TXSTA1_BRGH 0x04
2119 #define _TXSTA1_SENDB 0x08
2120 #define _TXSTA1_SYNC 0x10
2121 #define _TXSTA1_TXEN 0x20
2122 #define _TXSTA1_TX9 0x40
2123 #define _TXSTA1_CSRC 0x80
2125 //==============================================================================
2128 //==============================================================================
2131 extern __at(0x019F) __sfr BAUD1CON
;
2142 unsigned ABDOVF
: 1;
2145 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2152 #define _ABDOVF 0x80
2154 //==============================================================================
2157 //==============================================================================
2160 extern __at(0x019F) __sfr BAUDCON
;
2171 unsigned ABDOVF
: 1;
2174 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2176 #define _BAUDCON_ABDEN 0x01
2177 #define _BAUDCON_WUE 0x02
2178 #define _BAUDCON_BRG16 0x08
2179 #define _BAUDCON_SCKP 0x10
2180 #define _BAUDCON_RCIDL 0x40
2181 #define _BAUDCON_ABDOVF 0x80
2183 //==============================================================================
2186 //==============================================================================
2189 extern __at(0x019F) __sfr BAUDCON1
;
2200 unsigned ABDOVF
: 1;
2203 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2205 #define _BAUDCON1_ABDEN 0x01
2206 #define _BAUDCON1_WUE 0x02
2207 #define _BAUDCON1_BRG16 0x08
2208 #define _BAUDCON1_SCKP 0x10
2209 #define _BAUDCON1_RCIDL 0x40
2210 #define _BAUDCON1_ABDOVF 0x80
2212 //==============================================================================
2215 //==============================================================================
2218 extern __at(0x019F) __sfr BAUDCTL
;
2229 unsigned ABDOVF
: 1;
2232 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2234 #define _BAUDCTL_ABDEN 0x01
2235 #define _BAUDCTL_WUE 0x02
2236 #define _BAUDCTL_BRG16 0x08
2237 #define _BAUDCTL_SCKP 0x10
2238 #define _BAUDCTL_RCIDL 0x40
2239 #define _BAUDCTL_ABDOVF 0x80
2241 //==============================================================================
2244 //==============================================================================
2247 extern __at(0x019F) __sfr BAUDCTL1
;
2258 unsigned ABDOVF
: 1;
2261 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2263 #define _BAUDCTL1_ABDEN 0x01
2264 #define _BAUDCTL1_WUE 0x02
2265 #define _BAUDCTL1_BRG16 0x08
2266 #define _BAUDCTL1_SCKP 0x10
2267 #define _BAUDCTL1_RCIDL 0x40
2268 #define _BAUDCTL1_ABDOVF 0x80
2270 //==============================================================================
2273 //==============================================================================
2276 extern __at(0x020C) __sfr WPUA
;
2299 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2308 //==============================================================================
2311 //==============================================================================
2314 extern __at(0x020D) __sfr WPUB
;
2328 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
2335 //==============================================================================
2338 //==============================================================================
2341 extern __at(0x020E) __sfr WPUC
;
2355 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2366 //==============================================================================
2369 //==============================================================================
2372 extern __at(0x0211) __sfr SSP1BUF
;
2378 unsigned SSP1BUF0
: 1;
2379 unsigned SSP1BUF1
: 1;
2380 unsigned SSP1BUF2
: 1;
2381 unsigned SSP1BUF3
: 1;
2382 unsigned SSP1BUF4
: 1;
2383 unsigned SSP1BUF5
: 1;
2384 unsigned SSP1BUF6
: 1;
2385 unsigned SSP1BUF7
: 1;
2401 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2403 #define _SSP1BUF0 0x01
2405 #define _SSP1BUF1 0x02
2407 #define _SSP1BUF2 0x04
2409 #define _SSP1BUF3 0x08
2411 #define _SSP1BUF4 0x10
2413 #define _SSP1BUF5 0x20
2415 #define _SSP1BUF6 0x40
2417 #define _SSP1BUF7 0x80
2420 //==============================================================================
2423 //==============================================================================
2426 extern __at(0x0211) __sfr SSPBUF
;
2432 unsigned SSP1BUF0
: 1;
2433 unsigned SSP1BUF1
: 1;
2434 unsigned SSP1BUF2
: 1;
2435 unsigned SSP1BUF3
: 1;
2436 unsigned SSP1BUF4
: 1;
2437 unsigned SSP1BUF5
: 1;
2438 unsigned SSP1BUF6
: 1;
2439 unsigned SSP1BUF7
: 1;
2455 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2457 #define _SSPBUF_SSP1BUF0 0x01
2458 #define _SSPBUF_BUF0 0x01
2459 #define _SSPBUF_SSP1BUF1 0x02
2460 #define _SSPBUF_BUF1 0x02
2461 #define _SSPBUF_SSP1BUF2 0x04
2462 #define _SSPBUF_BUF2 0x04
2463 #define _SSPBUF_SSP1BUF3 0x08
2464 #define _SSPBUF_BUF3 0x08
2465 #define _SSPBUF_SSP1BUF4 0x10
2466 #define _SSPBUF_BUF4 0x10
2467 #define _SSPBUF_SSP1BUF5 0x20
2468 #define _SSPBUF_BUF5 0x20
2469 #define _SSPBUF_SSP1BUF6 0x40
2470 #define _SSPBUF_BUF6 0x40
2471 #define _SSPBUF_SSP1BUF7 0x80
2472 #define _SSPBUF_BUF7 0x80
2474 //==============================================================================
2477 //==============================================================================
2480 extern __at(0x0212) __sfr SSP1ADD
;
2486 unsigned SSP1ADD0
: 1;
2487 unsigned SSP1ADD1
: 1;
2488 unsigned SSP1ADD2
: 1;
2489 unsigned SSP1ADD3
: 1;
2490 unsigned SSP1ADD4
: 1;
2491 unsigned SSP1ADD5
: 1;
2492 unsigned SSP1ADD6
: 1;
2493 unsigned SSP1ADD7
: 1;
2509 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2511 #define _SSP1ADD0 0x01
2513 #define _SSP1ADD1 0x02
2515 #define _SSP1ADD2 0x04
2517 #define _SSP1ADD3 0x08
2519 #define _SSP1ADD4 0x10
2521 #define _SSP1ADD5 0x20
2523 #define _SSP1ADD6 0x40
2525 #define _SSP1ADD7 0x80
2528 //==============================================================================
2531 //==============================================================================
2534 extern __at(0x0212) __sfr SSPADD
;
2540 unsigned SSP1ADD0
: 1;
2541 unsigned SSP1ADD1
: 1;
2542 unsigned SSP1ADD2
: 1;
2543 unsigned SSP1ADD3
: 1;
2544 unsigned SSP1ADD4
: 1;
2545 unsigned SSP1ADD5
: 1;
2546 unsigned SSP1ADD6
: 1;
2547 unsigned SSP1ADD7
: 1;
2563 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2565 #define _SSPADD_SSP1ADD0 0x01
2566 #define _SSPADD_ADD0 0x01
2567 #define _SSPADD_SSP1ADD1 0x02
2568 #define _SSPADD_ADD1 0x02
2569 #define _SSPADD_SSP1ADD2 0x04
2570 #define _SSPADD_ADD2 0x04
2571 #define _SSPADD_SSP1ADD3 0x08
2572 #define _SSPADD_ADD3 0x08
2573 #define _SSPADD_SSP1ADD4 0x10
2574 #define _SSPADD_ADD4 0x10
2575 #define _SSPADD_SSP1ADD5 0x20
2576 #define _SSPADD_ADD5 0x20
2577 #define _SSPADD_SSP1ADD6 0x40
2578 #define _SSPADD_ADD6 0x40
2579 #define _SSPADD_SSP1ADD7 0x80
2580 #define _SSPADD_ADD7 0x80
2582 //==============================================================================
2585 //==============================================================================
2588 extern __at(0x0213) __sfr SSP1MSK
;
2594 unsigned SSP1MSK0
: 1;
2595 unsigned SSP1MSK1
: 1;
2596 unsigned SSP1MSK2
: 1;
2597 unsigned SSP1MSK3
: 1;
2598 unsigned SSP1MSK4
: 1;
2599 unsigned SSP1MSK5
: 1;
2600 unsigned SSP1MSK6
: 1;
2601 unsigned SSP1MSK7
: 1;
2617 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2619 #define _SSP1MSK0 0x01
2621 #define _SSP1MSK1 0x02
2623 #define _SSP1MSK2 0x04
2625 #define _SSP1MSK3 0x08
2627 #define _SSP1MSK4 0x10
2629 #define _SSP1MSK5 0x20
2631 #define _SSP1MSK6 0x40
2633 #define _SSP1MSK7 0x80
2636 //==============================================================================
2639 //==============================================================================
2642 extern __at(0x0213) __sfr SSPMSK
;
2648 unsigned SSP1MSK0
: 1;
2649 unsigned SSP1MSK1
: 1;
2650 unsigned SSP1MSK2
: 1;
2651 unsigned SSP1MSK3
: 1;
2652 unsigned SSP1MSK4
: 1;
2653 unsigned SSP1MSK5
: 1;
2654 unsigned SSP1MSK6
: 1;
2655 unsigned SSP1MSK7
: 1;
2671 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2673 #define _SSPMSK_SSP1MSK0 0x01
2674 #define _SSPMSK_MSK0 0x01
2675 #define _SSPMSK_SSP1MSK1 0x02
2676 #define _SSPMSK_MSK1 0x02
2677 #define _SSPMSK_SSP1MSK2 0x04
2678 #define _SSPMSK_MSK2 0x04
2679 #define _SSPMSK_SSP1MSK3 0x08
2680 #define _SSPMSK_MSK3 0x08
2681 #define _SSPMSK_SSP1MSK4 0x10
2682 #define _SSPMSK_MSK4 0x10
2683 #define _SSPMSK_SSP1MSK5 0x20
2684 #define _SSPMSK_MSK5 0x20
2685 #define _SSPMSK_SSP1MSK6 0x40
2686 #define _SSPMSK_MSK6 0x40
2687 #define _SSPMSK_SSP1MSK7 0x80
2688 #define _SSPMSK_MSK7 0x80
2690 //==============================================================================
2693 //==============================================================================
2696 extern __at(0x0214) __sfr SSP1STAT
;
2702 unsigned R_NOT_W
: 1;
2705 unsigned D_NOT_A
: 1;
2710 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2714 #define _R_NOT_W 0x04
2717 #define _D_NOT_A 0x20
2721 //==============================================================================
2724 //==============================================================================
2727 extern __at(0x0214) __sfr SSPSTAT
;
2733 unsigned R_NOT_W
: 1;
2736 unsigned D_NOT_A
: 1;
2741 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2743 #define _SSPSTAT_BF 0x01
2744 #define _SSPSTAT_UA 0x02
2745 #define _SSPSTAT_R_NOT_W 0x04
2746 #define _SSPSTAT_S 0x08
2747 #define _SSPSTAT_P 0x10
2748 #define _SSPSTAT_D_NOT_A 0x20
2749 #define _SSPSTAT_CKE 0x40
2750 #define _SSPSTAT_SMP 0x80
2752 //==============================================================================
2755 //==============================================================================
2758 extern __at(0x0215) __sfr SSP1CON
;
2781 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2792 //==============================================================================
2795 //==============================================================================
2798 extern __at(0x0215) __sfr SSP1CON1
;
2821 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2823 #define _SSP1CON1_SSPM0 0x01
2824 #define _SSP1CON1_SSPM1 0x02
2825 #define _SSP1CON1_SSPM2 0x04
2826 #define _SSP1CON1_SSPM3 0x08
2827 #define _SSP1CON1_CKP 0x10
2828 #define _SSP1CON1_SSPEN 0x20
2829 #define _SSP1CON1_SSPOV 0x40
2830 #define _SSP1CON1_WCOL 0x80
2832 //==============================================================================
2835 //==============================================================================
2838 extern __at(0x0215) __sfr SSPCON
;
2861 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2863 #define _SSPCON_SSPM0 0x01
2864 #define _SSPCON_SSPM1 0x02
2865 #define _SSPCON_SSPM2 0x04
2866 #define _SSPCON_SSPM3 0x08
2867 #define _SSPCON_CKP 0x10
2868 #define _SSPCON_SSPEN 0x20
2869 #define _SSPCON_SSPOV 0x40
2870 #define _SSPCON_WCOL 0x80
2872 //==============================================================================
2875 //==============================================================================
2878 extern __at(0x0215) __sfr SSPCON1
;
2901 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2903 #define _SSPCON1_SSPM0 0x01
2904 #define _SSPCON1_SSPM1 0x02
2905 #define _SSPCON1_SSPM2 0x04
2906 #define _SSPCON1_SSPM3 0x08
2907 #define _SSPCON1_CKP 0x10
2908 #define _SSPCON1_SSPEN 0x20
2909 #define _SSPCON1_SSPOV 0x40
2910 #define _SSPCON1_WCOL 0x80
2912 //==============================================================================
2915 //==============================================================================
2918 extern __at(0x0216) __sfr SSP1CON2
;
2928 unsigned ACKSTAT
: 1;
2932 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2940 #define _ACKSTAT 0x40
2943 //==============================================================================
2946 //==============================================================================
2949 extern __at(0x0216) __sfr SSPCON2
;
2959 unsigned ACKSTAT
: 1;
2963 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2965 #define _SSPCON2_SEN 0x01
2966 #define _SSPCON2_RSEN 0x02
2967 #define _SSPCON2_PEN 0x04
2968 #define _SSPCON2_RCEN 0x08
2969 #define _SSPCON2_ACKEN 0x10
2970 #define _SSPCON2_ACKDT 0x20
2971 #define _SSPCON2_ACKSTAT 0x40
2972 #define _SSPCON2_GCEN 0x80
2974 //==============================================================================
2977 //==============================================================================
2980 extern __at(0x0217) __sfr SSP1CON3
;
2991 unsigned ACKTIM
: 1;
2994 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
3003 #define _ACKTIM 0x80
3005 //==============================================================================
3008 //==============================================================================
3011 extern __at(0x0217) __sfr SSPCON3
;
3022 unsigned ACKTIM
: 1;
3025 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
3027 #define _SSPCON3_DHEN 0x01
3028 #define _SSPCON3_AHEN 0x02
3029 #define _SSPCON3_SBCDE 0x04
3030 #define _SSPCON3_SDAHT 0x08
3031 #define _SSPCON3_BOEN 0x10
3032 #define _SSPCON3_SCIE 0x20
3033 #define _SSPCON3_PCIE 0x40
3034 #define _SSPCON3_ACKTIM 0x80
3036 //==============================================================================
3039 //==============================================================================
3042 extern __at(0x028C) __sfr ODCONA
;
3056 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
3064 //==============================================================================
3067 //==============================================================================
3070 extern __at(0x028D) __sfr ODCONB
;
3084 extern __at(0x028D) volatile __ODCONBbits_t ODCONBbits
;
3091 //==============================================================================
3094 //==============================================================================
3097 extern __at(0x028E) __sfr ODCONC
;
3111 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3122 //==============================================================================
3124 extern __at(0x0291) __sfr CCPR1
;
3125 extern __at(0x0291) __sfr CCPR1L
;
3126 extern __at(0x0292) __sfr CCPR1H
;
3128 //==============================================================================
3131 extern __at(0x0293) __sfr CCP1CON
;
3137 unsigned CCP1MODE0
: 1;
3138 unsigned CCP1MODE1
: 1;
3139 unsigned CCP1MODE2
: 1;
3140 unsigned CCP1MODE3
: 1;
3141 unsigned CCP1FMT
: 1;
3142 unsigned CCP1OUT
: 1;
3144 unsigned CCP1EN
: 1;
3149 unsigned CCP1MODE
: 4;
3154 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3156 #define _CCP1MODE0 0x01
3157 #define _CCP1MODE1 0x02
3158 #define _CCP1MODE2 0x04
3159 #define _CCP1MODE3 0x08
3160 #define _CCP1FMT 0x10
3161 #define _CCP1OUT 0x20
3162 #define _CCP1EN 0x80
3164 //==============================================================================
3167 //==============================================================================
3170 extern __at(0x0294) __sfr CCP1CAP
;
3176 unsigned CCP1CTS0
: 1;
3177 unsigned CCP1CTS1
: 1;
3178 unsigned CCP1CTS2
: 1;
3179 unsigned CCP1CTS3
: 1;
3188 unsigned CCP1CTS
: 4;
3193 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
3195 #define _CCP1CTS0 0x01
3196 #define _CCP1CTS1 0x02
3197 #define _CCP1CTS2 0x04
3198 #define _CCP1CTS3 0x08
3200 //==============================================================================
3202 extern __at(0x0295) __sfr CCPR2
;
3203 extern __at(0x0295) __sfr CCPR2L
;
3204 extern __at(0x0296) __sfr CCPR2H
;
3206 //==============================================================================
3209 extern __at(0x0297) __sfr CCP2CON
;
3215 unsigned CCP2MODE0
: 1;
3216 unsigned CCP2MODE1
: 1;
3217 unsigned CCP2MODE2
: 1;
3218 unsigned CCP2MODE3
: 1;
3219 unsigned CCP2FMT
: 1;
3220 unsigned CCP2OUT
: 1;
3222 unsigned CCP2EN
: 1;
3227 unsigned CCP2MODE
: 4;
3232 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
3234 #define _CCP2MODE0 0x01
3235 #define _CCP2MODE1 0x02
3236 #define _CCP2MODE2 0x04
3237 #define _CCP2MODE3 0x08
3238 #define _CCP2FMT 0x10
3239 #define _CCP2OUT 0x20
3240 #define _CCP2EN 0x80
3242 //==============================================================================
3245 //==============================================================================
3248 extern __at(0x0298) __sfr CCP2CAP
;
3254 unsigned CCP2CTS0
: 1;
3255 unsigned CCP2CTS1
: 1;
3256 unsigned CCP2CTS2
: 1;
3257 unsigned CCP2CTS3
: 1;
3266 unsigned CCP2CTS
: 4;
3271 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
3273 #define _CCP2CTS0 0x01
3274 #define _CCP2CTS1 0x02
3275 #define _CCP2CTS2 0x04
3276 #define _CCP2CTS3 0x08
3278 //==============================================================================
3281 //==============================================================================
3284 extern __at(0x029F) __sfr CCPTMRS
;
3290 unsigned C1TSEL0
: 1;
3291 unsigned C1TSEL1
: 1;
3292 unsigned C2TSEL0
: 1;
3293 unsigned C2TSEL1
: 1;
3294 unsigned C3TSEL0
: 1;
3295 unsigned C3TSEL1
: 1;
3296 unsigned C4TSEL0
: 1;
3297 unsigned C4TSEL1
: 1;
3302 unsigned C1TSEL
: 2;
3309 unsigned C2TSEL
: 2;
3316 unsigned C3TSEL
: 2;
3323 unsigned C4TSEL
: 2;
3327 extern __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits
;
3329 #define _C1TSEL0 0x01
3330 #define _C1TSEL1 0x02
3331 #define _C2TSEL0 0x04
3332 #define _C2TSEL1 0x08
3333 #define _C3TSEL0 0x10
3334 #define _C3TSEL1 0x20
3335 #define _C4TSEL0 0x40
3336 #define _C4TSEL1 0x80
3338 //==============================================================================
3341 //==============================================================================
3344 extern __at(0x030C) __sfr SLRCONA
;
3358 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3366 //==============================================================================
3369 //==============================================================================
3372 extern __at(0x030D) __sfr SLRCONB
;
3386 extern __at(0x030D) volatile __SLRCONBbits_t SLRCONBbits
;
3393 //==============================================================================
3396 //==============================================================================
3399 extern __at(0x030E) __sfr SLRCONC
;
3413 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3424 //==============================================================================
3426 extern __at(0x0311) __sfr CCPR3
;
3427 extern __at(0x0311) __sfr CCPR3L
;
3428 extern __at(0x0312) __sfr CCPR3H
;
3430 //==============================================================================
3433 extern __at(0x0313) __sfr CCP3CON
;
3439 unsigned CCP3MODE0
: 1;
3440 unsigned CCP3MODE1
: 1;
3441 unsigned CCP3MODE2
: 1;
3442 unsigned CCP3MODE3
: 1;
3443 unsigned CCP3FMT
: 1;
3444 unsigned CCP3OUT
: 1;
3446 unsigned CCP3EN
: 1;
3451 unsigned CCP3MODE
: 4;
3456 extern __at(0x0313) volatile __CCP3CONbits_t CCP3CONbits
;
3458 #define _CCP3MODE0 0x01
3459 #define _CCP3MODE1 0x02
3460 #define _CCP3MODE2 0x04
3461 #define _CCP3MODE3 0x08
3462 #define _CCP3FMT 0x10
3463 #define _CCP3OUT 0x20
3464 #define _CCP3EN 0x80
3466 //==============================================================================
3469 //==============================================================================
3472 extern __at(0x0314) __sfr CCP3CAP
;
3478 unsigned CCP3CTS0
: 1;
3479 unsigned CCP3CTS1
: 1;
3480 unsigned CCP3CTS2
: 1;
3481 unsigned CCP3CTS3
: 1;
3490 unsigned CCP3CTS
: 4;
3495 extern __at(0x0314) volatile __CCP3CAPbits_t CCP3CAPbits
;
3497 #define _CCP3CTS0 0x01
3498 #define _CCP3CTS1 0x02
3499 #define _CCP3CTS2 0x04
3500 #define _CCP3CTS3 0x08
3502 //==============================================================================
3504 extern __at(0x0315) __sfr CCPR4
;
3505 extern __at(0x0315) __sfr CCPR4L
;
3506 extern __at(0x0316) __sfr CCPR4H
;
3508 //==============================================================================
3511 extern __at(0x0317) __sfr CCP4CON
;
3517 unsigned CCP4MODE0
: 1;
3518 unsigned CCP4MODE1
: 1;
3519 unsigned CCP4MODE2
: 1;
3520 unsigned CCP4MODE3
: 1;
3521 unsigned CCP4FMT
: 1;
3522 unsigned CCP4OUT
: 1;
3524 unsigned CCP4EN
: 1;
3529 unsigned CCP4MODE
: 4;
3534 extern __at(0x0317) volatile __CCP4CONbits_t CCP4CONbits
;
3536 #define _CCP4MODE0 0x01
3537 #define _CCP4MODE1 0x02
3538 #define _CCP4MODE2 0x04
3539 #define _CCP4MODE3 0x08
3540 #define _CCP4FMT 0x10
3541 #define _CCP4OUT 0x20
3542 #define _CCP4EN 0x80
3544 //==============================================================================
3547 //==============================================================================
3550 extern __at(0x0318) __sfr CCP4CAP
;
3556 unsigned CCP4CTS0
: 1;
3557 unsigned CCP4CTS1
: 1;
3558 unsigned CCP4CTS2
: 1;
3559 unsigned CCP4CTS3
: 1;
3568 unsigned CCP4CTS
: 4;
3573 extern __at(0x0318) volatile __CCP4CAPbits_t CCP4CAPbits
;
3575 #define _CCP4CTS0 0x01
3576 #define _CCP4CTS1 0x02
3577 #define _CCP4CTS2 0x04
3578 #define _CCP4CTS3 0x08
3580 //==============================================================================
3583 //==============================================================================
3586 extern __at(0x038C) __sfr INLVLA
;
3592 unsigned INLVLA0
: 1;
3593 unsigned INLVLA1
: 1;
3594 unsigned INLVLA2
: 1;
3595 unsigned INLVLA3
: 1;
3596 unsigned INLVLA4
: 1;
3597 unsigned INLVLA5
: 1;
3604 unsigned INLVLA
: 6;
3609 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3611 #define _INLVLA0 0x01
3612 #define _INLVLA1 0x02
3613 #define _INLVLA2 0x04
3614 #define _INLVLA3 0x08
3615 #define _INLVLA4 0x10
3616 #define _INLVLA5 0x20
3618 //==============================================================================
3621 //==============================================================================
3624 extern __at(0x038D) __sfr INLVLB
;
3632 unsigned INLVLB4
: 1;
3633 unsigned INLVLB5
: 1;
3634 unsigned INLVLB6
: 1;
3635 unsigned INLVLB7
: 1;
3638 extern __at(0x038D) volatile __INLVLBbits_t INLVLBbits
;
3640 #define _INLVLB4 0x10
3641 #define _INLVLB5 0x20
3642 #define _INLVLB6 0x40
3643 #define _INLVLB7 0x80
3645 //==============================================================================
3648 //==============================================================================
3651 extern __at(0x038E) __sfr INLVLC
;
3655 unsigned INLVLC0
: 1;
3656 unsigned INLVLC1
: 1;
3657 unsigned INLVLC2
: 1;
3658 unsigned INLVLC3
: 1;
3659 unsigned INLVLC4
: 1;
3660 unsigned INLVLC5
: 1;
3661 unsigned INLVLC6
: 1;
3662 unsigned INLVLC7
: 1;
3665 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3667 #define _INLVLC0 0x01
3668 #define _INLVLC1 0x02
3669 #define _INLVLC2 0x04
3670 #define _INLVLC3 0x08
3671 #define _INLVLC4 0x10
3672 #define _INLVLC5 0x20
3673 #define _INLVLC6 0x40
3674 #define _INLVLC7 0x80
3676 //==============================================================================
3679 //==============================================================================
3682 extern __at(0x0391) __sfr IOCAP
;
3688 unsigned IOCAP0
: 1;
3689 unsigned IOCAP1
: 1;
3690 unsigned IOCAP2
: 1;
3691 unsigned IOCAP3
: 1;
3692 unsigned IOCAP4
: 1;
3693 unsigned IOCAP5
: 1;
3705 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3707 #define _IOCAP0 0x01
3708 #define _IOCAP1 0x02
3709 #define _IOCAP2 0x04
3710 #define _IOCAP3 0x08
3711 #define _IOCAP4 0x10
3712 #define _IOCAP5 0x20
3714 //==============================================================================
3717 //==============================================================================
3720 extern __at(0x0392) __sfr IOCAN
;
3726 unsigned IOCAN0
: 1;
3727 unsigned IOCAN1
: 1;
3728 unsigned IOCAN2
: 1;
3729 unsigned IOCAN3
: 1;
3730 unsigned IOCAN4
: 1;
3731 unsigned IOCAN5
: 1;
3743 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3745 #define _IOCAN0 0x01
3746 #define _IOCAN1 0x02
3747 #define _IOCAN2 0x04
3748 #define _IOCAN3 0x08
3749 #define _IOCAN4 0x10
3750 #define _IOCAN5 0x20
3752 //==============================================================================
3755 //==============================================================================
3758 extern __at(0x0393) __sfr IOCAF
;
3764 unsigned IOCAF0
: 1;
3765 unsigned IOCAF1
: 1;
3766 unsigned IOCAF2
: 1;
3767 unsigned IOCAF3
: 1;
3768 unsigned IOCAF4
: 1;
3769 unsigned IOCAF5
: 1;
3781 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3783 #define _IOCAF0 0x01
3784 #define _IOCAF1 0x02
3785 #define _IOCAF2 0x04
3786 #define _IOCAF3 0x08
3787 #define _IOCAF4 0x10
3788 #define _IOCAF5 0x20
3790 //==============================================================================
3793 //==============================================================================
3796 extern __at(0x0394) __sfr IOCBP
;
3804 unsigned IOCBP4
: 1;
3805 unsigned IOCBP5
: 1;
3806 unsigned IOCBP6
: 1;
3807 unsigned IOCBP7
: 1;
3810 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
3812 #define _IOCBP4 0x10
3813 #define _IOCBP5 0x20
3814 #define _IOCBP6 0x40
3815 #define _IOCBP7 0x80
3817 //==============================================================================
3820 //==============================================================================
3823 extern __at(0x0395) __sfr IOCBN
;
3831 unsigned IOCBN4
: 1;
3832 unsigned IOCBN5
: 1;
3833 unsigned IOCBN6
: 1;
3834 unsigned IOCBN7
: 1;
3837 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
3839 #define _IOCBN4 0x10
3840 #define _IOCBN5 0x20
3841 #define _IOCBN6 0x40
3842 #define _IOCBN7 0x80
3844 //==============================================================================
3847 //==============================================================================
3850 extern __at(0x0396) __sfr IOCBF
;
3858 unsigned IOCBF4
: 1;
3859 unsigned IOCBF5
: 1;
3860 unsigned IOCBF6
: 1;
3861 unsigned IOCBF7
: 1;
3864 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
3866 #define _IOCBF4 0x10
3867 #define _IOCBF5 0x20
3868 #define _IOCBF6 0x40
3869 #define _IOCBF7 0x80
3871 //==============================================================================
3874 //==============================================================================
3877 extern __at(0x0397) __sfr IOCCP
;
3881 unsigned IOCCP0
: 1;
3882 unsigned IOCCP1
: 1;
3883 unsigned IOCCP2
: 1;
3884 unsigned IOCCP3
: 1;
3885 unsigned IOCCP4
: 1;
3886 unsigned IOCCP5
: 1;
3887 unsigned IOCCP6
: 1;
3888 unsigned IOCCP7
: 1;
3891 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3893 #define _IOCCP0 0x01
3894 #define _IOCCP1 0x02
3895 #define _IOCCP2 0x04
3896 #define _IOCCP3 0x08
3897 #define _IOCCP4 0x10
3898 #define _IOCCP5 0x20
3899 #define _IOCCP6 0x40
3900 #define _IOCCP7 0x80
3902 //==============================================================================
3905 //==============================================================================
3908 extern __at(0x0398) __sfr IOCCN
;
3912 unsigned IOCCN0
: 1;
3913 unsigned IOCCN1
: 1;
3914 unsigned IOCCN2
: 1;
3915 unsigned IOCCN3
: 1;
3916 unsigned IOCCN4
: 1;
3917 unsigned IOCCN5
: 1;
3918 unsigned IOCCN6
: 1;
3919 unsigned IOCCN7
: 1;
3922 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
3924 #define _IOCCN0 0x01
3925 #define _IOCCN1 0x02
3926 #define _IOCCN2 0x04
3927 #define _IOCCN3 0x08
3928 #define _IOCCN4 0x10
3929 #define _IOCCN5 0x20
3930 #define _IOCCN6 0x40
3931 #define _IOCCN7 0x80
3933 //==============================================================================
3936 //==============================================================================
3939 extern __at(0x0399) __sfr IOCCF
;
3943 unsigned IOCCF0
: 1;
3944 unsigned IOCCF1
: 1;
3945 unsigned IOCCF2
: 1;
3946 unsigned IOCCF3
: 1;
3947 unsigned IOCCF4
: 1;
3948 unsigned IOCCF5
: 1;
3949 unsigned IOCCF6
: 1;
3950 unsigned IOCCF7
: 1;
3953 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
3955 #define _IOCCF0 0x01
3956 #define _IOCCF1 0x02
3957 #define _IOCCF2 0x04
3958 #define _IOCCF3 0x08
3959 #define _IOCCF4 0x10
3960 #define _IOCCF5 0x20
3961 #define _IOCCF6 0x40
3962 #define _IOCCF7 0x80
3964 //==============================================================================
3967 //==============================================================================
3970 extern __at(0x039A) __sfr CLKRCON
;
3976 unsigned CLKRDIV0
: 1;
3977 unsigned CLKRDIV1
: 1;
3978 unsigned CLKRDIV2
: 1;
3979 unsigned CLKRDC0
: 1;
3980 unsigned CLKRDC1
: 1;
3983 unsigned CLKREN
: 1;
3988 unsigned CLKRDIV
: 3;
3995 unsigned CLKRDC
: 2;
4000 extern __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits
;
4002 #define _CLKRDIV0 0x01
4003 #define _CLKRDIV1 0x02
4004 #define _CLKRDIV2 0x04
4005 #define _CLKRDC0 0x08
4006 #define _CLKRDC1 0x10
4007 #define _CLKREN 0x80
4009 //==============================================================================
4012 //==============================================================================
4015 extern __at(0x039C) __sfr MDCON
;
4023 unsigned MDOPOL
: 1;
4029 extern __at(0x039C) volatile __MDCONbits_t MDCONbits
;
4033 #define _MDOPOL 0x10
4036 //==============================================================================
4039 //==============================================================================
4042 extern __at(0x039D) __sfr MDSRC
;
4065 extern __at(0x039D) volatile __MDSRCbits_t MDSRCbits
;
4072 //==============================================================================
4075 //==============================================================================
4078 extern __at(0x039E) __sfr MDCARH
;
4089 unsigned MDCHSYNC
: 1;
4090 unsigned MDCHPOL
: 1;
4101 extern __at(0x039E) volatile __MDCARHbits_t MDCARHbits
;
4107 #define _MDCHSYNC 0x20
4108 #define _MDCHPOL 0x40
4110 //==============================================================================
4113 //==============================================================================
4116 extern __at(0x039F) __sfr MDCARL
;
4127 unsigned MDCLSYNC
: 1;
4128 unsigned MDCLPOL
: 1;
4139 extern __at(0x039F) volatile __MDCARLbits_t MDCARLbits
;
4145 #define _MDCLSYNC 0x20
4146 #define _MDCLPOL 0x40
4148 //==============================================================================
4151 //==============================================================================
4154 extern __at(0x040C) __sfr CCDNA
;
4158 unsigned CCDNA0
: 1;
4159 unsigned CCDNA1
: 1;
4160 unsigned CCDNA2
: 1;
4162 unsigned CCDNA4
: 1;
4163 unsigned CCDNA5
: 1;
4168 extern __at(0x040C) volatile __CCDNAbits_t CCDNAbits
;
4170 #define _CCDNA0 0x01
4171 #define _CCDNA1 0x02
4172 #define _CCDNA2 0x04
4173 #define _CCDNA4 0x10
4174 #define _CCDNA5 0x20
4176 //==============================================================================
4179 //==============================================================================
4182 extern __at(0x040D) __sfr CCDNB
;
4190 unsigned CCDNB4
: 1;
4191 unsigned CCDNB5
: 1;
4192 unsigned CCDNB6
: 1;
4193 unsigned CCDNB7
: 1;
4196 extern __at(0x040D) volatile __CCDNBbits_t CCDNBbits
;
4198 #define _CCDNB4 0x10
4199 #define _CCDNB5 0x20
4200 #define _CCDNB6 0x40
4201 #define _CCDNB7 0x80
4203 //==============================================================================
4206 //==============================================================================
4209 extern __at(0x040E) __sfr CCDNC
;
4213 unsigned CCDNC0
: 1;
4214 unsigned CCDNC1
: 1;
4215 unsigned CCDNC2
: 1;
4216 unsigned CCDNC3
: 1;
4217 unsigned CCDNC4
: 1;
4218 unsigned CCDNC5
: 1;
4219 unsigned CCDNC6
: 1;
4220 unsigned CCDNC7
: 1;
4223 extern __at(0x040E) volatile __CCDNCbits_t CCDNCbits
;
4225 #define _CCDNC0 0x01
4226 #define _CCDNC1 0x02
4227 #define _CCDNC2 0x04
4228 #define _CCDNC3 0x08
4229 #define _CCDNC4 0x10
4230 #define _CCDNC5 0x20
4231 #define _CCDNC6 0x40
4232 #define _CCDNC7 0x80
4234 //==============================================================================
4236 extern __at(0x0411) __sfr TMR3
;
4237 extern __at(0x0411) __sfr TMR3L
;
4238 extern __at(0x0412) __sfr TMR3H
;
4240 //==============================================================================
4243 extern __at(0x0413) __sfr T3CON
;
4249 unsigned TMR3ON
: 1;
4251 unsigned T3SYNC
: 1;
4252 unsigned T3SOSC
: 1;
4253 unsigned T3CKPS0
: 1;
4254 unsigned T3CKPS1
: 1;
4255 unsigned TMR3CS0
: 1;
4256 unsigned TMR3CS1
: 1;
4262 unsigned T3CKPS
: 2;
4269 unsigned TMR3CS
: 2;
4273 extern __at(0x0413) volatile __T3CONbits_t T3CONbits
;
4275 #define _TMR3ON 0x01
4276 #define _T3SYNC 0x04
4277 #define _T3SOSC 0x08
4278 #define _T3CKPS0 0x10
4279 #define _T3CKPS1 0x20
4280 #define _TMR3CS0 0x40
4281 #define _TMR3CS1 0x80
4283 //==============================================================================
4286 //==============================================================================
4289 extern __at(0x0414) __sfr T3GCON
;
4295 unsigned T3GSS0
: 1;
4296 unsigned T3GSS1
: 1;
4297 unsigned T3GVAL
: 1;
4298 unsigned T3GGO_NOT_DONE
: 1;
4299 unsigned T3GSPM
: 1;
4301 unsigned T3GPOL
: 1;
4302 unsigned TMR3GE
: 1;
4312 extern __at(0x0414) volatile __T3GCONbits_t T3GCONbits
;
4314 #define _T3GSS0 0x01
4315 #define _T3GSS1 0x02
4316 #define _T3GVAL 0x04
4317 #define _T3GGO_NOT_DONE 0x08
4318 #define _T3GSPM 0x10
4320 #define _T3GPOL 0x40
4321 #define _TMR3GE 0x80
4323 //==============================================================================
4325 extern __at(0x0415) __sfr TMR4
;
4326 extern __at(0x0416) __sfr PR4
;
4328 //==============================================================================
4331 extern __at(0x0417) __sfr T4CON
;
4337 unsigned T4CKPS0
: 1;
4338 unsigned T4CKPS1
: 1;
4339 unsigned TMR4ON
: 1;
4340 unsigned T4OUTPS0
: 1;
4341 unsigned T4OUTPS1
: 1;
4342 unsigned T4OUTPS2
: 1;
4343 unsigned T4OUTPS3
: 1;
4349 unsigned T4CKPS
: 2;
4356 unsigned T4OUTPS
: 4;
4361 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
4363 #define _T4CKPS0 0x01
4364 #define _T4CKPS1 0x02
4365 #define _TMR4ON 0x04
4366 #define _T4OUTPS0 0x08
4367 #define _T4OUTPS1 0x10
4368 #define _T4OUTPS2 0x20
4369 #define _T4OUTPS3 0x40
4371 //==============================================================================
4373 extern __at(0x0418) __sfr TMR5
;
4374 extern __at(0x0418) __sfr TMR5L
;
4375 extern __at(0x0419) __sfr TMR5H
;
4377 //==============================================================================
4380 extern __at(0x041A) __sfr T5CON
;
4386 unsigned TMR5ON
: 1;
4388 unsigned T5SYNC
: 1;
4389 unsigned T5SOSC
: 1;
4390 unsigned T5CKPS0
: 1;
4391 unsigned T5CKPS1
: 1;
4392 unsigned TMR5CS0
: 1;
4393 unsigned TMR5CS1
: 1;
4399 unsigned T5CKPS
: 2;
4406 unsigned TMR5CS
: 2;
4410 extern __at(0x041A) volatile __T5CONbits_t T5CONbits
;
4412 #define _TMR5ON 0x01
4413 #define _T5SYNC 0x04
4414 #define _T5SOSC 0x08
4415 #define _T5CKPS0 0x10
4416 #define _T5CKPS1 0x20
4417 #define _TMR5CS0 0x40
4418 #define _TMR5CS1 0x80
4420 //==============================================================================
4423 //==============================================================================
4426 extern __at(0x041B) __sfr T5GCON
;
4432 unsigned T5GSS0
: 1;
4433 unsigned T5GSS1
: 1;
4434 unsigned T5GVAL
: 1;
4435 unsigned T5GGO_NOT_DONE
: 1;
4436 unsigned T5GSPM
: 1;
4438 unsigned T5GPOL
: 1;
4439 unsigned TMR5GE
: 1;
4449 extern __at(0x041B) volatile __T5GCONbits_t T5GCONbits
;
4451 #define _T5GSS0 0x01
4452 #define _T5GSS1 0x02
4453 #define _T5GVAL 0x04
4454 #define _T5GGO_NOT_DONE 0x08
4455 #define _T5GSPM 0x10
4457 #define _T5GPOL 0x40
4458 #define _TMR5GE 0x80
4460 //==============================================================================
4462 extern __at(0x041C) __sfr TMR6
;
4463 extern __at(0x041D) __sfr PR6
;
4465 //==============================================================================
4468 extern __at(0x041E) __sfr T6CON
;
4474 unsigned T6CKPS0
: 1;
4475 unsigned T6CKPS1
: 1;
4476 unsigned TMR6ON
: 1;
4477 unsigned T6OUTPS0
: 1;
4478 unsigned T6OUTPS1
: 1;
4479 unsigned T6OUTPS2
: 1;
4480 unsigned T6OUTPS3
: 1;
4486 unsigned T6CKPS
: 2;
4493 unsigned T6OUTPS
: 4;
4498 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
4500 #define _T6CKPS0 0x01
4501 #define _T6CKPS1 0x02
4502 #define _TMR6ON 0x04
4503 #define _T6OUTPS0 0x08
4504 #define _T6OUTPS1 0x10
4505 #define _T6OUTPS2 0x20
4506 #define _T6OUTPS3 0x40
4508 //==============================================================================
4511 //==============================================================================
4514 extern __at(0x041F) __sfr CCDCON
;
4537 extern __at(0x041F) volatile __CCDCONbits_t CCDCONbits
;
4543 //==============================================================================
4546 //==============================================================================
4549 extern __at(0x048C) __sfr CCDPA
;
4553 unsigned CCDPA0
: 1;
4554 unsigned CCDPA1
: 1;
4555 unsigned CCDPA2
: 1;
4557 unsigned CCDPA4
: 1;
4558 unsigned CCDPA5
: 1;
4563 extern __at(0x048C) volatile __CCDPAbits_t CCDPAbits
;
4565 #define _CCDPA0 0x01
4566 #define _CCDPA1 0x02
4567 #define _CCDPA2 0x04
4568 #define _CCDPA4 0x10
4569 #define _CCDPA5 0x20
4571 //==============================================================================
4574 //==============================================================================
4577 extern __at(0x048D) __sfr CCDPB
;
4585 unsigned CCDPB4
: 1;
4586 unsigned CCDPB5
: 1;
4587 unsigned CCDPB6
: 1;
4588 unsigned CCDPB7
: 1;
4591 extern __at(0x048D) volatile __CCDPBbits_t CCDPBbits
;
4593 #define _CCDPB4 0x10
4594 #define _CCDPB5 0x20
4595 #define _CCDPB6 0x40
4596 #define _CCDPB7 0x80
4598 //==============================================================================
4601 //==============================================================================
4604 extern __at(0x048E) __sfr CCDPC
;
4608 unsigned CCDPC0
: 1;
4609 unsigned CCDPC1
: 1;
4610 unsigned CCDPC2
: 1;
4611 unsigned CCDPC3
: 1;
4612 unsigned CCDPC4
: 1;
4613 unsigned CCDPC5
: 1;
4614 unsigned CCDPC6
: 1;
4615 unsigned CCDPC7
: 1;
4618 extern __at(0x048E) volatile __CCDPCbits_t CCDPCbits
;
4620 #define _CCDPC0 0x01
4621 #define _CCDPC1 0x02
4622 #define _CCDPC2 0x04
4623 #define _CCDPC3 0x08
4624 #define _CCDPC4 0x10
4625 #define _CCDPC5 0x20
4626 #define _CCDPC6 0x40
4627 #define _CCDPC7 0x80
4629 //==============================================================================
4631 extern __at(0x0498) __sfr NCO1ACC
;
4632 extern __at(0x0498) __sfr NCO1ACCL
;
4633 extern __at(0x0499) __sfr NCO1ACCH
;
4634 extern __at(0x049A) __sfr NCO1ACCU
;
4635 extern __at(0x049B) __sfr NCO1INC
;
4636 extern __at(0x049B) __sfr NCO1INCL
;
4637 extern __at(0x049C) __sfr NCO1INCH
;
4638 extern __at(0x049D) __sfr NCO1INCU
;
4640 //==============================================================================
4643 extern __at(0x049E) __sfr NCO1CON
;
4657 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
4664 //==============================================================================
4666 extern __at(0x049F) __sfr NCO1CLK
;
4668 //==============================================================================
4671 extern __at(0x0617) __sfr PWM5DCL
;
4683 unsigned PWM5DCL0
: 1;
4684 unsigned PWM5DCL1
: 1;
4690 unsigned PWM5DCL
: 2;
4694 extern __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits
;
4696 #define _PWM5DCL0 0x40
4697 #define _PWM5DCL1 0x80
4699 //==============================================================================
4702 //==============================================================================
4705 extern __at(0x0618) __sfr PWM5DCH
;
4709 unsigned PWM5DCH0
: 1;
4710 unsigned PWM5DCH1
: 1;
4711 unsigned PWM5DCH2
: 1;
4712 unsigned PWM5DCH3
: 1;
4713 unsigned PWM5DCH4
: 1;
4714 unsigned PWM5DCH5
: 1;
4715 unsigned PWM5DCH6
: 1;
4716 unsigned PWM5DCH7
: 1;
4719 extern __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits
;
4721 #define _PWM5DCH0 0x01
4722 #define _PWM5DCH1 0x02
4723 #define _PWM5DCH2 0x04
4724 #define _PWM5DCH3 0x08
4725 #define _PWM5DCH4 0x10
4726 #define _PWM5DCH5 0x20
4727 #define _PWM5DCH6 0x40
4728 #define _PWM5DCH7 0x80
4730 //==============================================================================
4733 //==============================================================================
4736 extern __at(0x0619) __sfr PWM5CON
;
4744 unsigned PWM5POL
: 1;
4745 unsigned PWM5OUT
: 1;
4747 unsigned PWM5EN
: 1;
4750 extern __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits
;
4752 #define _PWM5POL 0x10
4753 #define _PWM5OUT 0x20
4754 #define _PWM5EN 0x80
4756 //==============================================================================
4759 //==============================================================================
4762 extern __at(0x0619) __sfr PWM5CON0
;
4770 unsigned PWM5POL
: 1;
4771 unsigned PWM5OUT
: 1;
4773 unsigned PWM5EN
: 1;
4776 extern __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits
;
4778 #define _PWM5CON0_PWM5POL 0x10
4779 #define _PWM5CON0_PWM5OUT 0x20
4780 #define _PWM5CON0_PWM5EN 0x80
4782 //==============================================================================
4785 //==============================================================================
4788 extern __at(0x061A) __sfr PWM6DCL
;
4800 unsigned PWM6DCL0
: 1;
4801 unsigned PWM6DCL1
: 1;
4807 unsigned PWM6DCL
: 2;
4811 extern __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits
;
4813 #define _PWM6DCL0 0x40
4814 #define _PWM6DCL1 0x80
4816 //==============================================================================
4819 //==============================================================================
4822 extern __at(0x061B) __sfr PWM6DCH
;
4826 unsigned PWM6DCH0
: 1;
4827 unsigned PWM6DCH1
: 1;
4828 unsigned PWM6DCH2
: 1;
4829 unsigned PWM6DCH3
: 1;
4830 unsigned PWM6DCH4
: 1;
4831 unsigned PWM6DCH5
: 1;
4832 unsigned PWM6DCH6
: 1;
4833 unsigned PWM6DCH7
: 1;
4836 extern __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits
;
4838 #define _PWM6DCH0 0x01
4839 #define _PWM6DCH1 0x02
4840 #define _PWM6DCH2 0x04
4841 #define _PWM6DCH3 0x08
4842 #define _PWM6DCH4 0x10
4843 #define _PWM6DCH5 0x20
4844 #define _PWM6DCH6 0x40
4845 #define _PWM6DCH7 0x80
4847 //==============================================================================
4850 //==============================================================================
4853 extern __at(0x061C) __sfr PWM6CON
;
4861 unsigned PWM6POL
: 1;
4862 unsigned PWM6OUT
: 1;
4864 unsigned PWM6EN
: 1;
4867 extern __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits
;
4869 #define _PWM6POL 0x10
4870 #define _PWM6OUT 0x20
4871 #define _PWM6EN 0x80
4873 //==============================================================================
4876 //==============================================================================
4879 extern __at(0x061C) __sfr PWM6CON0
;
4887 unsigned PWM6POL
: 1;
4888 unsigned PWM6OUT
: 1;
4890 unsigned PWM6EN
: 1;
4893 extern __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits
;
4895 #define _PWM6CON0_PWM6POL 0x10
4896 #define _PWM6CON0_PWM6OUT 0x20
4897 #define _PWM6CON0_PWM6EN 0x80
4899 //==============================================================================
4902 //==============================================================================
4905 extern __at(0x061F) __sfr PWMTMRS
;
4911 unsigned P5TSEL0
: 1;
4912 unsigned P5TSEL1
: 1;
4913 unsigned P6TSEL0
: 1;
4914 unsigned P6TSEL1
: 1;
4923 unsigned P5TSEL
: 2;
4930 unsigned P6TSEL
: 2;
4935 extern __at(0x061F) volatile __PWMTMRSbits_t PWMTMRSbits
;
4937 #define _P5TSEL0 0x01
4938 #define _P5TSEL1 0x02
4939 #define _P6TSEL0 0x04
4940 #define _P6TSEL1 0x08
4942 //==============================================================================
4945 //==============================================================================
4948 extern __at(0x0691) __sfr CWG1CLKCON
;
4966 unsigned CWG1CS
: 1;
4975 } __CWG1CLKCONbits_t
;
4977 extern __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits
;
4980 #define _CWG1CS 0x01
4982 //==============================================================================
4985 //==============================================================================
4988 extern __at(0x0692) __sfr CWG1DAT
;
4994 unsigned CWG1DAT0
: 1;
4995 unsigned CWG1DAT1
: 1;
4996 unsigned CWG1DAT2
: 1;
4997 unsigned CWG1DAT3
: 1;
5006 unsigned CWG1DAT
: 4;
5011 extern __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits
;
5013 #define _CWG1DAT0 0x01
5014 #define _CWG1DAT1 0x02
5015 #define _CWG1DAT2 0x04
5016 #define _CWG1DAT3 0x08
5018 //==============================================================================
5021 //==============================================================================
5024 extern __at(0x0693) __sfr CWG1DBR
;
5042 unsigned CWG1DBR0
: 1;
5043 unsigned CWG1DBR1
: 1;
5044 unsigned CWG1DBR2
: 1;
5045 unsigned CWG1DBR3
: 1;
5046 unsigned CWG1DBR4
: 1;
5047 unsigned CWG1DBR5
: 1;
5054 unsigned CWG1DBR
: 6;
5065 extern __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits
;
5068 #define _CWG1DBR0 0x01
5070 #define _CWG1DBR1 0x02
5072 #define _CWG1DBR2 0x04
5074 #define _CWG1DBR3 0x08
5076 #define _CWG1DBR4 0x10
5078 #define _CWG1DBR5 0x20
5080 //==============================================================================
5083 //==============================================================================
5086 extern __at(0x0694) __sfr CWG1DBF
;
5104 unsigned CWG1DBF0
: 1;
5105 unsigned CWG1DBF1
: 1;
5106 unsigned CWG1DBF2
: 1;
5107 unsigned CWG1DBF3
: 1;
5108 unsigned CWG1DBF4
: 1;
5109 unsigned CWG1DBF5
: 1;
5122 unsigned CWG1DBF
: 6;
5127 extern __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits
;
5130 #define _CWG1DBF0 0x01
5132 #define _CWG1DBF1 0x02
5134 #define _CWG1DBF2 0x04
5136 #define _CWG1DBF3 0x08
5138 #define _CWG1DBF4 0x10
5140 #define _CWG1DBF5 0x20
5142 //==============================================================================
5145 //==============================================================================
5148 extern __at(0x0695) __sfr CWG1CON0
;
5166 unsigned CWG1MODE0
: 1;
5167 unsigned CWG1MODE1
: 1;
5168 unsigned CWG1MODE2
: 1;
5172 unsigned CWG1LD
: 1;
5185 unsigned CWG1EN
: 1;
5190 unsigned CWG1MODE
: 3;
5201 extern __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits
;
5203 #define _CWG1CON0_MODE0 0x01
5204 #define _CWG1CON0_CWG1MODE0 0x01
5205 #define _CWG1CON0_MODE1 0x02
5206 #define _CWG1CON0_CWG1MODE1 0x02
5207 #define _CWG1CON0_MODE2 0x04
5208 #define _CWG1CON0_CWG1MODE2 0x04
5209 #define _CWG1CON0_LD 0x40
5210 #define _CWG1CON0_CWG1LD 0x40
5211 #define _CWG1CON0_EN 0x80
5212 #define _CWG1CON0_G1EN 0x80
5213 #define _CWG1CON0_CWG1EN 0x80
5215 //==============================================================================
5218 //==============================================================================
5221 extern __at(0x0696) __sfr CWG1CON1
;
5239 unsigned CWG1POLA
: 1;
5240 unsigned CWG1POLB
: 1;
5241 unsigned CWG1POLC
: 1;
5242 unsigned CWG1POLD
: 1;
5244 unsigned CWG1IN
: 1;
5250 extern __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits
;
5253 #define _CWG1POLA 0x01
5255 #define _CWG1POLB 0x02
5257 #define _CWG1POLC 0x04
5259 #define _CWG1POLD 0x08
5261 #define _CWG1IN 0x20
5263 //==============================================================================
5266 //==============================================================================
5269 extern __at(0x0697) __sfr CWG1AS0
;
5282 unsigned SHUTDOWN
: 1;
5289 unsigned CWG1LSAC0
: 1;
5290 unsigned CWG1LSAC1
: 1;
5291 unsigned CWG1LSBD0
: 1;
5292 unsigned CWG1LSBD1
: 1;
5293 unsigned CWG1REN
: 1;
5294 unsigned CWG1SHUTDOWN
: 1;
5307 unsigned CWG1LSAC
: 2;
5321 unsigned CWG1LSBD
: 2;
5326 extern __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits
;
5329 #define _CWG1LSAC0 0x04
5331 #define _CWG1LSAC1 0x08
5333 #define _CWG1LSBD0 0x10
5335 #define _CWG1LSBD1 0x20
5337 #define _CWG1REN 0x40
5338 #define _SHUTDOWN 0x80
5339 #define _CWG1SHUTDOWN 0x80
5341 //==============================================================================
5344 //==============================================================================
5347 extern __at(0x0698) __sfr CWG1AS1
;
5361 extern __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits
;
5369 //==============================================================================
5372 //==============================================================================
5375 extern __at(0x0699) __sfr CWG1STR
;
5393 unsigned CWG1STRA
: 1;
5394 unsigned CWG1STRB
: 1;
5395 unsigned CWG1STRC
: 1;
5396 unsigned CWG1STRD
: 1;
5397 unsigned CWG1OVRA
: 1;
5398 unsigned CWG1OVRB
: 1;
5399 unsigned CWG1OVRC
: 1;
5400 unsigned CWG1OVRD
: 1;
5404 extern __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits
;
5407 #define _CWG1STRA 0x01
5409 #define _CWG1STRB 0x02
5411 #define _CWG1STRC 0x04
5413 #define _CWG1STRD 0x08
5415 #define _CWG1OVRA 0x10
5417 #define _CWG1OVRB 0x20
5419 #define _CWG1OVRC 0x40
5421 #define _CWG1OVRD 0x80
5423 //==============================================================================
5426 //==============================================================================
5429 extern __at(0x0711) __sfr CWG2CLKCON
;
5447 unsigned CWG2CS
: 1;
5456 } __CWG2CLKCONbits_t
;
5458 extern __at(0x0711) volatile __CWG2CLKCONbits_t CWG2CLKCONbits
;
5460 #define _CWG2CLKCON_CS 0x01
5461 #define _CWG2CLKCON_CWG2CS 0x01
5463 //==============================================================================
5466 //==============================================================================
5469 extern __at(0x0712) __sfr CWG2DAT
;
5475 unsigned CWG2DAT0
: 1;
5476 unsigned CWG2DAT1
: 1;
5477 unsigned CWG2DAT2
: 1;
5478 unsigned CWG2DAT3
: 1;
5487 unsigned CWG2DAT
: 4;
5492 extern __at(0x0712) volatile __CWG2DATbits_t CWG2DATbits
;
5494 #define _CWG2DAT0 0x01
5495 #define _CWG2DAT1 0x02
5496 #define _CWG2DAT2 0x04
5497 #define _CWG2DAT3 0x08
5499 //==============================================================================
5502 //==============================================================================
5505 extern __at(0x0713) __sfr CWG2DBR
;
5523 unsigned CWG2DBR0
: 1;
5524 unsigned CWG2DBR1
: 1;
5525 unsigned CWG2DBR2
: 1;
5526 unsigned CWG2DBR3
: 1;
5527 unsigned CWG2DBR4
: 1;
5528 unsigned CWG2DBR5
: 1;
5535 unsigned CWG2DBR
: 6;
5546 extern __at(0x0713) volatile __CWG2DBRbits_t CWG2DBRbits
;
5548 #define _CWG2DBR_DBR0 0x01
5549 #define _CWG2DBR_CWG2DBR0 0x01
5550 #define _CWG2DBR_DBR1 0x02
5551 #define _CWG2DBR_CWG2DBR1 0x02
5552 #define _CWG2DBR_DBR2 0x04
5553 #define _CWG2DBR_CWG2DBR2 0x04
5554 #define _CWG2DBR_DBR3 0x08
5555 #define _CWG2DBR_CWG2DBR3 0x08
5556 #define _CWG2DBR_DBR4 0x10
5557 #define _CWG2DBR_CWG2DBR4 0x10
5558 #define _CWG2DBR_DBR5 0x20
5559 #define _CWG2DBR_CWG2DBR5 0x20
5561 //==============================================================================
5564 //==============================================================================
5567 extern __at(0x0714) __sfr CWG2DBF
;
5585 unsigned CWG2DBF0
: 1;
5586 unsigned CWG2DBF1
: 1;
5587 unsigned CWG2DBF2
: 1;
5588 unsigned CWG2DBF3
: 1;
5589 unsigned CWG2DBF4
: 1;
5590 unsigned CWG2DBF5
: 1;
5597 unsigned CWG2DBF
: 6;
5608 extern __at(0x0714) volatile __CWG2DBFbits_t CWG2DBFbits
;
5610 #define _CWG2DBF_DBF0 0x01
5611 #define _CWG2DBF_CWG2DBF0 0x01
5612 #define _CWG2DBF_DBF1 0x02
5613 #define _CWG2DBF_CWG2DBF1 0x02
5614 #define _CWG2DBF_DBF2 0x04
5615 #define _CWG2DBF_CWG2DBF2 0x04
5616 #define _CWG2DBF_DBF3 0x08
5617 #define _CWG2DBF_CWG2DBF3 0x08
5618 #define _CWG2DBF_DBF4 0x10
5619 #define _CWG2DBF_CWG2DBF4 0x10
5620 #define _CWG2DBF_DBF5 0x20
5621 #define _CWG2DBF_CWG2DBF5 0x20
5623 //==============================================================================
5626 //==============================================================================
5629 extern __at(0x0715) __sfr CWG2CON0
;
5647 unsigned CWG2MODE0
: 1;
5648 unsigned CWG2MODE1
: 1;
5649 unsigned CWG2MODE2
: 1;
5653 unsigned CWG2LD
: 1;
5666 unsigned CWG2EN
: 1;
5677 unsigned CWG2MODE
: 3;
5682 extern __at(0x0715) volatile __CWG2CON0bits_t CWG2CON0bits
;
5684 #define _CWG2CON0_MODE0 0x01
5685 #define _CWG2CON0_CWG2MODE0 0x01
5686 #define _CWG2CON0_MODE1 0x02
5687 #define _CWG2CON0_CWG2MODE1 0x02
5688 #define _CWG2CON0_MODE2 0x04
5689 #define _CWG2CON0_CWG2MODE2 0x04
5690 #define _CWG2CON0_LD 0x40
5691 #define _CWG2CON0_CWG2LD 0x40
5692 #define _CWG2CON0_EN 0x80
5693 #define _CWG2CON0_G2EN 0x80
5694 #define _CWG2CON0_CWG2EN 0x80
5696 //==============================================================================
5699 //==============================================================================
5702 extern __at(0x0716) __sfr CWG2CON1
;
5720 unsigned CWG2POLA
: 1;
5721 unsigned CWG2POLB
: 1;
5722 unsigned CWG2POLC
: 1;
5723 unsigned CWG2POLD
: 1;
5725 unsigned CWG2IN
: 1;
5731 extern __at(0x0716) volatile __CWG2CON1bits_t CWG2CON1bits
;
5733 #define _CWG2CON1_POLA 0x01
5734 #define _CWG2CON1_CWG2POLA 0x01
5735 #define _CWG2CON1_POLB 0x02
5736 #define _CWG2CON1_CWG2POLB 0x02
5737 #define _CWG2CON1_POLC 0x04
5738 #define _CWG2CON1_CWG2POLC 0x04
5739 #define _CWG2CON1_POLD 0x08
5740 #define _CWG2CON1_CWG2POLD 0x08
5741 #define _CWG2CON1_IN 0x20
5742 #define _CWG2CON1_CWG2IN 0x20
5744 //==============================================================================
5747 //==============================================================================
5750 extern __at(0x0717) __sfr CWG2AS0
;
5763 unsigned SHUTDOWN
: 1;
5770 unsigned CWG2LSAC0
: 1;
5771 unsigned CWG2LSAC1
: 1;
5772 unsigned CWG2LSBD0
: 1;
5773 unsigned CWG2LSBD1
: 1;
5774 unsigned CWG2REN
: 1;
5775 unsigned CWG2SHUTDOWN
: 1;
5781 unsigned CWG2LSAC
: 2;
5802 unsigned CWG2LSBD
: 2;
5807 extern __at(0x0717) volatile __CWG2AS0bits_t CWG2AS0bits
;
5809 #define _CWG2AS0_LSAC0 0x04
5810 #define _CWG2AS0_CWG2LSAC0 0x04
5811 #define _CWG2AS0_LSAC1 0x08
5812 #define _CWG2AS0_CWG2LSAC1 0x08
5813 #define _CWG2AS0_LSBD0 0x10
5814 #define _CWG2AS0_CWG2LSBD0 0x10
5815 #define _CWG2AS0_LSBD1 0x20
5816 #define _CWG2AS0_CWG2LSBD1 0x20
5817 #define _CWG2AS0_REN 0x40
5818 #define _CWG2AS0_CWG2REN 0x40
5819 #define _CWG2AS0_SHUTDOWN 0x80
5820 #define _CWG2AS0_CWG2SHUTDOWN 0x80
5822 //==============================================================================
5825 //==============================================================================
5828 extern __at(0x0718) __sfr CWG2AS1
;
5842 extern __at(0x0718) volatile __CWG2AS1bits_t CWG2AS1bits
;
5844 #define _CWG2AS1_AS0E 0x01
5845 #define _CWG2AS1_AS1E 0x02
5846 #define _CWG2AS1_AS2E 0x04
5847 #define _CWG2AS1_AS3E 0x08
5848 #define _CWG2AS1_AS4E 0x10
5850 //==============================================================================
5853 //==============================================================================
5856 extern __at(0x0719) __sfr CWG2STR
;
5874 unsigned CWG2STRA
: 1;
5875 unsigned CWG2STRB
: 1;
5876 unsigned CWG2STRC
: 1;
5877 unsigned CWG2STRD
: 1;
5878 unsigned CWG2OVRA
: 1;
5879 unsigned CWG2OVRB
: 1;
5880 unsigned CWG2OVRC
: 1;
5881 unsigned CWG2OVRD
: 1;
5885 extern __at(0x0719) volatile __CWG2STRbits_t CWG2STRbits
;
5887 #define _CWG2STR_STRA 0x01
5888 #define _CWG2STR_CWG2STRA 0x01
5889 #define _CWG2STR_STRB 0x02
5890 #define _CWG2STR_CWG2STRB 0x02
5891 #define _CWG2STR_STRC 0x04
5892 #define _CWG2STR_CWG2STRC 0x04
5893 #define _CWG2STR_STRD 0x08
5894 #define _CWG2STR_CWG2STRD 0x08
5895 #define _CWG2STR_OVRA 0x10
5896 #define _CWG2STR_CWG2OVRA 0x10
5897 #define _CWG2STR_OVRB 0x20
5898 #define _CWG2STR_CWG2OVRB 0x20
5899 #define _CWG2STR_OVRC 0x40
5900 #define _CWG2STR_CWG2OVRC 0x40
5901 #define _CWG2STR_OVRD 0x80
5902 #define _CWG2STR_CWG2OVRD 0x80
5904 //==============================================================================
5906 extern __at(0x0891) __sfr NVMADR
;
5908 //==============================================================================
5911 extern __at(0x0891) __sfr NVMADRL
;
5915 unsigned NVMADR0
: 1;
5916 unsigned NVMADR1
: 1;
5917 unsigned NVMADR2
: 1;
5918 unsigned NVMADR3
: 1;
5919 unsigned NVMADR4
: 1;
5920 unsigned NVMADR5
: 1;
5921 unsigned NVMADR6
: 1;
5922 unsigned NVMADR7
: 1;
5925 extern __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits
;
5927 #define _NVMADR0 0x01
5928 #define _NVMADR1 0x02
5929 #define _NVMADR2 0x04
5930 #define _NVMADR3 0x08
5931 #define _NVMADR4 0x10
5932 #define _NVMADR5 0x20
5933 #define _NVMADR6 0x40
5934 #define _NVMADR7 0x80
5936 //==============================================================================
5939 //==============================================================================
5942 extern __at(0x0892) __sfr NVMADRH
;
5946 unsigned NVMADR8
: 1;
5947 unsigned NVMADR9
: 1;
5948 unsigned NVMADR10
: 1;
5949 unsigned NVMADR11
: 1;
5950 unsigned NVMADR12
: 1;
5951 unsigned NVMADR13
: 1;
5952 unsigned NVMADR14
: 1;
5956 extern __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits
;
5958 #define _NVMADR8 0x01
5959 #define _NVMADR9 0x02
5960 #define _NVMADR10 0x04
5961 #define _NVMADR11 0x08
5962 #define _NVMADR12 0x10
5963 #define _NVMADR13 0x20
5964 #define _NVMADR14 0x40
5966 //==============================================================================
5968 extern __at(0x0893) __sfr NVMDAT
;
5970 //==============================================================================
5973 extern __at(0x0893) __sfr NVMDATL
;
5977 unsigned NVMDAT0
: 1;
5978 unsigned NVMDAT1
: 1;
5979 unsigned NVMDAT2
: 1;
5980 unsigned NVMDAT3
: 1;
5981 unsigned NVMDAT4
: 1;
5982 unsigned NVMDAT5
: 1;
5983 unsigned NVMDAT6
: 1;
5984 unsigned NVMDAT7
: 1;
5987 extern __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits
;
5989 #define _NVMDAT0 0x01
5990 #define _NVMDAT1 0x02
5991 #define _NVMDAT2 0x04
5992 #define _NVMDAT3 0x08
5993 #define _NVMDAT4 0x10
5994 #define _NVMDAT5 0x20
5995 #define _NVMDAT6 0x40
5996 #define _NVMDAT7 0x80
5998 //==============================================================================
6001 //==============================================================================
6004 extern __at(0x0894) __sfr NVMDATH
;
6008 unsigned NVMDAT8
: 1;
6009 unsigned NVMDAT9
: 1;
6010 unsigned NVMDAT10
: 1;
6011 unsigned NVMDAT11
: 1;
6012 unsigned NVMDAT12
: 1;
6013 unsigned NVMDAT13
: 1;
6018 extern __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits
;
6020 #define _NVMDAT8 0x01
6021 #define _NVMDAT9 0x02
6022 #define _NVMDAT10 0x04
6023 #define _NVMDAT11 0x08
6024 #define _NVMDAT12 0x10
6025 #define _NVMDAT13 0x20
6027 //==============================================================================
6030 //==============================================================================
6033 extern __at(0x0895) __sfr NVMCON1
;
6043 unsigned NVMREGS
: 1;
6047 extern __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits
;
6055 #define _NVMREGS 0x40
6057 //==============================================================================
6059 extern __at(0x0896) __sfr NVMCON2
;
6061 //==============================================================================
6064 extern __at(0x089B) __sfr PCON0
;
6068 unsigned NOT_BOR
: 1;
6069 unsigned NOT_POR
: 1;
6070 unsigned NOT_RI
: 1;
6071 unsigned NOT_RMCLR
: 1;
6072 unsigned NOT_RWDT
: 1;
6074 unsigned STKUNF
: 1;
6075 unsigned STKOVF
: 1;
6078 extern __at(0x089B) volatile __PCON0bits_t PCON0bits
;
6080 #define _NOT_BOR 0x01
6081 #define _NOT_POR 0x02
6082 #define _NOT_RI 0x04
6083 #define _NOT_RMCLR 0x08
6084 #define _NOT_RWDT 0x10
6085 #define _STKUNF 0x40
6086 #define _STKOVF 0x80
6088 //==============================================================================
6091 //==============================================================================
6094 extern __at(0x0911) __sfr PMD0
;
6099 unsigned CLKRMD
: 1;
6105 unsigned SYSCMD
: 1;
6108 extern __at(0x0911) volatile __PMD0bits_t PMD0bits
;
6111 #define _CLKRMD 0x02
6114 #define _SYSCMD 0x80
6116 //==============================================================================
6119 //==============================================================================
6122 extern __at(0x0912) __sfr PMD1
;
6126 unsigned TMR0MD
: 1;
6127 unsigned TMR1MD
: 1;
6128 unsigned TMR2MD
: 1;
6129 unsigned TMR3MD
: 1;
6130 unsigned TMR4MD
: 1;
6131 unsigned TMR5MD
: 1;
6132 unsigned TMR6MD
: 1;
6136 extern __at(0x0912) volatile __PMD1bits_t PMD1bits
;
6138 #define _TMR0MD 0x01
6139 #define _TMR1MD 0x02
6140 #define _TMR2MD 0x04
6141 #define _TMR3MD 0x08
6142 #define _TMR4MD 0x10
6143 #define _TMR5MD 0x20
6144 #define _TMR6MD 0x40
6147 //==============================================================================
6150 //==============================================================================
6153 extern __at(0x0913) __sfr PMD2
;
6158 unsigned CMP1MD
: 1;
6159 unsigned CMP2MD
: 1;
6167 extern __at(0x0913) volatile __PMD2bits_t PMD2bits
;
6169 #define _CMP1MD 0x02
6170 #define _CMP2MD 0x04
6174 //==============================================================================
6177 //==============================================================================
6180 extern __at(0x0914) __sfr PMD3
;
6184 unsigned CCP1MD
: 1;
6185 unsigned CCP2MD
: 1;
6186 unsigned CCP3MD
: 1;
6187 unsigned CCP4MD
: 1;
6188 unsigned PWM5MD
: 1;
6189 unsigned PWM6MD
: 1;
6190 unsigned CWG1MD
: 1;
6191 unsigned CWG2MD
: 1;
6194 extern __at(0x0914) volatile __PMD3bits_t PMD3bits
;
6196 #define _CCP1MD 0x01
6197 #define _CCP2MD 0x02
6198 #define _CCP3MD 0x04
6199 #define _CCP4MD 0x08
6200 #define _PWM5MD 0x10
6201 #define _PWM6MD 0x20
6202 #define _CWG1MD 0x40
6203 #define _CWG2MD 0x80
6205 //==============================================================================
6208 //==============================================================================
6211 extern __at(0x0915) __sfr PMD4
;
6216 unsigned MSSP1MD
: 1;
6220 unsigned UART1MD
: 1;
6225 extern __at(0x0915) volatile __PMD4bits_t PMD4bits
;
6227 #define _MSSP1MD 0x02
6228 #define _UART1MD 0x20
6230 //==============================================================================
6233 //==============================================================================
6236 extern __at(0x0916) __sfr PMD5
;
6241 unsigned CLC1MD
: 1;
6242 unsigned CLC2MD
: 1;
6243 unsigned CLC3MD
: 1;
6244 unsigned CLC4MD
: 1;
6250 extern __at(0x0916) volatile __PMD5bits_t PMD5bits
;
6253 #define _CLC1MD 0x02
6254 #define _CLC2MD 0x04
6255 #define _CLC3MD 0x08
6256 #define _CLC4MD 0x10
6258 //==============================================================================
6261 //==============================================================================
6264 extern __at(0x0918) __sfr CPUDOZE
;
6287 extern __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits
;
6297 //==============================================================================
6300 //==============================================================================
6303 extern __at(0x0919) __sfr OSCCON1
;
6333 extern __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits
;
6343 //==============================================================================
6346 //==============================================================================
6349 extern __at(0x091A) __sfr OSCCON2
;
6379 extern __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits
;
6389 //==============================================================================
6392 //==============================================================================
6395 extern __at(0x091B) __sfr OSCCON3
;
6404 unsigned SOSCBE
: 1;
6405 unsigned SOSCPWR
: 1;
6406 unsigned CSWHOLD
: 1;
6409 extern __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits
;
6413 #define _SOSCBE 0x20
6414 #define _SOSCPWR 0x40
6415 #define _CSWHOLD 0x80
6417 //==============================================================================
6420 //==============================================================================
6423 extern __at(0x091C) __sfr OSCSTAT1
;
6437 extern __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits
;
6446 //==============================================================================
6449 //==============================================================================
6452 extern __at(0x091D) __sfr OSCEN
;
6459 unsigned SOSCEN
: 1;
6463 unsigned EXTOEN
: 1;
6466 extern __at(0x091D) volatile __OSCENbits_t OSCENbits
;
6469 #define _SOSCEN 0x08
6472 #define _EXTOEN 0x80
6474 //==============================================================================
6477 //==============================================================================
6480 extern __at(0x091E) __sfr OSCTUNE
;
6486 unsigned HFTUN0
: 1;
6487 unsigned HFTUN1
: 1;
6488 unsigned HFTUN2
: 1;
6489 unsigned HFTUN3
: 1;
6490 unsigned HFTUN4
: 1;
6491 unsigned HFTUN5
: 1;
6503 extern __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits
;
6505 #define _HFTUN0 0x01
6506 #define _HFTUN1 0x02
6507 #define _HFTUN2 0x04
6508 #define _HFTUN3 0x08
6509 #define _HFTUN4 0x10
6510 #define _HFTUN5 0x20
6512 //==============================================================================
6515 //==============================================================================
6518 extern __at(0x091F) __sfr OSCFRQ
;
6524 unsigned HFFRQ0
: 1;
6525 unsigned HFFRQ1
: 1;
6526 unsigned HFFRQ2
: 1;
6527 unsigned HFFRQ3
: 1;
6541 extern __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits
;
6543 #define _HFFRQ0 0x01
6544 #define _HFFRQ1 0x02
6545 #define _HFFRQ2 0x04
6546 #define _HFFRQ3 0x08
6548 //==============================================================================
6551 //==============================================================================
6554 extern __at(0x0E0F) __sfr PPSLOCK
;
6558 unsigned PPSLOCKED
: 1;
6568 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
6570 #define _PPSLOCKED 0x01
6572 //==============================================================================
6575 //==============================================================================
6578 extern __at(0x0E10) __sfr INTPPS
;
6584 unsigned INTPPS0
: 1;
6585 unsigned INTPPS1
: 1;
6586 unsigned INTPPS2
: 1;
6587 unsigned INTPPS3
: 1;
6588 unsigned INTPPS4
: 1;
6596 unsigned INTPPS
: 5;
6601 extern __at(0x0E10) volatile __INTPPSbits_t INTPPSbits
;
6603 #define _INTPPS0 0x01
6604 #define _INTPPS1 0x02
6605 #define _INTPPS2 0x04
6606 #define _INTPPS3 0x08
6607 #define _INTPPS4 0x10
6609 //==============================================================================
6612 //==============================================================================
6615 extern __at(0x0E11) __sfr T0CKIPPS
;
6621 unsigned T0CKIPPS0
: 1;
6622 unsigned T0CKIPPS1
: 1;
6623 unsigned T0CKIPPS2
: 1;
6624 unsigned T0CKIPPS3
: 1;
6625 unsigned T0CKIPPS4
: 1;
6633 unsigned T0CKIPPS
: 5;
6638 extern __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits
;
6640 #define _T0CKIPPS0 0x01
6641 #define _T0CKIPPS1 0x02
6642 #define _T0CKIPPS2 0x04
6643 #define _T0CKIPPS3 0x08
6644 #define _T0CKIPPS4 0x10
6646 //==============================================================================
6649 //==============================================================================
6652 extern __at(0x0E12) __sfr T1CKIPPS
;
6658 unsigned T1CKIPPS0
: 1;
6659 unsigned T1CKIPPS1
: 1;
6660 unsigned T1CKIPPS2
: 1;
6661 unsigned T1CKIPPS3
: 1;
6662 unsigned T1CKIPPS4
: 1;
6670 unsigned T1CKIPPS
: 5;
6675 extern __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits
;
6677 #define _T1CKIPPS0 0x01
6678 #define _T1CKIPPS1 0x02
6679 #define _T1CKIPPS2 0x04
6680 #define _T1CKIPPS3 0x08
6681 #define _T1CKIPPS4 0x10
6683 //==============================================================================
6686 //==============================================================================
6689 extern __at(0x0E13) __sfr T1GPPS
;
6695 unsigned T1GPPS0
: 1;
6696 unsigned T1GPPS1
: 1;
6697 unsigned T1GPPS2
: 1;
6698 unsigned T1GPPS3
: 1;
6699 unsigned T1GPPS4
: 1;
6707 unsigned T1GPPS
: 5;
6712 extern __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits
;
6714 #define _T1GPPS0 0x01
6715 #define _T1GPPS1 0x02
6716 #define _T1GPPS2 0x04
6717 #define _T1GPPS3 0x08
6718 #define _T1GPPS4 0x10
6720 //==============================================================================
6723 //==============================================================================
6726 extern __at(0x0E14) __sfr CCP1PPS
;
6732 unsigned CCP1PPS0
: 1;
6733 unsigned CCP1PPS1
: 1;
6734 unsigned CCP1PPS2
: 1;
6735 unsigned CCP1PPS3
: 1;
6736 unsigned CCP1PPS4
: 1;
6744 unsigned CCP1PPS
: 5;
6749 extern __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits
;
6751 #define _CCP1PPS0 0x01
6752 #define _CCP1PPS1 0x02
6753 #define _CCP1PPS2 0x04
6754 #define _CCP1PPS3 0x08
6755 #define _CCP1PPS4 0x10
6757 //==============================================================================
6760 //==============================================================================
6763 extern __at(0x0E15) __sfr CCP2PPS
;
6769 unsigned CCP2PPS0
: 1;
6770 unsigned CCP2PPS1
: 1;
6771 unsigned CCP2PPS2
: 1;
6772 unsigned CCP2PPS3
: 1;
6773 unsigned CCP2PPS4
: 1;
6781 unsigned CCP2PPS
: 5;
6786 extern __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits
;
6788 #define _CCP2PPS0 0x01
6789 #define _CCP2PPS1 0x02
6790 #define _CCP2PPS2 0x04
6791 #define _CCP2PPS3 0x08
6792 #define _CCP2PPS4 0x10
6794 //==============================================================================
6797 //==============================================================================
6800 extern __at(0x0E16) __sfr CCP3PPS
;
6806 unsigned CCP3PPS0
: 1;
6807 unsigned CCP3PPS1
: 1;
6808 unsigned CCP3PPS2
: 1;
6809 unsigned CCP3PPS3
: 1;
6810 unsigned CCP3PPS4
: 1;
6818 unsigned CCP3PPS
: 5;
6823 extern __at(0x0E16) volatile __CCP3PPSbits_t CCP3PPSbits
;
6825 #define _CCP3PPS0 0x01
6826 #define _CCP3PPS1 0x02
6827 #define _CCP3PPS2 0x04
6828 #define _CCP3PPS3 0x08
6829 #define _CCP3PPS4 0x10
6831 //==============================================================================
6834 //==============================================================================
6837 extern __at(0x0E17) __sfr CCP4PPS
;
6843 unsigned CCP4PPS0
: 1;
6844 unsigned CCP4PPS1
: 1;
6845 unsigned CCP4PPS2
: 1;
6846 unsigned CCP4PPS3
: 1;
6847 unsigned CCP4PPS4
: 1;
6855 unsigned CCP4PPS
: 5;
6860 extern __at(0x0E17) volatile __CCP4PPSbits_t CCP4PPSbits
;
6862 #define _CCP4PPS0 0x01
6863 #define _CCP4PPS1 0x02
6864 #define _CCP4PPS2 0x04
6865 #define _CCP4PPS3 0x08
6866 #define _CCP4PPS4 0x10
6868 //==============================================================================
6871 //==============================================================================
6874 extern __at(0x0E18) __sfr CWG1PPS
;
6880 unsigned CWG1PPS0
: 1;
6881 unsigned CWG1PPS1
: 1;
6882 unsigned CWG1PPS2
: 1;
6883 unsigned CWG1PPS3
: 1;
6884 unsigned CWG1PPS4
: 1;
6892 unsigned CWG1PPS
: 5;
6897 extern __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits
;
6899 #define _CWG1PPS0 0x01
6900 #define _CWG1PPS1 0x02
6901 #define _CWG1PPS2 0x04
6902 #define _CWG1PPS3 0x08
6903 #define _CWG1PPS4 0x10
6905 //==============================================================================
6908 //==============================================================================
6911 extern __at(0x0E19) __sfr CWG2PPS
;
6917 unsigned CWG2PPS0
: 1;
6918 unsigned CWG2PPS1
: 1;
6919 unsigned CWG2PPS2
: 1;
6920 unsigned CWG2PPS3
: 1;
6921 unsigned CWG2PPS4
: 1;
6929 unsigned CWG2PPS
: 5;
6934 extern __at(0x0E19) volatile __CWG2PPSbits_t CWG2PPSbits
;
6936 #define _CWG2PPS0 0x01
6937 #define _CWG2PPS1 0x02
6938 #define _CWG2PPS2 0x04
6939 #define _CWG2PPS3 0x08
6940 #define _CWG2PPS4 0x10
6942 //==============================================================================
6945 //==============================================================================
6948 extern __at(0x0E1A) __sfr MDCIN1PPS
;
6954 unsigned MDCIN1PPS0
: 1;
6955 unsigned MDCIN1PPS1
: 1;
6956 unsigned MDCIN1PPS2
: 1;
6957 unsigned MDCIN1PPS3
: 1;
6958 unsigned MDCIN1PPS4
: 1;
6966 unsigned MDCIN1PPS
: 5;
6969 } __MDCIN1PPSbits_t
;
6971 extern __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits
;
6973 #define _MDCIN1PPS0 0x01
6974 #define _MDCIN1PPS1 0x02
6975 #define _MDCIN1PPS2 0x04
6976 #define _MDCIN1PPS3 0x08
6977 #define _MDCIN1PPS4 0x10
6979 //==============================================================================
6982 //==============================================================================
6985 extern __at(0x0E1B) __sfr MDCIN2PPS
;
6991 unsigned MDCIN2PPS0
: 1;
6992 unsigned MDCIN2PPS1
: 1;
6993 unsigned MDCIN2PPS2
: 1;
6994 unsigned MDCIN2PPS3
: 1;
6995 unsigned MDCIN2PPS4
: 1;
7003 unsigned MDCIN2PPS
: 5;
7006 } __MDCIN2PPSbits_t
;
7008 extern __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits
;
7010 #define _MDCIN2PPS0 0x01
7011 #define _MDCIN2PPS1 0x02
7012 #define _MDCIN2PPS2 0x04
7013 #define _MDCIN2PPS3 0x08
7014 #define _MDCIN2PPS4 0x10
7016 //==============================================================================
7019 //==============================================================================
7022 extern __at(0x0E1C) __sfr MDMINPPS
;
7028 unsigned MDMINPPS0
: 1;
7029 unsigned MDMINPPS1
: 1;
7030 unsigned MDMINPPS2
: 1;
7031 unsigned MDMINPPS3
: 1;
7032 unsigned MDMINPPS4
: 1;
7040 unsigned MDMINPPS
: 5;
7045 extern __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits
;
7047 #define _MDMINPPS0 0x01
7048 #define _MDMINPPS1 0x02
7049 #define _MDMINPPS2 0x04
7050 #define _MDMINPPS3 0x08
7051 #define _MDMINPPS4 0x10
7053 //==============================================================================
7056 //==============================================================================
7059 extern __at(0x0E20) __sfr SSP1CLKPPS
;
7065 unsigned SSP1CLKPPS0
: 1;
7066 unsigned SSP1CLKPPS1
: 1;
7067 unsigned SSP1CLKPPS2
: 1;
7068 unsigned SSP1CLKPPS3
: 1;
7069 unsigned SSP1CLKPPS4
: 1;
7077 unsigned SSP1CLKPPS
: 5;
7080 } __SSP1CLKPPSbits_t
;
7082 extern __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits
;
7084 #define _SSP1CLKPPS0 0x01
7085 #define _SSP1CLKPPS1 0x02
7086 #define _SSP1CLKPPS2 0x04
7087 #define _SSP1CLKPPS3 0x08
7088 #define _SSP1CLKPPS4 0x10
7090 //==============================================================================
7093 //==============================================================================
7096 extern __at(0x0E21) __sfr SSP1DATPPS
;
7102 unsigned SSP1DATPPS0
: 1;
7103 unsigned SSP1DATPPS1
: 1;
7104 unsigned SSP1DATPPS2
: 1;
7105 unsigned SSP1DATPPS3
: 1;
7106 unsigned SSP1DATPPS4
: 1;
7114 unsigned SSP1DATPPS
: 5;
7117 } __SSP1DATPPSbits_t
;
7119 extern __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits
;
7121 #define _SSP1DATPPS0 0x01
7122 #define _SSP1DATPPS1 0x02
7123 #define _SSP1DATPPS2 0x04
7124 #define _SSP1DATPPS3 0x08
7125 #define _SSP1DATPPS4 0x10
7127 //==============================================================================
7130 //==============================================================================
7133 extern __at(0x0E22) __sfr SSP1SSPPS
;
7139 unsigned SSP1SSPPS0
: 1;
7140 unsigned SSP1SSPPS1
: 1;
7141 unsigned SSP1SSPPS2
: 1;
7142 unsigned SSP1SSPPS3
: 1;
7143 unsigned SSP1SSPPS4
: 1;
7151 unsigned SSP1SSPPS
: 5;
7154 } __SSP1SSPPSbits_t
;
7156 extern __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits
;
7158 #define _SSP1SSPPS0 0x01
7159 #define _SSP1SSPPS1 0x02
7160 #define _SSP1SSPPS2 0x04
7161 #define _SSP1SSPPS3 0x08
7162 #define _SSP1SSPPS4 0x10
7164 //==============================================================================
7167 //==============================================================================
7170 extern __at(0x0E24) __sfr RXPPS
;
7176 unsigned RXDTPPS0
: 1;
7177 unsigned RXDTPPS1
: 1;
7178 unsigned RXDTPPS2
: 1;
7179 unsigned RXDTPPS3
: 1;
7180 unsigned RXDTPPS4
: 1;
7188 unsigned RXDTPPS
: 5;
7193 extern __at(0x0E24) volatile __RXPPSbits_t RXPPSbits
;
7195 #define _RXDTPPS0 0x01
7196 #define _RXDTPPS1 0x02
7197 #define _RXDTPPS2 0x04
7198 #define _RXDTPPS3 0x08
7199 #define _RXDTPPS4 0x10
7201 //==============================================================================
7204 //==============================================================================
7207 extern __at(0x0E25) __sfr TXPPS
;
7213 unsigned TXCKPPS0
: 1;
7214 unsigned TXCKPPS1
: 1;
7215 unsigned TXCKPPS2
: 1;
7216 unsigned TXCKPPS3
: 1;
7217 unsigned TXCKPPS4
: 1;
7225 unsigned TXCKPPS
: 5;
7230 extern __at(0x0E25) volatile __TXPPSbits_t TXPPSbits
;
7232 #define _TXCKPPS0 0x01
7233 #define _TXCKPPS1 0x02
7234 #define _TXCKPPS2 0x04
7235 #define _TXCKPPS3 0x08
7236 #define _TXCKPPS4 0x10
7238 //==============================================================================
7241 //==============================================================================
7244 extern __at(0x0E28) __sfr CLCIN0PPS
;
7250 unsigned CLCIN0PPS0
: 1;
7251 unsigned CLCIN0PPS1
: 1;
7252 unsigned CLCIN0PPS2
: 1;
7253 unsigned CLCIN0PPS3
: 1;
7254 unsigned CLCIN0PPS4
: 1;
7262 unsigned CLCIN0PPS
: 5;
7265 } __CLCIN0PPSbits_t
;
7267 extern __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits
;
7269 #define _CLCIN0PPS0 0x01
7270 #define _CLCIN0PPS1 0x02
7271 #define _CLCIN0PPS2 0x04
7272 #define _CLCIN0PPS3 0x08
7273 #define _CLCIN0PPS4 0x10
7275 //==============================================================================
7278 //==============================================================================
7281 extern __at(0x0E29) __sfr CLCIN1PPS
;
7287 unsigned CLCIN1PPS0
: 1;
7288 unsigned CLCIN1PPS1
: 1;
7289 unsigned CLCIN1PPS2
: 1;
7290 unsigned CLCIN1PPS3
: 1;
7291 unsigned CLCIN1PPS4
: 1;
7299 unsigned CLCIN1PPS
: 5;
7302 } __CLCIN1PPSbits_t
;
7304 extern __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits
;
7306 #define _CLCIN1PPS0 0x01
7307 #define _CLCIN1PPS1 0x02
7308 #define _CLCIN1PPS2 0x04
7309 #define _CLCIN1PPS3 0x08
7310 #define _CLCIN1PPS4 0x10
7312 //==============================================================================
7315 //==============================================================================
7318 extern __at(0x0E2A) __sfr CLCIN2PPS
;
7324 unsigned CLCIN2PPS0
: 1;
7325 unsigned CLCIN2PPS1
: 1;
7326 unsigned CLCIN2PPS2
: 1;
7327 unsigned CLCIN2PPS3
: 1;
7328 unsigned CLCIN2PPS4
: 1;
7336 unsigned CLCIN2PPS
: 5;
7339 } __CLCIN2PPSbits_t
;
7341 extern __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits
;
7343 #define _CLCIN2PPS0 0x01
7344 #define _CLCIN2PPS1 0x02
7345 #define _CLCIN2PPS2 0x04
7346 #define _CLCIN2PPS3 0x08
7347 #define _CLCIN2PPS4 0x10
7349 //==============================================================================
7352 //==============================================================================
7355 extern __at(0x0E2B) __sfr CLCIN3PPS
;
7361 unsigned CLCIN3PPS0
: 1;
7362 unsigned CLCIN3PPS1
: 1;
7363 unsigned CLCIN3PPS2
: 1;
7364 unsigned CLCIN3PPS3
: 1;
7365 unsigned CLCIN3PPS4
: 1;
7373 unsigned CLCIN3PPS
: 5;
7376 } __CLCIN3PPSbits_t
;
7378 extern __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits
;
7380 #define _CLCIN3PPS0 0x01
7381 #define _CLCIN3PPS1 0x02
7382 #define _CLCIN3PPS2 0x04
7383 #define _CLCIN3PPS3 0x08
7384 #define _CLCIN3PPS4 0x10
7386 //==============================================================================
7388 extern __at(0x0E2C) __sfr T3CKIPPS
;
7389 extern __at(0x0E2D) __sfr T3GPPS
;
7390 extern __at(0x0E2E) __sfr T5CKIPPS
;
7391 extern __at(0x0E2F) __sfr T5GPPS
;
7393 //==============================================================================
7396 extern __at(0x0E90) __sfr RA0PPS
;
7402 unsigned RA0PPS0
: 1;
7403 unsigned RA0PPS1
: 1;
7404 unsigned RA0PPS2
: 1;
7405 unsigned RA0PPS3
: 1;
7406 unsigned RA0PPS4
: 1;
7414 unsigned RA0PPS
: 5;
7419 extern __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits
;
7421 #define _RA0PPS0 0x01
7422 #define _RA0PPS1 0x02
7423 #define _RA0PPS2 0x04
7424 #define _RA0PPS3 0x08
7425 #define _RA0PPS4 0x10
7427 //==============================================================================
7430 //==============================================================================
7433 extern __at(0x0E91) __sfr RA1PPS
;
7439 unsigned RA1PPS0
: 1;
7440 unsigned RA1PPS1
: 1;
7441 unsigned RA1PPS2
: 1;
7442 unsigned RA1PPS3
: 1;
7443 unsigned RA1PPS4
: 1;
7451 unsigned RA1PPS
: 5;
7456 extern __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits
;
7458 #define _RA1PPS0 0x01
7459 #define _RA1PPS1 0x02
7460 #define _RA1PPS2 0x04
7461 #define _RA1PPS3 0x08
7462 #define _RA1PPS4 0x10
7464 //==============================================================================
7467 //==============================================================================
7470 extern __at(0x0E92) __sfr RA2PPS
;
7476 unsigned RA2PPS0
: 1;
7477 unsigned RA2PPS1
: 1;
7478 unsigned RA2PPS2
: 1;
7479 unsigned RA2PPS3
: 1;
7480 unsigned RA2PPS4
: 1;
7488 unsigned RA2PPS
: 5;
7493 extern __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits
;
7495 #define _RA2PPS0 0x01
7496 #define _RA2PPS1 0x02
7497 #define _RA2PPS2 0x04
7498 #define _RA2PPS3 0x08
7499 #define _RA2PPS4 0x10
7501 //==============================================================================
7504 //==============================================================================
7507 extern __at(0x0E94) __sfr RA4PPS
;
7513 unsigned RA4PPS0
: 1;
7514 unsigned RA4PPS1
: 1;
7515 unsigned RA4PPS2
: 1;
7516 unsigned RA4PPS3
: 1;
7517 unsigned RA4PPS4
: 1;
7525 unsigned RA4PPS
: 5;
7530 extern __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits
;
7532 #define _RA4PPS0 0x01
7533 #define _RA4PPS1 0x02
7534 #define _RA4PPS2 0x04
7535 #define _RA4PPS3 0x08
7536 #define _RA4PPS4 0x10
7538 //==============================================================================
7541 //==============================================================================
7544 extern __at(0x0E95) __sfr RA5PPS
;
7550 unsigned RA5PPS0
: 1;
7551 unsigned RA5PPS1
: 1;
7552 unsigned RA5PPS2
: 1;
7553 unsigned RA5PPS3
: 1;
7554 unsigned RA5PPS4
: 1;
7562 unsigned RA5PPS
: 5;
7567 extern __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits
;
7569 #define _RA5PPS0 0x01
7570 #define _RA5PPS1 0x02
7571 #define _RA5PPS2 0x04
7572 #define _RA5PPS3 0x08
7573 #define _RA5PPS4 0x10
7575 //==============================================================================
7577 extern __at(0x0E9C) __sfr RB4PPS
;
7578 extern __at(0x0E9D) __sfr RB5PPS
;
7579 extern __at(0x0E9E) __sfr RB6PPS
;
7580 extern __at(0x0E9F) __sfr RB7PPS
;
7582 //==============================================================================
7585 extern __at(0x0EA0) __sfr RC0PPS
;
7591 unsigned RC0PPS0
: 1;
7592 unsigned RC0PPS1
: 1;
7593 unsigned RC0PPS2
: 1;
7594 unsigned RC0PPS3
: 1;
7595 unsigned RC0PPS4
: 1;
7603 unsigned RC0PPS
: 5;
7608 extern __at(0x0EA0) volatile __RC0PPSbits_t RC0PPSbits
;
7610 #define _RC0PPS0 0x01
7611 #define _RC0PPS1 0x02
7612 #define _RC0PPS2 0x04
7613 #define _RC0PPS3 0x08
7614 #define _RC0PPS4 0x10
7616 //==============================================================================
7619 //==============================================================================
7622 extern __at(0x0EA1) __sfr RC1PPS
;
7628 unsigned RC1PPS0
: 1;
7629 unsigned RC1PPS1
: 1;
7630 unsigned RC1PPS2
: 1;
7631 unsigned RC1PPS3
: 1;
7632 unsigned RC1PPS4
: 1;
7640 unsigned RC1PPS
: 5;
7645 extern __at(0x0EA1) volatile __RC1PPSbits_t RC1PPSbits
;
7647 #define _RC1PPS0 0x01
7648 #define _RC1PPS1 0x02
7649 #define _RC1PPS2 0x04
7650 #define _RC1PPS3 0x08
7651 #define _RC1PPS4 0x10
7653 //==============================================================================
7656 //==============================================================================
7659 extern __at(0x0EA2) __sfr RC2PPS
;
7665 unsigned RC2PPS0
: 1;
7666 unsigned RC2PPS1
: 1;
7667 unsigned RC2PPS2
: 1;
7668 unsigned RC2PPS3
: 1;
7669 unsigned RC2PPS4
: 1;
7677 unsigned RC2PPS
: 5;
7682 extern __at(0x0EA2) volatile __RC2PPSbits_t RC2PPSbits
;
7684 #define _RC2PPS0 0x01
7685 #define _RC2PPS1 0x02
7686 #define _RC2PPS2 0x04
7687 #define _RC2PPS3 0x08
7688 #define _RC2PPS4 0x10
7690 //==============================================================================
7693 //==============================================================================
7696 extern __at(0x0EA3) __sfr RC3PPS
;
7702 unsigned RC3PPS0
: 1;
7703 unsigned RC3PPS1
: 1;
7704 unsigned RC3PPS2
: 1;
7705 unsigned RC3PPS3
: 1;
7706 unsigned RC3PPS4
: 1;
7714 unsigned RC3PPS
: 5;
7719 extern __at(0x0EA3) volatile __RC3PPSbits_t RC3PPSbits
;
7721 #define _RC3PPS0 0x01
7722 #define _RC3PPS1 0x02
7723 #define _RC3PPS2 0x04
7724 #define _RC3PPS3 0x08
7725 #define _RC3PPS4 0x10
7727 //==============================================================================
7730 //==============================================================================
7733 extern __at(0x0EA4) __sfr RC4PPS
;
7739 unsigned RC4PPS0
: 1;
7740 unsigned RC4PPS1
: 1;
7741 unsigned RC4PPS2
: 1;
7742 unsigned RC4PPS3
: 1;
7743 unsigned RC4PPS4
: 1;
7751 unsigned RC4PPS
: 5;
7756 extern __at(0x0EA4) volatile __RC4PPSbits_t RC4PPSbits
;
7758 #define _RC4PPS0 0x01
7759 #define _RC4PPS1 0x02
7760 #define _RC4PPS2 0x04
7761 #define _RC4PPS3 0x08
7762 #define _RC4PPS4 0x10
7764 //==============================================================================
7767 //==============================================================================
7770 extern __at(0x0EA5) __sfr RC5PPS
;
7776 unsigned RC5PPS0
: 1;
7777 unsigned RC5PPS1
: 1;
7778 unsigned RC5PPS2
: 1;
7779 unsigned RC5PPS3
: 1;
7780 unsigned RC5PPS4
: 1;
7788 unsigned RC5PPS
: 5;
7793 extern __at(0x0EA5) volatile __RC5PPSbits_t RC5PPSbits
;
7795 #define _RC5PPS0 0x01
7796 #define _RC5PPS1 0x02
7797 #define _RC5PPS2 0x04
7798 #define _RC5PPS3 0x08
7799 #define _RC5PPS4 0x10
7801 //==============================================================================
7803 extern __at(0x0EA6) __sfr RC6PPS
;
7804 extern __at(0x0EA7) __sfr RC7PPS
;
7806 //==============================================================================
7809 extern __at(0x0F0F) __sfr CLCDATA
;
7813 unsigned MLC1OUT
: 1;
7814 unsigned MLC2OUT
: 1;
7815 unsigned MLC3OUT
: 1;
7816 unsigned MLC4OUT
: 1;
7823 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
7825 #define _MLC1OUT 0x01
7826 #define _MLC2OUT 0x02
7827 #define _MLC3OUT 0x04
7828 #define _MLC4OUT 0x08
7830 //==============================================================================
7833 //==============================================================================
7836 extern __at(0x0F10) __sfr CLC1CON
;
7842 unsigned LC1MODE0
: 1;
7843 unsigned LC1MODE1
: 1;
7844 unsigned LC1MODE2
: 1;
7845 unsigned LC1INTN
: 1;
7846 unsigned LC1INTP
: 1;
7847 unsigned LC1OUT
: 1;
7866 unsigned LC1MODE
: 3;
7877 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
7879 #define _LC1MODE0 0x01
7881 #define _LC1MODE1 0x02
7883 #define _LC1MODE2 0x04
7885 #define _LC1INTN 0x08
7887 #define _LC1INTP 0x10
7889 #define _LC1OUT 0x20
7894 //==============================================================================
7897 //==============================================================================
7900 extern __at(0x0F11) __sfr CLC1POL
;
7906 unsigned LC1G1POL
: 1;
7907 unsigned LC1G2POL
: 1;
7908 unsigned LC1G3POL
: 1;
7909 unsigned LC1G4POL
: 1;
7913 unsigned LC1POL
: 1;
7929 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
7931 #define _LC1G1POL 0x01
7933 #define _LC1G2POL 0x02
7935 #define _LC1G3POL 0x04
7937 #define _LC1G4POL 0x08
7939 #define _LC1POL 0x80
7942 //==============================================================================
7945 //==============================================================================
7948 extern __at(0x0F12) __sfr CLC1SEL0
;
7954 unsigned LC1D1S0
: 1;
7955 unsigned LC1D1S1
: 1;
7956 unsigned LC1D1S2
: 1;
7957 unsigned LC1D1S3
: 1;
7958 unsigned LC1D1S4
: 1;
7959 unsigned LC1D1S5
: 1;
7978 unsigned LC1D1S
: 6;
7989 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
7991 #define _LC1D1S0 0x01
7993 #define _LC1D1S1 0x02
7995 #define _LC1D1S2 0x04
7997 #define _LC1D1S3 0x08
7999 #define _LC1D1S4 0x10
8001 #define _LC1D1S5 0x20
8004 //==============================================================================
8007 //==============================================================================
8010 extern __at(0x0F13) __sfr CLC1SEL1
;
8016 unsigned LC1D2S0
: 1;
8017 unsigned LC1D2S1
: 1;
8018 unsigned LC1D2S2
: 1;
8019 unsigned LC1D2S3
: 1;
8020 unsigned LC1D2S4
: 1;
8021 unsigned LC1D2S5
: 1;
8046 unsigned LC1D2S
: 6;
8051 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
8053 #define _LC1D2S0 0x01
8055 #define _LC1D2S1 0x02
8057 #define _LC1D2S2 0x04
8059 #define _LC1D2S3 0x08
8061 #define _LC1D2S4 0x10
8063 #define _LC1D2S5 0x20
8066 //==============================================================================
8069 //==============================================================================
8072 extern __at(0x0F14) __sfr CLC1SEL2
;
8078 unsigned LC1D3S0
: 1;
8079 unsigned LC1D3S1
: 1;
8080 unsigned LC1D3S2
: 1;
8081 unsigned LC1D3S3
: 1;
8082 unsigned LC1D3S4
: 1;
8083 unsigned LC1D3S5
: 1;
8102 unsigned LC1D3S
: 6;
8113 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
8115 #define _LC1D3S0 0x01
8117 #define _LC1D3S1 0x02
8119 #define _LC1D3S2 0x04
8121 #define _LC1D3S3 0x08
8123 #define _LC1D3S4 0x10
8125 #define _LC1D3S5 0x20
8128 //==============================================================================
8131 //==============================================================================
8134 extern __at(0x0F15) __sfr CLC1SEL3
;
8140 unsigned LC1D4S0
: 1;
8141 unsigned LC1D4S1
: 1;
8142 unsigned LC1D4S2
: 1;
8143 unsigned LC1D4S3
: 1;
8144 unsigned LC1D4S4
: 1;
8145 unsigned LC1D4S5
: 1;
8164 unsigned LC1D4S
: 6;
8175 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
8177 #define _LC1D4S0 0x01
8179 #define _LC1D4S1 0x02
8181 #define _LC1D4S2 0x04
8183 #define _LC1D4S3 0x08
8185 #define _LC1D4S4 0x10
8187 #define _LC1D4S5 0x20
8190 //==============================================================================
8193 //==============================================================================
8196 extern __at(0x0F16) __sfr CLC1GLS0
;
8202 unsigned LC1G1D1N
: 1;
8203 unsigned LC1G1D1T
: 1;
8204 unsigned LC1G1D2N
: 1;
8205 unsigned LC1G1D2T
: 1;
8206 unsigned LC1G1D3N
: 1;
8207 unsigned LC1G1D3T
: 1;
8208 unsigned LC1G1D4N
: 1;
8209 unsigned LC1G1D4T
: 1;
8225 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
8227 #define _LC1G1D1N 0x01
8229 #define _LC1G1D1T 0x02
8231 #define _LC1G1D2N 0x04
8233 #define _LC1G1D2T 0x08
8235 #define _LC1G1D3N 0x10
8237 #define _LC1G1D3T 0x20
8239 #define _LC1G1D4N 0x40
8241 #define _LC1G1D4T 0x80
8244 //==============================================================================
8247 //==============================================================================
8250 extern __at(0x0F17) __sfr CLC1GLS1
;
8256 unsigned LC1G2D1N
: 1;
8257 unsigned LC1G2D1T
: 1;
8258 unsigned LC1G2D2N
: 1;
8259 unsigned LC1G2D2T
: 1;
8260 unsigned LC1G2D3N
: 1;
8261 unsigned LC1G2D3T
: 1;
8262 unsigned LC1G2D4N
: 1;
8263 unsigned LC1G2D4T
: 1;
8279 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
8281 #define _CLC1GLS1_LC1G2D1N 0x01
8282 #define _CLC1GLS1_D1N 0x01
8283 #define _CLC1GLS1_LC1G2D1T 0x02
8284 #define _CLC1GLS1_D1T 0x02
8285 #define _CLC1GLS1_LC1G2D2N 0x04
8286 #define _CLC1GLS1_D2N 0x04
8287 #define _CLC1GLS1_LC1G2D2T 0x08
8288 #define _CLC1GLS1_D2T 0x08
8289 #define _CLC1GLS1_LC1G2D3N 0x10
8290 #define _CLC1GLS1_D3N 0x10
8291 #define _CLC1GLS1_LC1G2D3T 0x20
8292 #define _CLC1GLS1_D3T 0x20
8293 #define _CLC1GLS1_LC1G2D4N 0x40
8294 #define _CLC1GLS1_D4N 0x40
8295 #define _CLC1GLS1_LC1G2D4T 0x80
8296 #define _CLC1GLS1_D4T 0x80
8298 //==============================================================================
8301 //==============================================================================
8304 extern __at(0x0F18) __sfr CLC1GLS2
;
8310 unsigned LC1G3D1N
: 1;
8311 unsigned LC1G3D1T
: 1;
8312 unsigned LC1G3D2N
: 1;
8313 unsigned LC1G3D2T
: 1;
8314 unsigned LC1G3D3N
: 1;
8315 unsigned LC1G3D3T
: 1;
8316 unsigned LC1G3D4N
: 1;
8317 unsigned LC1G3D4T
: 1;
8333 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
8335 #define _CLC1GLS2_LC1G3D1N 0x01
8336 #define _CLC1GLS2_D1N 0x01
8337 #define _CLC1GLS2_LC1G3D1T 0x02
8338 #define _CLC1GLS2_D1T 0x02
8339 #define _CLC1GLS2_LC1G3D2N 0x04
8340 #define _CLC1GLS2_D2N 0x04
8341 #define _CLC1GLS2_LC1G3D2T 0x08
8342 #define _CLC1GLS2_D2T 0x08
8343 #define _CLC1GLS2_LC1G3D3N 0x10
8344 #define _CLC1GLS2_D3N 0x10
8345 #define _CLC1GLS2_LC1G3D3T 0x20
8346 #define _CLC1GLS2_D3T 0x20
8347 #define _CLC1GLS2_LC1G3D4N 0x40
8348 #define _CLC1GLS2_D4N 0x40
8349 #define _CLC1GLS2_LC1G3D4T 0x80
8350 #define _CLC1GLS2_D4T 0x80
8352 //==============================================================================
8355 //==============================================================================
8358 extern __at(0x0F19) __sfr CLC1GLS3
;
8364 unsigned LC1G4D1N
: 1;
8365 unsigned LC1G4D1T
: 1;
8366 unsigned LC1G4D2N
: 1;
8367 unsigned LC1G4D2T
: 1;
8368 unsigned LC1G4D3N
: 1;
8369 unsigned LC1G4D3T
: 1;
8370 unsigned LC1G4D4N
: 1;
8371 unsigned LC1G4D4T
: 1;
8387 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
8389 #define _LC1G4D1N 0x01
8391 #define _LC1G4D1T 0x02
8393 #define _LC1G4D2N 0x04
8395 #define _LC1G4D2T 0x08
8397 #define _LC1G4D3N 0x10
8399 #define _LC1G4D3T 0x20
8401 #define _LC1G4D4N 0x40
8403 #define _LC1G4D4T 0x80
8406 //==============================================================================
8409 //==============================================================================
8412 extern __at(0x0F1A) __sfr CLC2CON
;
8418 unsigned LC2MODE0
: 1;
8419 unsigned LC2MODE1
: 1;
8420 unsigned LC2MODE2
: 1;
8421 unsigned LC2INTN
: 1;
8422 unsigned LC2INTP
: 1;
8423 unsigned LC2OUT
: 1;
8448 unsigned LC2MODE
: 3;
8453 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
8455 #define _CLC2CON_LC2MODE0 0x01
8456 #define _CLC2CON_MODE0 0x01
8457 #define _CLC2CON_LC2MODE1 0x02
8458 #define _CLC2CON_MODE1 0x02
8459 #define _CLC2CON_LC2MODE2 0x04
8460 #define _CLC2CON_MODE2 0x04
8461 #define _CLC2CON_LC2INTN 0x08
8462 #define _CLC2CON_INTN 0x08
8463 #define _CLC2CON_LC2INTP 0x10
8464 #define _CLC2CON_INTP 0x10
8465 #define _CLC2CON_LC2OUT 0x20
8466 #define _CLC2CON_OUT 0x20
8467 #define _CLC2CON_LC2EN 0x80
8468 #define _CLC2CON_EN 0x80
8470 //==============================================================================
8473 //==============================================================================
8476 extern __at(0x0F1B) __sfr CLC2POL
;
8482 unsigned LC2G1POL
: 1;
8483 unsigned LC2G2POL
: 1;
8484 unsigned LC2G3POL
: 1;
8485 unsigned LC2G4POL
: 1;
8489 unsigned LC2POL
: 1;
8505 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
8507 #define _CLC2POL_LC2G1POL 0x01
8508 #define _CLC2POL_G1POL 0x01
8509 #define _CLC2POL_LC2G2POL 0x02
8510 #define _CLC2POL_G2POL 0x02
8511 #define _CLC2POL_LC2G3POL 0x04
8512 #define _CLC2POL_G3POL 0x04
8513 #define _CLC2POL_LC2G4POL 0x08
8514 #define _CLC2POL_G4POL 0x08
8515 #define _CLC2POL_LC2POL 0x80
8516 #define _CLC2POL_POL 0x80
8518 //==============================================================================
8521 //==============================================================================
8524 extern __at(0x0F1C) __sfr CLC2SEL0
;
8530 unsigned LC2D1S0
: 1;
8531 unsigned LC2D1S1
: 1;
8532 unsigned LC2D1S2
: 1;
8533 unsigned LC2D1S3
: 1;
8534 unsigned LC2D1S4
: 1;
8535 unsigned LC2D1S5
: 1;
8554 unsigned LC2D1S
: 6;
8565 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
8567 #define _CLC2SEL0_LC2D1S0 0x01
8568 #define _CLC2SEL0_D1S0 0x01
8569 #define _CLC2SEL0_LC2D1S1 0x02
8570 #define _CLC2SEL0_D1S1 0x02
8571 #define _CLC2SEL0_LC2D1S2 0x04
8572 #define _CLC2SEL0_D1S2 0x04
8573 #define _CLC2SEL0_LC2D1S3 0x08
8574 #define _CLC2SEL0_D1S3 0x08
8575 #define _CLC2SEL0_LC2D1S4 0x10
8576 #define _CLC2SEL0_D1S4 0x10
8577 #define _CLC2SEL0_LC2D1S5 0x20
8578 #define _CLC2SEL0_D1S5 0x20
8580 //==============================================================================
8583 //==============================================================================
8586 extern __at(0x0F1D) __sfr CLC2SEL1
;
8592 unsigned LC2D2S0
: 1;
8593 unsigned LC2D2S1
: 1;
8594 unsigned LC2D2S2
: 1;
8595 unsigned LC2D2S3
: 1;
8596 unsigned LC2D2S4
: 1;
8597 unsigned LC2D2S5
: 1;
8616 unsigned LC2D2S
: 6;
8627 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
8629 #define _CLC2SEL1_LC2D2S0 0x01
8630 #define _CLC2SEL1_D2S0 0x01
8631 #define _CLC2SEL1_LC2D2S1 0x02
8632 #define _CLC2SEL1_D2S1 0x02
8633 #define _CLC2SEL1_LC2D2S2 0x04
8634 #define _CLC2SEL1_D2S2 0x04
8635 #define _CLC2SEL1_LC2D2S3 0x08
8636 #define _CLC2SEL1_D2S3 0x08
8637 #define _CLC2SEL1_LC2D2S4 0x10
8638 #define _CLC2SEL1_D2S4 0x10
8639 #define _CLC2SEL1_LC2D2S5 0x20
8640 #define _CLC2SEL1_D2S5 0x20
8642 //==============================================================================
8645 //==============================================================================
8648 extern __at(0x0F1E) __sfr CLC2SEL2
;
8654 unsigned LC2D3S0
: 1;
8655 unsigned LC2D3S1
: 1;
8656 unsigned LC2D3S2
: 1;
8657 unsigned LC2D3S3
: 1;
8658 unsigned LC2D3S4
: 1;
8659 unsigned LC2D3S5
: 1;
8678 unsigned LC2D3S
: 6;
8689 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
8691 #define _CLC2SEL2_LC2D3S0 0x01
8692 #define _CLC2SEL2_D3S0 0x01
8693 #define _CLC2SEL2_LC2D3S1 0x02
8694 #define _CLC2SEL2_D3S1 0x02
8695 #define _CLC2SEL2_LC2D3S2 0x04
8696 #define _CLC2SEL2_D3S2 0x04
8697 #define _CLC2SEL2_LC2D3S3 0x08
8698 #define _CLC2SEL2_D3S3 0x08
8699 #define _CLC2SEL2_LC2D3S4 0x10
8700 #define _CLC2SEL2_D3S4 0x10
8701 #define _CLC2SEL2_LC2D3S5 0x20
8702 #define _CLC2SEL2_D3S5 0x20
8704 //==============================================================================
8707 //==============================================================================
8710 extern __at(0x0F1F) __sfr CLC2SEL3
;
8716 unsigned LC2D4S0
: 1;
8717 unsigned LC2D4S1
: 1;
8718 unsigned LC2D4S2
: 1;
8719 unsigned LC2D4S3
: 1;
8720 unsigned LC2D4S4
: 1;
8721 unsigned LC2D4S5
: 1;
8746 unsigned LC2D4S
: 6;
8751 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
8753 #define _CLC2SEL3_LC2D4S0 0x01
8754 #define _CLC2SEL3_D4S0 0x01
8755 #define _CLC2SEL3_LC2D4S1 0x02
8756 #define _CLC2SEL3_D4S1 0x02
8757 #define _CLC2SEL3_LC2D4S2 0x04
8758 #define _CLC2SEL3_D4S2 0x04
8759 #define _CLC2SEL3_LC2D4S3 0x08
8760 #define _CLC2SEL3_D4S3 0x08
8761 #define _CLC2SEL3_LC2D4S4 0x10
8762 #define _CLC2SEL3_D4S4 0x10
8763 #define _CLC2SEL3_LC2D4S5 0x20
8764 #define _CLC2SEL3_D4S5 0x20
8766 //==============================================================================
8769 //==============================================================================
8772 extern __at(0x0F20) __sfr CLC2GLS0
;
8778 unsigned LC2G1D1N
: 1;
8779 unsigned LC2G1D1T
: 1;
8780 unsigned LC2G1D2N
: 1;
8781 unsigned LC2G1D2T
: 1;
8782 unsigned LC2G1D3N
: 1;
8783 unsigned LC2G1D3T
: 1;
8784 unsigned LC2G1D4N
: 1;
8785 unsigned LC2G1D4T
: 1;
8801 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
8803 #define _CLC2GLS0_LC2G1D1N 0x01
8804 #define _CLC2GLS0_D1N 0x01
8805 #define _CLC2GLS0_LC2G1D1T 0x02
8806 #define _CLC2GLS0_D1T 0x02
8807 #define _CLC2GLS0_LC2G1D2N 0x04
8808 #define _CLC2GLS0_D2N 0x04
8809 #define _CLC2GLS0_LC2G1D2T 0x08
8810 #define _CLC2GLS0_D2T 0x08
8811 #define _CLC2GLS0_LC2G1D3N 0x10
8812 #define _CLC2GLS0_D3N 0x10
8813 #define _CLC2GLS0_LC2G1D3T 0x20
8814 #define _CLC2GLS0_D3T 0x20
8815 #define _CLC2GLS0_LC2G1D4N 0x40
8816 #define _CLC2GLS0_D4N 0x40
8817 #define _CLC2GLS0_LC2G1D4T 0x80
8818 #define _CLC2GLS0_D4T 0x80
8820 //==============================================================================
8823 //==============================================================================
8826 extern __at(0x0F21) __sfr CLC2GLS1
;
8832 unsigned LC2G2D1N
: 1;
8833 unsigned LC2G2D1T
: 1;
8834 unsigned LC2G2D2N
: 1;
8835 unsigned LC2G2D2T
: 1;
8836 unsigned LC2G2D3N
: 1;
8837 unsigned LC2G2D3T
: 1;
8838 unsigned LC2G2D4N
: 1;
8839 unsigned LC2G2D4T
: 1;
8855 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
8857 #define _CLC2GLS1_LC2G2D1N 0x01
8858 #define _CLC2GLS1_D1N 0x01
8859 #define _CLC2GLS1_LC2G2D1T 0x02
8860 #define _CLC2GLS1_D1T 0x02
8861 #define _CLC2GLS1_LC2G2D2N 0x04
8862 #define _CLC2GLS1_D2N 0x04
8863 #define _CLC2GLS1_LC2G2D2T 0x08
8864 #define _CLC2GLS1_D2T 0x08
8865 #define _CLC2GLS1_LC2G2D3N 0x10
8866 #define _CLC2GLS1_D3N 0x10
8867 #define _CLC2GLS1_LC2G2D3T 0x20
8868 #define _CLC2GLS1_D3T 0x20
8869 #define _CLC2GLS1_LC2G2D4N 0x40
8870 #define _CLC2GLS1_D4N 0x40
8871 #define _CLC2GLS1_LC2G2D4T 0x80
8872 #define _CLC2GLS1_D4T 0x80
8874 //==============================================================================
8877 //==============================================================================
8880 extern __at(0x0F22) __sfr CLC2GLS2
;
8886 unsigned LC2G3D1N
: 1;
8887 unsigned LC2G3D1T
: 1;
8888 unsigned LC2G3D2N
: 1;
8889 unsigned LC2G3D2T
: 1;
8890 unsigned LC2G3D3N
: 1;
8891 unsigned LC2G3D3T
: 1;
8892 unsigned LC2G3D4N
: 1;
8893 unsigned LC2G3D4T
: 1;
8909 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
8911 #define _CLC2GLS2_LC2G3D1N 0x01
8912 #define _CLC2GLS2_D1N 0x01
8913 #define _CLC2GLS2_LC2G3D1T 0x02
8914 #define _CLC2GLS2_D1T 0x02
8915 #define _CLC2GLS2_LC2G3D2N 0x04
8916 #define _CLC2GLS2_D2N 0x04
8917 #define _CLC2GLS2_LC2G3D2T 0x08
8918 #define _CLC2GLS2_D2T 0x08
8919 #define _CLC2GLS2_LC2G3D3N 0x10
8920 #define _CLC2GLS2_D3N 0x10
8921 #define _CLC2GLS2_LC2G3D3T 0x20
8922 #define _CLC2GLS2_D3T 0x20
8923 #define _CLC2GLS2_LC2G3D4N 0x40
8924 #define _CLC2GLS2_D4N 0x40
8925 #define _CLC2GLS2_LC2G3D4T 0x80
8926 #define _CLC2GLS2_D4T 0x80
8928 //==============================================================================
8931 //==============================================================================
8934 extern __at(0x0F23) __sfr CLC2GLS3
;
8940 unsigned LC2G4D1N
: 1;
8941 unsigned LC2G4D1T
: 1;
8942 unsigned LC2G4D2N
: 1;
8943 unsigned LC2G4D2T
: 1;
8944 unsigned LC2G4D3N
: 1;
8945 unsigned LC2G4D3T
: 1;
8946 unsigned LC2G4D4N
: 1;
8947 unsigned LC2G4D4T
: 1;
8963 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
8965 #define _CLC2GLS3_LC2G4D1N 0x01
8966 #define _CLC2GLS3_G4D1N 0x01
8967 #define _CLC2GLS3_LC2G4D1T 0x02
8968 #define _CLC2GLS3_G4D1T 0x02
8969 #define _CLC2GLS3_LC2G4D2N 0x04
8970 #define _CLC2GLS3_G4D2N 0x04
8971 #define _CLC2GLS3_LC2G4D2T 0x08
8972 #define _CLC2GLS3_G4D2T 0x08
8973 #define _CLC2GLS3_LC2G4D3N 0x10
8974 #define _CLC2GLS3_G4D3N 0x10
8975 #define _CLC2GLS3_LC2G4D3T 0x20
8976 #define _CLC2GLS3_G4D3T 0x20
8977 #define _CLC2GLS3_LC2G4D4N 0x40
8978 #define _CLC2GLS3_G4D4N 0x40
8979 #define _CLC2GLS3_LC2G4D4T 0x80
8980 #define _CLC2GLS3_G4D4T 0x80
8982 //==============================================================================
8985 //==============================================================================
8988 extern __at(0x0F24) __sfr CLC3CON
;
8994 unsigned LC3MODE0
: 1;
8995 unsigned LC3MODE1
: 1;
8996 unsigned LC3MODE2
: 1;
8997 unsigned LC3INTN
: 1;
8998 unsigned LC3INTP
: 1;
8999 unsigned LC3OUT
: 1;
9018 unsigned LC3MODE
: 3;
9029 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
9031 #define _CLC3CON_LC3MODE0 0x01
9032 #define _CLC3CON_MODE0 0x01
9033 #define _CLC3CON_LC3MODE1 0x02
9034 #define _CLC3CON_MODE1 0x02
9035 #define _CLC3CON_LC3MODE2 0x04
9036 #define _CLC3CON_MODE2 0x04
9037 #define _CLC3CON_LC3INTN 0x08
9038 #define _CLC3CON_INTN 0x08
9039 #define _CLC3CON_LC3INTP 0x10
9040 #define _CLC3CON_INTP 0x10
9041 #define _CLC3CON_LC3OUT 0x20
9042 #define _CLC3CON_OUT 0x20
9043 #define _CLC3CON_LC3EN 0x80
9044 #define _CLC3CON_EN 0x80
9046 //==============================================================================
9049 //==============================================================================
9052 extern __at(0x0F25) __sfr CLC3POL
;
9058 unsigned LC3G1POL
: 1;
9059 unsigned LC3G2POL
: 1;
9060 unsigned LC3G3POL
: 1;
9061 unsigned LC3G4POL
: 1;
9065 unsigned LC3POL
: 1;
9081 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
9083 #define _CLC3POL_LC3G1POL 0x01
9084 #define _CLC3POL_G1POL 0x01
9085 #define _CLC3POL_LC3G2POL 0x02
9086 #define _CLC3POL_G2POL 0x02
9087 #define _CLC3POL_LC3G3POL 0x04
9088 #define _CLC3POL_G3POL 0x04
9089 #define _CLC3POL_LC3G4POL 0x08
9090 #define _CLC3POL_G4POL 0x08
9091 #define _CLC3POL_LC3POL 0x80
9092 #define _CLC3POL_POL 0x80
9094 //==============================================================================
9097 //==============================================================================
9100 extern __at(0x0F26) __sfr CLC3SEL0
;
9106 unsigned LC3D1S0
: 1;
9107 unsigned LC3D1S1
: 1;
9108 unsigned LC3D1S2
: 1;
9109 unsigned LC3D1S3
: 1;
9110 unsigned LC3D1S4
: 1;
9111 unsigned LC3D1S5
: 1;
9130 unsigned LC3D1S
: 6;
9141 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
9143 #define _CLC3SEL0_LC3D1S0 0x01
9144 #define _CLC3SEL0_D1S0 0x01
9145 #define _CLC3SEL0_LC3D1S1 0x02
9146 #define _CLC3SEL0_D1S1 0x02
9147 #define _CLC3SEL0_LC3D1S2 0x04
9148 #define _CLC3SEL0_D1S2 0x04
9149 #define _CLC3SEL0_LC3D1S3 0x08
9150 #define _CLC3SEL0_D1S3 0x08
9151 #define _CLC3SEL0_LC3D1S4 0x10
9152 #define _CLC3SEL0_D1S4 0x10
9153 #define _CLC3SEL0_LC3D1S5 0x20
9154 #define _CLC3SEL0_D1S5 0x20
9156 //==============================================================================
9159 //==============================================================================
9162 extern __at(0x0F27) __sfr CLC3SEL1
;
9168 unsigned LC3D2S0
: 1;
9169 unsigned LC3D2S1
: 1;
9170 unsigned LC3D2S2
: 1;
9171 unsigned LC3D2S3
: 1;
9172 unsigned LC3D2S4
: 1;
9173 unsigned LC3D2S5
: 1;
9198 unsigned LC3D2S
: 6;
9203 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
9205 #define _CLC3SEL1_LC3D2S0 0x01
9206 #define _CLC3SEL1_D2S0 0x01
9207 #define _CLC3SEL1_LC3D2S1 0x02
9208 #define _CLC3SEL1_D2S1 0x02
9209 #define _CLC3SEL1_LC3D2S2 0x04
9210 #define _CLC3SEL1_D2S2 0x04
9211 #define _CLC3SEL1_LC3D2S3 0x08
9212 #define _CLC3SEL1_D2S3 0x08
9213 #define _CLC3SEL1_LC3D2S4 0x10
9214 #define _CLC3SEL1_D2S4 0x10
9215 #define _CLC3SEL1_LC3D2S5 0x20
9216 #define _CLC3SEL1_D2S5 0x20
9218 //==============================================================================
9221 //==============================================================================
9224 extern __at(0x0F28) __sfr CLC3SEL2
;
9230 unsigned LC3D3S0
: 1;
9231 unsigned LC3D3S1
: 1;
9232 unsigned LC3D3S2
: 1;
9233 unsigned LC3D3S3
: 1;
9234 unsigned LC3D3S4
: 1;
9235 unsigned LC3D3S5
: 1;
9254 unsigned LC3D3S
: 6;
9265 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
9267 #define _CLC3SEL2_LC3D3S0 0x01
9268 #define _CLC3SEL2_D3S0 0x01
9269 #define _CLC3SEL2_LC3D3S1 0x02
9270 #define _CLC3SEL2_D3S1 0x02
9271 #define _CLC3SEL2_LC3D3S2 0x04
9272 #define _CLC3SEL2_D3S2 0x04
9273 #define _CLC3SEL2_LC3D3S3 0x08
9274 #define _CLC3SEL2_D3S3 0x08
9275 #define _CLC3SEL2_LC3D3S4 0x10
9276 #define _CLC3SEL2_D3S4 0x10
9277 #define _CLC3SEL2_LC3D3S5 0x20
9278 #define _CLC3SEL2_D3S5 0x20
9280 //==============================================================================
9283 //==============================================================================
9286 extern __at(0x0F29) __sfr CLC3SEL3
;
9292 unsigned LC3D4S0
: 1;
9293 unsigned LC3D4S1
: 1;
9294 unsigned LC3D4S2
: 1;
9295 unsigned LC3D4S3
: 1;
9296 unsigned LC3D4S4
: 1;
9297 unsigned LC3D4S5
: 1;
9322 unsigned LC3D4S
: 6;
9327 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
9329 #define _CLC3SEL3_LC3D4S0 0x01
9330 #define _CLC3SEL3_D4S0 0x01
9331 #define _CLC3SEL3_LC3D4S1 0x02
9332 #define _CLC3SEL3_D4S1 0x02
9333 #define _CLC3SEL3_LC3D4S2 0x04
9334 #define _CLC3SEL3_D4S2 0x04
9335 #define _CLC3SEL3_LC3D4S3 0x08
9336 #define _CLC3SEL3_D4S3 0x08
9337 #define _CLC3SEL3_LC3D4S4 0x10
9338 #define _CLC3SEL3_D4S4 0x10
9339 #define _CLC3SEL3_LC3D4S5 0x20
9340 #define _CLC3SEL3_D4S5 0x20
9342 //==============================================================================
9345 //==============================================================================
9348 extern __at(0x0F2A) __sfr CLC3GLS0
;
9354 unsigned LC3G1D1N
: 1;
9355 unsigned LC3G1D1T
: 1;
9356 unsigned LC3G1D2N
: 1;
9357 unsigned LC3G1D2T
: 1;
9358 unsigned LC3G1D3N
: 1;
9359 unsigned LC3G1D3T
: 1;
9360 unsigned LC3G1D4N
: 1;
9361 unsigned LC3G1D4T
: 1;
9377 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
9379 #define _CLC3GLS0_LC3G1D1N 0x01
9380 #define _CLC3GLS0_D1N 0x01
9381 #define _CLC3GLS0_LC3G1D1T 0x02
9382 #define _CLC3GLS0_D1T 0x02
9383 #define _CLC3GLS0_LC3G1D2N 0x04
9384 #define _CLC3GLS0_D2N 0x04
9385 #define _CLC3GLS0_LC3G1D2T 0x08
9386 #define _CLC3GLS0_D2T 0x08
9387 #define _CLC3GLS0_LC3G1D3N 0x10
9388 #define _CLC3GLS0_D3N 0x10
9389 #define _CLC3GLS0_LC3G1D3T 0x20
9390 #define _CLC3GLS0_D3T 0x20
9391 #define _CLC3GLS0_LC3G1D4N 0x40
9392 #define _CLC3GLS0_D4N 0x40
9393 #define _CLC3GLS0_LC3G1D4T 0x80
9394 #define _CLC3GLS0_D4T 0x80
9396 //==============================================================================
9399 //==============================================================================
9402 extern __at(0x0F2B) __sfr CLC3GLS1
;
9408 unsigned LC3G2D1N
: 1;
9409 unsigned LC3G2D1T
: 1;
9410 unsigned LC3G2D2N
: 1;
9411 unsigned LC3G2D2T
: 1;
9412 unsigned LC3G2D3N
: 1;
9413 unsigned LC3G2D3T
: 1;
9414 unsigned LC3G2D4N
: 1;
9415 unsigned LC3G2D4T
: 1;
9431 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
9433 #define _CLC3GLS1_LC3G2D1N 0x01
9434 #define _CLC3GLS1_D1N 0x01
9435 #define _CLC3GLS1_LC3G2D1T 0x02
9436 #define _CLC3GLS1_D1T 0x02
9437 #define _CLC3GLS1_LC3G2D2N 0x04
9438 #define _CLC3GLS1_D2N 0x04
9439 #define _CLC3GLS1_LC3G2D2T 0x08
9440 #define _CLC3GLS1_D2T 0x08
9441 #define _CLC3GLS1_LC3G2D3N 0x10
9442 #define _CLC3GLS1_D3N 0x10
9443 #define _CLC3GLS1_LC3G2D3T 0x20
9444 #define _CLC3GLS1_D3T 0x20
9445 #define _CLC3GLS1_LC3G2D4N 0x40
9446 #define _CLC3GLS1_D4N 0x40
9447 #define _CLC3GLS1_LC3G2D4T 0x80
9448 #define _CLC3GLS1_D4T 0x80
9450 //==============================================================================
9453 //==============================================================================
9456 extern __at(0x0F2C) __sfr CLC3GLS2
;
9462 unsigned LC3G3D1N
: 1;
9463 unsigned LC3G3D1T
: 1;
9464 unsigned LC3G3D2N
: 1;
9465 unsigned LC3G3D2T
: 1;
9466 unsigned LC3G3D3N
: 1;
9467 unsigned LC3G3D3T
: 1;
9468 unsigned LC3G3D4N
: 1;
9469 unsigned LC3G3D4T
: 1;
9485 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
9487 #define _CLC3GLS2_LC3G3D1N 0x01
9488 #define _CLC3GLS2_D1N 0x01
9489 #define _CLC3GLS2_LC3G3D1T 0x02
9490 #define _CLC3GLS2_D1T 0x02
9491 #define _CLC3GLS2_LC3G3D2N 0x04
9492 #define _CLC3GLS2_D2N 0x04
9493 #define _CLC3GLS2_LC3G3D2T 0x08
9494 #define _CLC3GLS2_D2T 0x08
9495 #define _CLC3GLS2_LC3G3D3N 0x10
9496 #define _CLC3GLS2_D3N 0x10
9497 #define _CLC3GLS2_LC3G3D3T 0x20
9498 #define _CLC3GLS2_D3T 0x20
9499 #define _CLC3GLS2_LC3G3D4N 0x40
9500 #define _CLC3GLS2_D4N 0x40
9501 #define _CLC3GLS2_LC3G3D4T 0x80
9502 #define _CLC3GLS2_D4T 0x80
9504 //==============================================================================
9507 //==============================================================================
9510 extern __at(0x0F2D) __sfr CLC3GLS3
;
9516 unsigned LC3G4D1N
: 1;
9517 unsigned LC3G4D1T
: 1;
9518 unsigned LC3G4D2N
: 1;
9519 unsigned LC3G4D2T
: 1;
9520 unsigned LC3G4D3N
: 1;
9521 unsigned LC3G4D3T
: 1;
9522 unsigned LC3G4D4N
: 1;
9523 unsigned LC3G4D4T
: 1;
9539 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
9541 #define _CLC3GLS3_LC3G4D1N 0x01
9542 #define _CLC3GLS3_G4D1N 0x01
9543 #define _CLC3GLS3_LC3G4D1T 0x02
9544 #define _CLC3GLS3_G4D1T 0x02
9545 #define _CLC3GLS3_LC3G4D2N 0x04
9546 #define _CLC3GLS3_G4D2N 0x04
9547 #define _CLC3GLS3_LC3G4D2T 0x08
9548 #define _CLC3GLS3_G4D2T 0x08
9549 #define _CLC3GLS3_LC3G4D3N 0x10
9550 #define _CLC3GLS3_G4D3N 0x10
9551 #define _CLC3GLS3_LC3G4D3T 0x20
9552 #define _CLC3GLS3_G4D3T 0x20
9553 #define _CLC3GLS3_LC3G4D4N 0x40
9554 #define _CLC3GLS3_G4D4N 0x40
9555 #define _CLC3GLS3_LC3G4D4T 0x80
9556 #define _CLC3GLS3_G4D4T 0x80
9558 //==============================================================================
9561 //==============================================================================
9564 extern __at(0x0F2E) __sfr CLC4CON
;
9570 unsigned LC4MODE0
: 1;
9571 unsigned LC4MODE1
: 1;
9572 unsigned LC4MODE2
: 1;
9573 unsigned LC4INTN
: 1;
9574 unsigned LC4INTP
: 1;
9575 unsigned LC4OUT
: 1;
9594 unsigned LC4MODE
: 3;
9605 extern __at(0x0F2E) volatile __CLC4CONbits_t CLC4CONbits
;
9607 #define _CLC4CON_LC4MODE0 0x01
9608 #define _CLC4CON_MODE0 0x01
9609 #define _CLC4CON_LC4MODE1 0x02
9610 #define _CLC4CON_MODE1 0x02
9611 #define _CLC4CON_LC4MODE2 0x04
9612 #define _CLC4CON_MODE2 0x04
9613 #define _CLC4CON_LC4INTN 0x08
9614 #define _CLC4CON_INTN 0x08
9615 #define _CLC4CON_LC4INTP 0x10
9616 #define _CLC4CON_INTP 0x10
9617 #define _CLC4CON_LC4OUT 0x20
9618 #define _CLC4CON_OUT 0x20
9619 #define _CLC4CON_LC4EN 0x80
9620 #define _CLC4CON_EN 0x80
9622 //==============================================================================
9625 //==============================================================================
9628 extern __at(0x0F2F) __sfr CLC4POL
;
9634 unsigned LC4G1POL
: 1;
9635 unsigned LC4G2POL
: 1;
9636 unsigned LC4G3POL
: 1;
9637 unsigned LC4G4POL
: 1;
9641 unsigned LC4POL
: 1;
9657 extern __at(0x0F2F) volatile __CLC4POLbits_t CLC4POLbits
;
9659 #define _CLC4POL_LC4G1POL 0x01
9660 #define _CLC4POL_G1POL 0x01
9661 #define _CLC4POL_LC4G2POL 0x02
9662 #define _CLC4POL_G2POL 0x02
9663 #define _CLC4POL_LC4G3POL 0x04
9664 #define _CLC4POL_G3POL 0x04
9665 #define _CLC4POL_LC4G4POL 0x08
9666 #define _CLC4POL_G4POL 0x08
9667 #define _CLC4POL_LC4POL 0x80
9668 #define _CLC4POL_POL 0x80
9670 //==============================================================================
9673 //==============================================================================
9676 extern __at(0x0F30) __sfr CLC4SEL0
;
9682 unsigned LC4D1S0
: 1;
9683 unsigned LC4D1S1
: 1;
9684 unsigned LC4D1S2
: 1;
9685 unsigned LC4D1S3
: 1;
9686 unsigned LC4D1S4
: 1;
9687 unsigned LC4D1S5
: 1;
9712 unsigned LC4D1S
: 6;
9717 extern __at(0x0F30) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
9719 #define _CLC4SEL0_LC4D1S0 0x01
9720 #define _CLC4SEL0_D1S0 0x01
9721 #define _CLC4SEL0_LC4D1S1 0x02
9722 #define _CLC4SEL0_D1S1 0x02
9723 #define _CLC4SEL0_LC4D1S2 0x04
9724 #define _CLC4SEL0_D1S2 0x04
9725 #define _CLC4SEL0_LC4D1S3 0x08
9726 #define _CLC4SEL0_D1S3 0x08
9727 #define _CLC4SEL0_LC4D1S4 0x10
9728 #define _CLC4SEL0_D1S4 0x10
9729 #define _CLC4SEL0_LC4D1S5 0x20
9730 #define _CLC4SEL0_D1S5 0x20
9732 //==============================================================================
9735 //==============================================================================
9738 extern __at(0x0F31) __sfr CLC4SEL1
;
9744 unsigned LC4D2S0
: 1;
9745 unsigned LC4D2S1
: 1;
9746 unsigned LC4D2S2
: 1;
9747 unsigned LC4D2S3
: 1;
9748 unsigned LC4D2S4
: 1;
9749 unsigned LC4D2S5
: 1;
9774 unsigned LC4D2S
: 6;
9779 extern __at(0x0F31) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
9781 #define _CLC4SEL1_LC4D2S0 0x01
9782 #define _CLC4SEL1_D2S0 0x01
9783 #define _CLC4SEL1_LC4D2S1 0x02
9784 #define _CLC4SEL1_D2S1 0x02
9785 #define _CLC4SEL1_LC4D2S2 0x04
9786 #define _CLC4SEL1_D2S2 0x04
9787 #define _CLC4SEL1_LC4D2S3 0x08
9788 #define _CLC4SEL1_D2S3 0x08
9789 #define _CLC4SEL1_LC4D2S4 0x10
9790 #define _CLC4SEL1_D2S4 0x10
9791 #define _CLC4SEL1_LC4D2S5 0x20
9792 #define _CLC4SEL1_D2S5 0x20
9794 //==============================================================================
9797 //==============================================================================
9800 extern __at(0x0F32) __sfr CLC4SEL2
;
9806 unsigned LC4D3S0
: 1;
9807 unsigned LC4D3S1
: 1;
9808 unsigned LC4D3S2
: 1;
9809 unsigned LC4D3S3
: 1;
9810 unsigned LC4D3S4
: 1;
9811 unsigned LC4D3S5
: 1;
9830 unsigned LC4D3S
: 6;
9841 extern __at(0x0F32) volatile __CLC4SEL2bits_t CLC4SEL2bits
;
9843 #define _CLC4SEL2_LC4D3S0 0x01
9844 #define _CLC4SEL2_D3S0 0x01
9845 #define _CLC4SEL2_LC4D3S1 0x02
9846 #define _CLC4SEL2_D3S1 0x02
9847 #define _CLC4SEL2_LC4D3S2 0x04
9848 #define _CLC4SEL2_D3S2 0x04
9849 #define _CLC4SEL2_LC4D3S3 0x08
9850 #define _CLC4SEL2_D3S3 0x08
9851 #define _CLC4SEL2_LC4D3S4 0x10
9852 #define _CLC4SEL2_D3S4 0x10
9853 #define _CLC4SEL2_LC4D3S5 0x20
9854 #define _CLC4SEL2_D3S5 0x20
9856 //==============================================================================
9859 //==============================================================================
9862 extern __at(0x0F33) __sfr CLC4SEL3
;
9868 unsigned LC4D4S0
: 1;
9869 unsigned LC4D4S1
: 1;
9870 unsigned LC4D4S2
: 1;
9871 unsigned LC4D4S3
: 1;
9872 unsigned LC4D4S4
: 1;
9873 unsigned LC4D4S5
: 1;
9892 unsigned LC4D4S
: 6;
9903 extern __at(0x0F33) volatile __CLC4SEL3bits_t CLC4SEL3bits
;
9905 #define _CLC4SEL3_LC4D4S0 0x01
9906 #define _CLC4SEL3_D4S0 0x01
9907 #define _CLC4SEL3_LC4D4S1 0x02
9908 #define _CLC4SEL3_D4S1 0x02
9909 #define _CLC4SEL3_LC4D4S2 0x04
9910 #define _CLC4SEL3_D4S2 0x04
9911 #define _CLC4SEL3_LC4D4S3 0x08
9912 #define _CLC4SEL3_D4S3 0x08
9913 #define _CLC4SEL3_LC4D4S4 0x10
9914 #define _CLC4SEL3_D4S4 0x10
9915 #define _CLC4SEL3_LC4D4S5 0x20
9916 #define _CLC4SEL3_D4S5 0x20
9918 //==============================================================================
9921 //==============================================================================
9924 extern __at(0x0F34) __sfr CLC4GLS0
;
9930 unsigned LC4G1D1N
: 1;
9931 unsigned LC4G1D1T
: 1;
9932 unsigned LC4G1D2N
: 1;
9933 unsigned LC4G1D2T
: 1;
9934 unsigned LC4G1D3N
: 1;
9935 unsigned LC4G1D3T
: 1;
9936 unsigned LC4G1D4N
: 1;
9937 unsigned LC4G1D4T
: 1;
9953 extern __at(0x0F34) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
9955 #define _CLC4GLS0_LC4G1D1N 0x01
9956 #define _CLC4GLS0_D1N 0x01
9957 #define _CLC4GLS0_LC4G1D1T 0x02
9958 #define _CLC4GLS0_D1T 0x02
9959 #define _CLC4GLS0_LC4G1D2N 0x04
9960 #define _CLC4GLS0_D2N 0x04
9961 #define _CLC4GLS0_LC4G1D2T 0x08
9962 #define _CLC4GLS0_D2T 0x08
9963 #define _CLC4GLS0_LC4G1D3N 0x10
9964 #define _CLC4GLS0_D3N 0x10
9965 #define _CLC4GLS0_LC4G1D3T 0x20
9966 #define _CLC4GLS0_D3T 0x20
9967 #define _CLC4GLS0_LC4G1D4N 0x40
9968 #define _CLC4GLS0_D4N 0x40
9969 #define _CLC4GLS0_LC4G1D4T 0x80
9970 #define _CLC4GLS0_D4T 0x80
9972 //==============================================================================
9975 //==============================================================================
9978 extern __at(0x0F35) __sfr CLC4GLS1
;
9984 unsigned LC4G2D1N
: 1;
9985 unsigned LC4G2D1T
: 1;
9986 unsigned LC4G2D2N
: 1;
9987 unsigned LC4G2D2T
: 1;
9988 unsigned LC4G2D3N
: 1;
9989 unsigned LC4G2D3T
: 1;
9990 unsigned LC4G2D4N
: 1;
9991 unsigned LC4G2D4T
: 1;
10005 } __CLC4GLS1bits_t
;
10007 extern __at(0x0F35) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
10009 #define _CLC4GLS1_LC4G2D1N 0x01
10010 #define _CLC4GLS1_D1N 0x01
10011 #define _CLC4GLS1_LC4G2D1T 0x02
10012 #define _CLC4GLS1_D1T 0x02
10013 #define _CLC4GLS1_LC4G2D2N 0x04
10014 #define _CLC4GLS1_D2N 0x04
10015 #define _CLC4GLS1_LC4G2D2T 0x08
10016 #define _CLC4GLS1_D2T 0x08
10017 #define _CLC4GLS1_LC4G2D3N 0x10
10018 #define _CLC4GLS1_D3N 0x10
10019 #define _CLC4GLS1_LC4G2D3T 0x20
10020 #define _CLC4GLS1_D3T 0x20
10021 #define _CLC4GLS1_LC4G2D4N 0x40
10022 #define _CLC4GLS1_D4N 0x40
10023 #define _CLC4GLS1_LC4G2D4T 0x80
10024 #define _CLC4GLS1_D4T 0x80
10026 //==============================================================================
10029 //==============================================================================
10032 extern __at(0x0F36) __sfr CLC4GLS2
;
10038 unsigned LC4G3D1N
: 1;
10039 unsigned LC4G3D1T
: 1;
10040 unsigned LC4G3D2N
: 1;
10041 unsigned LC4G3D2T
: 1;
10042 unsigned LC4G3D3N
: 1;
10043 unsigned LC4G3D3T
: 1;
10044 unsigned LC4G3D4N
: 1;
10045 unsigned LC4G3D4T
: 1;
10059 } __CLC4GLS2bits_t
;
10061 extern __at(0x0F36) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
10063 #define _CLC4GLS2_LC4G3D1N 0x01
10064 #define _CLC4GLS2_D1N 0x01
10065 #define _CLC4GLS2_LC4G3D1T 0x02
10066 #define _CLC4GLS2_D1T 0x02
10067 #define _CLC4GLS2_LC4G3D2N 0x04
10068 #define _CLC4GLS2_D2N 0x04
10069 #define _CLC4GLS2_LC4G3D2T 0x08
10070 #define _CLC4GLS2_D2T 0x08
10071 #define _CLC4GLS2_LC4G3D3N 0x10
10072 #define _CLC4GLS2_D3N 0x10
10073 #define _CLC4GLS2_LC4G3D3T 0x20
10074 #define _CLC4GLS2_D3T 0x20
10075 #define _CLC4GLS2_LC4G3D4N 0x40
10076 #define _CLC4GLS2_D4N 0x40
10077 #define _CLC4GLS2_LC4G3D4T 0x80
10078 #define _CLC4GLS2_D4T 0x80
10080 //==============================================================================
10083 //==============================================================================
10086 extern __at(0x0F37) __sfr CLC4GLS3
;
10092 unsigned LC4G4D1N
: 1;
10093 unsigned LC4G4D1T
: 1;
10094 unsigned LC4G4D2N
: 1;
10095 unsigned LC4G4D2T
: 1;
10096 unsigned LC4G4D3N
: 1;
10097 unsigned LC4G4D3T
: 1;
10098 unsigned LC4G4D4N
: 1;
10099 unsigned LC4G4D4T
: 1;
10104 unsigned G4D1N
: 1;
10105 unsigned G4D1T
: 1;
10106 unsigned G4D2N
: 1;
10107 unsigned G4D2T
: 1;
10108 unsigned G4D3N
: 1;
10109 unsigned G4D3T
: 1;
10110 unsigned G4D4N
: 1;
10111 unsigned G4D4T
: 1;
10113 } __CLC4GLS3bits_t
;
10115 extern __at(0x0F37) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
10117 #define _CLC4GLS3_LC4G4D1N 0x01
10118 #define _CLC4GLS3_G4D1N 0x01
10119 #define _CLC4GLS3_LC4G4D1T 0x02
10120 #define _CLC4GLS3_G4D1T 0x02
10121 #define _CLC4GLS3_LC4G4D2N 0x04
10122 #define _CLC4GLS3_G4D2N 0x04
10123 #define _CLC4GLS3_LC4G4D2T 0x08
10124 #define _CLC4GLS3_G4D2T 0x08
10125 #define _CLC4GLS3_LC4G4D3N 0x10
10126 #define _CLC4GLS3_G4D3N 0x10
10127 #define _CLC4GLS3_LC4G4D3T 0x20
10128 #define _CLC4GLS3_G4D3T 0x20
10129 #define _CLC4GLS3_LC4G4D4N 0x40
10130 #define _CLC4GLS3_G4D4N 0x40
10131 #define _CLC4GLS3_LC4G4D4T 0x80
10132 #define _CLC4GLS3_G4D4T 0x80
10134 //==============================================================================
10137 //==============================================================================
10138 // STATUS_SHAD Bits
10140 extern __at(0x0FE4) __sfr STATUS_SHAD
;
10144 unsigned C_SHAD
: 1;
10145 unsigned DC_SHAD
: 1;
10146 unsigned Z_SHAD
: 1;
10152 } __STATUS_SHADbits_t
;
10154 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
10156 #define _C_SHAD 0x01
10157 #define _DC_SHAD 0x02
10158 #define _Z_SHAD 0x04
10160 //==============================================================================
10162 extern __at(0x0FE5) __sfr WREG_SHAD
;
10163 extern __at(0x0FE6) __sfr BSR_SHAD
;
10164 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
10165 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
10166 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
10167 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
10168 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
10169 extern __at(0x0FED) __sfr STKPTR
;
10170 extern __at(0x0FEE) __sfr TOSL
;
10171 extern __at(0x0FEF) __sfr TOSH
;
10173 //==============================================================================
10175 // Configuration Bits
10177 //==============================================================================
10179 #define _CONFIG1 0x8007
10180 #define _CONFIG2 0x8008
10181 #define _CONFIG3 0x8009
10182 #define _CONFIG4 0x800A
10184 //----------------------------- CONFIG1 Options -------------------------------
10186 #define _FEXTOSC_LP 0x3FF8 // LP (crystal oscillator) optimized for 32.768 kHz.
10187 #define _FEXTOSC_XT 0x3FF9 // XT (crystal oscillator) from 100 kHz to 4 MHz.
10188 #define _FEXTOSC_HS 0x3FFA // HS (crystal oscillator) above 4 MHz.
10189 #define _FEXTOSC_OFF 0x3FFC // Oscillator not enabled.
10190 #define _FEXTOSC_ECL 0x3FFD // EC (external clock) below 100 kHz.
10191 #define _FEXTOSC_ECM 0x3FFE // EC (external clock) for 100 kHz to 8 MHz.
10192 #define _FEXTOSC_ECH 0x3FFF // EC (external clock) above 8 MHz.
10193 #define _RSTOSC_HFINT32 0x3F8F // HFINTOSC with 2x PLL (32MHz).
10194 #define _RSTOSC_EXT4X 0x3F9F // EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
10195 #define _RSTOSC_SOSC 0x3FBF // SOSC (31kHz).
10196 #define _RSTOSC_LFINT 0x3FCF // LFINTOSC (31kHz).
10197 #define _RSTOSC_HFINT1 0x3FEF // HFINTOSC (1MHz).
10198 #define _RSTOSC_EXT1X 0x3FFF // EXTOSC operating per FEXTOSC bits.
10199 #define _CLKOUTEN_ON 0x3EFF // CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
10200 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled; I/O or oscillator function on OSC2.
10201 #define _CSWEN_OFF 0x37FF // The NOSC and NDIV bits cannot be changed by user software.
10202 #define _CSWEN_ON 0x3FFF // Writing to NOSC and NDIV is allowed.
10203 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
10204 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
10206 //----------------------------- CONFIG2 Options -------------------------------
10208 #define _MCLRE_OFF 0x3FFE // MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
10209 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR; Weak pull-up enabled.
10210 #define _PWRTE_ON 0x3FFD // PWRT enabled.
10211 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
10212 #define _WDTE_OFF 0x3FF3 // WDT disabled; SWDTEN is ignored.
10213 #define _WDTE_SWDTEN 0x3FF7 // WDT controlled by the SWDTEN bit in the WDTCON register.
10214 #define _WDTE_SLEEP 0x3FFB // WDT enabled while running and disabled in SLEEP/IDLE; SWDTEN is ignored.
10215 #define _WDTE_ON 0x3FFF // WDT enabled, SWDTEN is ignored.
10216 #define _LPBOREN_ON 0x3FDF // ULPBOR enabled.
10217 #define _LPBOREN_OFF 0x3FFF // ULPBOR disabled.
10218 #define _BOREN_OFF 0x3F3F // Brown-out Reset disabled.
10219 #define _BOREN_SBOREN 0x3F7F // Brown-out Reset enabled according to SBOREN.
10220 #define _BOREN_SLEEP 0x3FBF // Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
10221 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled, SBOREN bit ignored.
10222 #define _BORV_HIGH 0x3DFF // Brown-out voltage (Vbor) set to 2.7V.
10223 #define _BORV_LOW 0x3FFF // Brown-out voltage (Vbor) set to 2.45V.
10224 #define _PPS1WAY_OFF 0x37FF // The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
10225 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
10226 #define _STVREN_OFF 0x2FFF // Stack Overflow or Underflow will not cause a Reset.
10227 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
10228 #define _DEBUG_ON 0x1FFF // Background debugger enabled.
10229 #define _DEBUG_OFF 0x3FFF // Background debugger disabled.
10231 //----------------------------- CONFIG3 Options -------------------------------
10233 #define _WRT_ALL 0x3FFC // 0000h to 0FFFh write protected, no addresses may be modified.
10234 #define _WRT_HALF 0x3FFD // 0000h to 03FFh write-protected, 0400h to 0FFFh may be modified.
10235 #define _WRT_BOOT 0x3FFE // 0000h to 01FFh write-protected, 0200h to 0FFFh may be modified.
10236 #define _WRT_OFF 0x3FFF // Write protection off.
10237 #define _LVP_OFF 0x1FFF // High Voltage on MCLR/VPP must be used for programming.
10238 #define _LVP_ON 0x3FFF // Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
10240 //----------------------------- CONFIG4 Options -------------------------------
10242 #define _CP_ON 0x3FFE // User NVM code protection enabled.
10243 #define _CP_OFF 0x3FFF // User NVM code protection disabled.
10244 #define _CPD_ON 0x3FFD // Data NVM code protection enabled.
10245 #define _CPD_OFF 0x3FFF // Data NVM code protection disabled.
10247 //==============================================================================
10249 #define _DEVID1 0x8006
10251 #define _IDLOC0 0x8000
10252 #define _IDLOC1 0x8001
10253 #define _IDLOC2 0x8002
10254 #define _IDLOC3 0x8003
10256 //==============================================================================
10258 #ifndef NO_BIT_DEFINES
10260 #define ADACT0 ADACTbits.ADACT0 // bit 0
10261 #define ADACT1 ADACTbits.ADACT1 // bit 1
10262 #define ADACT2 ADACTbits.ADACT2 // bit 2
10263 #define ADACT3 ADACTbits.ADACT3 // bit 3
10264 #define ADACT4 ADACTbits.ADACT4 // bit 4
10266 #define ADON ADCON0bits.ADON // bit 0
10267 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
10268 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
10269 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
10270 #define CHS0 ADCON0bits.CHS0 // bit 2
10271 #define CHS1 ADCON0bits.CHS1 // bit 3
10272 #define CHS2 ADCON0bits.CHS2 // bit 4
10273 #define CHS3 ADCON0bits.CHS3 // bit 5
10274 #define CHS4 ADCON0bits.CHS4 // bit 6
10275 #define CHS5 ADCON0bits.CHS5 // bit 7
10277 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
10278 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
10279 #define ADNREF ADCON1bits.ADNREF // bit 2
10280 #define ADCS0 ADCON1bits.ADCS0 // bit 4
10281 #define ADCS1 ADCON1bits.ADCS1 // bit 5
10282 #define ADCS2 ADCON1bits.ADCS2 // bit 6
10283 #define ADFM ADCON1bits.ADFM // bit 7
10285 #define ANSA0 ANSELAbits.ANSA0 // bit 0
10286 #define ANSA1 ANSELAbits.ANSA1 // bit 1
10287 #define ANSA2 ANSELAbits.ANSA2 // bit 2
10288 #define ANSA4 ANSELAbits.ANSA4 // bit 4
10289 #define ANSA5 ANSELAbits.ANSA5 // bit 5
10291 #define ANSB4 ANSELBbits.ANSB4 // bit 4
10292 #define ANSB5 ANSELBbits.ANSB5 // bit 5
10293 #define ANSB6 ANSELBbits.ANSB6 // bit 6
10294 #define ANSB7 ANSELBbits.ANSB7 // bit 7
10296 #define ANSC0 ANSELCbits.ANSC0 // bit 0
10297 #define ANSC1 ANSELCbits.ANSC1 // bit 1
10298 #define ANSC2 ANSELCbits.ANSC2 // bit 2
10299 #define ANSC3 ANSELCbits.ANSC3 // bit 3
10300 #define ANSC4 ANSELCbits.ANSC4 // bit 4
10301 #define ANSC5 ANSELCbits.ANSC5 // bit 5
10302 #define ANSC6 ANSELCbits.ANSC6 // bit 6
10303 #define ANSC7 ANSELCbits.ANSC7 // bit 7
10305 #define ABDEN BAUD1CONbits.ABDEN // bit 0
10306 #define WUE BAUD1CONbits.WUE // bit 1
10307 #define BRG16 BAUD1CONbits.BRG16 // bit 3
10308 #define SCKP BAUD1CONbits.SCKP // bit 4
10309 #define RCIDL BAUD1CONbits.RCIDL // bit 6
10310 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
10312 #define BORRDY BORCONbits.BORRDY // bit 0
10313 #define SBOREN BORCONbits.SBOREN // bit 7
10315 #define BSR0 BSRbits.BSR0 // bit 0
10316 #define BSR1 BSRbits.BSR1 // bit 1
10317 #define BSR2 BSRbits.BSR2 // bit 2
10318 #define BSR3 BSRbits.BSR3 // bit 3
10319 #define BSR4 BSRbits.BSR4 // bit 4
10321 #define CCDS0 CCDCONbits.CCDS0 // bit 0
10322 #define CCDS1 CCDCONbits.CCDS1 // bit 1
10323 #define CCDEN CCDCONbits.CCDEN // bit 7
10325 #define CCDNA0 CCDNAbits.CCDNA0 // bit 0
10326 #define CCDNA1 CCDNAbits.CCDNA1 // bit 1
10327 #define CCDNA2 CCDNAbits.CCDNA2 // bit 2
10328 #define CCDNA4 CCDNAbits.CCDNA4 // bit 4
10329 #define CCDNA5 CCDNAbits.CCDNA5 // bit 5
10331 #define CCDNB4 CCDNBbits.CCDNB4 // bit 4
10332 #define CCDNB5 CCDNBbits.CCDNB5 // bit 5
10333 #define CCDNB6 CCDNBbits.CCDNB6 // bit 6
10334 #define CCDNB7 CCDNBbits.CCDNB7 // bit 7
10336 #define CCDNC0 CCDNCbits.CCDNC0 // bit 0
10337 #define CCDNC1 CCDNCbits.CCDNC1 // bit 1
10338 #define CCDNC2 CCDNCbits.CCDNC2 // bit 2
10339 #define CCDNC3 CCDNCbits.CCDNC3 // bit 3
10340 #define CCDNC4 CCDNCbits.CCDNC4 // bit 4
10341 #define CCDNC5 CCDNCbits.CCDNC5 // bit 5
10342 #define CCDNC6 CCDNCbits.CCDNC6 // bit 6
10343 #define CCDNC7 CCDNCbits.CCDNC7 // bit 7
10345 #define CCDPA0 CCDPAbits.CCDPA0 // bit 0
10346 #define CCDPA1 CCDPAbits.CCDPA1 // bit 1
10347 #define CCDPA2 CCDPAbits.CCDPA2 // bit 2
10348 #define CCDPA4 CCDPAbits.CCDPA4 // bit 4
10349 #define CCDPA5 CCDPAbits.CCDPA5 // bit 5
10351 #define CCDPB4 CCDPBbits.CCDPB4 // bit 4
10352 #define CCDPB5 CCDPBbits.CCDPB5 // bit 5
10353 #define CCDPB6 CCDPBbits.CCDPB6 // bit 6
10354 #define CCDPB7 CCDPBbits.CCDPB7 // bit 7
10356 #define CCDPC0 CCDPCbits.CCDPC0 // bit 0
10357 #define CCDPC1 CCDPCbits.CCDPC1 // bit 1
10358 #define CCDPC2 CCDPCbits.CCDPC2 // bit 2
10359 #define CCDPC3 CCDPCbits.CCDPC3 // bit 3
10360 #define CCDPC4 CCDPCbits.CCDPC4 // bit 4
10361 #define CCDPC5 CCDPCbits.CCDPC5 // bit 5
10362 #define CCDPC6 CCDPCbits.CCDPC6 // bit 6
10363 #define CCDPC7 CCDPCbits.CCDPC7 // bit 7
10365 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0
10366 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1
10367 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2
10368 #define CCP1CTS3 CCP1CAPbits.CCP1CTS3 // bit 3
10370 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0
10371 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1
10372 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2
10373 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3
10374 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4
10375 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5
10376 #define CCP1EN CCP1CONbits.CCP1EN // bit 7
10378 #define CCP1PPS0 CCP1PPSbits.CCP1PPS0 // bit 0
10379 #define CCP1PPS1 CCP1PPSbits.CCP1PPS1 // bit 1
10380 #define CCP1PPS2 CCP1PPSbits.CCP1PPS2 // bit 2
10381 #define CCP1PPS3 CCP1PPSbits.CCP1PPS3 // bit 3
10382 #define CCP1PPS4 CCP1PPSbits.CCP1PPS4 // bit 4
10384 #define CCP2CTS0 CCP2CAPbits.CCP2CTS0 // bit 0
10385 #define CCP2CTS1 CCP2CAPbits.CCP2CTS1 // bit 1
10386 #define CCP2CTS2 CCP2CAPbits.CCP2CTS2 // bit 2
10387 #define CCP2CTS3 CCP2CAPbits.CCP2CTS3 // bit 3
10389 #define CCP2MODE0 CCP2CONbits.CCP2MODE0 // bit 0
10390 #define CCP2MODE1 CCP2CONbits.CCP2MODE1 // bit 1
10391 #define CCP2MODE2 CCP2CONbits.CCP2MODE2 // bit 2
10392 #define CCP2MODE3 CCP2CONbits.CCP2MODE3 // bit 3
10393 #define CCP2FMT CCP2CONbits.CCP2FMT // bit 4
10394 #define CCP2OUT CCP2CONbits.CCP2OUT // bit 5
10395 #define CCP2EN CCP2CONbits.CCP2EN // bit 7
10397 #define CCP2PPS0 CCP2PPSbits.CCP2PPS0 // bit 0
10398 #define CCP2PPS1 CCP2PPSbits.CCP2PPS1 // bit 1
10399 #define CCP2PPS2 CCP2PPSbits.CCP2PPS2 // bit 2
10400 #define CCP2PPS3 CCP2PPSbits.CCP2PPS3 // bit 3
10401 #define CCP2PPS4 CCP2PPSbits.CCP2PPS4 // bit 4
10403 #define CCP3CTS0 CCP3CAPbits.CCP3CTS0 // bit 0
10404 #define CCP3CTS1 CCP3CAPbits.CCP3CTS1 // bit 1
10405 #define CCP3CTS2 CCP3CAPbits.CCP3CTS2 // bit 2
10406 #define CCP3CTS3 CCP3CAPbits.CCP3CTS3 // bit 3
10408 #define CCP3MODE0 CCP3CONbits.CCP3MODE0 // bit 0
10409 #define CCP3MODE1 CCP3CONbits.CCP3MODE1 // bit 1
10410 #define CCP3MODE2 CCP3CONbits.CCP3MODE2 // bit 2
10411 #define CCP3MODE3 CCP3CONbits.CCP3MODE3 // bit 3
10412 #define CCP3FMT CCP3CONbits.CCP3FMT // bit 4
10413 #define CCP3OUT CCP3CONbits.CCP3OUT // bit 5
10414 #define CCP3EN CCP3CONbits.CCP3EN // bit 7
10416 #define CCP3PPS0 CCP3PPSbits.CCP3PPS0 // bit 0
10417 #define CCP3PPS1 CCP3PPSbits.CCP3PPS1 // bit 1
10418 #define CCP3PPS2 CCP3PPSbits.CCP3PPS2 // bit 2
10419 #define CCP3PPS3 CCP3PPSbits.CCP3PPS3 // bit 3
10420 #define CCP3PPS4 CCP3PPSbits.CCP3PPS4 // bit 4
10422 #define CCP4CTS0 CCP4CAPbits.CCP4CTS0 // bit 0
10423 #define CCP4CTS1 CCP4CAPbits.CCP4CTS1 // bit 1
10424 #define CCP4CTS2 CCP4CAPbits.CCP4CTS2 // bit 2
10425 #define CCP4CTS3 CCP4CAPbits.CCP4CTS3 // bit 3
10427 #define CCP4MODE0 CCP4CONbits.CCP4MODE0 // bit 0
10428 #define CCP4MODE1 CCP4CONbits.CCP4MODE1 // bit 1
10429 #define CCP4MODE2 CCP4CONbits.CCP4MODE2 // bit 2
10430 #define CCP4MODE3 CCP4CONbits.CCP4MODE3 // bit 3
10431 #define CCP4FMT CCP4CONbits.CCP4FMT // bit 4
10432 #define CCP4OUT CCP4CONbits.CCP4OUT // bit 5
10433 #define CCP4EN CCP4CONbits.CCP4EN // bit 7
10435 #define CCP4PPS0 CCP4PPSbits.CCP4PPS0 // bit 0
10436 #define CCP4PPS1 CCP4PPSbits.CCP4PPS1 // bit 1
10437 #define CCP4PPS2 CCP4PPSbits.CCP4PPS2 // bit 2
10438 #define CCP4PPS3 CCP4PPSbits.CCP4PPS3 // bit 3
10439 #define CCP4PPS4 CCP4PPSbits.CCP4PPS4 // bit 4
10441 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
10442 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
10443 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
10444 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
10445 #define C3TSEL0 CCPTMRSbits.C3TSEL0 // bit 4
10446 #define C3TSEL1 CCPTMRSbits.C3TSEL1 // bit 5
10447 #define C4TSEL0 CCPTMRSbits.C4TSEL0 // bit 6
10448 #define C4TSEL1 CCPTMRSbits.C4TSEL1 // bit 7
10450 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
10451 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
10452 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
10453 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
10454 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
10455 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
10456 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
10457 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
10458 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
10459 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
10460 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
10461 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
10462 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
10463 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
10465 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
10466 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
10467 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
10468 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
10469 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
10470 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
10471 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
10472 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
10473 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
10474 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
10475 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
10476 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
10477 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
10478 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
10479 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
10480 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
10482 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
10483 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
10484 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
10485 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
10486 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
10487 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
10488 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
10489 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
10490 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
10491 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
10492 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
10493 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
10494 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
10495 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
10496 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
10497 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
10499 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
10500 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
10501 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
10502 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
10503 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
10504 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
10505 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
10506 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
10507 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
10508 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
10510 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
10511 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
10512 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
10513 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
10514 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
10515 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
10516 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
10517 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
10518 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
10519 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
10520 #define LC1D1S5 CLC1SEL0bits.LC1D1S5 // bit 5, shadows bit in CLC1SEL0bits
10521 #define D1S5 CLC1SEL0bits.D1S5 // bit 5, shadows bit in CLC1SEL0bits
10523 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
10524 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
10525 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
10526 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
10527 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
10528 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
10529 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
10530 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
10531 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
10532 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
10533 #define LC1D2S5 CLC1SEL1bits.LC1D2S5 // bit 5, shadows bit in CLC1SEL1bits
10534 #define D2S5 CLC1SEL1bits.D2S5 // bit 5, shadows bit in CLC1SEL1bits
10536 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
10537 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
10538 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
10539 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
10540 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
10541 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
10542 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
10543 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
10544 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
10545 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
10546 #define LC1D3S5 CLC1SEL2bits.LC1D3S5 // bit 5, shadows bit in CLC1SEL2bits
10547 #define D3S5 CLC1SEL2bits.D3S5 // bit 5, shadows bit in CLC1SEL2bits
10549 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
10550 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
10551 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
10552 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
10553 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
10554 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
10555 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
10556 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
10557 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
10558 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
10559 #define LC1D4S5 CLC1SEL3bits.LC1D4S5 // bit 5, shadows bit in CLC1SEL3bits
10560 #define D4S5 CLC1SEL3bits.D4S5 // bit 5, shadows bit in CLC1SEL3bits
10562 #define MLC1OUT CLCDATAbits.MLC1OUT // bit 0
10563 #define MLC2OUT CLCDATAbits.MLC2OUT // bit 1
10564 #define MLC3OUT CLCDATAbits.MLC3OUT // bit 2
10565 #define MLC4OUT CLCDATAbits.MLC4OUT // bit 3
10567 #define CLCIN0PPS0 CLCIN0PPSbits.CLCIN0PPS0 // bit 0
10568 #define CLCIN0PPS1 CLCIN0PPSbits.CLCIN0PPS1 // bit 1
10569 #define CLCIN0PPS2 CLCIN0PPSbits.CLCIN0PPS2 // bit 2
10570 #define CLCIN0PPS3 CLCIN0PPSbits.CLCIN0PPS3 // bit 3
10571 #define CLCIN0PPS4 CLCIN0PPSbits.CLCIN0PPS4 // bit 4
10573 #define CLCIN1PPS0 CLCIN1PPSbits.CLCIN1PPS0 // bit 0
10574 #define CLCIN1PPS1 CLCIN1PPSbits.CLCIN1PPS1 // bit 1
10575 #define CLCIN1PPS2 CLCIN1PPSbits.CLCIN1PPS2 // bit 2
10576 #define CLCIN1PPS3 CLCIN1PPSbits.CLCIN1PPS3 // bit 3
10577 #define CLCIN1PPS4 CLCIN1PPSbits.CLCIN1PPS4 // bit 4
10579 #define CLCIN2PPS0 CLCIN2PPSbits.CLCIN2PPS0 // bit 0
10580 #define CLCIN2PPS1 CLCIN2PPSbits.CLCIN2PPS1 // bit 1
10581 #define CLCIN2PPS2 CLCIN2PPSbits.CLCIN2PPS2 // bit 2
10582 #define CLCIN2PPS3 CLCIN2PPSbits.CLCIN2PPS3 // bit 3
10583 #define CLCIN2PPS4 CLCIN2PPSbits.CLCIN2PPS4 // bit 4
10585 #define CLCIN3PPS0 CLCIN3PPSbits.CLCIN3PPS0 // bit 0
10586 #define CLCIN3PPS1 CLCIN3PPSbits.CLCIN3PPS1 // bit 1
10587 #define CLCIN3PPS2 CLCIN3PPSbits.CLCIN3PPS2 // bit 2
10588 #define CLCIN3PPS3 CLCIN3PPSbits.CLCIN3PPS3 // bit 3
10589 #define CLCIN3PPS4 CLCIN3PPSbits.CLCIN3PPS4 // bit 4
10591 #define CLKRDIV0 CLKRCONbits.CLKRDIV0 // bit 0
10592 #define CLKRDIV1 CLKRCONbits.CLKRDIV1 // bit 1
10593 #define CLKRDIV2 CLKRCONbits.CLKRDIV2 // bit 2
10594 #define CLKRDC0 CLKRCONbits.CLKRDC0 // bit 3
10595 #define CLKRDC1 CLKRCONbits.CLKRDC1 // bit 4
10596 #define CLKREN CLKRCONbits.CLKREN // bit 7
10598 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
10599 #define C1HYS CM1CON0bits.C1HYS // bit 1
10600 #define C1SP CM1CON0bits.C1SP // bit 2
10601 #define C1POL CM1CON0bits.C1POL // bit 4
10602 #define C1OUT CM1CON0bits.C1OUT // bit 6
10603 #define C1ON CM1CON0bits.C1ON // bit 7
10605 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
10606 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
10607 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
10608 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
10609 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
10610 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
10611 #define C1INTN CM1CON1bits.C1INTN // bit 6
10612 #define C1INTP CM1CON1bits.C1INTP // bit 7
10614 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
10615 #define C2HYS CM2CON0bits.C2HYS // bit 1
10616 #define C2SP CM2CON0bits.C2SP // bit 2
10617 #define C2POL CM2CON0bits.C2POL // bit 4
10618 #define C2OUT CM2CON0bits.C2OUT // bit 6
10619 #define C2ON CM2CON0bits.C2ON // bit 7
10621 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
10622 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
10623 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
10624 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
10625 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
10626 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
10627 #define C2INTN CM2CON1bits.C2INTN // bit 6
10628 #define C2INTP CM2CON1bits.C2INTP // bit 7
10630 #define MC1OUT CMOUTbits.MC1OUT // bit 0
10631 #define MC2OUT CMOUTbits.MC2OUT // bit 1
10633 #define DOZE0 CPUDOZEbits.DOZE0 // bit 0
10634 #define DOZE1 CPUDOZEbits.DOZE1 // bit 1
10635 #define DOZE2 CPUDOZEbits.DOZE2 // bit 2
10636 #define DOE CPUDOZEbits.DOE // bit 4
10637 #define ROI CPUDOZEbits.ROI // bit 5
10638 #define DOZEN CPUDOZEbits.DOZEN // bit 6
10639 #define IDLEN CPUDOZEbits.IDLEN // bit 7
10641 #define LSAC0 CWG1AS0bits.LSAC0 // bit 2, shadows bit in CWG1AS0bits
10642 #define CWG1LSAC0 CWG1AS0bits.CWG1LSAC0 // bit 2, shadows bit in CWG1AS0bits
10643 #define LSAC1 CWG1AS0bits.LSAC1 // bit 3, shadows bit in CWG1AS0bits
10644 #define CWG1LSAC1 CWG1AS0bits.CWG1LSAC1 // bit 3, shadows bit in CWG1AS0bits
10645 #define LSBD0 CWG1AS0bits.LSBD0 // bit 4, shadows bit in CWG1AS0bits
10646 #define CWG1LSBD0 CWG1AS0bits.CWG1LSBD0 // bit 4, shadows bit in CWG1AS0bits
10647 #define LSBD1 CWG1AS0bits.LSBD1 // bit 5, shadows bit in CWG1AS0bits
10648 #define CWG1LSBD1 CWG1AS0bits.CWG1LSBD1 // bit 5, shadows bit in CWG1AS0bits
10649 #define REN CWG1AS0bits.REN // bit 6, shadows bit in CWG1AS0bits
10650 #define CWG1REN CWG1AS0bits.CWG1REN // bit 6, shadows bit in CWG1AS0bits
10651 #define SHUTDOWN CWG1AS0bits.SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10652 #define CWG1SHUTDOWN CWG1AS0bits.CWG1SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10654 #define AS0E CWG1AS1bits.AS0E // bit 0
10655 #define AS1E CWG1AS1bits.AS1E // bit 1
10656 #define AS2E CWG1AS1bits.AS2E // bit 2
10657 #define AS3E CWG1AS1bits.AS3E // bit 3
10658 #define AS4E CWG1AS1bits.AS4E // bit 4
10660 #define CS CWG1CLKCONbits.CS // bit 0, shadows bit in CWG1CLKCONbits
10661 #define CWG1CS CWG1CLKCONbits.CWG1CS // bit 0, shadows bit in CWG1CLKCONbits
10663 #define POLA CWG1CON1bits.POLA // bit 0, shadows bit in CWG1CON1bits
10664 #define CWG1POLA CWG1CON1bits.CWG1POLA // bit 0, shadows bit in CWG1CON1bits
10665 #define POLB CWG1CON1bits.POLB // bit 1, shadows bit in CWG1CON1bits
10666 #define CWG1POLB CWG1CON1bits.CWG1POLB // bit 1, shadows bit in CWG1CON1bits
10667 #define POLC CWG1CON1bits.POLC // bit 2, shadows bit in CWG1CON1bits
10668 #define CWG1POLC CWG1CON1bits.CWG1POLC // bit 2, shadows bit in CWG1CON1bits
10669 #define POLD CWG1CON1bits.POLD // bit 3, shadows bit in CWG1CON1bits
10670 #define CWG1POLD CWG1CON1bits.CWG1POLD // bit 3, shadows bit in CWG1CON1bits
10671 #define IN CWG1CON1bits.IN // bit 5, shadows bit in CWG1CON1bits
10672 #define CWG1IN CWG1CON1bits.CWG1IN // bit 5, shadows bit in CWG1CON1bits
10674 #define CWG1DAT0 CWG1DATbits.CWG1DAT0 // bit 0
10675 #define CWG1DAT1 CWG1DATbits.CWG1DAT1 // bit 1
10676 #define CWG1DAT2 CWG1DATbits.CWG1DAT2 // bit 2
10677 #define CWG1DAT3 CWG1DATbits.CWG1DAT3 // bit 3
10679 #define DBF0 CWG1DBFbits.DBF0 // bit 0, shadows bit in CWG1DBFbits
10680 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0, shadows bit in CWG1DBFbits
10681 #define DBF1 CWG1DBFbits.DBF1 // bit 1, shadows bit in CWG1DBFbits
10682 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1, shadows bit in CWG1DBFbits
10683 #define DBF2 CWG1DBFbits.DBF2 // bit 2, shadows bit in CWG1DBFbits
10684 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2, shadows bit in CWG1DBFbits
10685 #define DBF3 CWG1DBFbits.DBF3 // bit 3, shadows bit in CWG1DBFbits
10686 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3, shadows bit in CWG1DBFbits
10687 #define DBF4 CWG1DBFbits.DBF4 // bit 4, shadows bit in CWG1DBFbits
10688 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4, shadows bit in CWG1DBFbits
10689 #define DBF5 CWG1DBFbits.DBF5 // bit 5, shadows bit in CWG1DBFbits
10690 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5, shadows bit in CWG1DBFbits
10692 #define DBR0 CWG1DBRbits.DBR0 // bit 0, shadows bit in CWG1DBRbits
10693 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0, shadows bit in CWG1DBRbits
10694 #define DBR1 CWG1DBRbits.DBR1 // bit 1, shadows bit in CWG1DBRbits
10695 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1, shadows bit in CWG1DBRbits
10696 #define DBR2 CWG1DBRbits.DBR2 // bit 2, shadows bit in CWG1DBRbits
10697 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2, shadows bit in CWG1DBRbits
10698 #define DBR3 CWG1DBRbits.DBR3 // bit 3, shadows bit in CWG1DBRbits
10699 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3, shadows bit in CWG1DBRbits
10700 #define DBR4 CWG1DBRbits.DBR4 // bit 4, shadows bit in CWG1DBRbits
10701 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4, shadows bit in CWG1DBRbits
10702 #define DBR5 CWG1DBRbits.DBR5 // bit 5, shadows bit in CWG1DBRbits
10703 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5, shadows bit in CWG1DBRbits
10705 #define CWG1PPS0 CWG1PPSbits.CWG1PPS0 // bit 0
10706 #define CWG1PPS1 CWG1PPSbits.CWG1PPS1 // bit 1
10707 #define CWG1PPS2 CWG1PPSbits.CWG1PPS2 // bit 2
10708 #define CWG1PPS3 CWG1PPSbits.CWG1PPS3 // bit 3
10709 #define CWG1PPS4 CWG1PPSbits.CWG1PPS4 // bit 4
10711 #define STRA CWG1STRbits.STRA // bit 0, shadows bit in CWG1STRbits
10712 #define CWG1STRA CWG1STRbits.CWG1STRA // bit 0, shadows bit in CWG1STRbits
10713 #define STRB CWG1STRbits.STRB // bit 1, shadows bit in CWG1STRbits
10714 #define CWG1STRB CWG1STRbits.CWG1STRB // bit 1, shadows bit in CWG1STRbits
10715 #define STRC CWG1STRbits.STRC // bit 2, shadows bit in CWG1STRbits
10716 #define CWG1STRC CWG1STRbits.CWG1STRC // bit 2, shadows bit in CWG1STRbits
10717 #define STRD CWG1STRbits.STRD // bit 3, shadows bit in CWG1STRbits
10718 #define CWG1STRD CWG1STRbits.CWG1STRD // bit 3, shadows bit in CWG1STRbits
10719 #define OVRA CWG1STRbits.OVRA // bit 4, shadows bit in CWG1STRbits
10720 #define CWG1OVRA CWG1STRbits.CWG1OVRA // bit 4, shadows bit in CWG1STRbits
10721 #define OVRB CWG1STRbits.OVRB // bit 5, shadows bit in CWG1STRbits
10722 #define CWG1OVRB CWG1STRbits.CWG1OVRB // bit 5, shadows bit in CWG1STRbits
10723 #define OVRC CWG1STRbits.OVRC // bit 6, shadows bit in CWG1STRbits
10724 #define CWG1OVRC CWG1STRbits.CWG1OVRC // bit 6, shadows bit in CWG1STRbits
10725 #define OVRD CWG1STRbits.OVRD // bit 7, shadows bit in CWG1STRbits
10726 #define CWG1OVRD CWG1STRbits.CWG1OVRD // bit 7, shadows bit in CWG1STRbits
10728 #define CWG2DAT0 CWG2DATbits.CWG2DAT0 // bit 0
10729 #define CWG2DAT1 CWG2DATbits.CWG2DAT1 // bit 1
10730 #define CWG2DAT2 CWG2DATbits.CWG2DAT2 // bit 2
10731 #define CWG2DAT3 CWG2DATbits.CWG2DAT3 // bit 3
10733 #define CWG2PPS0 CWG2PPSbits.CWG2PPS0 // bit 0
10734 #define CWG2PPS1 CWG2PPSbits.CWG2PPS1 // bit 1
10735 #define CWG2PPS2 CWG2PPSbits.CWG2PPS2 // bit 2
10736 #define CWG2PPS3 CWG2PPSbits.CWG2PPS3 // bit 3
10737 #define CWG2PPS4 CWG2PPSbits.CWG2PPS4 // bit 4
10739 #define DAC1NSS DACCON0bits.DAC1NSS // bit 0
10740 #define DAC1PSS0 DACCON0bits.DAC1PSS0 // bit 2
10741 #define DAC1PSS1 DACCON0bits.DAC1PSS1 // bit 3
10742 #define DAC1OE DACCON0bits.DAC1OE // bit 5
10743 #define DAC1EN DACCON0bits.DAC1EN // bit 7
10745 #define DAC1R0 DACCON1bits.DAC1R0 // bit 0
10746 #define DAC1R1 DACCON1bits.DAC1R1 // bit 1
10747 #define DAC1R2 DACCON1bits.DAC1R2 // bit 2
10748 #define DAC1R3 DACCON1bits.DAC1R3 // bit 3
10749 #define DAC1R4 DACCON1bits.DAC1R4 // bit 4
10751 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
10752 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
10753 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
10754 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
10755 #define TSRNG FVRCONbits.TSRNG // bit 4
10756 #define TSEN FVRCONbits.TSEN // bit 5
10757 #define FVRRDY FVRCONbits.FVRRDY // bit 6
10758 #define FVREN FVRCONbits.FVREN // bit 7
10760 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
10761 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
10762 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
10763 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
10764 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
10765 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
10767 #define INLVLB4 INLVLBbits.INLVLB4 // bit 4
10768 #define INLVLB5 INLVLBbits.INLVLB5 // bit 5
10769 #define INLVLB6 INLVLBbits.INLVLB6 // bit 6
10770 #define INLVLB7 INLVLBbits.INLVLB7 // bit 7
10772 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
10773 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
10774 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
10775 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
10776 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
10777 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
10778 #define INLVLC6 INLVLCbits.INLVLC6 // bit 6
10779 #define INLVLC7 INLVLCbits.INLVLC7 // bit 7
10781 #define INTEDG INTCONbits.INTEDG // bit 0
10782 #define PEIE INTCONbits.PEIE // bit 6
10783 #define GIE INTCONbits.GIE // bit 7
10785 #define INTPPS0 INTPPSbits.INTPPS0 // bit 0
10786 #define INTPPS1 INTPPSbits.INTPPS1 // bit 1
10787 #define INTPPS2 INTPPSbits.INTPPS2 // bit 2
10788 #define INTPPS3 INTPPSbits.INTPPS3 // bit 3
10789 #define INTPPS4 INTPPSbits.INTPPS4 // bit 4
10791 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
10792 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
10793 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
10794 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
10795 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
10796 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
10798 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
10799 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
10800 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
10801 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
10802 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
10803 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
10805 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
10806 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
10807 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
10808 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
10809 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
10810 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
10812 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
10813 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
10814 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
10815 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
10817 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
10818 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
10819 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
10820 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
10822 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
10823 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
10824 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
10825 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
10827 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
10828 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
10829 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
10830 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
10831 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
10832 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
10833 #define IOCCF6 IOCCFbits.IOCCF6 // bit 6
10834 #define IOCCF7 IOCCFbits.IOCCF7 // bit 7
10836 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
10837 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
10838 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
10839 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
10840 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
10841 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
10842 #define IOCCN6 IOCCNbits.IOCCN6 // bit 6
10843 #define IOCCN7 IOCCNbits.IOCCN7 // bit 7
10845 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
10846 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
10847 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
10848 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
10849 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
10850 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
10851 #define IOCCP6 IOCCPbits.IOCCP6 // bit 6
10852 #define IOCCP7 IOCCPbits.IOCCP7 // bit 7
10854 #define LATA0 LATAbits.LATA0 // bit 0
10855 #define LATA1 LATAbits.LATA1 // bit 1
10856 #define LATA2 LATAbits.LATA2 // bit 2
10857 #define LATA4 LATAbits.LATA4 // bit 4
10858 #define LATA5 LATAbits.LATA5 // bit 5
10860 #define LATB4 LATBbits.LATB4 // bit 4
10861 #define LATB5 LATBbits.LATB5 // bit 5
10862 #define LATB6 LATBbits.LATB6 // bit 6
10863 #define LATB7 LATBbits.LATB7 // bit 7
10865 #define LATC0 LATCbits.LATC0 // bit 0
10866 #define LATC1 LATCbits.LATC1 // bit 1
10867 #define LATC2 LATCbits.LATC2 // bit 2
10868 #define LATC3 LATCbits.LATC3 // bit 3
10869 #define LATC4 LATCbits.LATC4 // bit 4
10870 #define LATC5 LATCbits.LATC5 // bit 5
10871 #define LATC6 LATCbits.LATC6 // bit 6
10872 #define LATC7 LATCbits.LATC7 // bit 7
10874 #define MDCH0 MDCARHbits.MDCH0 // bit 0
10875 #define MDCH1 MDCARHbits.MDCH1 // bit 1
10876 #define MDCH2 MDCARHbits.MDCH2 // bit 2
10877 #define MDCH3 MDCARHbits.MDCH3 // bit 3
10878 #define MDCHSYNC MDCARHbits.MDCHSYNC // bit 5
10879 #define MDCHPOL MDCARHbits.MDCHPOL // bit 6
10881 #define MDCL0 MDCARLbits.MDCL0 // bit 0
10882 #define MDCL1 MDCARLbits.MDCL1 // bit 1
10883 #define MDCL2 MDCARLbits.MDCL2 // bit 2
10884 #define MDCL3 MDCARLbits.MDCL3 // bit 3
10885 #define MDCLSYNC MDCARLbits.MDCLSYNC // bit 5
10886 #define MDCLPOL MDCARLbits.MDCLPOL // bit 6
10888 #define MDCIN1PPS0 MDCIN1PPSbits.MDCIN1PPS0 // bit 0
10889 #define MDCIN1PPS1 MDCIN1PPSbits.MDCIN1PPS1 // bit 1
10890 #define MDCIN1PPS2 MDCIN1PPSbits.MDCIN1PPS2 // bit 2
10891 #define MDCIN1PPS3 MDCIN1PPSbits.MDCIN1PPS3 // bit 3
10892 #define MDCIN1PPS4 MDCIN1PPSbits.MDCIN1PPS4 // bit 4
10894 #define MDCIN2PPS0 MDCIN2PPSbits.MDCIN2PPS0 // bit 0
10895 #define MDCIN2PPS1 MDCIN2PPSbits.MDCIN2PPS1 // bit 1
10896 #define MDCIN2PPS2 MDCIN2PPSbits.MDCIN2PPS2 // bit 2
10897 #define MDCIN2PPS3 MDCIN2PPSbits.MDCIN2PPS3 // bit 3
10898 #define MDCIN2PPS4 MDCIN2PPSbits.MDCIN2PPS4 // bit 4
10900 #define MDBIT MDCONbits.MDBIT // bit 0
10901 #define MDOUT MDCONbits.MDOUT // bit 3
10902 #define MDOPOL MDCONbits.MDOPOL // bit 4
10903 #define MDEN MDCONbits.MDEN // bit 7
10905 #define MDMINPPS0 MDMINPPSbits.MDMINPPS0 // bit 0
10906 #define MDMINPPS1 MDMINPPSbits.MDMINPPS1 // bit 1
10907 #define MDMINPPS2 MDMINPPSbits.MDMINPPS2 // bit 2
10908 #define MDMINPPS3 MDMINPPSbits.MDMINPPS3 // bit 3
10909 #define MDMINPPS4 MDMINPPSbits.MDMINPPS4 // bit 4
10911 #define MDMS0 MDSRCbits.MDMS0 // bit 0
10912 #define MDMS1 MDSRCbits.MDMS1 // bit 1
10913 #define MDMS2 MDSRCbits.MDMS2 // bit 2
10914 #define MDMS3 MDSRCbits.MDMS3 // bit 3
10916 #define N1PFM NCO1CONbits.N1PFM // bit 0
10917 #define N1POL NCO1CONbits.N1POL // bit 4
10918 #define N1OUT NCO1CONbits.N1OUT // bit 5
10919 #define N1EN NCO1CONbits.N1EN // bit 7
10921 #define NVMADR8 NVMADRHbits.NVMADR8 // bit 0
10922 #define NVMADR9 NVMADRHbits.NVMADR9 // bit 1
10923 #define NVMADR10 NVMADRHbits.NVMADR10 // bit 2
10924 #define NVMADR11 NVMADRHbits.NVMADR11 // bit 3
10925 #define NVMADR12 NVMADRHbits.NVMADR12 // bit 4
10926 #define NVMADR13 NVMADRHbits.NVMADR13 // bit 5
10927 #define NVMADR14 NVMADRHbits.NVMADR14 // bit 6
10929 #define NVMADR0 NVMADRLbits.NVMADR0 // bit 0
10930 #define NVMADR1 NVMADRLbits.NVMADR1 // bit 1
10931 #define NVMADR2 NVMADRLbits.NVMADR2 // bit 2
10932 #define NVMADR3 NVMADRLbits.NVMADR3 // bit 3
10933 #define NVMADR4 NVMADRLbits.NVMADR4 // bit 4
10934 #define NVMADR5 NVMADRLbits.NVMADR5 // bit 5
10935 #define NVMADR6 NVMADRLbits.NVMADR6 // bit 6
10936 #define NVMADR7 NVMADRLbits.NVMADR7 // bit 7
10938 #define RD NVMCON1bits.RD // bit 0
10939 #define WR NVMCON1bits.WR // bit 1
10940 #define WREN NVMCON1bits.WREN // bit 2
10941 #define WRERR NVMCON1bits.WRERR // bit 3
10942 #define FREE NVMCON1bits.FREE // bit 4
10943 #define LWLO NVMCON1bits.LWLO // bit 5
10944 #define NVMREGS NVMCON1bits.NVMREGS // bit 6
10946 #define NVMDAT8 NVMDATHbits.NVMDAT8 // bit 0
10947 #define NVMDAT9 NVMDATHbits.NVMDAT9 // bit 1
10948 #define NVMDAT10 NVMDATHbits.NVMDAT10 // bit 2
10949 #define NVMDAT11 NVMDATHbits.NVMDAT11 // bit 3
10950 #define NVMDAT12 NVMDATHbits.NVMDAT12 // bit 4
10951 #define NVMDAT13 NVMDATHbits.NVMDAT13 // bit 5
10953 #define NVMDAT0 NVMDATLbits.NVMDAT0 // bit 0
10954 #define NVMDAT1 NVMDATLbits.NVMDAT1 // bit 1
10955 #define NVMDAT2 NVMDATLbits.NVMDAT2 // bit 2
10956 #define NVMDAT3 NVMDATLbits.NVMDAT3 // bit 3
10957 #define NVMDAT4 NVMDATLbits.NVMDAT4 // bit 4
10958 #define NVMDAT5 NVMDATLbits.NVMDAT5 // bit 5
10959 #define NVMDAT6 NVMDATLbits.NVMDAT6 // bit 6
10960 #define NVMDAT7 NVMDATLbits.NVMDAT7 // bit 7
10962 #define ODCA0 ODCONAbits.ODCA0 // bit 0
10963 #define ODCA1 ODCONAbits.ODCA1 // bit 1
10964 #define ODCA2 ODCONAbits.ODCA2 // bit 2
10965 #define ODCA4 ODCONAbits.ODCA4 // bit 4
10966 #define ODCA5 ODCONAbits.ODCA5 // bit 5
10968 #define ODCB4 ODCONBbits.ODCB4 // bit 4
10969 #define ODCB5 ODCONBbits.ODCB5 // bit 5
10970 #define ODCB6 ODCONBbits.ODCB6 // bit 6
10971 #define ODCB7 ODCONBbits.ODCB7 // bit 7
10973 #define ODCC0 ODCONCbits.ODCC0 // bit 0
10974 #define ODCC1 ODCONCbits.ODCC1 // bit 1
10975 #define ODCC2 ODCONCbits.ODCC2 // bit 2
10976 #define ODCC3 ODCONCbits.ODCC3 // bit 3
10977 #define ODCC4 ODCONCbits.ODCC4 // bit 4
10978 #define ODCC5 ODCONCbits.ODCC5 // bit 5
10979 #define ODCC6 ODCONCbits.ODCC6 // bit 6
10980 #define ODCC7 ODCONCbits.ODCC7 // bit 7
10982 #define NDIV0 OSCCON1bits.NDIV0 // bit 0
10983 #define NDIV1 OSCCON1bits.NDIV1 // bit 1
10984 #define NDIV2 OSCCON1bits.NDIV2 // bit 2
10985 #define NDIV3 OSCCON1bits.NDIV3 // bit 3
10986 #define NOSC0 OSCCON1bits.NOSC0 // bit 4
10987 #define NOSC1 OSCCON1bits.NOSC1 // bit 5
10988 #define NOSC2 OSCCON1bits.NOSC2 // bit 6
10990 #define CDIV0 OSCCON2bits.CDIV0 // bit 0
10991 #define CDIV1 OSCCON2bits.CDIV1 // bit 1
10992 #define CDIV2 OSCCON2bits.CDIV2 // bit 2
10993 #define CDIV3 OSCCON2bits.CDIV3 // bit 3
10994 #define COSC0 OSCCON2bits.COSC0 // bit 4
10995 #define COSC1 OSCCON2bits.COSC1 // bit 5
10996 #define COSC2 OSCCON2bits.COSC2 // bit 6
10998 #define NOSCR OSCCON3bits.NOSCR // bit 3
10999 #define ORDY OSCCON3bits.ORDY // bit 4
11000 #define SOSCBE OSCCON3bits.SOSCBE // bit 5
11001 #define SOSCPWR OSCCON3bits.SOSCPWR // bit 6
11002 #define CSWHOLD OSCCON3bits.CSWHOLD // bit 7
11004 #define ADOEN OSCENbits.ADOEN // bit 2
11005 #define SOSCEN OSCENbits.SOSCEN // bit 3
11006 #define LFOEN OSCENbits.LFOEN // bit 4
11007 #define HFOEN OSCENbits.HFOEN // bit 6
11008 #define EXTOEN OSCENbits.EXTOEN // bit 7
11010 #define HFFRQ0 OSCFRQbits.HFFRQ0 // bit 0
11011 #define HFFRQ1 OSCFRQbits.HFFRQ1 // bit 1
11012 #define HFFRQ2 OSCFRQbits.HFFRQ2 // bit 2
11013 #define HFFRQ3 OSCFRQbits.HFFRQ3 // bit 3
11015 #define PLLR OSCSTAT1bits.PLLR // bit 0
11016 #define ADOR OSCSTAT1bits.ADOR // bit 2
11017 #define SOR OSCSTAT1bits.SOR // bit 3
11018 #define LFOR OSCSTAT1bits.LFOR // bit 4
11019 #define HFOR OSCSTAT1bits.HFOR // bit 6
11020 #define EXTOR OSCSTAT1bits.EXTOR // bit 7
11022 #define HFTUN0 OSCTUNEbits.HFTUN0 // bit 0
11023 #define HFTUN1 OSCTUNEbits.HFTUN1 // bit 1
11024 #define HFTUN2 OSCTUNEbits.HFTUN2 // bit 2
11025 #define HFTUN3 OSCTUNEbits.HFTUN3 // bit 3
11026 #define HFTUN4 OSCTUNEbits.HFTUN4 // bit 4
11027 #define HFTUN5 OSCTUNEbits.HFTUN5 // bit 5
11029 #define NOT_BOR PCON0bits.NOT_BOR // bit 0
11030 #define NOT_POR PCON0bits.NOT_POR // bit 1
11031 #define NOT_RI PCON0bits.NOT_RI // bit 2
11032 #define NOT_RMCLR PCON0bits.NOT_RMCLR // bit 3
11033 #define NOT_RWDT PCON0bits.NOT_RWDT // bit 4
11034 #define STKUNF PCON0bits.STKUNF // bit 6
11035 #define STKOVF PCON0bits.STKOVF // bit 7
11037 #define INTE PIE0bits.INTE // bit 0
11038 #define IOCIE PIE0bits.IOCIE // bit 4
11039 #define TMR0IE PIE0bits.TMR0IE // bit 5
11041 #define TMR1IE PIE1bits.TMR1IE // bit 0
11042 #define TMR2IE PIE1bits.TMR2IE // bit 1
11043 #define BCL1IE PIE1bits.BCL1IE // bit 2
11044 #define SSP1IE PIE1bits.SSP1IE // bit 3
11045 #define TXIE PIE1bits.TXIE // bit 4
11046 #define RCIE PIE1bits.RCIE // bit 5
11047 #define ADIE PIE1bits.ADIE // bit 6
11048 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
11050 #define NCO1IE PIE2bits.NCO1IE // bit 0
11051 #define TMR4IE PIE2bits.TMR4IE // bit 1
11052 #define NVMIE PIE2bits.NVMIE // bit 4
11053 #define C1IE PIE2bits.C1IE // bit 5
11054 #define C2IE PIE2bits.C2IE // bit 6
11055 #define TMR6IE PIE2bits.TMR6IE // bit 7
11057 #define CLC1IE PIE3bits.CLC1IE // bit 0
11058 #define CLC2IE PIE3bits.CLC2IE // bit 1
11059 #define CLC3IE PIE3bits.CLC3IE // bit 2
11060 #define CLC4IE PIE3bits.CLC4IE // bit 3
11061 #define TMR3IE PIE3bits.TMR3IE // bit 4
11062 #define TMR3GIE PIE3bits.TMR3GIE // bit 5
11063 #define CSWIE PIE3bits.CSWIE // bit 6
11064 #define OSFIE PIE3bits.OSFIE // bit 7
11066 #define CCP1IE PIE4bits.CCP1IE // bit 0
11067 #define CCP2IE PIE4bits.CCP2IE // bit 1
11068 #define CCP3IE PIE4bits.CCP3IE // bit 2
11069 #define CCP4IE PIE4bits.CCP4IE // bit 3
11070 #define TMR5IE PIE4bits.TMR5IE // bit 4
11071 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
11072 #define CWG1IE PIE4bits.CWG1IE // bit 6
11073 #define CWG2IE PIE4bits.CWG2IE // bit 7
11075 #define INTF PIR0bits.INTF // bit 0
11076 #define IOCIF PIR0bits.IOCIF // bit 4
11077 #define TMR0IF PIR0bits.TMR0IF // bit 5
11079 #define TMR1IF PIR1bits.TMR1IF // bit 0
11080 #define TMR2IF PIR1bits.TMR2IF // bit 1
11081 #define BCL1IF PIR1bits.BCL1IF // bit 2
11082 #define SSP1IF PIR1bits.SSP1IF // bit 3
11083 #define TXIF PIR1bits.TXIF // bit 4
11084 #define RCIF PIR1bits.RCIF // bit 5
11085 #define ADIF PIR1bits.ADIF // bit 6
11086 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
11088 #define NCO1IF PIR2bits.NCO1IF // bit 0
11089 #define TMR4IF PIR2bits.TMR4IF // bit 1
11090 #define NVMIF PIR2bits.NVMIF // bit 4
11091 #define C1IF PIR2bits.C1IF // bit 5
11092 #define C2IF PIR2bits.C2IF // bit 6
11093 #define TMR6IF PIR2bits.TMR6IF // bit 7
11095 #define CLC1IF PIR3bits.CLC1IF // bit 0
11096 #define CLC2IF PIR3bits.CLC2IF // bit 1
11097 #define CLC3IF PIR3bits.CLC3IF // bit 2
11098 #define CLC4IF PIR3bits.CLC4IF // bit 3
11099 #define TMR3IF PIR3bits.TMR3IF // bit 4
11100 #define TMR3GIF PIR3bits.TMR3GIF // bit 5
11101 #define CSWIF PIR3bits.CSWIF // bit 6
11102 #define OSFIF PIR3bits.OSFIF // bit 7
11104 #define CCP1IF PIR4bits.CCP1IF // bit 0
11105 #define CCP2IF PIR4bits.CCP2IF // bit 1
11106 #define CCP3IF PIR4bits.CCP3IF // bit 2
11107 #define CCP4IF PIR4bits.CCP4IF // bit 3
11108 #define TMR5IF PIR4bits.TMR5IF // bit 4
11109 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
11110 #define CWG1IF PIR4bits.CWG1IF // bit 6
11111 #define CWG2IF PIR4bits.CWG2IF // bit 7
11113 #define IOCMD PMD0bits.IOCMD // bit 0
11114 #define CLKRMD PMD0bits.CLKRMD // bit 1
11115 #define NVMMD PMD0bits.NVMMD // bit 2
11116 #define FVRMD PMD0bits.FVRMD // bit 6
11117 #define SYSCMD PMD0bits.SYSCMD // bit 7
11119 #define TMR0MD PMD1bits.TMR0MD // bit 0
11120 #define TMR1MD PMD1bits.TMR1MD // bit 1
11121 #define TMR2MD PMD1bits.TMR2MD // bit 2
11122 #define TMR3MD PMD1bits.TMR3MD // bit 3
11123 #define TMR4MD PMD1bits.TMR4MD // bit 4
11124 #define TMR5MD PMD1bits.TMR5MD // bit 5
11125 #define TMR6MD PMD1bits.TMR6MD // bit 6
11126 #define NCOMD PMD1bits.NCOMD // bit 7
11128 #define CMP1MD PMD2bits.CMP1MD // bit 1
11129 #define CMP2MD PMD2bits.CMP2MD // bit 2
11130 #define ADCMD PMD2bits.ADCMD // bit 5
11131 #define DACMD PMD2bits.DACMD // bit 6
11133 #define CCP1MD PMD3bits.CCP1MD // bit 0
11134 #define CCP2MD PMD3bits.CCP2MD // bit 1
11135 #define CCP3MD PMD3bits.CCP3MD // bit 2
11136 #define CCP4MD PMD3bits.CCP4MD // bit 3
11137 #define PWM5MD PMD3bits.PWM5MD // bit 4
11138 #define PWM6MD PMD3bits.PWM6MD // bit 5
11139 #define CWG1MD PMD3bits.CWG1MD // bit 6
11140 #define CWG2MD PMD3bits.CWG2MD // bit 7
11142 #define MSSP1MD PMD4bits.MSSP1MD // bit 1
11143 #define UART1MD PMD4bits.UART1MD // bit 5
11145 #define DSMMD PMD5bits.DSMMD // bit 0
11146 #define CLC1MD PMD5bits.CLC1MD // bit 1
11147 #define CLC2MD PMD5bits.CLC2MD // bit 2
11148 #define CLC3MD PMD5bits.CLC3MD // bit 3
11149 #define CLC4MD PMD5bits.CLC4MD // bit 4
11151 #define RA0 PORTAbits.RA0 // bit 0
11152 #define RA1 PORTAbits.RA1 // bit 1
11153 #define RA2 PORTAbits.RA2 // bit 2
11154 #define RA3 PORTAbits.RA3 // bit 3
11155 #define RA4 PORTAbits.RA4 // bit 4
11156 #define RA5 PORTAbits.RA5 // bit 5
11158 #define RB4 PORTBbits.RB4 // bit 4
11159 #define RB5 PORTBbits.RB5 // bit 5
11160 #define RB6 PORTBbits.RB6 // bit 6
11161 #define RB7 PORTBbits.RB7 // bit 7
11163 #define RC0 PORTCbits.RC0 // bit 0
11164 #define RC1 PORTCbits.RC1 // bit 1
11165 #define RC2 PORTCbits.RC2 // bit 2
11166 #define RC3 PORTCbits.RC3 // bit 3
11167 #define RC4 PORTCbits.RC4 // bit 4
11168 #define RC5 PORTCbits.RC5 // bit 5
11169 #define RC6 PORTCbits.RC6 // bit 6
11170 #define RC7 PORTCbits.RC7 // bit 7
11172 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
11174 #define PWM5POL PWM5CONbits.PWM5POL // bit 4
11175 #define PWM5OUT PWM5CONbits.PWM5OUT // bit 5
11176 #define PWM5EN PWM5CONbits.PWM5EN // bit 7
11178 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
11179 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
11180 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
11181 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
11182 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
11183 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
11184 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
11185 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
11187 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 6
11188 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 7
11190 #define PWM6POL PWM6CONbits.PWM6POL // bit 4
11191 #define PWM6OUT PWM6CONbits.PWM6OUT // bit 5
11192 #define PWM6EN PWM6CONbits.PWM6EN // bit 7
11194 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
11195 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
11196 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
11197 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
11198 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
11199 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
11200 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
11201 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
11203 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 6
11204 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 7
11206 #define P5TSEL0 PWMTMRSbits.P5TSEL0 // bit 0
11207 #define P5TSEL1 PWMTMRSbits.P5TSEL1 // bit 1
11208 #define P6TSEL0 PWMTMRSbits.P6TSEL0 // bit 2
11209 #define P6TSEL1 PWMTMRSbits.P6TSEL1 // bit 3
11211 #define RA0PPS0 RA0PPSbits.RA0PPS0 // bit 0
11212 #define RA0PPS1 RA0PPSbits.RA0PPS1 // bit 1
11213 #define RA0PPS2 RA0PPSbits.RA0PPS2 // bit 2
11214 #define RA0PPS3 RA0PPSbits.RA0PPS3 // bit 3
11215 #define RA0PPS4 RA0PPSbits.RA0PPS4 // bit 4
11217 #define RA1PPS0 RA1PPSbits.RA1PPS0 // bit 0
11218 #define RA1PPS1 RA1PPSbits.RA1PPS1 // bit 1
11219 #define RA1PPS2 RA1PPSbits.RA1PPS2 // bit 2
11220 #define RA1PPS3 RA1PPSbits.RA1PPS3 // bit 3
11221 #define RA1PPS4 RA1PPSbits.RA1PPS4 // bit 4
11223 #define RA2PPS0 RA2PPSbits.RA2PPS0 // bit 0
11224 #define RA2PPS1 RA2PPSbits.RA2PPS1 // bit 1
11225 #define RA2PPS2 RA2PPSbits.RA2PPS2 // bit 2
11226 #define RA2PPS3 RA2PPSbits.RA2PPS3 // bit 3
11227 #define RA2PPS4 RA2PPSbits.RA2PPS4 // bit 4
11229 #define RA4PPS0 RA4PPSbits.RA4PPS0 // bit 0
11230 #define RA4PPS1 RA4PPSbits.RA4PPS1 // bit 1
11231 #define RA4PPS2 RA4PPSbits.RA4PPS2 // bit 2
11232 #define RA4PPS3 RA4PPSbits.RA4PPS3 // bit 3
11233 #define RA4PPS4 RA4PPSbits.RA4PPS4 // bit 4
11235 #define RA5PPS0 RA5PPSbits.RA5PPS0 // bit 0
11236 #define RA5PPS1 RA5PPSbits.RA5PPS1 // bit 1
11237 #define RA5PPS2 RA5PPSbits.RA5PPS2 // bit 2
11238 #define RA5PPS3 RA5PPSbits.RA5PPS3 // bit 3
11239 #define RA5PPS4 RA5PPSbits.RA5PPS4 // bit 4
11241 #define RC0PPS0 RC0PPSbits.RC0PPS0 // bit 0
11242 #define RC0PPS1 RC0PPSbits.RC0PPS1 // bit 1
11243 #define RC0PPS2 RC0PPSbits.RC0PPS2 // bit 2
11244 #define RC0PPS3 RC0PPSbits.RC0PPS3 // bit 3
11245 #define RC0PPS4 RC0PPSbits.RC0PPS4 // bit 4
11247 #define RC1PPS0 RC1PPSbits.RC1PPS0 // bit 0
11248 #define RC1PPS1 RC1PPSbits.RC1PPS1 // bit 1
11249 #define RC1PPS2 RC1PPSbits.RC1PPS2 // bit 2
11250 #define RC1PPS3 RC1PPSbits.RC1PPS3 // bit 3
11251 #define RC1PPS4 RC1PPSbits.RC1PPS4 // bit 4
11253 #define RX9D RC1STAbits.RX9D // bit 0
11254 #define OERR RC1STAbits.OERR // bit 1
11255 #define FERR RC1STAbits.FERR // bit 2
11256 #define ADDEN RC1STAbits.ADDEN // bit 3
11257 #define CREN RC1STAbits.CREN // bit 4
11258 #define SREN RC1STAbits.SREN // bit 5
11259 #define RX9 RC1STAbits.RX9 // bit 6
11260 #define SPEN RC1STAbits.SPEN // bit 7
11262 #define RC2PPS0 RC2PPSbits.RC2PPS0 // bit 0
11263 #define RC2PPS1 RC2PPSbits.RC2PPS1 // bit 1
11264 #define RC2PPS2 RC2PPSbits.RC2PPS2 // bit 2
11265 #define RC2PPS3 RC2PPSbits.RC2PPS3 // bit 3
11266 #define RC2PPS4 RC2PPSbits.RC2PPS4 // bit 4
11268 #define RC3PPS0 RC3PPSbits.RC3PPS0 // bit 0
11269 #define RC3PPS1 RC3PPSbits.RC3PPS1 // bit 1
11270 #define RC3PPS2 RC3PPSbits.RC3PPS2 // bit 2
11271 #define RC3PPS3 RC3PPSbits.RC3PPS3 // bit 3
11272 #define RC3PPS4 RC3PPSbits.RC3PPS4 // bit 4
11274 #define RC4PPS0 RC4PPSbits.RC4PPS0 // bit 0
11275 #define RC4PPS1 RC4PPSbits.RC4PPS1 // bit 1
11276 #define RC4PPS2 RC4PPSbits.RC4PPS2 // bit 2
11277 #define RC4PPS3 RC4PPSbits.RC4PPS3 // bit 3
11278 #define RC4PPS4 RC4PPSbits.RC4PPS4 // bit 4
11280 #define RC5PPS0 RC5PPSbits.RC5PPS0 // bit 0
11281 #define RC5PPS1 RC5PPSbits.RC5PPS1 // bit 1
11282 #define RC5PPS2 RC5PPSbits.RC5PPS2 // bit 2
11283 #define RC5PPS3 RC5PPSbits.RC5PPS3 // bit 3
11284 #define RC5PPS4 RC5PPSbits.RC5PPS4 // bit 4
11286 #define RXDTPPS0 RXPPSbits.RXDTPPS0 // bit 0
11287 #define RXDTPPS1 RXPPSbits.RXDTPPS1 // bit 1
11288 #define RXDTPPS2 RXPPSbits.RXDTPPS2 // bit 2
11289 #define RXDTPPS3 RXPPSbits.RXDTPPS3 // bit 3
11290 #define RXDTPPS4 RXPPSbits.RXDTPPS4 // bit 4
11292 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
11293 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
11294 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
11295 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
11296 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
11298 #define SLRB4 SLRCONBbits.SLRB4 // bit 4
11299 #define SLRB5 SLRCONBbits.SLRB5 // bit 5
11300 #define SLRB6 SLRCONBbits.SLRB6 // bit 6
11301 #define SLRB7 SLRCONBbits.SLRB7 // bit 7
11303 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
11304 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
11305 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
11306 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
11307 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
11308 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
11309 #define SLRC6 SLRCONCbits.SLRC6 // bit 6
11310 #define SLRC7 SLRCONCbits.SLRC7 // bit 7
11312 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
11313 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
11314 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
11315 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
11316 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
11317 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
11318 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
11319 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
11320 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
11321 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
11322 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
11323 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
11324 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
11325 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
11326 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
11327 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
11329 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
11330 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
11331 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
11332 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
11333 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
11334 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
11335 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
11336 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
11337 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
11338 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
11339 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
11340 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
11341 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
11342 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
11343 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
11344 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
11346 #define SSP1CLKPPS0 SSP1CLKPPSbits.SSP1CLKPPS0 // bit 0
11347 #define SSP1CLKPPS1 SSP1CLKPPSbits.SSP1CLKPPS1 // bit 1
11348 #define SSP1CLKPPS2 SSP1CLKPPSbits.SSP1CLKPPS2 // bit 2
11349 #define SSP1CLKPPS3 SSP1CLKPPSbits.SSP1CLKPPS3 // bit 3
11350 #define SSP1CLKPPS4 SSP1CLKPPSbits.SSP1CLKPPS4 // bit 4
11352 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
11353 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
11354 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
11355 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
11356 #define CKP SSP1CONbits.CKP // bit 4
11357 #define SSPEN SSP1CONbits.SSPEN // bit 5
11358 #define SSPOV SSP1CONbits.SSPOV // bit 6
11359 #define WCOL SSP1CONbits.WCOL // bit 7
11361 #define SEN SSP1CON2bits.SEN // bit 0
11362 #define RSEN SSP1CON2bits.RSEN // bit 1
11363 #define PEN SSP1CON2bits.PEN // bit 2
11364 #define RCEN SSP1CON2bits.RCEN // bit 3
11365 #define ACKEN SSP1CON2bits.ACKEN // bit 4
11366 #define ACKDT SSP1CON2bits.ACKDT // bit 5
11367 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
11368 #define GCEN SSP1CON2bits.GCEN // bit 7
11370 #define DHEN SSP1CON3bits.DHEN // bit 0
11371 #define AHEN SSP1CON3bits.AHEN // bit 1
11372 #define SBCDE SSP1CON3bits.SBCDE // bit 2
11373 #define SDAHT SSP1CON3bits.SDAHT // bit 3
11374 #define BOEN SSP1CON3bits.BOEN // bit 4
11375 #define SCIE SSP1CON3bits.SCIE // bit 5
11376 #define PCIE SSP1CON3bits.PCIE // bit 6
11377 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
11379 #define SSP1DATPPS0 SSP1DATPPSbits.SSP1DATPPS0 // bit 0
11380 #define SSP1DATPPS1 SSP1DATPPSbits.SSP1DATPPS1 // bit 1
11381 #define SSP1DATPPS2 SSP1DATPPSbits.SSP1DATPPS2 // bit 2
11382 #define SSP1DATPPS3 SSP1DATPPSbits.SSP1DATPPS3 // bit 3
11383 #define SSP1DATPPS4 SSP1DATPPSbits.SSP1DATPPS4 // bit 4
11385 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
11386 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
11387 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
11388 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
11389 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
11390 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
11391 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
11392 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
11393 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
11394 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
11395 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
11396 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
11397 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
11398 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
11399 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
11400 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
11402 #define SSP1SSPPS0 SSP1SSPPSbits.SSP1SSPPS0 // bit 0
11403 #define SSP1SSPPS1 SSP1SSPPSbits.SSP1SSPPS1 // bit 1
11404 #define SSP1SSPPS2 SSP1SSPPSbits.SSP1SSPPS2 // bit 2
11405 #define SSP1SSPPS3 SSP1SSPPSbits.SSP1SSPPS3 // bit 3
11406 #define SSP1SSPPS4 SSP1SSPPSbits.SSP1SSPPS4 // bit 4
11408 #define BF SSP1STATbits.BF // bit 0
11409 #define UA SSP1STATbits.UA // bit 1
11410 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
11411 #define S SSP1STATbits.S // bit 3
11412 #define P SSP1STATbits.P // bit 4
11413 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
11414 #define CKE SSP1STATbits.CKE // bit 6
11415 #define SMP SSP1STATbits.SMP // bit 7
11417 #define C STATUSbits.C // bit 0
11418 #define DC STATUSbits.DC // bit 1
11419 #define Z STATUSbits.Z // bit 2
11420 #define NOT_PD STATUSbits.NOT_PD // bit 3
11421 #define NOT_TO STATUSbits.NOT_TO // bit 4
11423 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
11424 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
11425 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
11427 #define T0CKIPPS0 T0CKIPPSbits.T0CKIPPS0 // bit 0
11428 #define T0CKIPPS1 T0CKIPPSbits.T0CKIPPS1 // bit 1
11429 #define T0CKIPPS2 T0CKIPPSbits.T0CKIPPS2 // bit 2
11430 #define T0CKIPPS3 T0CKIPPSbits.T0CKIPPS3 // bit 3
11431 #define T0CKIPPS4 T0CKIPPSbits.T0CKIPPS4 // bit 4
11433 #define T0OUTPS0 T0CON0bits.T0OUTPS0 // bit 0
11434 #define T0OUTPS1 T0CON0bits.T0OUTPS1 // bit 1
11435 #define T0OUTPS2 T0CON0bits.T0OUTPS2 // bit 2
11436 #define T0OUTPS3 T0CON0bits.T0OUTPS3 // bit 3
11437 #define T016BIT T0CON0bits.T016BIT // bit 4
11438 #define T0OUT T0CON0bits.T0OUT // bit 5
11439 #define T0EN T0CON0bits.T0EN // bit 7
11441 #define T0CKPS0 T0CON1bits.T0CKPS0 // bit 0
11442 #define T0CKPS1 T0CON1bits.T0CKPS1 // bit 1
11443 #define T0CKPS2 T0CON1bits.T0CKPS2 // bit 2
11444 #define T0CKPS3 T0CON1bits.T0CKPS3 // bit 3
11445 #define T0ASYNC T0CON1bits.T0ASYNC // bit 4
11446 #define T0CS0 T0CON1bits.T0CS0 // bit 5
11447 #define T0CS1 T0CON1bits.T0CS1 // bit 6
11448 #define T0CS2 T0CON1bits.T0CS2 // bit 7
11450 #define T1CKIPPS0 T1CKIPPSbits.T1CKIPPS0 // bit 0
11451 #define T1CKIPPS1 T1CKIPPSbits.T1CKIPPS1 // bit 1
11452 #define T1CKIPPS2 T1CKIPPSbits.T1CKIPPS2 // bit 2
11453 #define T1CKIPPS3 T1CKIPPSbits.T1CKIPPS3 // bit 3
11454 #define T1CKIPPS4 T1CKIPPSbits.T1CKIPPS4 // bit 4
11456 #define TMR1ON T1CONbits.TMR1ON // bit 0
11457 #define T1SYNC T1CONbits.T1SYNC // bit 2
11458 #define T1SOSC T1CONbits.T1SOSC // bit 3
11459 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
11460 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
11461 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
11462 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
11464 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
11465 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
11466 #define T1GVAL T1GCONbits.T1GVAL // bit 2
11467 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
11468 #define T1GSPM T1GCONbits.T1GSPM // bit 4
11469 #define T1GTM T1GCONbits.T1GTM // bit 5
11470 #define T1GPOL T1GCONbits.T1GPOL // bit 6
11471 #define TMR1GE T1GCONbits.TMR1GE // bit 7
11473 #define T1GPPS0 T1GPPSbits.T1GPPS0 // bit 0
11474 #define T1GPPS1 T1GPPSbits.T1GPPS1 // bit 1
11475 #define T1GPPS2 T1GPPSbits.T1GPPS2 // bit 2
11476 #define T1GPPS3 T1GPPSbits.T1GPPS3 // bit 3
11477 #define T1GPPS4 T1GPPSbits.T1GPPS4 // bit 4
11479 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
11480 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
11481 #define TMR2ON T2CONbits.TMR2ON // bit 2
11482 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
11483 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
11484 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
11485 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
11487 #define TMR3ON T3CONbits.TMR3ON // bit 0
11488 #define T3SYNC T3CONbits.T3SYNC // bit 2
11489 #define T3SOSC T3CONbits.T3SOSC // bit 3
11490 #define T3CKPS0 T3CONbits.T3CKPS0 // bit 4
11491 #define T3CKPS1 T3CONbits.T3CKPS1 // bit 5
11492 #define TMR3CS0 T3CONbits.TMR3CS0 // bit 6
11493 #define TMR3CS1 T3CONbits.TMR3CS1 // bit 7
11495 #define T3GSS0 T3GCONbits.T3GSS0 // bit 0
11496 #define T3GSS1 T3GCONbits.T3GSS1 // bit 1
11497 #define T3GVAL T3GCONbits.T3GVAL // bit 2
11498 #define T3GGO_NOT_DONE T3GCONbits.T3GGO_NOT_DONE // bit 3
11499 #define T3GSPM T3GCONbits.T3GSPM // bit 4
11500 #define T3GTM T3GCONbits.T3GTM // bit 5
11501 #define T3GPOL T3GCONbits.T3GPOL // bit 6
11502 #define TMR3GE T3GCONbits.TMR3GE // bit 7
11504 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
11505 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
11506 #define TMR4ON T4CONbits.TMR4ON // bit 2
11507 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
11508 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
11509 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
11510 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
11512 #define TMR5ON T5CONbits.TMR5ON // bit 0
11513 #define T5SYNC T5CONbits.T5SYNC // bit 2
11514 #define T5SOSC T5CONbits.T5SOSC // bit 3
11515 #define T5CKPS0 T5CONbits.T5CKPS0 // bit 4
11516 #define T5CKPS1 T5CONbits.T5CKPS1 // bit 5
11517 #define TMR5CS0 T5CONbits.TMR5CS0 // bit 6
11518 #define TMR5CS1 T5CONbits.TMR5CS1 // bit 7
11520 #define T5GSS0 T5GCONbits.T5GSS0 // bit 0
11521 #define T5GSS1 T5GCONbits.T5GSS1 // bit 1
11522 #define T5GVAL T5GCONbits.T5GVAL // bit 2
11523 #define T5GGO_NOT_DONE T5GCONbits.T5GGO_NOT_DONE // bit 3
11524 #define T5GSPM T5GCONbits.T5GSPM // bit 4
11525 #define T5GTM T5GCONbits.T5GTM // bit 5
11526 #define T5GPOL T5GCONbits.T5GPOL // bit 6
11527 #define TMR5GE T5GCONbits.TMR5GE // bit 7
11529 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
11530 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
11531 #define TMR6ON T6CONbits.TMR6ON // bit 2
11532 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
11533 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
11534 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
11535 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
11537 #define TMR08 TMR0Hbits.TMR08 // bit 0
11538 #define TMR09 TMR0Hbits.TMR09 // bit 1
11539 #define TMR010 TMR0Hbits.TMR010 // bit 2
11540 #define TMR011 TMR0Hbits.TMR011 // bit 3
11541 #define TMR012 TMR0Hbits.TMR012 // bit 4
11542 #define TMR013 TMR0Hbits.TMR013 // bit 5
11543 #define TMR014 TMR0Hbits.TMR014 // bit 6
11544 #define TMR015 TMR0Hbits.TMR015 // bit 7
11546 #define TMR00 TMR0Lbits.TMR00 // bit 0
11547 #define TMR01 TMR0Lbits.TMR01 // bit 1
11548 #define TMR02 TMR0Lbits.TMR02 // bit 2
11549 #define TMR03 TMR0Lbits.TMR03 // bit 3
11550 #define TMR04 TMR0Lbits.TMR04 // bit 4
11551 #define TMR05 TMR0Lbits.TMR05 // bit 5
11552 #define TMR06 TMR0Lbits.TMR06 // bit 6
11553 #define TMR07 TMR0Lbits.TMR07 // bit 7
11555 #define TRISA0 TRISAbits.TRISA0 // bit 0
11556 #define TRISA1 TRISAbits.TRISA1 // bit 1
11557 #define TRISA2 TRISAbits.TRISA2 // bit 2
11558 #define TRISA4 TRISAbits.TRISA4 // bit 4
11559 #define TRISA5 TRISAbits.TRISA5 // bit 5
11561 #define TRISB4 TRISBbits.TRISB4 // bit 4
11562 #define TRISB5 TRISBbits.TRISB5 // bit 5
11563 #define TRISB6 TRISBbits.TRISB6 // bit 6
11564 #define TRISB7 TRISBbits.TRISB7 // bit 7
11566 #define TRISC0 TRISCbits.TRISC0 // bit 0
11567 #define TRISC1 TRISCbits.TRISC1 // bit 1
11568 #define TRISC2 TRISCbits.TRISC2 // bit 2
11569 #define TRISC3 TRISCbits.TRISC3 // bit 3
11570 #define TRISC4 TRISCbits.TRISC4 // bit 4
11571 #define TRISC5 TRISCbits.TRISC5 // bit 5
11572 #define TRISC6 TRISCbits.TRISC6 // bit 6
11573 #define TRISC7 TRISCbits.TRISC7 // bit 7
11575 #define TX9D TX1STAbits.TX9D // bit 0
11576 #define TRMT TX1STAbits.TRMT // bit 1
11577 #define BRGH TX1STAbits.BRGH // bit 2
11578 #define SENDB TX1STAbits.SENDB // bit 3
11579 #define SYNC TX1STAbits.SYNC // bit 4
11580 #define TXEN TX1STAbits.TXEN // bit 5
11581 #define TX9 TX1STAbits.TX9 // bit 6
11582 #define CSRC TX1STAbits.CSRC // bit 7
11584 #define TXCKPPS0 TXPPSbits.TXCKPPS0 // bit 0
11585 #define TXCKPPS1 TXPPSbits.TXCKPPS1 // bit 1
11586 #define TXCKPPS2 TXPPSbits.TXCKPPS2 // bit 2
11587 #define TXCKPPS3 TXPPSbits.TXCKPPS3 // bit 3
11588 #define TXCKPPS4 TXPPSbits.TXCKPPS4 // bit 4
11590 #define SWDTEN WDTCONbits.SWDTEN // bit 0
11591 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
11592 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
11593 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
11594 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
11595 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
11597 #define WPUA0 WPUAbits.WPUA0 // bit 0
11598 #define WPUA1 WPUAbits.WPUA1 // bit 1
11599 #define WPUA2 WPUAbits.WPUA2 // bit 2
11600 #define WPUA3 WPUAbits.WPUA3 // bit 3
11601 #define WPUA4 WPUAbits.WPUA4 // bit 4
11602 #define WPUA5 WPUAbits.WPUA5 // bit 5
11604 #define WPUB4 WPUBbits.WPUB4 // bit 4
11605 #define WPUB5 WPUBbits.WPUB5 // bit 5
11606 #define WPUB6 WPUBbits.WPUB6 // bit 6
11607 #define WPUB7 WPUBbits.WPUB7 // bit 7
11609 #define WPUC0 WPUCbits.WPUC0 // bit 0
11610 #define WPUC1 WPUCbits.WPUC1 // bit 1
11611 #define WPUC2 WPUCbits.WPUC2 // bit 2
11612 #define WPUC3 WPUCbits.WPUC3 // bit 3
11613 #define WPUC4 WPUCbits.WPUC4 // bit 4
11614 #define WPUC5 WPUCbits.WPUC5 // bit 5
11615 #define WPUC6 WPUCbits.WPUC6 // bit 6
11616 #define WPUC7 WPUCbits.WPUC7 // bit 7
11618 #endif // #ifndef NO_BIT_DEFINES
11620 #endif // #ifndef __PIC16LF18344_H__