sdcc/device/non-free/lib/pic16/libdev/pic18f14k22.c

   1 /*
   2  * This definitions of the PIC18F14K22 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:26 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18f14k22.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F68) __sfr SRCON0;
  30 __at(0x0F68) volatile __SRCON0bits_t SRCON0bits;
  31
  32 __at(0x0F69) __sfr SRCON1;
  33 __at(0x0F69) volatile __SRCON1bits_t SRCON1bits;
  34
  35 __at(0x0F6B) __sfr CM2CON0;
  36 __at(0x0F6B) volatile __CM2CON0bits_t CM2CON0bits;
  37
  38 __at(0x0F6C) __sfr CM2CON1;
  39 __at(0x0F6C) volatile __CM2CON1bits_t CM2CON1bits;
  40
  41 __at(0x0F6D) __sfr CM1CON0;
  42 __at(0x0F6D) volatile __CM1CON0bits_t CM1CON0bits;
  43
  44 __at(0x0F6F) __sfr SSPMSK;
  45 __at(0x0F6F) volatile __SSPMSKbits_t SSPMSKbits;
  46
  47 __at(0x0F76) __sfr SLRCON;
  48 __at(0x0F76) volatile __SLRCONbits_t SLRCONbits;
  49
  50 __at(0x0F77) __sfr WPUA;
  51 __at(0x0F77) volatile __WPUAbits_t WPUAbits;
  52
  53 __at(0x0F78) __sfr WPUB;
  54 __at(0x0F78) volatile __WPUBbits_t WPUBbits;
  55
  56 __at(0x0F79) __sfr IOCA;
  57 __at(0x0F79) volatile __IOCAbits_t IOCAbits;
  58
  59 __at(0x0F7A) __sfr IOCB;
  60 __at(0x0F7A) volatile __IOCBbits_t IOCBbits;
  61
  62 __at(0x0F7E) __sfr ANSEL;
  63 __at(0x0F7E) volatile __ANSELbits_t ANSELbits;
  64
  65 __at(0x0F7F) __sfr ANSELH;
  66 __at(0x0F7F) volatile __ANSELHbits_t ANSELHbits;
  67
  68 __at(0x0F80) __sfr PORTA;
  69 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
  70
  71 __at(0x0F81) __sfr PORTB;
  72 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
  73
  74 __at(0x0F82) __sfr PORTC;
  75 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
  76
  77 __at(0x0F89) __sfr LATA;
  78 __at(0x0F89) volatile __LATAbits_t LATAbits;
  79
  80 __at(0x0F8A) __sfr LATB;
  81 __at(0x0F8A) volatile __LATBbits_t LATBbits;
  82
  83 __at(0x0F8B) __sfr LATC;
  84 __at(0x0F8B) volatile __LATCbits_t LATCbits;
  85
  86 __at(0x0F92) __sfr DDRA;
  87 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
  88
  89 __at(0x0F92) __sfr TRISA;
  90 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
  91
  92 __at(0x0F93) __sfr DDRB;
  93 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
  94
  95 __at(0x0F93) __sfr TRISB;
  96 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
  97
  98 __at(0x0F94) __sfr DDRC;
  99 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
 100
 101 __at(0x0F94) __sfr TRISC;
 102 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 103
 104 __at(0x0F9B) __sfr OSCTUNE;
 105 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 106
 107 __at(0x0F9D) __sfr PIE1;
 108 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 109
 110 __at(0x0F9E) __sfr PIR1;
 111 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 112
 113 __at(0x0F9F) __sfr IPR1;
 114 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 115
 116 __at(0x0FA0) __sfr PIE2;
 117 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 118
 119 __at(0x0FA1) __sfr PIR2;
 120 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 121
 122 __at(0x0FA2) __sfr IPR2;
 123 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 124
 125 __at(0x0FA6) __sfr EECON1;
 126 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 127
 128 __at(0x0FA7) __sfr EECON2;
 129
 130 __at(0x0FA8) __sfr EEDATA;
 131
 132 __at(0x0FA9) __sfr EEADR;
 133 __at(0x0FA9) volatile __EEADRbits_t EEADRbits;
 134
 135 __at(0x0FAB) __sfr RCSTA;
 136 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 137
 138 __at(0x0FAC) __sfr TXSTA;
 139 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 140
 141 __at(0x0FAD) __sfr TXREG;
 142
 143 __at(0x0FAE) __sfr RCREG;
 144
 145 __at(0x0FAF) __sfr SPBRG;
 146
 147 __at(0x0FB0) __sfr SPBRGH;
 148
 149 __at(0x0FB1) __sfr T3CON;
 150 __at(0x0FB1) volatile __T3CONbits_t T3CONbits;
 151
 152 __at(0x0FB2) __sfr TMR3;
 153
 154 __at(0x0FB2) __sfr TMR3L;
 155
 156 __at(0x0FB3) __sfr TMR3H;
 157
 158 __at(0x0FB6) __sfr ECCP1AS;
 159 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits;
 160
 161 __at(0x0FB7) __sfr PWM1CON;
 162 __at(0x0FB7) volatile __PWM1CONbits_t PWM1CONbits;
 163
 164 __at(0x0FB8) __sfr BAUDCON;
 165 __at(0x0FB8) volatile __BAUDCONbits_t BAUDCONbits;
 166
 167 __at(0x0FB8) __sfr BAUDCTL;
 168 __at(0x0FB8) volatile __BAUDCTLbits_t BAUDCTLbits;
 169
 170 __at(0x0FB9) __sfr PSTRCON;
 171 __at(0x0FB9) volatile __PSTRCONbits_t PSTRCONbits;
 172
 173 __at(0x0FBA) __sfr REFCON0;
 174 __at(0x0FBA) volatile __REFCON0bits_t REFCON0bits;
 175
 176 __at(0x0FBA) __sfr VREFCON0;
 177 __at(0x0FBA) volatile __VREFCON0bits_t VREFCON0bits;
 178
 179 __at(0x0FBB) __sfr REFCON1;
 180 __at(0x0FBB) volatile __REFCON1bits_t REFCON1bits;
 181
 182 __at(0x0FBB) __sfr VREFCON1;
 183 __at(0x0FBB) volatile __VREFCON1bits_t VREFCON1bits;
 184
 185 __at(0x0FBC) __sfr REFCON2;
 186 __at(0x0FBC) volatile __REFCON2bits_t REFCON2bits;
 187
 188 __at(0x0FBC) __sfr VREFCON2;
 189 __at(0x0FBC) volatile __VREFCON2bits_t VREFCON2bits;
 190
 191 __at(0x0FBD) __sfr CCP1CON;
 192 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits;
 193
 194 __at(0x0FBE) __sfr CCPR1;
 195
 196 __at(0x0FBE) __sfr CCPR1L;
 197
 198 __at(0x0FBF) __sfr CCPR1H;
 199
 200 __at(0x0FC0) __sfr ADCON2;
 201 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 202
 203 __at(0x0FC1) __sfr ADCON1;
 204 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 205
 206 __at(0x0FC2) __sfr ADCON0;
 207 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 208
 209 __at(0x0FC3) __sfr ADRES;
 210
 211 __at(0x0FC3) __sfr ADRESL;
 212
 213 __at(0x0FC4) __sfr ADRESH;
 214
 215 __at(0x0FC5) __sfr SSPCON2;
 216 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 217
 218 __at(0x0FC6) __sfr SSPCON1;
 219 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 220
 221 __at(0x0FC7) __sfr SSPSTAT;
 222 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 223
 224 __at(0x0FC8) __sfr SSPADD;
 225
 226 __at(0x0FC9) __sfr SSPBUF;
 227
 228 __at(0x0FCA) __sfr T2CON;
 229 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 230
 231 __at(0x0FCB) __sfr PR2;
 232
 233 __at(0x0FCC) __sfr TMR2;
 234
 235 __at(0x0FCD) __sfr T1CON;
 236 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 237
 238 __at(0x0FCE) __sfr TMR1;
 239
 240 __at(0x0FCE) __sfr TMR1L;
 241
 242 __at(0x0FCF) __sfr TMR1H;
 243
 244 __at(0x0FD0) __sfr RCON;
 245 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 246
 247 __at(0x0FD1) __sfr WDTCON;
 248 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 249
 250 __at(0x0FD2) __sfr OSCCON2;
 251 __at(0x0FD2) volatile __OSCCON2bits_t OSCCON2bits;
 252
 253 __at(0x0FD3) __sfr OSCCON;
 254 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 255
 256 __at(0x0FD5) __sfr T0CON;
 257 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 258
 259 __at(0x0FD6) __sfr TMR0;
 260
 261 __at(0x0FD6) __sfr TMR0L;
 262
 263 __at(0x0FD7) __sfr TMR0H;
 264
 265 __at(0x0FD8) __sfr STATUS;
 266 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 267
 268 __at(0x0FD9) __sfr FSR2L;
 269
 270 __at(0x0FDA) __sfr FSR2H;
 271
 272 __at(0x0FDB) __sfr PLUSW2;
 273
 274 __at(0x0FDC) __sfr PREINC2;
 275
 276 __at(0x0FDD) __sfr POSTDEC2;
 277
 278 __at(0x0FDE) __sfr POSTINC2;
 279
 280 __at(0x0FDF) __sfr INDF2;
 281
 282 __at(0x0FE0) __sfr BSR;
 283
 284 __at(0x0FE1) __sfr FSR1L;
 285
 286 __at(0x0FE2) __sfr FSR1H;
 287
 288 __at(0x0FE3) __sfr PLUSW1;
 289
 290 __at(0x0FE4) __sfr PREINC1;
 291
 292 __at(0x0FE5) __sfr POSTDEC1;
 293
 294 __at(0x0FE6) __sfr POSTINC1;
 295
 296 __at(0x0FE7) __sfr INDF1;
 297
 298 __at(0x0FE8) __sfr WREG;
 299
 300 __at(0x0FE9) __sfr FSR0L;
 301
 302 __at(0x0FEA) __sfr FSR0H;
 303
 304 __at(0x0FEB) __sfr PLUSW0;
 305
 306 __at(0x0FEC) __sfr PREINC0;
 307
 308 __at(0x0FED) __sfr POSTDEC0;
 309
 310 __at(0x0FEE) __sfr POSTINC0;
 311
 312 __at(0x0FEF) __sfr INDF0;
 313
 314 __at(0x0FF0) __sfr INTCON3;
 315 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 316
 317 __at(0x0FF1) __sfr INTCON2;
 318 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 319
 320 __at(0x0FF2) __sfr INTCON;
 321 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 322
 323 __at(0x0FF3) __sfr PROD;
 324
 325 __at(0x0FF3) __sfr PRODL;
 326
 327 __at(0x0FF4) __sfr PRODH;
 328
 329 __at(0x0FF5) __sfr TABLAT;
 330
 331 __at(0x0FF6) __sfr TBLPTR;
 332
 333 __at(0x0FF6) __sfr TBLPTRL;
 334
 335 __at(0x0FF7) __sfr TBLPTRH;
 336
 337 __at(0x0FF8) __sfr TBLPTRU;
 338
 339 __at(0x0FF9) __sfr PC;
 340
 341 __at(0x0FF9) __sfr PCL;
 342
 343 __at(0x0FFA) __sfr PCLATH;
 344
 345 __at(0x0FFB) __sfr PCLATU;
 346
 347 __at(0x0FFC) __sfr STKPTR;
 348 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 349
 350 __at(0x0FFD) __sfr TOS;
 351
 352 __at(0x0FFD) __sfr TOSL;
 353
 354 __at(0x0FFE) __sfr TOSH;
 355
 356 __at(0x0FFF) __sfr TOSU;