sdcc/device/non-free/lib/pic16/libdev/pic18f44j10.c

   1 /*
   2  * This definitions of the PIC18F44J10 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:29 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18f44j10.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F80) __sfr PORTA;
  30 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
  31
  32 __at(0x0F81) __sfr PORTB;
  33 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
  34
  35 __at(0x0F82) __sfr PORTC;
  36 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
  37
  38 __at(0x0F83) __sfr PORTD;
  39 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
  40
  41 __at(0x0F84) __sfr PORTE;
  42 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
  43
  44 __at(0x0F85) __sfr SSP2CON2;
  45 __at(0x0F85) volatile __SSP2CON2bits_t SSP2CON2bits;
  46
  47 __at(0x0F86) __sfr SSP2CON1;
  48 __at(0x0F86) volatile __SSP2CON1bits_t SSP2CON1bits;
  49
  50 __at(0x0F87) __sfr SSP2STAT;
  51 __at(0x0F87) volatile __SSP2STATbits_t SSP2STATbits;
  52
  53 __at(0x0F88) __sfr SSP2ADD;
  54
  55 __at(0x0F89) __sfr LATA;
  56 __at(0x0F89) volatile __LATAbits_t LATAbits;
  57
  58 __at(0x0F8A) __sfr LATB;
  59 __at(0x0F8A) volatile __LATBbits_t LATBbits;
  60
  61 __at(0x0F8B) __sfr LATC;
  62 __at(0x0F8B) volatile __LATCbits_t LATCbits;
  63
  64 __at(0x0F8C) __sfr LATD;
  65 __at(0x0F8C) volatile __LATDbits_t LATDbits;
  66
  67 __at(0x0F8D) __sfr LATE;
  68 __at(0x0F8D) volatile __LATEbits_t LATEbits;
  69
  70 __at(0x0F8E) __sfr SSP2BUF;
  71
  72 __at(0x0F92) __sfr DDRA;
  73 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
  74
  75 __at(0x0F92) __sfr TRISA;
  76 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
  77
  78 __at(0x0F93) __sfr DDRB;
  79 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
  80
  81 __at(0x0F93) __sfr TRISB;
  82 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
  83
  84 __at(0x0F94) __sfr DDRC;
  85 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
  86
  87 __at(0x0F94) __sfr TRISC;
  88 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
  89
  90 __at(0x0F95) __sfr DDRD;
  91 __at(0x0F95) volatile __DDRDbits_t DDRDbits;
  92
  93 __at(0x0F95) __sfr TRISD;
  94 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
  95
  96 __at(0x0F96) __sfr DDRE;
  97 __at(0x0F96) volatile __DDREbits_t DDREbits;
  98
  99 __at(0x0F96) __sfr TRISE;
 100 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 101
 102 __at(0x0F9B) __sfr OSCTUNE;
 103 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 104
 105 __at(0x0F9D) __sfr PIE1;
 106 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 107
 108 __at(0x0F9E) __sfr PIR1;
 109 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 110
 111 __at(0x0F9F) __sfr IPR1;
 112 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 113
 114 __at(0x0FA0) __sfr PIE2;
 115 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 116
 117 __at(0x0FA1) __sfr PIR2;
 118 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 119
 120 __at(0x0FA2) __sfr IPR2;
 121 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 122
 123 __at(0x0FA3) __sfr PIE3;
 124 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 125
 126 __at(0x0FA4) __sfr PIR3;
 127 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 128
 129 __at(0x0FA5) __sfr IPR3;
 130 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 131
 132 __at(0x0FA6) __sfr EECON1;
 133 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 134
 135 __at(0x0FA7) __sfr EECON2;
 136
 137 __at(0x0FAB) __sfr RCSTA;
 138 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 139
 140 __at(0x0FAB) __sfr RCSTA1;
 141 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits;
 142
 143 __at(0x0FAC) __sfr TXSTA;
 144 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 145
 146 __at(0x0FAC) __sfr TXSTA1;
 147 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits;
 148
 149 __at(0x0FAD) __sfr TXREG;
 150
 151 __at(0x0FAD) __sfr TXREG1;
 152
 153 __at(0x0FAE) __sfr RCREG;
 154
 155 __at(0x0FAE) __sfr RCREG1;
 156
 157 __at(0x0FAF) __sfr SPBRG;
 158
 159 __at(0x0FAF) __sfr SPBRG1;
 160
 161 __at(0x0FB0) __sfr SPBRGH;
 162
 163 __at(0x0FB4) __sfr CMCON;
 164 __at(0x0FB4) volatile __CMCONbits_t CMCONbits;
 165
 166 __at(0x0FB5) __sfr CVRCON;
 167 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits;
 168
 169 __at(0x0FB6) __sfr ECCP1AS;
 170 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits;
 171
 172 __at(0x0FB7) __sfr ECCP1DEL;
 173 __at(0x0FB7) volatile __ECCP1DELbits_t ECCP1DELbits;
 174
 175 __at(0x0FB7) __sfr PWM1CON;
 176 __at(0x0FB7) volatile __PWM1CONbits_t PWM1CONbits;
 177
 178 __at(0x0FB8) __sfr BAUDCON;
 179 __at(0x0FB8) volatile __BAUDCONbits_t BAUDCONbits;
 180
 181 __at(0x0FB8) __sfr BAUDCTL;
 182 __at(0x0FB8) volatile __BAUDCTLbits_t BAUDCTLbits;
 183
 184 __at(0x0FBA) __sfr CCP2CON;
 185 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits;
 186
 187 __at(0x0FBB) __sfr CCPR2;
 188
 189 __at(0x0FBB) __sfr CCPR2L;
 190
 191 __at(0x0FBC) __sfr CCPR2H;
 192
 193 __at(0x0FBD) __sfr CCP1CON;
 194 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits;
 195
 196 __at(0x0FBD) __sfr ECCP1CON;
 197 __at(0x0FBD) volatile __ECCP1CONbits_t ECCP1CONbits;
 198
 199 __at(0x0FBE) __sfr CCPR1;
 200
 201 __at(0x0FBE) __sfr CCPR1L;
 202
 203 __at(0x0FBF) __sfr CCPR1H;
 204
 205 __at(0x0FC0) __sfr ADCON2;
 206 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 207
 208 __at(0x0FC1) __sfr ADCON1;
 209 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 210
 211 __at(0x0FC2) __sfr ADCON0;
 212 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 213
 214 __at(0x0FC3) __sfr ADRES;
 215
 216 __at(0x0FC3) __sfr ADRESL;
 217
 218 __at(0x0FC4) __sfr ADRESH;
 219
 220 __at(0x0FC5) __sfr SSP1CON2;
 221 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits;
 222
 223 __at(0x0FC5) __sfr SSPCON2;
 224 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 225
 226 __at(0x0FC6) __sfr SSP1CON1;
 227 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits;
 228
 229 __at(0x0FC6) __sfr SSPCON1;
 230 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 231
 232 __at(0x0FC7) __sfr SSP1STAT;
 233 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits;
 234
 235 __at(0x0FC7) __sfr SSPSTAT;
 236 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 237
 238 __at(0x0FC8) __sfr SSP1ADD;
 239
 240 __at(0x0FC8) __sfr SSPADD;
 241
 242 __at(0x0FC9) __sfr SSP1BUF;
 243
 244 __at(0x0FC9) __sfr SSPBUF;
 245
 246 __at(0x0FCA) __sfr T2CON;
 247 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 248
 249 __at(0x0FCB) __sfr PR2;
 250
 251 __at(0x0FCC) __sfr TMR2;
 252
 253 __at(0x0FCD) __sfr T1CON;
 254 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 255
 256 __at(0x0FCE) __sfr TMR1;
 257
 258 __at(0x0FCE) __sfr TMR1L;
 259
 260 __at(0x0FCF) __sfr TMR1H;
 261
 262 __at(0x0FD0) __sfr RCON;
 263 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 264
 265 __at(0x0FD1) __sfr WDTCON;
 266 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 267
 268 __at(0x0FD3) __sfr OSCCON;
 269 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 270
 271 __at(0x0FD5) __sfr T0CON;
 272 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 273
 274 __at(0x0FD6) __sfr TMR0;
 275
 276 __at(0x0FD6) __sfr TMR0L;
 277
 278 __at(0x0FD7) __sfr TMR0H;
 279
 280 __at(0x0FD8) __sfr STATUS;
 281 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 282
 283 __at(0x0FD9) __sfr FSR2L;
 284
 285 __at(0x0FDA) __sfr FSR2H;
 286
 287 __at(0x0FDB) __sfr PLUSW2;
 288
 289 __at(0x0FDC) __sfr PREINC2;
 290
 291 __at(0x0FDD) __sfr POSTDEC2;
 292
 293 __at(0x0FDE) __sfr POSTINC2;
 294
 295 __at(0x0FDF) __sfr INDF2;
 296
 297 __at(0x0FE0) __sfr BSR;
 298
 299 __at(0x0FE1) __sfr FSR1L;
 300
 301 __at(0x0FE2) __sfr FSR1H;
 302
 303 __at(0x0FE3) __sfr PLUSW1;
 304
 305 __at(0x0FE4) __sfr PREINC1;
 306
 307 __at(0x0FE5) __sfr POSTDEC1;
 308
 309 __at(0x0FE6) __sfr POSTINC1;
 310
 311 __at(0x0FE7) __sfr INDF1;
 312
 313 __at(0x0FE8) __sfr WREG;
 314
 315 __at(0x0FE9) __sfr FSR0L;
 316
 317 __at(0x0FEA) __sfr FSR0H;
 318
 319 __at(0x0FEB) __sfr PLUSW0;
 320
 321 __at(0x0FEC) __sfr PREINC0;
 322
 323 __at(0x0FED) __sfr POSTDEC0;
 324
 325 __at(0x0FEE) __sfr POSTINC0;
 326
 327 __at(0x0FEF) __sfr INDF0;
 328
 329 __at(0x0FF0) __sfr INTCON3;
 330 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 331
 332 __at(0x0FF1) __sfr INTCON2;
 333 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 334
 335 __at(0x0FF2) __sfr INTCON;
 336 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 337
 338 __at(0x0FF3) __sfr PROD;
 339
 340 __at(0x0FF3) __sfr PRODL;
 341
 342 __at(0x0FF4) __sfr PRODH;
 343
 344 __at(0x0FF5) __sfr TABLAT;
 345
 346 __at(0x0FF6) __sfr TBLPTR;
 347
 348 __at(0x0FF6) __sfr TBLPTRL;
 349
 350 __at(0x0FF7) __sfr TBLPTRH;
 351
 352 __at(0x0FF8) __sfr TBLPTRU;
 353
 354 __at(0x0FF9) __sfr PC;
 355
 356 __at(0x0FF9) __sfr PCL;
 357
 358 __at(0x0FFA) __sfr PCLATH;
 359
 360 __at(0x0FFB) __sfr PCLATU;
 361
 362 __at(0x0FFC) __sfr STKPTR;
 363 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 364
 365 __at(0x0FFD) __sfr TOS;
 366
 367 __at(0x0FFD) __sfr TOSL;
 368
 369 __at(0x0FFE) __sfr TOSH;
 370
 371 __at(0x0FFF) __sfr TOSU;