sdcc/device/non-free/lib/pic16/libdev/pic18f45k50.c

   1 /*
   2  * This definitions of the PIC18F45K50 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:30 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18f45k50.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F57) __sfr SRCON1;
  30 __at(0x0F57) volatile __SRCON1bits_t SRCON1bits;
  31
  32 __at(0x0F58) __sfr SRCON0;
  33 __at(0x0F58) volatile __SRCON0bits_t SRCON0bits;
  34
  35 __at(0x0F59) __sfr CCPTMRS;
  36 __at(0x0F59) volatile __CCPTMRSbits_t CCPTMRSbits;
  37
  38 __at(0x0F5A) __sfr VREGCON;
  39
  40 __at(0x0F5B) __sfr ANSELA;
  41 __at(0x0F5B) volatile __ANSELAbits_t ANSELAbits;
  42
  43 __at(0x0F5C) __sfr ANSELB;
  44 __at(0x0F5C) volatile __ANSELBbits_t ANSELBbits;
  45
  46 __at(0x0F5D) __sfr ANSELC;
  47 __at(0x0F5D) volatile __ANSELCbits_t ANSELCbits;
  48
  49 __at(0x0F5E) __sfr ANSELD;
  50 __at(0x0F5E) volatile __ANSELDbits_t ANSELDbits;
  51
  52 __at(0x0F5F) __sfr ANSELE;
  53 __at(0x0F5F) volatile __ANSELEbits_t ANSELEbits;
  54
  55 __at(0x0F60) __sfr UCON;
  56 __at(0x0F60) volatile __UCONbits_t UCONbits;
  57
  58 __at(0x0F61) __sfr USTAT;
  59 __at(0x0F61) volatile __USTATbits_t USTATbits;
  60
  61 __at(0x0F62) __sfr UCFG;
  62 __at(0x0F62) volatile __UCFGbits_t UCFGbits;
  63
  64 __at(0x0F63) __sfr UADDR;
  65 __at(0x0F63) volatile __UADDRbits_t UADDRbits;
  66
  67 __at(0x0F64) __sfr UIE;
  68 __at(0x0F64) volatile __UIEbits_t UIEbits;
  69
  70 __at(0x0F65) __sfr UIR;
  71 __at(0x0F65) volatile __UIRbits_t UIRbits;
  72
  73 __at(0x0F66) __sfr UEIE;
  74 __at(0x0F66) volatile __UEIEbits_t UEIEbits;
  75
  76 __at(0x0F67) __sfr UEIR;
  77 __at(0x0F67) volatile __UEIRbits_t UEIRbits;
  78
  79 __at(0x0F68) __sfr UFRM;
  80
  81 __at(0x0F68) __sfr UFRML;
  82 __at(0x0F68) volatile __UFRMLbits_t UFRMLbits;
  83
  84 __at(0x0F69) __sfr UFRMH;
  85 __at(0x0F69) volatile __UFRMHbits_t UFRMHbits;
  86
  87 __at(0x0F6A) __sfr UEP0;
  88 __at(0x0F6A) volatile __UEP0bits_t UEP0bits;
  89
  90 __at(0x0F6B) __sfr UEP1;
  91 __at(0x0F6B) volatile __UEP1bits_t UEP1bits;
  92
  93 __at(0x0F6C) __sfr UEP2;
  94 __at(0x0F6C) volatile __UEP2bits_t UEP2bits;
  95
  96 __at(0x0F6D) __sfr UEP3;
  97 __at(0x0F6D) volatile __UEP3bits_t UEP3bits;
  98
  99 __at(0x0F6E) __sfr UEP4;
 100 __at(0x0F6E) volatile __UEP4bits_t UEP4bits;
 101
 102 __at(0x0F6F) __sfr UEP5;
 103 __at(0x0F6F) volatile __UEP5bits_t UEP5bits;
 104
 105 __at(0x0F70) __sfr UEP6;
 106 __at(0x0F70) volatile __UEP6bits_t UEP6bits;
 107
 108 __at(0x0F71) __sfr UEP7;
 109 __at(0x0F71) volatile __UEP7bits_t UEP7bits;
 110
 111 __at(0x0F72) __sfr UEP8;
 112 __at(0x0F72) volatile __UEP8bits_t UEP8bits;
 113
 114 __at(0x0F73) __sfr UEP9;
 115 __at(0x0F73) volatile __UEP9bits_t UEP9bits;
 116
 117 __at(0x0F74) __sfr UEP10;
 118 __at(0x0F74) volatile __UEP10bits_t UEP10bits;
 119
 120 __at(0x0F75) __sfr UEP11;
 121 __at(0x0F75) volatile __UEP11bits_t UEP11bits;
 122
 123 __at(0x0F76) __sfr UEP12;
 124 __at(0x0F76) volatile __UEP12bits_t UEP12bits;
 125
 126 __at(0x0F77) __sfr UEP13;
 127 __at(0x0F77) volatile __UEP13bits_t UEP13bits;
 128
 129 __at(0x0F78) __sfr UEP14;
 130 __at(0x0F78) volatile __UEP14bits_t UEP14bits;
 131
 132 __at(0x0F79) __sfr UEP15;
 133 __at(0x0F79) volatile __UEP15bits_t UEP15bits;
 134
 135 __at(0x0F7A) __sfr SLRCON;
 136 __at(0x0F7A) volatile __SLRCONbits_t SLRCONbits;
 137
 138 __at(0x0F7B) __sfr VREFCON2;
 139 __at(0x0F7B) volatile __VREFCON2bits_t VREFCON2bits;
 140
 141 __at(0x0F7C) __sfr VREFCON1;
 142 __at(0x0F7C) volatile __VREFCON1bits_t VREFCON1bits;
 143
 144 __at(0x0F7D) __sfr VREFCON0;
 145 __at(0x0F7D) volatile __VREFCON0bits_t VREFCON0bits;
 146
 147 __at(0x0F7E) __sfr PMD0;
 148 __at(0x0F7E) volatile __PMD0bits_t PMD0bits;
 149
 150 __at(0x0F7F) __sfr PMD1;
 151 __at(0x0F7F) volatile __PMD1bits_t PMD1bits;
 152
 153 __at(0x0F80) __sfr PORTA;
 154 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
 155
 156 __at(0x0F81) __sfr PORTB;
 157 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
 158
 159 __at(0x0F82) __sfr PORTC;
 160 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
 161
 162 __at(0x0F83) __sfr PORTD;
 163 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
 164
 165 __at(0x0F84) __sfr PORTE;
 166 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
 167
 168 __at(0x0F85) __sfr WPUB;
 169 __at(0x0F85) volatile __WPUBbits_t WPUBbits;
 170
 171 __at(0x0F86) __sfr IOCB;
 172 __at(0x0F86) volatile __IOCBbits_t IOCBbits;
 173
 174 __at(0x0F87) __sfr IOCC;
 175 __at(0x0F87) volatile __IOCCbits_t IOCCbits;
 176
 177 __at(0x0F88) __sfr CTMUICON;
 178 __at(0x0F88) volatile __CTMUICONbits_t CTMUICONbits;
 179
 180 __at(0x0F89) __sfr LATA;
 181 __at(0x0F89) volatile __LATAbits_t LATAbits;
 182
 183 __at(0x0F8A) __sfr LATB;
 184 __at(0x0F8A) volatile __LATBbits_t LATBbits;
 185
 186 __at(0x0F8B) __sfr LATC;
 187 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 188
 189 __at(0x0F8C) __sfr LATD;
 190 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 191
 192 __at(0x0F8D) __sfr LATE;
 193 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 194
 195 __at(0x0F8E) __sfr CTMUCON1;
 196 __at(0x0F8E) volatile __CTMUCON1bits_t CTMUCON1bits;
 197
 198 __at(0x0F8E) __sfr CTMUCONL;
 199 __at(0x0F8E) volatile __CTMUCONLbits_t CTMUCONLbits;
 200
 201 __at(0x0F8F) __sfr CTMUCON0;
 202 __at(0x0F8F) volatile __CTMUCON0bits_t CTMUCON0bits;
 203
 204 __at(0x0F8F) __sfr CTMUCONH;
 205 __at(0x0F8F) volatile __CTMUCONHbits_t CTMUCONHbits;
 206
 207 __at(0x0F90) __sfr CCPR2;
 208
 209 __at(0x0F90) __sfr CCPR2L;
 210
 211 __at(0x0F91) __sfr CCPR2H;
 212
 213 __at(0x0F92) __sfr DDRA;
 214 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
 215
 216 __at(0x0F92) __sfr TRISA;
 217 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 218
 219 __at(0x0F93) __sfr DDRB;
 220 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
 221
 222 __at(0x0F93) __sfr TRISB;
 223 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 224
 225 __at(0x0F94) __sfr DDRC;
 226 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
 227
 228 __at(0x0F94) __sfr TRISC;
 229 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 230
 231 __at(0x0F95) __sfr DDRD;
 232 __at(0x0F95) volatile __DDRDbits_t DDRDbits;
 233
 234 __at(0x0F95) __sfr TRISD;
 235 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 236
 237 __at(0x0F96) __sfr DDRE;
 238 __at(0x0F96) volatile __DDREbits_t DDREbits;
 239
 240 __at(0x0F96) __sfr TRISE;
 241 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 242
 243 __at(0x0F97) __sfr CCP2CON;
 244 __at(0x0F97) volatile __CCP2CONbits_t CCP2CONbits;
 245
 246 __at(0x0F97) __sfr ECCP2CON;
 247 __at(0x0F97) volatile __ECCP2CONbits_t ECCP2CONbits;
 248
 249 __at(0x0F98) __sfr CM1CON0;
 250 __at(0x0F98) volatile __CM1CON0bits_t CM1CON0bits;
 251
 252 __at(0x0F99) __sfr CM2CON0;
 253 __at(0x0F99) volatile __CM2CON0bits_t CM2CON0bits;
 254
 255 __at(0x0F9A) __sfr CM2CON1;
 256 __at(0x0F9A) volatile __CM2CON1bits_t CM2CON1bits;
 257
 258 __at(0x0F9B) __sfr OSCTUNE;
 259 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 260
 261 __at(0x0F9C) __sfr HLVDCON;
 262 __at(0x0F9C) volatile __HLVDCONbits_t HLVDCONbits;
 263
 264 __at(0x0F9D) __sfr PIE1;
 265 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 266
 267 __at(0x0F9E) __sfr PIR1;
 268 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 269
 270 __at(0x0F9F) __sfr IPR1;
 271 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 272
 273 __at(0x0FA0) __sfr PIE2;
 274 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 275
 276 __at(0x0FA1) __sfr PIR2;
 277 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 278
 279 __at(0x0FA2) __sfr IPR2;
 280 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 281
 282 __at(0x0FA3) __sfr PIE3;
 283 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 284
 285 __at(0x0FA4) __sfr PIR3;
 286 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 287
 288 __at(0x0FA5) __sfr IPR3;
 289 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 290
 291 __at(0x0FA6) __sfr EECON1;
 292 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 293
 294 __at(0x0FA7) __sfr EECON2;
 295
 296 __at(0x0FA8) __sfr EEDATA;
 297
 298 __at(0x0FA9) __sfr EEADR;
 299
 300 __at(0x0FAB) __sfr RCSTA;
 301 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 302
 303 __at(0x0FAB) __sfr RCSTA1;
 304 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits;
 305
 306 __at(0x0FAC) __sfr TXSTA;
 307 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 308
 309 __at(0x0FAC) __sfr TXSTA1;
 310 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits;
 311
 312 __at(0x0FAD) __sfr TXREG;
 313
 314 __at(0x0FAD) __sfr TXREG1;
 315
 316 __at(0x0FAE) __sfr RCREG;
 317
 318 __at(0x0FAE) __sfr RCREG1;
 319
 320 __at(0x0FAF) __sfr SPBRG;
 321 __at(0x0FAF) volatile __SPBRGbits_t SPBRGbits;
 322
 323 __at(0x0FAF) __sfr SPBRG1;
 324 __at(0x0FAF) volatile __SPBRG1bits_t SPBRG1bits;
 325
 326 __at(0x0FB0) __sfr SPBRGH;
 327 __at(0x0FB0) volatile __SPBRGHbits_t SPBRGHbits;
 328
 329 __at(0x0FB0) __sfr SPBRGH1;
 330 __at(0x0FB0) volatile __SPBRGH1bits_t SPBRGH1bits;
 331
 332 __at(0x0FB1) __sfr T3CON;
 333 __at(0x0FB1) volatile __T3CONbits_t T3CONbits;
 334
 335 __at(0x0FB2) __sfr TMR3;
 336
 337 __at(0x0FB2) __sfr TMR3L;
 338
 339 __at(0x0FB3) __sfr TMR3H;
 340
 341 __at(0x0FB4) __sfr T3GCON;
 342 __at(0x0FB4) volatile __T3GCONbits_t T3GCONbits;
 343
 344 __at(0x0FB5) __sfr ACTCON;
 345 __at(0x0FB5) volatile __ACTCONbits_t ACTCONbits;
 346
 347 __at(0x0FB5) __sfr STCON;
 348 __at(0x0FB5) volatile __STCONbits_t STCONbits;
 349
 350 __at(0x0FB6) __sfr ECCP1AS;
 351 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits;
 352
 353 __at(0x0FB7) __sfr ECCP1DEL;
 354 __at(0x0FB7) volatile __ECCP1DELbits_t ECCP1DELbits;
 355
 356 __at(0x0FB7) __sfr PWM1CON;
 357 __at(0x0FB7) volatile __PWM1CONbits_t PWM1CONbits;
 358
 359 __at(0x0FB8) __sfr BAUDCON;
 360 __at(0x0FB8) volatile __BAUDCONbits_t BAUDCONbits;
 361
 362 __at(0x0FB8) __sfr BAUDCON1;
 363 __at(0x0FB8) volatile __BAUDCON1bits_t BAUDCON1bits;
 364
 365 __at(0x0FB9) __sfr PSTR1CON;
 366 __at(0x0FB9) volatile __PSTR1CONbits_t PSTR1CONbits;
 367
 368 __at(0x0FBA) __sfr T2CON;
 369 __at(0x0FBA) volatile __T2CONbits_t T2CONbits;
 370
 371 __at(0x0FBB) __sfr PR2;
 372
 373 __at(0x0FBC) __sfr TMR2;
 374
 375 __at(0x0FBD) __sfr CCP1CON;
 376 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits;
 377
 378 __at(0x0FBD) __sfr ECCP1CON;
 379 __at(0x0FBD) volatile __ECCP1CONbits_t ECCP1CONbits;
 380
 381 __at(0x0FBE) __sfr CCPR1;
 382
 383 __at(0x0FBE) __sfr CCPR1L;
 384
 385 __at(0x0FBF) __sfr CCPR1H;
 386
 387 __at(0x0FC0) __sfr ADCON2;
 388 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 389
 390 __at(0x0FC1) __sfr ADCON1;
 391 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 392
 393 __at(0x0FC2) __sfr ADCON0;
 394 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 395
 396 __at(0x0FC3) __sfr ADRESL;
 397
 398 __at(0x0FC4) __sfr ADRESH;
 399
 400 __at(0x0FC5) __sfr SSP1CON2;
 401 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits;
 402
 403 __at(0x0FC5) __sfr SSPCON2;
 404 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 405
 406 __at(0x0FC6) __sfr SSP1CON1;
 407 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits;
 408
 409 __at(0x0FC6) __sfr SSPCON;
 410 __at(0x0FC6) volatile __SSPCONbits_t SSPCONbits;
 411
 412 __at(0x0FC6) __sfr SSPCON1;
 413 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 414
 415 __at(0x0FC7) __sfr SSP1STAT;
 416 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits;
 417
 418 __at(0x0FC7) __sfr SSPSTAT;
 419 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 420
 421 __at(0x0FC8) __sfr SSP1ADD;
 422 __at(0x0FC8) volatile __SSP1ADDbits_t SSP1ADDbits;
 423
 424 __at(0x0FC8) __sfr SSPADD;
 425 __at(0x0FC8) volatile __SSPADDbits_t SSPADDbits;
 426
 427 __at(0x0FC9) __sfr SSP1BUF;
 428
 429 __at(0x0FC9) __sfr SSPBUF;
 430
 431 __at(0x0FCA) __sfr SSP1MSK;
 432 __at(0x0FCA) volatile __SSP1MSKbits_t SSP1MSKbits;
 433
 434 __at(0x0FCA) __sfr SSPMSK;
 435 __at(0x0FCA) volatile __SSPMSKbits_t SSPMSKbits;
 436
 437 __at(0x0FCB) __sfr SSP1CON3;
 438 __at(0x0FCB) volatile __SSP1CON3bits_t SSP1CON3bits;
 439
 440 __at(0x0FCB) __sfr SSPCON3;
 441 __at(0x0FCB) volatile __SSPCON3bits_t SSPCON3bits;
 442
 443 __at(0x0FCC) __sfr T1GCON;
 444 __at(0x0FCC) volatile __T1GCONbits_t T1GCONbits;
 445
 446 __at(0x0FCD) __sfr T1CON;
 447 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 448
 449 __at(0x0FCE) __sfr TMR1;
 450
 451 __at(0x0FCE) __sfr TMR1L;
 452
 453 __at(0x0FCF) __sfr TMR1H;
 454
 455 __at(0x0FD0) __sfr RCON;
 456 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 457
 458 __at(0x0FD1) __sfr WDTCON;
 459 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 460
 461 __at(0x0FD2) __sfr OSCCON2;
 462 __at(0x0FD2) volatile __OSCCON2bits_t OSCCON2bits;
 463
 464 __at(0x0FD3) __sfr OSCCON;
 465 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 466
 467 __at(0x0FD5) __sfr T0CON;
 468 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 469
 470 __at(0x0FD6) __sfr TMR0;
 471
 472 __at(0x0FD6) __sfr TMR0L;
 473
 474 __at(0x0FD7) __sfr TMR0H;
 475
 476 __at(0x0FD8) __sfr STATUS;
 477 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 478
 479 __at(0x0FD9) __sfr FSR2L;
 480
 481 __at(0x0FDA) __sfr FSR2H;
 482
 483 __at(0x0FDB) __sfr PLUSW2;
 484
 485 __at(0x0FDC) __sfr PREINC2;
 486
 487 __at(0x0FDD) __sfr POSTDEC2;
 488
 489 __at(0x0FDE) __sfr POSTINC2;
 490
 491 __at(0x0FDF) __sfr INDF2;
 492
 493 __at(0x0FE0) __sfr BSR;
 494
 495 __at(0x0FE1) __sfr FSR1L;
 496
 497 __at(0x0FE2) __sfr FSR1H;
 498
 499 __at(0x0FE3) __sfr PLUSW1;
 500
 501 __at(0x0FE4) __sfr PREINC1;
 502
 503 __at(0x0FE5) __sfr POSTDEC1;
 504
 505 __at(0x0FE6) __sfr POSTINC1;
 506
 507 __at(0x0FE7) __sfr INDF1;
 508
 509 __at(0x0FE8) __sfr WREG;
 510
 511 __at(0x0FE9) __sfr FSR0L;
 512
 513 __at(0x0FEA) __sfr FSR0H;
 514
 515 __at(0x0FEB) __sfr PLUSW0;
 516
 517 __at(0x0FEC) __sfr PREINC0;
 518
 519 __at(0x0FED) __sfr POSTDEC0;
 520
 521 __at(0x0FEE) __sfr POSTINC0;
 522
 523 __at(0x0FEF) __sfr INDF0;
 524
 525 __at(0x0FF0) __sfr INTCON3;
 526 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 527
 528 __at(0x0FF1) __sfr INTCON2;
 529 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 530
 531 __at(0x0FF2) __sfr INTCON;
 532 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 533
 534 __at(0x0FF3) __sfr PROD;
 535
 536 __at(0x0FF3) __sfr PRODL;
 537
 538 __at(0x0FF4) __sfr PRODH;
 539
 540 __at(0x0FF5) __sfr TABLAT;
 541
 542 __at(0x0FF6) __sfr TBLPTR;
 543
 544 __at(0x0FF6) __sfr TBLPTRL;
 545
 546 __at(0x0FF7) __sfr TBLPTRH;
 547
 548 __at(0x0FF8) __sfr TBLPTRU;
 549
 550 __at(0x0FF9) __sfr PC;
 551
 552 __at(0x0FF9) __sfr PCL;
 553
 554 __at(0x0FFA) __sfr PCLATH;
 555
 556 __at(0x0FFB) __sfr PCLATU;
 557
 558 __at(0x0FFC) __sfr STKPTR;
 559 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 560
 561 __at(0x0FFD) __sfr TOS;
 562
 563 __at(0x0FFD) __sfr TOSL;
 564
 565 __at(0x0FFE) __sfr TOSH;
 566
 567 __at(0x0FFF) __sfr TOSU;