sdcc/device/non-free/lib/pic16/libdev/pic18f46j50.c

   1 /*
   2  * This definitions of the PIC18F46J50 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:30 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18f46j50.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0EC6) __sfr RPOR0;
  30
  31 __at(0x0EC7) __sfr RPOR1;
  32
  33 __at(0x0EC8) __sfr RPOR2;
  34
  35 __at(0x0EC9) __sfr RPOR3;
  36
  37 __at(0x0ECA) __sfr RPOR4;
  38
  39 __at(0x0ECB) __sfr RPOR5;
  40
  41 __at(0x0ECC) __sfr RPOR6;
  42
  43 __at(0x0ECD) __sfr RPOR7;
  44
  45 __at(0x0ECE) __sfr RPOR8;
  46
  47 __at(0x0ECF) __sfr RPOR9;
  48
  49 __at(0x0ED0) __sfr RPOR10;
  50
  51 __at(0x0ED1) __sfr RPOR11;
  52
  53 __at(0x0ED2) __sfr RPOR12;
  54
  55 __at(0x0ED3) __sfr RPOR13;
  56
  57 __at(0x0ED7) __sfr RPOR17;
  58
  59 __at(0x0ED8) __sfr RPOR18;
  60
  61 __at(0x0ED9) __sfr RPOR19;
  62
  63 __at(0x0EDA) __sfr RPOR20;
  64
  65 __at(0x0EDB) __sfr RPOR21;
  66
  67 __at(0x0EDC) __sfr RPOR22;
  68
  69 __at(0x0EDD) __sfr RPOR23;
  70
  71 __at(0x0EDE) __sfr RPOR24;
  72
  73 __at(0x0EE7) __sfr RPINR1;
  74
  75 __at(0x0EE8) __sfr RPINR2;
  76
  77 __at(0x0EE9) __sfr RPINR3;
  78
  79 __at(0x0EEA) __sfr RPINR4;
  80
  81 __at(0x0EEC) __sfr RPINR6;
  82
  83 __at(0x0EED) __sfr RPINR7;
  84
  85 __at(0x0EEE) __sfr RPINR8;
  86
  87 __at(0x0EF2) __sfr RPINR12;
  88
  89 __at(0x0EF3) __sfr RPINR13;
  90
  91 __at(0x0EF6) __sfr RPINR16;
  92
  93 __at(0x0EF7) __sfr RPINR17;
  94
  95 __at(0x0EFB) __sfr RPINR21;
  96
  97 __at(0x0EFC) __sfr RPINR22;
  98
  99 __at(0x0EFD) __sfr RPINR23;
 100
 101 __at(0x0EFE) __sfr RPINR24;
 102
 103 __at(0x0EFF) __sfr PPSCON;
 104 __at(0x0EFF) volatile __PPSCONbits_t PPSCONbits;
 105
 106 __at(0x0F26) __sfr UEP0;
 107 __at(0x0F26) volatile __UEP0bits_t UEP0bits;
 108
 109 __at(0x0F27) __sfr UEP1;
 110 __at(0x0F27) volatile __UEP1bits_t UEP1bits;
 111
 112 __at(0x0F28) __sfr UEP2;
 113 __at(0x0F28) volatile __UEP2bits_t UEP2bits;
 114
 115 __at(0x0F29) __sfr UEP3;
 116 __at(0x0F29) volatile __UEP3bits_t UEP3bits;
 117
 118 __at(0x0F2A) __sfr UEP4;
 119 __at(0x0F2A) volatile __UEP4bits_t UEP4bits;
 120
 121 __at(0x0F2B) __sfr UEP5;
 122 __at(0x0F2B) volatile __UEP5bits_t UEP5bits;
 123
 124 __at(0x0F2C) __sfr UEP6;
 125 __at(0x0F2C) volatile __UEP6bits_t UEP6bits;
 126
 127 __at(0x0F2D) __sfr UEP7;
 128 __at(0x0F2D) volatile __UEP7bits_t UEP7bits;
 129
 130 __at(0x0F2E) __sfr UEP8;
 131 __at(0x0F2E) volatile __UEP8bits_t UEP8bits;
 132
 133 __at(0x0F2F) __sfr UEP9;
 134 __at(0x0F2F) volatile __UEP9bits_t UEP9bits;
 135
 136 __at(0x0F30) __sfr UEP10;
 137 __at(0x0F30) volatile __UEP10bits_t UEP10bits;
 138
 139 __at(0x0F31) __sfr UEP11;
 140 __at(0x0F31) volatile __UEP11bits_t UEP11bits;
 141
 142 __at(0x0F32) __sfr UEP12;
 143 __at(0x0F32) volatile __UEP12bits_t UEP12bits;
 144
 145 __at(0x0F33) __sfr UEP13;
 146 __at(0x0F33) volatile __UEP13bits_t UEP13bits;
 147
 148 __at(0x0F34) __sfr UEP14;
 149 __at(0x0F34) volatile __UEP14bits_t UEP14bits;
 150
 151 __at(0x0F35) __sfr UEP15;
 152 __at(0x0F35) volatile __UEP15bits_t UEP15bits;
 153
 154 __at(0x0F36) __sfr UIE;
 155 __at(0x0F36) volatile __UIEbits_t UIEbits;
 156
 157 __at(0x0F37) __sfr UEIE;
 158 __at(0x0F37) volatile __UEIEbits_t UEIEbits;
 159
 160 __at(0x0F38) __sfr UADDR;
 161 __at(0x0F38) volatile __UADDRbits_t UADDRbits;
 162
 163 __at(0x0F39) __sfr UCFG;
 164 __at(0x0F39) volatile __UCFGbits_t UCFGbits;
 165
 166 __at(0x0F3C) __sfr PADCFG1;
 167 __at(0x0F3C) volatile __PADCFG1bits_t PADCFG1bits;
 168
 169 __at(0x0F3D) __sfr REFOCON;
 170 __at(0x0F3D) volatile __REFOCONbits_t REFOCONbits;
 171
 172 __at(0x0F3E) __sfr RTCCAL;
 173 __at(0x0F3E) volatile __RTCCALbits_t RTCCALbits;
 174
 175 __at(0x0F3F) __sfr RTCCFG;
 176 __at(0x0F3F) volatile __RTCCFGbits_t RTCCFGbits;
 177
 178 __at(0x0F40) __sfr ODCON3;
 179 __at(0x0F40) volatile __ODCON3bits_t ODCON3bits;
 180
 181 __at(0x0F41) __sfr ODCON2;
 182 __at(0x0F41) volatile __ODCON2bits_t ODCON2bits;
 183
 184 __at(0x0F42) __sfr ODCON1;
 185 __at(0x0F42) volatile __ODCON1bits_t ODCON1bits;
 186
 187 __at(0x0F48) __sfr ANCON0;
 188 __at(0x0F48) volatile __ANCON0bits_t ANCON0bits;
 189
 190 __at(0x0F49) __sfr ANCON1;
 191 __at(0x0F49) volatile __ANCON1bits_t ANCON1bits;
 192
 193 __at(0x0F4A) __sfr DSWAKEL;
 194 __at(0x0F4A) volatile __DSWAKELbits_t DSWAKELbits;
 195
 196 __at(0x0F4B) __sfr DSWAKEH;
 197 __at(0x0F4B) volatile __DSWAKEHbits_t DSWAKEHbits;
 198
 199 __at(0x0F4C) __sfr DSCONL;
 200 __at(0x0F4C) volatile __DSCONLbits_t DSCONLbits;
 201
 202 __at(0x0F4D) __sfr DSCONH;
 203 __at(0x0F4D) volatile __DSCONHbits_t DSCONHbits;
 204
 205 __at(0x0F4E) __sfr DSGPR0;
 206
 207 __at(0x0F4F) __sfr DSGPR1;
 208
 209 __at(0x0F52) __sfr TCLKCON;
 210 __at(0x0F52) volatile __TCLKCONbits_t TCLKCONbits;
 211
 212 __at(0x0F53) __sfr CVRCON;
 213 __at(0x0F53) volatile __CVRCONbits_t CVRCONbits;
 214
 215 __at(0x0F54) __sfr PMSTATL;
 216 __at(0x0F54) volatile __PMSTATLbits_t PMSTATLbits;
 217
 218 __at(0x0F55) __sfr PMSTATH;
 219 __at(0x0F55) volatile __PMSTATHbits_t PMSTATHbits;
 220
 221 __at(0x0F56) __sfr PMEL;
 222 __at(0x0F56) volatile __PMELbits_t PMELbits;
 223
 224 __at(0x0F57) __sfr PMEH;
 225 __at(0x0F57) volatile __PMEHbits_t PMEHbits;
 226
 227 __at(0x0F58) __sfr PMDIN2L;
 228
 229 __at(0x0F59) __sfr PMDIN2H;
 230
 231 __at(0x0F5A) __sfr PMDOUT2L;
 232
 233 __at(0x0F5B) __sfr PMDOUT2H;
 234
 235 __at(0x0F5C) __sfr PMMODEL;
 236 __at(0x0F5C) volatile __PMMODELbits_t PMMODELbits;
 237
 238 __at(0x0F5D) __sfr PMMODEH;
 239 __at(0x0F5D) volatile __PMMODEHbits_t PMMODEHbits;
 240
 241 __at(0x0F5E) __sfr PMCONL;
 242 __at(0x0F5E) volatile __PMCONLbits_t PMCONLbits;
 243
 244 __at(0x0F5F) __sfr PMCONH;
 245 __at(0x0F5F) volatile __PMCONHbits_t PMCONHbits;
 246
 247 __at(0x0F60) __sfr UFRM;
 248
 249 __at(0x0F60) __sfr UFRML;
 250 __at(0x0F60) volatile __UFRMLbits_t UFRMLbits;
 251
 252 __at(0x0F61) __sfr UFRMH;
 253 __at(0x0F61) volatile __UFRMHbits_t UFRMHbits;
 254
 255 __at(0x0F62) __sfr UIR;
 256 __at(0x0F62) volatile __UIRbits_t UIRbits;
 257
 258 __at(0x0F63) __sfr UEIR;
 259 __at(0x0F63) volatile __UEIRbits_t UEIRbits;
 260
 261 __at(0x0F64) __sfr USTAT;
 262 __at(0x0F64) volatile __USTATbits_t USTATbits;
 263
 264 __at(0x0F65) __sfr UCON;
 265 __at(0x0F65) volatile __UCONbits_t UCONbits;
 266
 267 __at(0x0F66) __sfr DMABCH;
 268
 269 __at(0x0F67) __sfr DMABCL;
 270
 271 __at(0x0F68) __sfr RXADDRH;
 272
 273 __at(0x0F69) __sfr RXADDRL;
 274
 275 __at(0x0F6A) __sfr TXADDRH;
 276
 277 __at(0x0F6B) __sfr TXADDRL;
 278
 279 __at(0x0F6C) __sfr PMDIN1L;
 280
 281 __at(0x0F6D) __sfr PMDIN1H;
 282
 283 __at(0x0F6E) __sfr PMADDRL;
 284
 285 __at(0x0F6E) __sfr PMDOUT1L;
 286
 287 __at(0x0F6F) __sfr PMADDRH;
 288 __at(0x0F6F) volatile __PMADDRHbits_t PMADDRHbits;
 289
 290 __at(0x0F6F) __sfr PMDOUT1H;
 291
 292 __at(0x0F70) __sfr CMSTAT;
 293 __at(0x0F70) volatile __CMSTATbits_t CMSTATbits;
 294
 295 __at(0x0F70) __sfr CMSTATUS;
 296 __at(0x0F70) volatile __CMSTATUSbits_t CMSTATUSbits;
 297
 298 __at(0x0F71) __sfr SSP2CON2;
 299 __at(0x0F71) volatile __SSP2CON2bits_t SSP2CON2bits;
 300
 301 __at(0x0F72) __sfr SSP2CON1;
 302 __at(0x0F72) volatile __SSP2CON1bits_t SSP2CON1bits;
 303
 304 __at(0x0F73) __sfr SSP2STAT;
 305 __at(0x0F73) volatile __SSP2STATbits_t SSP2STATbits;
 306
 307 __at(0x0F74) __sfr SSP2ADD;
 308 __at(0x0F74) volatile __SSP2ADDbits_t SSP2ADDbits;
 309
 310 __at(0x0F74) __sfr SSP2MSK;
 311 __at(0x0F74) volatile __SSP2MSKbits_t SSP2MSKbits;
 312
 313 __at(0x0F75) __sfr SSP2BUF;
 314
 315 __at(0x0F76) __sfr T4CON;
 316 __at(0x0F76) volatile __T4CONbits_t T4CONbits;
 317
 318 __at(0x0F77) __sfr PR4;
 319
 320 __at(0x0F78) __sfr TMR4;
 321
 322 __at(0x0F79) __sfr T3CON;
 323 __at(0x0F79) volatile __T3CONbits_t T3CONbits;
 324
 325 __at(0x0F7A) __sfr TMR3;
 326
 327 __at(0x0F7A) __sfr TMR3L;
 328
 329 __at(0x0F7B) __sfr TMR3H;
 330
 331 __at(0x0F7C) __sfr BAUDCON2;
 332 __at(0x0F7C) volatile __BAUDCON2bits_t BAUDCON2bits;
 333
 334 __at(0x0F7D) __sfr SPBRGH2;
 335
 336 __at(0x0F7E) __sfr BAUDCON;
 337 __at(0x0F7E) volatile __BAUDCONbits_t BAUDCONbits;
 338
 339 __at(0x0F7E) __sfr BAUDCON1;
 340 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits;
 341
 342 __at(0x0F7E) __sfr BAUDCTL;
 343 __at(0x0F7E) volatile __BAUDCTLbits_t BAUDCTLbits;
 344
 345 __at(0x0F7F) __sfr SPBRGH;
 346
 347 __at(0x0F7F) __sfr SPBRGH1;
 348
 349 __at(0x0F80) __sfr PORTA;
 350 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
 351
 352 __at(0x0F81) __sfr PORTB;
 353 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
 354
 355 __at(0x0F82) __sfr PORTC;
 356 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
 357
 358 __at(0x0F83) __sfr PORTD;
 359 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
 360
 361 __at(0x0F84) __sfr PORTE;
 362 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
 363
 364 __at(0x0F85) __sfr HLVDCON;
 365 __at(0x0F85) volatile __HLVDCONbits_t HLVDCONbits;
 366
 367 __at(0x0F86) __sfr DMACON2;
 368 __at(0x0F86) volatile __DMACON2bits_t DMACON2bits;
 369
 370 __at(0x0F88) __sfr DMACON1;
 371 __at(0x0F88) volatile __DMACON1bits_t DMACON1bits;
 372
 373 __at(0x0F89) __sfr LATA;
 374 __at(0x0F89) volatile __LATAbits_t LATAbits;
 375
 376 __at(0x0F8A) __sfr LATB;
 377 __at(0x0F8A) volatile __LATBbits_t LATBbits;
 378
 379 __at(0x0F8B) __sfr LATC;
 380 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 381
 382 __at(0x0F8C) __sfr LATD;
 383 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 384
 385 __at(0x0F8D) __sfr LATE;
 386 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 387
 388 __at(0x0F8E) __sfr ALRMVALL;
 389
 390 __at(0x0F8F) __sfr ALRMVALH;
 391
 392 __at(0x0F90) __sfr ALRMRPT;
 393 __at(0x0F90) volatile __ALRMRPTbits_t ALRMRPTbits;
 394
 395 __at(0x0F91) __sfr ALRMCFG;
 396 __at(0x0F91) volatile __ALRMCFGbits_t ALRMCFGbits;
 397
 398 __at(0x0F92) __sfr TRISA;
 399 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 400
 401 __at(0x0F93) __sfr TRISB;
 402 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 403
 404 __at(0x0F94) __sfr TRISC;
 405 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 406
 407 __at(0x0F95) __sfr TRISD;
 408 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 409
 410 __at(0x0F96) __sfr TRISE;
 411 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 412
 413 __at(0x0F97) __sfr T3GCON;
 414 __at(0x0F97) volatile __T3GCONbits_t T3GCONbits;
 415
 416 __at(0x0F98) __sfr RTCVALL;
 417
 418 __at(0x0F99) __sfr RTCVALH;
 419
 420 __at(0x0F9A) __sfr T1GCON;
 421 __at(0x0F9A) volatile __T1GCONbits_t T1GCONbits;
 422
 423 __at(0x0F9B) __sfr OSCTUNE;
 424 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 425
 426 __at(0x0F9C) __sfr RCSTA2;
 427 __at(0x0F9C) volatile __RCSTA2bits_t RCSTA2bits;
 428
 429 __at(0x0F9D) __sfr PIE1;
 430 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 431
 432 __at(0x0F9E) __sfr PIR1;
 433 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 434
 435 __at(0x0F9F) __sfr IPR1;
 436 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 437
 438 __at(0x0FA0) __sfr PIE2;
 439 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 440
 441 __at(0x0FA1) __sfr PIR2;
 442 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 443
 444 __at(0x0FA2) __sfr IPR2;
 445 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 446
 447 __at(0x0FA3) __sfr PIE3;
 448 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 449
 450 __at(0x0FA4) __sfr PIR3;
 451 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 452
 453 __at(0x0FA5) __sfr IPR3;
 454 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 455
 456 __at(0x0FA6) __sfr EECON1;
 457 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 458
 459 __at(0x0FA7) __sfr EECON2;
 460
 461 __at(0x0FA8) __sfr TXSTA2;
 462 __at(0x0FA8) volatile __TXSTA2bits_t TXSTA2bits;
 463
 464 __at(0x0FA9) __sfr TXREG2;
 465
 466 __at(0x0FAA) __sfr RCREG2;
 467
 468 __at(0x0FAB) __sfr SPBRG2;
 469
 470 __at(0x0FAC) __sfr RCSTA;
 471 __at(0x0FAC) volatile __RCSTAbits_t RCSTAbits;
 472
 473 __at(0x0FAC) __sfr RCSTA1;
 474 __at(0x0FAC) volatile __RCSTA1bits_t RCSTA1bits;
 475
 476 __at(0x0FAD) __sfr TXSTA;
 477 __at(0x0FAD) volatile __TXSTAbits_t TXSTAbits;
 478
 479 __at(0x0FAD) __sfr TXSTA1;
 480 __at(0x0FAD) volatile __TXSTA1bits_t TXSTA1bits;
 481
 482 __at(0x0FAE) __sfr TXREG;
 483
 484 __at(0x0FAE) __sfr TXREG1;
 485
 486 __at(0x0FAF) __sfr RCREG;
 487
 488 __at(0x0FAF) __sfr RCREG1;
 489
 490 __at(0x0FB0) __sfr SPBRG;
 491
 492 __at(0x0FB0) __sfr SPBRG1;
 493
 494 __at(0x0FB1) __sfr CTMUICON;
 495 __at(0x0FB1) volatile __CTMUICONbits_t CTMUICONbits;
 496
 497 __at(0x0FB2) __sfr CTMUCONL;
 498 __at(0x0FB2) volatile __CTMUCONLbits_t CTMUCONLbits;
 499
 500 __at(0x0FB3) __sfr CTMUCONH;
 501 __at(0x0FB3) volatile __CTMUCONHbits_t CTMUCONHbits;
 502
 503 __at(0x0FB4) __sfr CCP2CON;
 504 __at(0x0FB4) volatile __CCP2CONbits_t CCP2CONbits;
 505
 506 __at(0x0FB4) __sfr ECCP2CON;
 507 __at(0x0FB4) volatile __ECCP2CONbits_t ECCP2CONbits;
 508
 509 __at(0x0FB5) __sfr CCPR2;
 510
 511 __at(0x0FB5) __sfr CCPR2L;
 512
 513 __at(0x0FB6) __sfr CCPR2H;
 514
 515 __at(0x0FB7) __sfr ECCP2DEL;
 516 __at(0x0FB7) volatile __ECCP2DELbits_t ECCP2DELbits;
 517
 518 __at(0x0FB7) __sfr PWM2CON;
 519 __at(0x0FB7) volatile __PWM2CONbits_t PWM2CONbits;
 520
 521 __at(0x0FB8) __sfr ECCP2AS;
 522 __at(0x0FB8) volatile __ECCP2ASbits_t ECCP2ASbits;
 523
 524 __at(0x0FB9) __sfr PSTR2CON;
 525 __at(0x0FB9) volatile __PSTR2CONbits_t PSTR2CONbits;
 526
 527 __at(0x0FBA) __sfr CCP1CON;
 528 __at(0x0FBA) volatile __CCP1CONbits_t CCP1CONbits;
 529
 530 __at(0x0FBA) __sfr ECCP1CON;
 531 __at(0x0FBA) volatile __ECCP1CONbits_t ECCP1CONbits;
 532
 533 __at(0x0FBB) __sfr CCPR1;
 534
 535 __at(0x0FBB) __sfr CCPR1L;
 536
 537 __at(0x0FBC) __sfr CCPR1H;
 538
 539 __at(0x0FBD) __sfr ECCP1DEL;
 540 __at(0x0FBD) volatile __ECCP1DELbits_t ECCP1DELbits;
 541
 542 __at(0x0FBD) __sfr PWM1CON;
 543 __at(0x0FBD) volatile __PWM1CONbits_t PWM1CONbits;
 544
 545 __at(0x0FBE) __sfr ECCP1AS;
 546 __at(0x0FBE) volatile __ECCP1ASbits_t ECCP1ASbits;
 547
 548 __at(0x0FBF) __sfr PSTR1CON;
 549 __at(0x0FBF) volatile __PSTR1CONbits_t PSTR1CONbits;
 550
 551 __at(0x0FC0) __sfr WDTCON;
 552 __at(0x0FC0) volatile __WDTCONbits_t WDTCONbits;
 553
 554 __at(0x0FC1) __sfr ADCON1;
 555 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 556
 557 __at(0x0FC2) __sfr ADCON0;
 558 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 559
 560 __at(0x0FC3) __sfr ADRES;
 561
 562 __at(0x0FC3) __sfr ADRESL;
 563
 564 __at(0x0FC4) __sfr ADRESH;
 565
 566 __at(0x0FC5) __sfr SSP1CON2;
 567 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits;
 568
 569 __at(0x0FC5) __sfr SSPCON2;
 570 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 571
 572 __at(0x0FC6) __sfr SSP1CON1;
 573 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits;
 574
 575 __at(0x0FC6) __sfr SSPCON1;
 576 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 577
 578 __at(0x0FC7) __sfr SSP1STAT;
 579 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits;
 580
 581 __at(0x0FC7) __sfr SSPSTAT;
 582 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 583
 584 __at(0x0FC8) __sfr SSP1ADD;
 585 __at(0x0FC8) volatile __SSP1ADDbits_t SSP1ADDbits;
 586
 587 __at(0x0FC8) __sfr SSP1MSK;
 588 __at(0x0FC8) volatile __SSP1MSKbits_t SSP1MSKbits;
 589
 590 __at(0x0FC8) __sfr SSPADD;
 591 __at(0x0FC8) volatile __SSPADDbits_t SSPADDbits;
 592
 593 __at(0x0FC9) __sfr SSP1BUF;
 594
 595 __at(0x0FC9) __sfr SSPBUF;
 596
 597 __at(0x0FCA) __sfr T2CON;
 598 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 599
 600 __at(0x0FCB) __sfr PR2;
 601
 602 __at(0x0FCC) __sfr TMR2;
 603
 604 __at(0x0FCD) __sfr T1CON;
 605 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 606
 607 __at(0x0FCE) __sfr TMR1;
 608
 609 __at(0x0FCE) __sfr TMR1L;
 610
 611 __at(0x0FCF) __sfr TMR1H;
 612
 613 __at(0x0FD0) __sfr RCON;
 614 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 615
 616 __at(0x0FD1) __sfr CM2CON;
 617 __at(0x0FD1) volatile __CM2CONbits_t CM2CONbits;
 618
 619 __at(0x0FD1) __sfr CM2CON1;
 620 __at(0x0FD1) volatile __CM2CON1bits_t CM2CON1bits;
 621
 622 __at(0x0FD2) __sfr CM1CON;
 623 __at(0x0FD2) volatile __CM1CONbits_t CM1CONbits;
 624
 625 __at(0x0FD2) __sfr CM1CON1;
 626 __at(0x0FD2) volatile __CM1CON1bits_t CM1CON1bits;
 627
 628 __at(0x0FD3) __sfr OSCCON;
 629 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 630
 631 __at(0x0FD5) __sfr T0CON;
 632 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 633
 634 __at(0x0FD6) __sfr TMR0;
 635
 636 __at(0x0FD6) __sfr TMR0L;
 637
 638 __at(0x0FD7) __sfr TMR0H;
 639
 640 __at(0x0FD8) __sfr STATUS;
 641 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 642
 643 __at(0x0FD9) __sfr FSR2L;
 644
 645 __at(0x0FDA) __sfr FSR2H;
 646
 647 __at(0x0FDB) __sfr PLUSW2;
 648
 649 __at(0x0FDC) __sfr PREINC2;
 650
 651 __at(0x0FDD) __sfr POSTDEC2;
 652
 653 __at(0x0FDE) __sfr POSTINC2;
 654
 655 __at(0x0FDF) __sfr INDF2;
 656
 657 __at(0x0FE0) __sfr BSR;
 658
 659 __at(0x0FE1) __sfr FSR1L;
 660
 661 __at(0x0FE2) __sfr FSR1H;
 662
 663 __at(0x0FE3) __sfr PLUSW1;
 664
 665 __at(0x0FE4) __sfr PREINC1;
 666
 667 __at(0x0FE5) __sfr POSTDEC1;
 668
 669 __at(0x0FE6) __sfr POSTINC1;
 670
 671 __at(0x0FE7) __sfr INDF1;
 672
 673 __at(0x0FE8) __sfr WREG;
 674
 675 __at(0x0FE9) __sfr FSR0L;
 676
 677 __at(0x0FEA) __sfr FSR0H;
 678
 679 __at(0x0FEB) __sfr PLUSW0;
 680
 681 __at(0x0FEC) __sfr PREINC0;
 682
 683 __at(0x0FED) __sfr POSTDEC0;
 684
 685 __at(0x0FEE) __sfr POSTINC0;
 686
 687 __at(0x0FEF) __sfr INDF0;
 688
 689 __at(0x0FF0) __sfr INTCON3;
 690 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 691
 692 __at(0x0FF1) __sfr INTCON2;
 693 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 694
 695 __at(0x0FF2) __sfr INTCON;
 696 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 697
 698 __at(0x0FF3) __sfr PROD;
 699
 700 __at(0x0FF3) __sfr PRODL;
 701
 702 __at(0x0FF4) __sfr PRODH;
 703
 704 __at(0x0FF5) __sfr TABLAT;
 705
 706 __at(0x0FF6) __sfr TBLPTR;
 707
 708 __at(0x0FF6) __sfr TBLPTRL;
 709
 710 __at(0x0FF7) __sfr TBLPTRH;
 711
 712 __at(0x0FF8) __sfr TBLPTRU;
 713
 714 __at(0x0FF9) __sfr PC;
 715
 716 __at(0x0FF9) __sfr PCL;
 717
 718 __at(0x0FFA) __sfr PCLATH;
 719
 720 __at(0x0FFB) __sfr PCLATU;
 721
 722 __at(0x0FFC) __sfr STKPTR;
 723 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 724
 725 __at(0x0FFD) __sfr TOS;
 726
 727 __at(0x0FFD) __sfr TOSL;
 728
 729 __at(0x0FFE) __sfr TOSH;
 730
 731 __at(0x0FFF) __sfr TOSU;