sdcc/device/non-free/lib/pic16/libdev/pic18f66j65.c

   1 /*
   2  * This definitions of the PIC18F66J65 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:33 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18f66j65.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0E80) __sfr MAADR5;
  30
  31 __at(0x0E81) __sfr MAADR6;
  32
  33 __at(0x0E82) __sfr MAADR3;
  34
  35 __at(0x0E83) __sfr MAADR4;
  36
  37 __at(0x0E84) __sfr MAADR1;
  38
  39 __at(0x0E85) __sfr MAADR2;
  40
  41 __at(0x0E8A) __sfr MISTAT;
  42 __at(0x0E8A) volatile __MISTATbits_t MISTATbits;
  43
  44 __at(0x0E97) __sfr EFLOCON;
  45 __at(0x0E97) volatile __EFLOCONbits_t EFLOCONbits;
  46
  47 __at(0x0E98) __sfr EPAUS;
  48
  49 __at(0x0E98) __sfr EPAUSL;
  50
  51 __at(0x0E99) __sfr EPAUSH;
  52
  53 __at(0x0EA0) __sfr MACON1;
  54 __at(0x0EA0) volatile __MACON1bits_t MACON1bits;
  55
  56 __at(0x0EA2) __sfr MACON3;
  57 __at(0x0EA2) volatile __MACON3bits_t MACON3bits;
  58
  59 __at(0x0EA3) __sfr MACON4;
  60 __at(0x0EA3) volatile __MACON4bits_t MACON4bits;
  61
  62 __at(0x0EA4) __sfr MABBIPG;
  63 __at(0x0EA4) volatile __MABBIPGbits_t MABBIPGbits;
  64
  65 __at(0x0EA6) __sfr MAIPG;
  66
  67 __at(0x0EA6) __sfr MAIPGL;
  68
  69 __at(0x0EA7) __sfr MAIPGH;
  70
  71 __at(0x0EAA) __sfr MAMXFL;
  72
  73 __at(0x0EAA) __sfr MAMXFLL;
  74
  75 __at(0x0EAB) __sfr MAMXFLH;
  76
  77 __at(0x0EB2) __sfr MICMD;
  78 __at(0x0EB2) volatile __MICMDbits_t MICMDbits;
  79
  80 __at(0x0EB4) __sfr MIREGADR;
  81
  82 __at(0x0EB6) __sfr MIWR;
  83
  84 __at(0x0EB6) __sfr MIWRL;
  85
  86 __at(0x0EB7) __sfr MIWRH;
  87
  88 __at(0x0EB8) __sfr MIRD;
  89
  90 __at(0x0EB8) __sfr MIRDL;
  91
  92 __at(0x0EB9) __sfr MIRDH;
  93
  94 __at(0x0EC0) __sfr EHT0;
  95
  96 __at(0x0EC1) __sfr EHT1;
  97
  98 __at(0x0EC2) __sfr EHT2;
  99
 100 __at(0x0EC3) __sfr EHT3;
 101
 102 __at(0x0EC4) __sfr EHT4;
 103
 104 __at(0x0EC5) __sfr EHT5;
 105
 106 __at(0x0EC6) __sfr EHT6;
 107
 108 __at(0x0EC7) __sfr EHT7;
 109
 110 __at(0x0EC8) __sfr EPMM0;
 111
 112 __at(0x0EC9) __sfr EPMM1;
 113
 114 __at(0x0ECA) __sfr EPMM2;
 115
 116 __at(0x0ECB) __sfr EPMM3;
 117
 118 __at(0x0ECC) __sfr EPMM4;
 119
 120 __at(0x0ECD) __sfr EPMM5;
 121
 122 __at(0x0ECE) __sfr EPMM6;
 123
 124 __at(0x0ECF) __sfr EPMM7;
 125
 126 __at(0x0ED0) __sfr EPMCS;
 127
 128 __at(0x0ED0) __sfr EPMCSL;
 129
 130 __at(0x0ED1) __sfr EPMCSH;
 131
 132 __at(0x0ED4) __sfr EPMO;
 133
 134 __at(0x0ED4) __sfr EPMOL;
 135
 136 __at(0x0ED5) __sfr EPMOH;
 137
 138 __at(0x0ED8) __sfr ERXFCON;
 139 __at(0x0ED8) volatile __ERXFCONbits_t ERXFCONbits;
 140
 141 __at(0x0ED9) __sfr EPKTCNT;
 142
 143 __at(0x0EE2) __sfr EWRPT;
 144
 145 __at(0x0EE2) __sfr EWRPTL;
 146
 147 __at(0x0EE3) __sfr EWRPTH;
 148
 149 __at(0x0EE4) __sfr ETXST;
 150
 151 __at(0x0EE4) __sfr ETXSTL;
 152
 153 __at(0x0EE5) __sfr ETXSTH;
 154
 155 __at(0x0EE6) __sfr ETXND;
 156
 157 __at(0x0EE6) __sfr ETXNDL;
 158
 159 __at(0x0EE7) __sfr ETXNDH;
 160
 161 __at(0x0EE8) __sfr ERXST;
 162
 163 __at(0x0EE8) __sfr ERXSTL;
 164
 165 __at(0x0EE9) __sfr ERXSTH;
 166
 167 __at(0x0EEA) __sfr ERXND;
 168
 169 __at(0x0EEA) __sfr ERXNDL;
 170
 171 __at(0x0EEB) __sfr ERXNDH;
 172
 173 __at(0x0EEC) __sfr ERXRDPT;
 174
 175 __at(0x0EEC) __sfr ERXRDPTL;
 176
 177 __at(0x0EED) __sfr ERXRDPTH;
 178
 179 __at(0x0EEE) __sfr ERXWRPT;
 180
 181 __at(0x0EEE) __sfr ERXWRPTL;
 182
 183 __at(0x0EEF) __sfr ERXWRPTH;
 184
 185 __at(0x0EF0) __sfr EDMAST;
 186
 187 __at(0x0EF0) __sfr EDMASTL;
 188
 189 __at(0x0EF1) __sfr EDMASTH;
 190
 191 __at(0x0EF2) __sfr EDMAND;
 192
 193 __at(0x0EF2) __sfr EDMANDL;
 194
 195 __at(0x0EF3) __sfr EDMANDH;
 196
 197 __at(0x0EF4) __sfr EDMADST;
 198
 199 __at(0x0EF4) __sfr EDMADSTL;
 200
 201 __at(0x0EF5) __sfr EDMADSTH;
 202
 203 __at(0x0EF6) __sfr EDMACS;
 204
 205 __at(0x0EF6) __sfr EDMACSL;
 206
 207 __at(0x0EF7) __sfr EDMACSH;
 208
 209 __at(0x0EFB) __sfr EIE;
 210 __at(0x0EFB) volatile __EIEbits_t EIEbits;
 211
 212 __at(0x0EFD) __sfr ESTAT;
 213 __at(0x0EFD) volatile __ESTATbits_t ESTATbits;
 214
 215 __at(0x0EFE) __sfr ECON2;
 216 __at(0x0EFE) volatile __ECON2bits_t ECON2bits;
 217
 218 __at(0x0F60) __sfr EIR;
 219 __at(0x0F60) volatile __EIRbits_t EIRbits;
 220
 221 __at(0x0F61) __sfr EDATA;
 222 __at(0x0F61) volatile __EDATAbits_t EDATAbits;
 223
 224 __at(0x0F67) __sfr ECCP2DEL;
 225 __at(0x0F67) volatile __ECCP2DELbits_t ECCP2DELbits;
 226
 227 __at(0x0F68) __sfr ECCP2AS;
 228 __at(0x0F68) volatile __ECCP2ASbits_t ECCP2ASbits;
 229
 230 __at(0x0F69) __sfr ECCP3DEL;
 231 __at(0x0F69) volatile __ECCP3DELbits_t ECCP3DELbits;
 232
 233 __at(0x0F6A) __sfr ECCP3AS;
 234 __at(0x0F6A) volatile __ECCP3ASbits_t ECCP3ASbits;
 235
 236 __at(0x0F70) __sfr CCP5CON;
 237 __at(0x0F70) volatile __CCP5CONbits_t CCP5CONbits;
 238
 239 __at(0x0F71) __sfr CCPR5;
 240
 241 __at(0x0F71) __sfr CCPR5L;
 242
 243 __at(0x0F72) __sfr CCPR5H;
 244
 245 __at(0x0F73) __sfr CCP4CON;
 246 __at(0x0F73) volatile __CCP4CONbits_t CCP4CONbits;
 247
 248 __at(0x0F74) __sfr CCPR4;
 249
 250 __at(0x0F74) __sfr CCPR4L;
 251
 252 __at(0x0F75) __sfr CCPR4H;
 253
 254 __at(0x0F76) __sfr T4CON;
 255 __at(0x0F76) volatile __T4CONbits_t T4CONbits;
 256
 257 __at(0x0F77) __sfr PR4;
 258
 259 __at(0x0F78) __sfr TMR4;
 260
 261 __at(0x0F79) __sfr ECCP1DEL;
 262 __at(0x0F79) volatile __ECCP1DELbits_t ECCP1DELbits;
 263
 264 __at(0x0F7A) __sfr ERDPT;
 265
 266 __at(0x0F7A) __sfr ERDPTL;
 267
 268 __at(0x0F7B) __sfr ERDPTH;
 269
 270 __at(0x0F7E) __sfr BAUDCON;
 271 __at(0x0F7E) volatile __BAUDCONbits_t BAUDCONbits;
 272
 273 __at(0x0F7E) __sfr BAUDCON1;
 274 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits;
 275
 276 __at(0x0F7E) __sfr BAUDCTL;
 277 __at(0x0F7E) volatile __BAUDCTLbits_t BAUDCTLbits;
 278
 279 __at(0x0F7E) __sfr BAUDCTL1;
 280 __at(0x0F7E) volatile __BAUDCTL1bits_t BAUDCTL1bits;
 281
 282 __at(0x0F7F) __sfr SPBRGH;
 283
 284 __at(0x0F7F) __sfr SPBRGH1;
 285
 286 __at(0x0F80) __sfr PORTA;
 287 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
 288
 289 __at(0x0F81) __sfr PORTB;
 290 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
 291
 292 __at(0x0F82) __sfr PORTC;
 293 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
 294
 295 __at(0x0F83) __sfr PORTD;
 296 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
 297
 298 __at(0x0F84) __sfr PORTE;
 299 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
 300
 301 __at(0x0F85) __sfr PORTF;
 302 __at(0x0F85) volatile __PORTFbits_t PORTFbits;
 303
 304 __at(0x0F86) __sfr PORTG;
 305 __at(0x0F86) volatile __PORTGbits_t PORTGbits;
 306
 307 __at(0x0F89) __sfr LATA;
 308 __at(0x0F89) volatile __LATAbits_t LATAbits;
 309
 310 __at(0x0F8A) __sfr LATB;
 311 __at(0x0F8A) volatile __LATBbits_t LATBbits;
 312
 313 __at(0x0F8B) __sfr LATC;
 314 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 315
 316 __at(0x0F8C) __sfr LATD;
 317 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 318
 319 __at(0x0F8D) __sfr LATE;
 320 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 321
 322 __at(0x0F8E) __sfr LATF;
 323 __at(0x0F8E) volatile __LATFbits_t LATFbits;
 324
 325 __at(0x0F8F) __sfr LATG;
 326 __at(0x0F8F) volatile __LATGbits_t LATGbits;
 327
 328 __at(0x0F92) __sfr DDRA;
 329 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
 330
 331 __at(0x0F92) __sfr TRISA;
 332 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 333
 334 __at(0x0F93) __sfr DDRB;
 335 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
 336
 337 __at(0x0F93) __sfr TRISB;
 338 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 339
 340 __at(0x0F94) __sfr DDRC;
 341 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
 342
 343 __at(0x0F94) __sfr TRISC;
 344 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 345
 346 __at(0x0F95) __sfr DDRD;
 347 __at(0x0F95) volatile __DDRDbits_t DDRDbits;
 348
 349 __at(0x0F95) __sfr TRISD;
 350 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 351
 352 __at(0x0F96) __sfr DDRE;
 353 __at(0x0F96) volatile __DDREbits_t DDREbits;
 354
 355 __at(0x0F96) __sfr TRISE;
 356 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 357
 358 __at(0x0F97) __sfr DDRF;
 359 __at(0x0F97) volatile __DDRFbits_t DDRFbits;
 360
 361 __at(0x0F97) __sfr TRISF;
 362 __at(0x0F97) volatile __TRISFbits_t TRISFbits;
 363
 364 __at(0x0F98) __sfr DDRG;
 365 __at(0x0F98) volatile __DDRGbits_t DDRGbits;
 366
 367 __at(0x0F98) __sfr TRISG;
 368 __at(0x0F98) volatile __TRISGbits_t TRISGbits;
 369
 370 __at(0x0F9B) __sfr OSCTUNE;
 371 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 372
 373 __at(0x0F9D) __sfr PIE1;
 374 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 375
 376 __at(0x0F9E) __sfr PIR1;
 377 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 378
 379 __at(0x0F9F) __sfr IPR1;
 380 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 381
 382 __at(0x0FA0) __sfr PIE2;
 383 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 384
 385 __at(0x0FA1) __sfr PIR2;
 386 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 387
 388 __at(0x0FA2) __sfr IPR2;
 389 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 390
 391 __at(0x0FA3) __sfr PIE3;
 392 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 393
 394 __at(0x0FA4) __sfr PIR3;
 395 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 396
 397 __at(0x0FA5) __sfr IPR3;
 398 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 399
 400 __at(0x0FA6) __sfr EECON1;
 401 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 402
 403 __at(0x0FA7) __sfr EECON2;
 404
 405 __at(0x0FAB) __sfr RCSTA;
 406 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 407
 408 __at(0x0FAB) __sfr RCSTA1;
 409 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits;
 410
 411 __at(0x0FAC) __sfr TXSTA;
 412 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 413
 414 __at(0x0FAC) __sfr TXSTA1;
 415 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits;
 416
 417 __at(0x0FAD) __sfr TXREG;
 418
 419 __at(0x0FAD) __sfr TXREG1;
 420
 421 __at(0x0FAE) __sfr RCREG;
 422
 423 __at(0x0FAE) __sfr RCREG1;
 424
 425 __at(0x0FAF) __sfr SPBRG;
 426
 427 __at(0x0FAF) __sfr SPBRG1;
 428
 429 __at(0x0FB1) __sfr T3CON;
 430 __at(0x0FB1) volatile __T3CONbits_t T3CONbits;
 431
 432 __at(0x0FB2) __sfr TMR3;
 433
 434 __at(0x0FB2) __sfr TMR3L;
 435
 436 __at(0x0FB3) __sfr TMR3H;
 437
 438 __at(0x0FB4) __sfr CMCON;
 439 __at(0x0FB4) volatile __CMCONbits_t CMCONbits;
 440
 441 __at(0x0FB5) __sfr CVRCON;
 442 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits;
 443
 444 __at(0x0FB6) __sfr ECCP1AS;
 445 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits;
 446
 447 __at(0x0FB7) __sfr CCP3CON;
 448 __at(0x0FB7) volatile __CCP3CONbits_t CCP3CONbits;
 449
 450 __at(0x0FB7) __sfr ECCP3CON;
 451 __at(0x0FB7) volatile __ECCP3CONbits_t ECCP3CONbits;
 452
 453 __at(0x0FB8) __sfr CCPR3;
 454
 455 __at(0x0FB8) __sfr CCPR3L;
 456
 457 __at(0x0FB9) __sfr CCPR3H;
 458
 459 __at(0x0FBA) __sfr CCP2CON;
 460 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits;
 461
 462 __at(0x0FBA) __sfr ECCP2CON;
 463 __at(0x0FBA) volatile __ECCP2CONbits_t ECCP2CONbits;
 464
 465 __at(0x0FBB) __sfr CCPR2;
 466
 467 __at(0x0FBB) __sfr CCPR2L;
 468
 469 __at(0x0FBC) __sfr CCPR2H;
 470
 471 __at(0x0FBD) __sfr CCP1CON;
 472 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits;
 473
 474 __at(0x0FBD) __sfr ECCP1CON;
 475 __at(0x0FBD) volatile __ECCP1CONbits_t ECCP1CONbits;
 476
 477 __at(0x0FBE) __sfr CCPR1;
 478
 479 __at(0x0FBE) __sfr CCPR1L;
 480
 481 __at(0x0FBF) __sfr CCPR1H;
 482
 483 __at(0x0FC0) __sfr ADCON2;
 484 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 485
 486 __at(0x0FC1) __sfr ADCON1;
 487 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 488
 489 __at(0x0FC2) __sfr ADCON0;
 490 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 491
 492 __at(0x0FC3) __sfr ADRES;
 493
 494 __at(0x0FC3) __sfr ADRESL;
 495
 496 __at(0x0FC4) __sfr ADRESH;
 497
 498 __at(0x0FC5) __sfr SSP1CON2;
 499 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits;
 500
 501 __at(0x0FC5) __sfr SSPCON2;
 502 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 503
 504 __at(0x0FC6) __sfr SSP1CON1;
 505 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits;
 506
 507 __at(0x0FC6) __sfr SSPCON1;
 508 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 509
 510 __at(0x0FC7) __sfr SSP1STAT;
 511 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits;
 512
 513 __at(0x0FC7) __sfr SSPSTAT;
 514 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 515
 516 __at(0x0FC8) __sfr SSP1ADD;
 517
 518 __at(0x0FC8) __sfr SSPADD;
 519
 520 __at(0x0FC9) __sfr SSP1BUF;
 521
 522 __at(0x0FC9) __sfr SSPBUF;
 523
 524 __at(0x0FCA) __sfr T2CON;
 525 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 526
 527 __at(0x0FCB) __sfr PR2;
 528
 529 __at(0x0FCC) __sfr TMR2;
 530
 531 __at(0x0FCD) __sfr T1CON;
 532 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 533
 534 __at(0x0FCE) __sfr TMR1;
 535
 536 __at(0x0FCE) __sfr TMR1L;
 537
 538 __at(0x0FCF) __sfr TMR1H;
 539
 540 __at(0x0FD0) __sfr RCON;
 541 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 542
 543 __at(0x0FD1) __sfr WDTCON;
 544 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 545
 546 __at(0x0FD2) __sfr ECON1;
 547 __at(0x0FD2) volatile __ECON1bits_t ECON1bits;
 548
 549 __at(0x0FD3) __sfr OSCCON;
 550 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 551
 552 __at(0x0FD5) __sfr T0CON;
 553 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 554
 555 __at(0x0FD6) __sfr TMR0;
 556
 557 __at(0x0FD6) __sfr TMR0L;
 558
 559 __at(0x0FD7) __sfr TMR0H;
 560
 561 __at(0x0FD8) __sfr STATUS;
 562 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 563
 564 __at(0x0FD9) __sfr FSR2L;
 565
 566 __at(0x0FDA) __sfr FSR2H;
 567
 568 __at(0x0FDB) __sfr PLUSW2;
 569
 570 __at(0x0FDC) __sfr PREINC2;
 571
 572 __at(0x0FDD) __sfr POSTDEC2;
 573
 574 __at(0x0FDE) __sfr POSTINC2;
 575
 576 __at(0x0FDF) __sfr INDF2;
 577
 578 __at(0x0FE0) __sfr BSR;
 579
 580 __at(0x0FE1) __sfr FSR1L;
 581
 582 __at(0x0FE2) __sfr FSR1H;
 583
 584 __at(0x0FE3) __sfr PLUSW1;
 585
 586 __at(0x0FE4) __sfr PREINC1;
 587
 588 __at(0x0FE5) __sfr POSTDEC1;
 589
 590 __at(0x0FE6) __sfr POSTINC1;
 591
 592 __at(0x0FE7) __sfr INDF1;
 593
 594 __at(0x0FE8) __sfr WREG;
 595
 596 __at(0x0FE9) __sfr FSR0L;
 597
 598 __at(0x0FEA) __sfr FSR0H;
 599
 600 __at(0x0FEB) __sfr PLUSW0;
 601
 602 __at(0x0FEC) __sfr PREINC0;
 603
 604 __at(0x0FED) __sfr POSTDEC0;
 605
 606 __at(0x0FEE) __sfr POSTINC0;
 607
 608 __at(0x0FEF) __sfr INDF0;
 609
 610 __at(0x0FF0) __sfr INTCON3;
 611 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 612
 613 __at(0x0FF1) __sfr INTCON2;
 614 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 615
 616 __at(0x0FF2) __sfr INTCON;
 617 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 618
 619 __at(0x0FF3) __sfr PROD;
 620
 621 __at(0x0FF3) __sfr PRODL;
 622
 623 __at(0x0FF4) __sfr PRODH;
 624
 625 __at(0x0FF5) __sfr TABLAT;
 626
 627 __at(0x0FF6) __sfr TBLPTR;
 628
 629 __at(0x0FF6) __sfr TBLPTRL;
 630
 631 __at(0x0FF7) __sfr TBLPTRH;
 632
 633 __at(0x0FF8) __sfr TBLPTRU;
 634
 635 __at(0x0FF9) __sfr PC;
 636
 637 __at(0x0FF9) __sfr PCL;
 638
 639 __at(0x0FFA) __sfr PCLATH;
 640
 641 __at(0x0FFB) __sfr PCLATU;
 642
 643 __at(0x0FFC) __sfr STKPTR;
 644 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 645
 646 __at(0x0FFD) __sfr TOS;
 647
 648 __at(0x0FFD) __sfr TOSL;
 649
 650 __at(0x0FFE) __sfr TOSH;
 651
 652 __at(0x0FFF) __sfr TOSU;