sdcc/device/non-free/lib/pic16/libdev/pic18f83j11.c

   1 /*
   2  * This definitions of the PIC18F83J11 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:36 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18f83j11.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F60) __sfr RCSTA2;
  30 __at(0x0F60) volatile __RCSTA2bits_t RCSTA2bits;
  31
  32 __at(0x0F61) __sfr TXSTA2;
  33 __at(0x0F61) volatile __TXSTA2bits_t TXSTA2bits;
  34
  35 __at(0x0F62) __sfr TXREG2;
  36
  37 __at(0x0F63) __sfr RCREG2;
  38
  39 __at(0x0F64) __sfr SPBRG2;
  40
  41 __at(0x0F65) __sfr CCP2CON;
  42 __at(0x0F65) volatile __CCP2CONbits_t CCP2CONbits;
  43
  44 __at(0x0F66) __sfr CCPR2;
  45
  46 __at(0x0F66) __sfr CCPR2L;
  47
  48 __at(0x0F67) __sfr CCPR2H;
  49
  50 __at(0x0F68) __sfr CCP1CON;
  51 __at(0x0F68) volatile __CCP1CONbits_t CCP1CONbits;
  52
  53 __at(0x0F69) __sfr CCPR1;
  54
  55 __at(0x0F69) __sfr CCPR1L;
  56
  57 __at(0x0F6A) __sfr CCPR1H;
  58
  59 __at(0x0F7E) __sfr BAUDCON1;
  60 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits;
  61
  62 __at(0x0F7F) __sfr SPBRGH1;
  63
  64 __at(0x0F80) __sfr PORTA;
  65 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
  66
  67 __at(0x0F81) __sfr PORTB;
  68 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
  69
  70 __at(0x0F82) __sfr PORTC;
  71 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
  72
  73 __at(0x0F83) __sfr PORTD;
  74 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
  75
  76 __at(0x0F84) __sfr PORTE;
  77 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
  78
  79 __at(0x0F85) __sfr PORTF;
  80 __at(0x0F85) volatile __PORTFbits_t PORTFbits;
  81
  82 __at(0x0F86) __sfr PORTG;
  83 __at(0x0F86) volatile __PORTGbits_t PORTGbits;
  84
  85 __at(0x0F87) __sfr PORTH;
  86 __at(0x0F87) volatile __PORTHbits_t PORTHbits;
  87
  88 __at(0x0F88) __sfr PORTJ;
  89 __at(0x0F88) volatile __PORTJbits_t PORTJbits;
  90
  91 __at(0x0F89) __sfr LATA;
  92 __at(0x0F89) volatile __LATAbits_t LATAbits;
  93
  94 __at(0x0F8A) __sfr LATB;
  95 __at(0x0F8A) volatile __LATBbits_t LATBbits;
  96
  97 __at(0x0F8B) __sfr LATC;
  98 __at(0x0F8B) volatile __LATCbits_t LATCbits;
  99
 100 __at(0x0F8C) __sfr LATD;
 101 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 102
 103 __at(0x0F8D) __sfr LATE;
 104 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 105
 106 __at(0x0F8E) __sfr LATF;
 107 __at(0x0F8E) volatile __LATFbits_t LATFbits;
 108
 109 __at(0x0F8F) __sfr LATG;
 110 __at(0x0F8F) volatile __LATGbits_t LATGbits;
 111
 112 __at(0x0F90) __sfr LATH;
 113 __at(0x0F90) volatile __LATHbits_t LATHbits;
 114
 115 __at(0x0F91) __sfr LATJ;
 116 __at(0x0F91) volatile __LATJbits_t LATJbits;
 117
 118 __at(0x0F92) __sfr DDRA;
 119 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
 120
 121 __at(0x0F92) __sfr TRISA;
 122 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 123
 124 __at(0x0F93) __sfr DDRB;
 125 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
 126
 127 __at(0x0F93) __sfr TRISB;
 128 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 129
 130 __at(0x0F94) __sfr DDRC;
 131 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
 132
 133 __at(0x0F94) __sfr TRISC;
 134 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 135
 136 __at(0x0F95) __sfr DDRD;
 137 __at(0x0F95) volatile __DDRDbits_t DDRDbits;
 138
 139 __at(0x0F95) __sfr TRISD;
 140 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 141
 142 __at(0x0F96) __sfr DDRE;
 143 __at(0x0F96) volatile __DDREbits_t DDREbits;
 144
 145 __at(0x0F96) __sfr TRISE;
 146 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 147
 148 __at(0x0F97) __sfr DDRF;
 149 __at(0x0F97) volatile __DDRFbits_t DDRFbits;
 150
 151 __at(0x0F97) __sfr TRISF;
 152 __at(0x0F97) volatile __TRISFbits_t TRISFbits;
 153
 154 __at(0x0F98) __sfr DDRG;
 155 __at(0x0F98) volatile __DDRGbits_t DDRGbits;
 156
 157 __at(0x0F98) __sfr TRISG;
 158 __at(0x0F98) volatile __TRISGbits_t TRISGbits;
 159
 160 __at(0x0F99) __sfr DDRH;
 161 __at(0x0F99) volatile __DDRHbits_t DDRHbits;
 162
 163 __at(0x0F99) __sfr TRISH;
 164 __at(0x0F99) volatile __TRISHbits_t TRISHbits;
 165
 166 __at(0x0F9A) __sfr DDRJ;
 167 __at(0x0F9A) volatile __DDRJbits_t DDRJbits;
 168
 169 __at(0x0F9A) __sfr TRISJ;
 170 __at(0x0F9A) volatile __TRISJbits_t TRISJbits;
 171
 172 __at(0x0F9B) __sfr OSCTUNE;
 173 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 174
 175 __at(0x0F9C) __sfr MEMCON;
 176 __at(0x0F9C) volatile __MEMCONbits_t MEMCONbits;
 177
 178 __at(0x0F9D) __sfr PIE1;
 179 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 180
 181 __at(0x0F9E) __sfr PIR1;
 182 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 183
 184 __at(0x0F9F) __sfr IPR1;
 185 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 186
 187 __at(0x0FA0) __sfr PIE2;
 188 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 189
 190 __at(0x0FA1) __sfr PIR2;
 191 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 192
 193 __at(0x0FA2) __sfr IPR2;
 194 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 195
 196 __at(0x0FA3) __sfr PIE3;
 197 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 198
 199 __at(0x0FA4) __sfr PIR3;
 200 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 201
 202 __at(0x0FA5) __sfr IPR3;
 203 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 204
 205 __at(0x0FA6) __sfr EECON1;
 206 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 207
 208 __at(0x0FA7) __sfr EECON2;
 209
 210 __at(0x0FAB) __sfr RCSTA;
 211 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 212
 213 __at(0x0FAB) __sfr RCSTA1;
 214 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits;
 215
 216 __at(0x0FAC) __sfr TXSTA;
 217 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 218
 219 __at(0x0FAC) __sfr TXSTA1;
 220 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits;
 221
 222 __at(0x0FAD) __sfr TXREG;
 223
 224 __at(0x0FAD) __sfr TXREG1;
 225
 226 __at(0x0FAE) __sfr RCREG;
 227
 228 __at(0x0FAE) __sfr RCREG1;
 229
 230 __at(0x0FAF) __sfr SPBRG;
 231
 232 __at(0x0FAF) __sfr SPBRG1;
 233
 234 __at(0x0FB0) __sfr PSPCON;
 235 __at(0x0FB0) volatile __PSPCONbits_t PSPCONbits;
 236
 237 __at(0x0FB1) __sfr T3CON;
 238 __at(0x0FB1) volatile __T3CONbits_t T3CONbits;
 239
 240 __at(0x0FB2) __sfr TMR3;
 241
 242 __at(0x0FB2) __sfr TMR3L;
 243
 244 __at(0x0FB3) __sfr TMR3H;
 245
 246 __at(0x0FB4) __sfr CMCON;
 247 __at(0x0FB4) volatile __CMCONbits_t CMCONbits;
 248
 249 __at(0x0FB5) __sfr CVRCON;
 250 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits;
 251
 252 __at(0x0FC0) __sfr ADCON2;
 253 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 254
 255 __at(0x0FC1) __sfr ADCON1;
 256 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 257
 258 __at(0x0FC2) __sfr ADCON0;
 259 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 260
 261 __at(0x0FC3) __sfr ADRES;
 262
 263 __at(0x0FC3) __sfr ADRESL;
 264
 265 __at(0x0FC4) __sfr ADRESH;
 266
 267 __at(0x0FC5) __sfr SSP1CON2;
 268 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits;
 269
 270 __at(0x0FC5) __sfr SSPCON2;
 271 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 272
 273 __at(0x0FC6) __sfr SSP1CON1;
 274 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits;
 275
 276 __at(0x0FC6) __sfr SSPCON1;
 277 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 278
 279 __at(0x0FC7) __sfr SSP1STAT;
 280 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits;
 281
 282 __at(0x0FC7) __sfr SSPSTAT;
 283 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 284
 285 __at(0x0FC8) __sfr SSP1ADD;
 286
 287 __at(0x0FC8) __sfr SSPADD;
 288
 289 __at(0x0FC9) __sfr SSP1BUF;
 290
 291 __at(0x0FC9) __sfr SSPBUF;
 292
 293 __at(0x0FCA) __sfr T2CON;
 294 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 295
 296 __at(0x0FCB) __sfr PR2;
 297
 298 __at(0x0FCC) __sfr TMR2;
 299
 300 __at(0x0FCD) __sfr T1CON;
 301 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 302
 303 __at(0x0FCE) __sfr TMR1;
 304
 305 __at(0x0FCE) __sfr TMR1L;
 306
 307 __at(0x0FCF) __sfr TMR1H;
 308
 309 __at(0x0FD0) __sfr RCON;
 310 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 311
 312 __at(0x0FD1) __sfr WDTCON;
 313 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 314
 315 __at(0x0FD3) __sfr OSCCON;
 316 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 317
 318 __at(0x0FD5) __sfr T0CON;
 319 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 320
 321 __at(0x0FD6) __sfr TMR0;
 322
 323 __at(0x0FD6) __sfr TMR0L;
 324
 325 __at(0x0FD7) __sfr TMR0H;
 326
 327 __at(0x0FD8) __sfr STATUS;
 328 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 329
 330 __at(0x0FD9) __sfr FSR2L;
 331
 332 __at(0x0FDA) __sfr FSR2H;
 333
 334 __at(0x0FDB) __sfr PLUSW2;
 335
 336 __at(0x0FDC) __sfr PREINC2;
 337
 338 __at(0x0FDD) __sfr POSTDEC2;
 339
 340 __at(0x0FDE) __sfr POSTINC2;
 341
 342 __at(0x0FDF) __sfr INDF2;
 343
 344 __at(0x0FE0) __sfr BSR;
 345
 346 __at(0x0FE1) __sfr FSR1L;
 347
 348 __at(0x0FE2) __sfr FSR1H;
 349
 350 __at(0x0FE3) __sfr PLUSW1;
 351
 352 __at(0x0FE4) __sfr PREINC1;
 353
 354 __at(0x0FE5) __sfr POSTDEC1;
 355
 356 __at(0x0FE6) __sfr POSTINC1;
 357
 358 __at(0x0FE7) __sfr INDF1;
 359
 360 __at(0x0FE8) __sfr WREG;
 361
 362 __at(0x0FE9) __sfr FSR0L;
 363
 364 __at(0x0FEA) __sfr FSR0H;
 365
 366 __at(0x0FEB) __sfr PLUSW0;
 367
 368 __at(0x0FEC) __sfr PREINC0;
 369
 370 __at(0x0FED) __sfr POSTDEC0;
 371
 372 __at(0x0FEE) __sfr POSTINC0;
 373
 374 __at(0x0FEF) __sfr INDF0;
 375
 376 __at(0x0FF0) __sfr INTCON3;
 377 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 378
 379 __at(0x0FF1) __sfr INTCON2;
 380 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 381
 382 __at(0x0FF2) __sfr INTCON;
 383 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 384
 385 __at(0x0FF3) __sfr PROD;
 386
 387 __at(0x0FF3) __sfr PRODL;
 388
 389 __at(0x0FF4) __sfr PRODH;
 390
 391 __at(0x0FF5) __sfr TABLAT;
 392
 393 __at(0x0FF6) __sfr TBLPTR;
 394
 395 __at(0x0FF6) __sfr TBLPTRL;
 396
 397 __at(0x0FF7) __sfr TBLPTRH;
 398
 399 __at(0x0FF8) __sfr TBLPTRU;
 400
 401 __at(0x0FF9) __sfr PC;
 402
 403 __at(0x0FF9) __sfr PCL;
 404
 405 __at(0x0FFA) __sfr PCLATH;
 406
 407 __at(0x0FFB) __sfr PCLATU;
 408
 409 __at(0x0FFC) __sfr STKPTR;
 410 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 411
 412 __at(0x0FFD) __sfr TOS;
 413
 414 __at(0x0FFD) __sfr TOSL;
 415
 416 __at(0x0FFE) __sfr TOSH;
 417
 418 __at(0x0FFF) __sfr TOSU;