sdcc/device/non-free/lib/pic16/libdev/pic18f8622.c

   1 /*
   2  * This definitions of the PIC18F8622 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:52 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18f8622.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F62) __sfr SSP2CON2;
  30 __at(0x0F62) volatile __SSP2CON2bits_t SSP2CON2bits;
  31
  32 __at(0x0F63) __sfr SSP2CON1;
  33 __at(0x0F63) volatile __SSP2CON1bits_t SSP2CON1bits;
  34
  35 __at(0x0F64) __sfr SSP2STAT;
  36 __at(0x0F64) volatile __SSP2STATbits_t SSP2STATbits;
  37
  38 __at(0x0F65) __sfr SSP2ADD;
  39
  40 __at(0x0F66) __sfr SSP2BUF;
  41
  42 __at(0x0F67) __sfr ECCP2DEL;
  43 __at(0x0F67) volatile __ECCP2DELbits_t ECCP2DELbits;
  44
  45 __at(0x0F68) __sfr ECCP2AS;
  46 __at(0x0F68) volatile __ECCP2ASbits_t ECCP2ASbits;
  47
  48 __at(0x0F69) __sfr ECCP3DEL;
  49 __at(0x0F69) volatile __ECCP3DELbits_t ECCP3DELbits;
  50
  51 __at(0x0F6A) __sfr ECCP3AS;
  52 __at(0x0F6A) volatile __ECCP3ASbits_t ECCP3ASbits;
  53
  54 __at(0x0F6B) __sfr RCSTA2;
  55 __at(0x0F6B) volatile __RCSTA2bits_t RCSTA2bits;
  56
  57 __at(0x0F6C) __sfr TXSTA2;
  58 __at(0x0F6C) volatile __TXSTA2bits_t TXSTA2bits;
  59
  60 __at(0x0F6D) __sfr TXREG2;
  61
  62 __at(0x0F6E) __sfr RCREG2;
  63
  64 __at(0x0F6F) __sfr SPBRG2;
  65
  66 __at(0x0F70) __sfr CCP5CON;
  67 __at(0x0F70) volatile __CCP5CONbits_t CCP5CONbits;
  68
  69 __at(0x0F71) __sfr CCPR5;
  70
  71 __at(0x0F71) __sfr CCPR5L;
  72
  73 __at(0x0F72) __sfr CCPR5H;
  74
  75 __at(0x0F73) __sfr CCP4CON;
  76 __at(0x0F73) volatile __CCP4CONbits_t CCP4CONbits;
  77
  78 __at(0x0F74) __sfr CCPR4;
  79
  80 __at(0x0F74) __sfr CCPR4L;
  81
  82 __at(0x0F75) __sfr CCPR4H;
  83
  84 __at(0x0F76) __sfr T4CON;
  85 __at(0x0F76) volatile __T4CONbits_t T4CONbits;
  86
  87 __at(0x0F77) __sfr PR4;
  88
  89 __at(0x0F78) __sfr TMR4;
  90
  91 __at(0x0F79) __sfr ECCP1DEL;
  92 __at(0x0F79) volatile __ECCP1DELbits_t ECCP1DELbits;
  93
  94 __at(0x0F7C) __sfr BAUDCON2;
  95 __at(0x0F7C) volatile __BAUDCON2bits_t BAUDCON2bits;
  96
  97 __at(0x0F7D) __sfr SPBRGH2;
  98
  99 __at(0x0F7E) __sfr BAUDCON;
 100 __at(0x0F7E) volatile __BAUDCONbits_t BAUDCONbits;
 101
 102 __at(0x0F7E) __sfr BAUDCON1;
 103 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits;
 104
 105 __at(0x0F7F) __sfr SPBRGH;
 106
 107 __at(0x0F7F) __sfr SPBRGH1;
 108
 109 __at(0x0F80) __sfr PORTA;
 110 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
 111
 112 __at(0x0F81) __sfr PORTB;
 113 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
 114
 115 __at(0x0F82) __sfr PORTC;
 116 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
 117
 118 __at(0x0F83) __sfr PORTD;
 119 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
 120
 121 __at(0x0F84) __sfr PORTE;
 122 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
 123
 124 __at(0x0F85) __sfr PORTF;
 125 __at(0x0F85) volatile __PORTFbits_t PORTFbits;
 126
 127 __at(0x0F86) __sfr PORTG;
 128 __at(0x0F86) volatile __PORTGbits_t PORTGbits;
 129
 130 __at(0x0F87) __sfr PORTH;
 131 __at(0x0F87) volatile __PORTHbits_t PORTHbits;
 132
 133 __at(0x0F88) __sfr PORTJ;
 134 __at(0x0F88) volatile __PORTJbits_t PORTJbits;
 135
 136 __at(0x0F89) __sfr LATA;
 137 __at(0x0F89) volatile __LATAbits_t LATAbits;
 138
 139 __at(0x0F8A) __sfr LATB;
 140 __at(0x0F8A) volatile __LATBbits_t LATBbits;
 141
 142 __at(0x0F8B) __sfr LATC;
 143 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 144
 145 __at(0x0F8C) __sfr LATD;
 146 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 147
 148 __at(0x0F8D) __sfr LATE;
 149 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 150
 151 __at(0x0F8E) __sfr LATF;
 152 __at(0x0F8E) volatile __LATFbits_t LATFbits;
 153
 154 __at(0x0F8F) __sfr LATG;
 155 __at(0x0F8F) volatile __LATGbits_t LATGbits;
 156
 157 __at(0x0F90) __sfr LATH;
 158 __at(0x0F90) volatile __LATHbits_t LATHbits;
 159
 160 __at(0x0F91) __sfr LATJ;
 161 __at(0x0F91) volatile __LATJbits_t LATJbits;
 162
 163 __at(0x0F92) __sfr DDRA;
 164 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
 165
 166 __at(0x0F92) __sfr TRISA;
 167 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 168
 169 __at(0x0F93) __sfr DDRB;
 170 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
 171
 172 __at(0x0F93) __sfr TRISB;
 173 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 174
 175 __at(0x0F94) __sfr DDRC;
 176 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
 177
 178 __at(0x0F94) __sfr TRISC;
 179 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 180
 181 __at(0x0F95) __sfr DDRD;
 182 __at(0x0F95) volatile __DDRDbits_t DDRDbits;
 183
 184 __at(0x0F95) __sfr TRISD;
 185 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 186
 187 __at(0x0F96) __sfr DDRE;
 188 __at(0x0F96) volatile __DDREbits_t DDREbits;
 189
 190 __at(0x0F96) __sfr TRISE;
 191 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 192
 193 __at(0x0F97) __sfr DDRF;
 194 __at(0x0F97) volatile __DDRFbits_t DDRFbits;
 195
 196 __at(0x0F97) __sfr TRISF;
 197 __at(0x0F97) volatile __TRISFbits_t TRISFbits;
 198
 199 __at(0x0F98) __sfr DDRG;
 200 __at(0x0F98) volatile __DDRGbits_t DDRGbits;
 201
 202 __at(0x0F98) __sfr TRISG;
 203 __at(0x0F98) volatile __TRISGbits_t TRISGbits;
 204
 205 __at(0x0F99) __sfr DDRH;
 206 __at(0x0F99) volatile __DDRHbits_t DDRHbits;
 207
 208 __at(0x0F99) __sfr TRISH;
 209 __at(0x0F99) volatile __TRISHbits_t TRISHbits;
 210
 211 __at(0x0F9A) __sfr DDRJ;
 212 __at(0x0F9A) volatile __DDRJbits_t DDRJbits;
 213
 214 __at(0x0F9A) __sfr TRISJ;
 215 __at(0x0F9A) volatile __TRISJbits_t TRISJbits;
 216
 217 __at(0x0F9B) __sfr OSCTUNE;
 218 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 219
 220 __at(0x0F9C) __sfr MEMCON;
 221 __at(0x0F9C) volatile __MEMCONbits_t MEMCONbits;
 222
 223 __at(0x0F9D) __sfr PIE1;
 224 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 225
 226 __at(0x0F9E) __sfr PIR1;
 227 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 228
 229 __at(0x0F9F) __sfr IPR1;
 230 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 231
 232 __at(0x0FA0) __sfr PIE2;
 233 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 234
 235 __at(0x0FA1) __sfr PIR2;
 236 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 237
 238 __at(0x0FA2) __sfr IPR2;
 239 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 240
 241 __at(0x0FA3) __sfr PIE3;
 242 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 243
 244 __at(0x0FA4) __sfr PIR3;
 245 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 246
 247 __at(0x0FA5) __sfr IPR3;
 248 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 249
 250 __at(0x0FA6) __sfr EECON1;
 251 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 252
 253 __at(0x0FA7) __sfr EECON2;
 254
 255 __at(0x0FA8) __sfr EEDATA;
 256
 257 __at(0x0FA9) __sfr EEADR;
 258
 259 __at(0x0FAA) __sfr EEADRH;
 260
 261 __at(0x0FAB) __sfr RCSTA;
 262 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 263
 264 __at(0x0FAB) __sfr RCSTA1;
 265 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits;
 266
 267 __at(0x0FAC) __sfr TXSTA;
 268 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 269
 270 __at(0x0FAC) __sfr TXSTA1;
 271 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits;
 272
 273 __at(0x0FAD) __sfr TXREG;
 274
 275 __at(0x0FAD) __sfr TXREG1;
 276
 277 __at(0x0FAE) __sfr RCREG;
 278
 279 __at(0x0FAE) __sfr RCREG1;
 280
 281 __at(0x0FAF) __sfr SPBRG;
 282
 283 __at(0x0FAF) __sfr SPBRG1;
 284
 285 __at(0x0FB0) __sfr PSPCON;
 286 __at(0x0FB0) volatile __PSPCONbits_t PSPCONbits;
 287
 288 __at(0x0FB1) __sfr T3CON;
 289 __at(0x0FB1) volatile __T3CONbits_t T3CONbits;
 290
 291 __at(0x0FB2) __sfr TMR3;
 292
 293 __at(0x0FB2) __sfr TMR3L;
 294
 295 __at(0x0FB3) __sfr TMR3H;
 296
 297 __at(0x0FB4) __sfr CMCON;
 298 __at(0x0FB4) volatile __CMCONbits_t CMCONbits;
 299
 300 __at(0x0FB5) __sfr CVRCON;
 301 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits;
 302
 303 __at(0x0FB6) __sfr ECCP1AS;
 304 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits;
 305
 306 __at(0x0FB7) __sfr CCP3CON;
 307 __at(0x0FB7) volatile __CCP3CONbits_t CCP3CONbits;
 308
 309 __at(0x0FB7) __sfr ECCP3CON;
 310 __at(0x0FB7) volatile __ECCP3CONbits_t ECCP3CONbits;
 311
 312 __at(0x0FB8) __sfr CCPR3;
 313
 314 __at(0x0FB8) __sfr CCPR3L;
 315
 316 __at(0x0FB9) __sfr CCPR3H;
 317
 318 __at(0x0FBA) __sfr CCP2CON;
 319 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits;
 320
 321 __at(0x0FBA) __sfr ECCP2CON;
 322 __at(0x0FBA) volatile __ECCP2CONbits_t ECCP2CONbits;
 323
 324 __at(0x0FBB) __sfr CCPR2;
 325
 326 __at(0x0FBB) __sfr CCPR2L;
 327
 328 __at(0x0FBC) __sfr CCPR2H;
 329
 330 __at(0x0FBD) __sfr CCP1CON;
 331 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits;
 332
 333 __at(0x0FBD) __sfr ECCP1CON;
 334 __at(0x0FBD) volatile __ECCP1CONbits_t ECCP1CONbits;
 335
 336 __at(0x0FBE) __sfr CCPR1;
 337
 338 __at(0x0FBE) __sfr CCPR1L;
 339
 340 __at(0x0FBF) __sfr CCPR1H;
 341
 342 __at(0x0FC0) __sfr ADCON2;
 343 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 344
 345 __at(0x0FC1) __sfr ADCON1;
 346 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 347
 348 __at(0x0FC2) __sfr ADCON0;
 349 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 350
 351 __at(0x0FC3) __sfr ADRES;
 352
 353 __at(0x0FC3) __sfr ADRESL;
 354
 355 __at(0x0FC4) __sfr ADRESH;
 356
 357 __at(0x0FC5) __sfr SSP1CON2;
 358 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits;
 359
 360 __at(0x0FC5) __sfr SSPCON2;
 361 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 362
 363 __at(0x0FC6) __sfr SSP1CON1;
 364 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits;
 365
 366 __at(0x0FC6) __sfr SSPCON1;
 367 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 368
 369 __at(0x0FC7) __sfr SSP1STAT;
 370 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits;
 371
 372 __at(0x0FC7) __sfr SSPSTAT;
 373 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 374
 375 __at(0x0FC8) __sfr SSP1ADD;
 376
 377 __at(0x0FC8) __sfr SSPADD;
 378
 379 __at(0x0FC9) __sfr SSP1BUF;
 380
 381 __at(0x0FC9) __sfr SSPBUF;
 382
 383 __at(0x0FCA) __sfr T2CON;
 384 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 385
 386 __at(0x0FCB) __sfr PR2;
 387
 388 __at(0x0FCC) __sfr TMR2;
 389
 390 __at(0x0FCD) __sfr T1CON;
 391 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 392
 393 __at(0x0FCE) __sfr TMR1;
 394
 395 __at(0x0FCE) __sfr TMR1L;
 396
 397 __at(0x0FCF) __sfr TMR1H;
 398
 399 __at(0x0FD0) __sfr RCON;
 400 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 401
 402 __at(0x0FD1) __sfr WDTCON;
 403 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 404
 405 __at(0x0FD2) __sfr HLVDCON;
 406 __at(0x0FD2) volatile __HLVDCONbits_t HLVDCONbits;
 407
 408 __at(0x0FD2) __sfr LVDCON;
 409 __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits;
 410
 411 __at(0x0FD3) __sfr OSCCON;
 412 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 413
 414 __at(0x0FD5) __sfr T0CON;
 415 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 416
 417 __at(0x0FD6) __sfr TMR0;
 418
 419 __at(0x0FD6) __sfr TMR0L;
 420
 421 __at(0x0FD7) __sfr TMR0H;
 422
 423 __at(0x0FD8) __sfr STATUS;
 424 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 425
 426 __at(0x0FD9) __sfr FSR2L;
 427
 428 __at(0x0FDA) __sfr FSR2H;
 429
 430 __at(0x0FDB) __sfr PLUSW2;
 431
 432 __at(0x0FDC) __sfr PREINC2;
 433
 434 __at(0x0FDD) __sfr POSTDEC2;
 435
 436 __at(0x0FDE) __sfr POSTINC2;
 437
 438 __at(0x0FDF) __sfr INDF2;
 439
 440 __at(0x0FE0) __sfr BSR;
 441
 442 __at(0x0FE1) __sfr FSR1L;
 443
 444 __at(0x0FE2) __sfr FSR1H;
 445
 446 __at(0x0FE3) __sfr PLUSW1;
 447
 448 __at(0x0FE4) __sfr PREINC1;
 449
 450 __at(0x0FE5) __sfr POSTDEC1;
 451
 452 __at(0x0FE6) __sfr POSTINC1;
 453
 454 __at(0x0FE7) __sfr INDF1;
 455
 456 __at(0x0FE8) __sfr WREG;
 457
 458 __at(0x0FE9) __sfr FSR0L;
 459
 460 __at(0x0FEA) __sfr FSR0H;
 461
 462 __at(0x0FEB) __sfr PLUSW0;
 463
 464 __at(0x0FEC) __sfr PREINC0;
 465
 466 __at(0x0FED) __sfr POSTDEC0;
 467
 468 __at(0x0FEE) __sfr POSTINC0;
 469
 470 __at(0x0FEF) __sfr INDF0;
 471
 472 __at(0x0FF0) __sfr INTCON3;
 473 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 474
 475 __at(0x0FF1) __sfr INTCON2;
 476 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 477
 478 __at(0x0FF2) __sfr INTCON;
 479 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 480
 481 __at(0x0FF3) __sfr PROD;
 482
 483 __at(0x0FF3) __sfr PRODL;
 484
 485 __at(0x0FF4) __sfr PRODH;
 486
 487 __at(0x0FF5) __sfr TABLAT;
 488
 489 __at(0x0FF6) __sfr TBLPTR;
 490
 491 __at(0x0FF6) __sfr TBLPTRL;
 492
 493 __at(0x0FF7) __sfr TBLPTRH;
 494
 495 __at(0x0FF8) __sfr TBLPTRU;
 496
 497 __at(0x0FF9) __sfr PC;
 498
 499 __at(0x0FF9) __sfr PCL;
 500
 501 __at(0x0FFA) __sfr PCLATH;
 502
 503 __at(0x0FFB) __sfr PCLATU;
 504
 505 __at(0x0FFC) __sfr STKPTR;
 506 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 507
 508 __at(0x0FFD) __sfr TOS;
 509
 510 __at(0x0FFD) __sfr TOSL;
 511
 512 __at(0x0FFE) __sfr TOSH;
 513
 514 __at(0x0FFF) __sfr TOSU;