sdcc/device/non-free/lib/pic16/libdev/pic18f86j60.c

   1 /*
   2  * This definitions of the PIC18F86J60 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:38 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18f86j60.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0E80) __sfr MAADR5;
  30
  31 __at(0x0E81) __sfr MAADR6;
  32
  33 __at(0x0E82) __sfr MAADR3;
  34
  35 __at(0x0E83) __sfr MAADR4;
  36
  37 __at(0x0E84) __sfr MAADR1;
  38
  39 __at(0x0E85) __sfr MAADR2;
  40
  41 __at(0x0E8A) __sfr MISTAT;
  42 __at(0x0E8A) volatile __MISTATbits_t MISTATbits;
  43
  44 __at(0x0E97) __sfr EFLOCON;
  45 __at(0x0E97) volatile __EFLOCONbits_t EFLOCONbits;
  46
  47 __at(0x0E98) __sfr EPAUS;
  48
  49 __at(0x0E98) __sfr EPAUSL;
  50
  51 __at(0x0E99) __sfr EPAUSH;
  52
  53 __at(0x0EA0) __sfr MACON1;
  54 __at(0x0EA0) volatile __MACON1bits_t MACON1bits;
  55
  56 __at(0x0EA2) __sfr MACON3;
  57 __at(0x0EA2) volatile __MACON3bits_t MACON3bits;
  58
  59 __at(0x0EA3) __sfr MACON4;
  60 __at(0x0EA3) volatile __MACON4bits_t MACON4bits;
  61
  62 __at(0x0EA4) __sfr MABBIPG;
  63 __at(0x0EA4) volatile __MABBIPGbits_t MABBIPGbits;
  64
  65 __at(0x0EA6) __sfr MAIPG;
  66
  67 __at(0x0EA6) __sfr MAIPGL;
  68
  69 __at(0x0EA7) __sfr MAIPGH;
  70
  71 __at(0x0EAA) __sfr MAMXFL;
  72
  73 __at(0x0EAA) __sfr MAMXFLL;
  74
  75 __at(0x0EAB) __sfr MAMXFLH;
  76
  77 __at(0x0EB2) __sfr MICMD;
  78 __at(0x0EB2) volatile __MICMDbits_t MICMDbits;
  79
  80 __at(0x0EB4) __sfr MIREGADR;
  81
  82 __at(0x0EB6) __sfr MIWR;
  83
  84 __at(0x0EB6) __sfr MIWRL;
  85
  86 __at(0x0EB7) __sfr MIWRH;
  87
  88 __at(0x0EB8) __sfr MIRD;
  89
  90 __at(0x0EB8) __sfr MIRDL;
  91
  92 __at(0x0EB9) __sfr MIRDH;
  93
  94 __at(0x0EC0) __sfr EHT0;
  95
  96 __at(0x0EC1) __sfr EHT1;
  97
  98 __at(0x0EC2) __sfr EHT2;
  99
 100 __at(0x0EC3) __sfr EHT3;
 101
 102 __at(0x0EC4) __sfr EHT4;
 103
 104 __at(0x0EC5) __sfr EHT5;
 105
 106 __at(0x0EC6) __sfr EHT6;
 107
 108 __at(0x0EC7) __sfr EHT7;
 109
 110 __at(0x0EC8) __sfr EPMM0;
 111
 112 __at(0x0EC9) __sfr EPMM1;
 113
 114 __at(0x0ECA) __sfr EPMM2;
 115
 116 __at(0x0ECB) __sfr EPMM3;
 117
 118 __at(0x0ECC) __sfr EPMM4;
 119
 120 __at(0x0ECD) __sfr EPMM5;
 121
 122 __at(0x0ECE) __sfr EPMM6;
 123
 124 __at(0x0ECF) __sfr EPMM7;
 125
 126 __at(0x0ED0) __sfr EPMCS;
 127
 128 __at(0x0ED0) __sfr EPMCSL;
 129
 130 __at(0x0ED1) __sfr EPMCSH;
 131
 132 __at(0x0ED4) __sfr EPMO;
 133
 134 __at(0x0ED4) __sfr EPMOL;
 135
 136 __at(0x0ED5) __sfr EPMOH;
 137
 138 __at(0x0ED8) __sfr ERXFCON;
 139 __at(0x0ED8) volatile __ERXFCONbits_t ERXFCONbits;
 140
 141 __at(0x0ED9) __sfr EPKTCNT;
 142
 143 __at(0x0EE2) __sfr EWRPT;
 144
 145 __at(0x0EE2) __sfr EWRPTL;
 146
 147 __at(0x0EE3) __sfr EWRPTH;
 148
 149 __at(0x0EE4) __sfr ETXST;
 150
 151 __at(0x0EE4) __sfr ETXSTL;
 152
 153 __at(0x0EE5) __sfr ETXSTH;
 154
 155 __at(0x0EE6) __sfr ETXND;
 156
 157 __at(0x0EE6) __sfr ETXNDL;
 158
 159 __at(0x0EE7) __sfr ETXNDH;
 160
 161 __at(0x0EE8) __sfr ERXST;
 162
 163 __at(0x0EE8) __sfr ERXSTL;
 164
 165 __at(0x0EE9) __sfr ERXSTH;
 166
 167 __at(0x0EEA) __sfr ERXND;
 168
 169 __at(0x0EEA) __sfr ERXNDL;
 170
 171 __at(0x0EEB) __sfr ERXNDH;
 172
 173 __at(0x0EEC) __sfr ERXRDPT;
 174
 175 __at(0x0EEC) __sfr ERXRDPTL;
 176
 177 __at(0x0EED) __sfr ERXRDPTH;
 178
 179 __at(0x0EEE) __sfr ERXWRPT;
 180
 181 __at(0x0EEE) __sfr ERXWRPTL;
 182
 183 __at(0x0EEF) __sfr ERXWRPTH;
 184
 185 __at(0x0EF0) __sfr EDMAST;
 186
 187 __at(0x0EF0) __sfr EDMASTL;
 188
 189 __at(0x0EF1) __sfr EDMASTH;
 190
 191 __at(0x0EF2) __sfr EDMAND;
 192
 193 __at(0x0EF2) __sfr EDMANDL;
 194
 195 __at(0x0EF3) __sfr EDMANDH;
 196
 197 __at(0x0EF4) __sfr EDMADST;
 198
 199 __at(0x0EF4) __sfr EDMADSTL;
 200
 201 __at(0x0EF5) __sfr EDMADSTH;
 202
 203 __at(0x0EF6) __sfr EDMACS;
 204
 205 __at(0x0EF6) __sfr EDMACSL;
 206
 207 __at(0x0EF7) __sfr EDMACSH;
 208
 209 __at(0x0EFB) __sfr EIE;
 210 __at(0x0EFB) volatile __EIEbits_t EIEbits;
 211
 212 __at(0x0EFD) __sfr ESTAT;
 213 __at(0x0EFD) volatile __ESTATbits_t ESTATbits;
 214
 215 __at(0x0EFE) __sfr ECON2;
 216 __at(0x0EFE) volatile __ECON2bits_t ECON2bits;
 217
 218 __at(0x0F60) __sfr EIR;
 219 __at(0x0F60) volatile __EIRbits_t EIRbits;
 220
 221 __at(0x0F61) __sfr EDATA;
 222 __at(0x0F61) volatile __EDATAbits_t EDATAbits;
 223
 224 __at(0x0F67) __sfr ECCP2DEL;
 225 __at(0x0F67) volatile __ECCP2DELbits_t ECCP2DELbits;
 226
 227 __at(0x0F68) __sfr ECCP2AS;
 228 __at(0x0F68) volatile __ECCP2ASbits_t ECCP2ASbits;
 229
 230 __at(0x0F69) __sfr ECCP3DEL;
 231 __at(0x0F69) volatile __ECCP3DELbits_t ECCP3DELbits;
 232
 233 __at(0x0F6A) __sfr ECCP3AS;
 234 __at(0x0F6A) volatile __ECCP3ASbits_t ECCP3ASbits;
 235
 236 __at(0x0F6B) __sfr RCSTA2;
 237 __at(0x0F6B) volatile __RCSTA2bits_t RCSTA2bits;
 238
 239 __at(0x0F6C) __sfr TXSTA2;
 240 __at(0x0F6C) volatile __TXSTA2bits_t TXSTA2bits;
 241
 242 __at(0x0F6D) __sfr TXREG2;
 243
 244 __at(0x0F6E) __sfr RCREG2;
 245
 246 __at(0x0F6F) __sfr SPBRG2;
 247
 248 __at(0x0F70) __sfr CCP5CON;
 249 __at(0x0F70) volatile __CCP5CONbits_t CCP5CONbits;
 250
 251 __at(0x0F71) __sfr CCPR5;
 252
 253 __at(0x0F71) __sfr CCPR5L;
 254
 255 __at(0x0F72) __sfr CCPR5H;
 256
 257 __at(0x0F73) __sfr CCP4CON;
 258 __at(0x0F73) volatile __CCP4CONbits_t CCP4CONbits;
 259
 260 __at(0x0F74) __sfr CCPR4;
 261
 262 __at(0x0F74) __sfr CCPR4L;
 263
 264 __at(0x0F75) __sfr CCPR4H;
 265
 266 __at(0x0F76) __sfr T4CON;
 267 __at(0x0F76) volatile __T4CONbits_t T4CONbits;
 268
 269 __at(0x0F77) __sfr PR4;
 270
 271 __at(0x0F78) __sfr TMR4;
 272
 273 __at(0x0F79) __sfr ECCP1DEL;
 274 __at(0x0F79) volatile __ECCP1DELbits_t ECCP1DELbits;
 275
 276 __at(0x0F7A) __sfr ERDPT;
 277
 278 __at(0x0F7A) __sfr ERDPTL;
 279
 280 __at(0x0F7B) __sfr ERDPTH;
 281
 282 __at(0x0F7C) __sfr BAUDCON2;
 283 __at(0x0F7C) volatile __BAUDCON2bits_t BAUDCON2bits;
 284
 285 __at(0x0F7C) __sfr BAUDCTL2;
 286 __at(0x0F7C) volatile __BAUDCTL2bits_t BAUDCTL2bits;
 287
 288 __at(0x0F7D) __sfr SPBRGH2;
 289
 290 __at(0x0F7E) __sfr BAUDCON;
 291 __at(0x0F7E) volatile __BAUDCONbits_t BAUDCONbits;
 292
 293 __at(0x0F7E) __sfr BAUDCON1;
 294 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits;
 295
 296 __at(0x0F7E) __sfr BAUDCTL;
 297 __at(0x0F7E) volatile __BAUDCTLbits_t BAUDCTLbits;
 298
 299 __at(0x0F7E) __sfr BAUDCTL1;
 300 __at(0x0F7E) volatile __BAUDCTL1bits_t BAUDCTL1bits;
 301
 302 __at(0x0F7F) __sfr SPBRGH;
 303
 304 __at(0x0F7F) __sfr SPBRGH1;
 305
 306 __at(0x0F80) __sfr PORTA;
 307 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
 308
 309 __at(0x0F81) __sfr PORTB;
 310 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
 311
 312 __at(0x0F82) __sfr PORTC;
 313 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
 314
 315 __at(0x0F83) __sfr PORTD;
 316 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
 317
 318 __at(0x0F84) __sfr PORTE;
 319 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
 320
 321 __at(0x0F85) __sfr PORTF;
 322 __at(0x0F85) volatile __PORTFbits_t PORTFbits;
 323
 324 __at(0x0F86) __sfr PORTG;
 325 __at(0x0F86) volatile __PORTGbits_t PORTGbits;
 326
 327 __at(0x0F87) __sfr PORTH;
 328 __at(0x0F87) volatile __PORTHbits_t PORTHbits;
 329
 330 __at(0x0F88) __sfr PORTJ;
 331 __at(0x0F88) volatile __PORTJbits_t PORTJbits;
 332
 333 __at(0x0F89) __sfr LATA;
 334 __at(0x0F89) volatile __LATAbits_t LATAbits;
 335
 336 __at(0x0F8A) __sfr LATB;
 337 __at(0x0F8A) volatile __LATBbits_t LATBbits;
 338
 339 __at(0x0F8B) __sfr LATC;
 340 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 341
 342 __at(0x0F8C) __sfr LATD;
 343 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 344
 345 __at(0x0F8D) __sfr LATE;
 346 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 347
 348 __at(0x0F8E) __sfr LATF;
 349 __at(0x0F8E) volatile __LATFbits_t LATFbits;
 350
 351 __at(0x0F8F) __sfr LATG;
 352 __at(0x0F8F) volatile __LATGbits_t LATGbits;
 353
 354 __at(0x0F90) __sfr LATH;
 355 __at(0x0F90) volatile __LATHbits_t LATHbits;
 356
 357 __at(0x0F91) __sfr LATJ;
 358 __at(0x0F91) volatile __LATJbits_t LATJbits;
 359
 360 __at(0x0F92) __sfr DDRA;
 361 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
 362
 363 __at(0x0F92) __sfr TRISA;
 364 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 365
 366 __at(0x0F93) __sfr DDRB;
 367 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
 368
 369 __at(0x0F93) __sfr TRISB;
 370 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 371
 372 __at(0x0F94) __sfr DDRC;
 373 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
 374
 375 __at(0x0F94) __sfr TRISC;
 376 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 377
 378 __at(0x0F95) __sfr DDRD;
 379 __at(0x0F95) volatile __DDRDbits_t DDRDbits;
 380
 381 __at(0x0F95) __sfr TRISD;
 382 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 383
 384 __at(0x0F96) __sfr DDRE;
 385 __at(0x0F96) volatile __DDREbits_t DDREbits;
 386
 387 __at(0x0F96) __sfr TRISE;
 388 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 389
 390 __at(0x0F97) __sfr DDRF;
 391 __at(0x0F97) volatile __DDRFbits_t DDRFbits;
 392
 393 __at(0x0F97) __sfr TRISF;
 394 __at(0x0F97) volatile __TRISFbits_t TRISFbits;
 395
 396 __at(0x0F98) __sfr DDRG;
 397 __at(0x0F98) volatile __DDRGbits_t DDRGbits;
 398
 399 __at(0x0F98) __sfr TRISG;
 400 __at(0x0F98) volatile __TRISGbits_t TRISGbits;
 401
 402 __at(0x0F99) __sfr DDRH;
 403 __at(0x0F99) volatile __DDRHbits_t DDRHbits;
 404
 405 __at(0x0F99) __sfr TRISH;
 406 __at(0x0F99) volatile __TRISHbits_t TRISHbits;
 407
 408 __at(0x0F9A) __sfr DDRJ;
 409 __at(0x0F9A) volatile __DDRJbits_t DDRJbits;
 410
 411 __at(0x0F9A) __sfr TRISJ;
 412 __at(0x0F9A) volatile __TRISJbits_t TRISJbits;
 413
 414 __at(0x0F9B) __sfr OSCTUNE;
 415 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 416
 417 __at(0x0F9D) __sfr PIE1;
 418 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 419
 420 __at(0x0F9E) __sfr PIR1;
 421 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 422
 423 __at(0x0F9F) __sfr IPR1;
 424 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 425
 426 __at(0x0FA0) __sfr PIE2;
 427 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 428
 429 __at(0x0FA1) __sfr PIR2;
 430 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 431
 432 __at(0x0FA2) __sfr IPR2;
 433 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 434
 435 __at(0x0FA3) __sfr PIE3;
 436 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 437
 438 __at(0x0FA4) __sfr PIR3;
 439 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 440
 441 __at(0x0FA5) __sfr IPR3;
 442 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 443
 444 __at(0x0FA6) __sfr EECON1;
 445 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 446
 447 __at(0x0FA7) __sfr EECON2;
 448
 449 __at(0x0FAB) __sfr RCSTA;
 450 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 451
 452 __at(0x0FAB) __sfr RCSTA1;
 453 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits;
 454
 455 __at(0x0FAC) __sfr TXSTA;
 456 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 457
 458 __at(0x0FAC) __sfr TXSTA1;
 459 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits;
 460
 461 __at(0x0FAD) __sfr TXREG;
 462
 463 __at(0x0FAD) __sfr TXREG1;
 464
 465 __at(0x0FAE) __sfr RCREG;
 466
 467 __at(0x0FAE) __sfr RCREG1;
 468
 469 __at(0x0FAF) __sfr SPBRG;
 470
 471 __at(0x0FAF) __sfr SPBRG1;
 472
 473 __at(0x0FB1) __sfr T3CON;
 474 __at(0x0FB1) volatile __T3CONbits_t T3CONbits;
 475
 476 __at(0x0FB2) __sfr TMR3;
 477
 478 __at(0x0FB2) __sfr TMR3L;
 479
 480 __at(0x0FB3) __sfr TMR3H;
 481
 482 __at(0x0FB4) __sfr CMCON;
 483 __at(0x0FB4) volatile __CMCONbits_t CMCONbits;
 484
 485 __at(0x0FB5) __sfr CVRCON;
 486 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits;
 487
 488 __at(0x0FB6) __sfr ECCP1AS;
 489 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits;
 490
 491 __at(0x0FB7) __sfr CCP3CON;
 492 __at(0x0FB7) volatile __CCP3CONbits_t CCP3CONbits;
 493
 494 __at(0x0FB7) __sfr ECCP3CON;
 495 __at(0x0FB7) volatile __ECCP3CONbits_t ECCP3CONbits;
 496
 497 __at(0x0FB8) __sfr CCPR3;
 498
 499 __at(0x0FB8) __sfr CCPR3L;
 500
 501 __at(0x0FB9) __sfr CCPR3H;
 502
 503 __at(0x0FBA) __sfr CCP2CON;
 504 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits;
 505
 506 __at(0x0FBA) __sfr ECCP2CON;
 507 __at(0x0FBA) volatile __ECCP2CONbits_t ECCP2CONbits;
 508
 509 __at(0x0FBB) __sfr CCPR2;
 510
 511 __at(0x0FBB) __sfr CCPR2L;
 512
 513 __at(0x0FBC) __sfr CCPR2H;
 514
 515 __at(0x0FBD) __sfr CCP1CON;
 516 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits;
 517
 518 __at(0x0FBD) __sfr ECCP1CON;
 519 __at(0x0FBD) volatile __ECCP1CONbits_t ECCP1CONbits;
 520
 521 __at(0x0FBE) __sfr CCPR1;
 522
 523 __at(0x0FBE) __sfr CCPR1L;
 524
 525 __at(0x0FBF) __sfr CCPR1H;
 526
 527 __at(0x0FC0) __sfr ADCON2;
 528 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 529
 530 __at(0x0FC1) __sfr ADCON1;
 531 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 532
 533 __at(0x0FC2) __sfr ADCON0;
 534 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 535
 536 __at(0x0FC3) __sfr ADRES;
 537
 538 __at(0x0FC3) __sfr ADRESL;
 539
 540 __at(0x0FC4) __sfr ADRESH;
 541
 542 __at(0x0FC5) __sfr SSP1CON2;
 543 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits;
 544
 545 __at(0x0FC5) __sfr SSPCON2;
 546 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 547
 548 __at(0x0FC6) __sfr SSP1CON1;
 549 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits;
 550
 551 __at(0x0FC6) __sfr SSPCON1;
 552 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 553
 554 __at(0x0FC7) __sfr SSP1STAT;
 555 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits;
 556
 557 __at(0x0FC7) __sfr SSPSTAT;
 558 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 559
 560 __at(0x0FC8) __sfr SSP1ADD;
 561
 562 __at(0x0FC8) __sfr SSPADD;
 563
 564 __at(0x0FC9) __sfr SSP1BUF;
 565
 566 __at(0x0FC9) __sfr SSPBUF;
 567
 568 __at(0x0FCA) __sfr T2CON;
 569 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 570
 571 __at(0x0FCB) __sfr PR2;
 572
 573 __at(0x0FCC) __sfr TMR2;
 574
 575 __at(0x0FCD) __sfr T1CON;
 576 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 577
 578 __at(0x0FCE) __sfr TMR1;
 579
 580 __at(0x0FCE) __sfr TMR1L;
 581
 582 __at(0x0FCF) __sfr TMR1H;
 583
 584 __at(0x0FD0) __sfr RCON;
 585 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 586
 587 __at(0x0FD1) __sfr WDTCON;
 588 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 589
 590 __at(0x0FD2) __sfr ECON1;
 591 __at(0x0FD2) volatile __ECON1bits_t ECON1bits;
 592
 593 __at(0x0FD3) __sfr OSCCON;
 594 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 595
 596 __at(0x0FD5) __sfr T0CON;
 597 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 598
 599 __at(0x0FD6) __sfr TMR0;
 600
 601 __at(0x0FD6) __sfr TMR0L;
 602
 603 __at(0x0FD7) __sfr TMR0H;
 604
 605 __at(0x0FD8) __sfr STATUS;
 606 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 607
 608 __at(0x0FD9) __sfr FSR2L;
 609
 610 __at(0x0FDA) __sfr FSR2H;
 611
 612 __at(0x0FDB) __sfr PLUSW2;
 613
 614 __at(0x0FDC) __sfr PREINC2;
 615
 616 __at(0x0FDD) __sfr POSTDEC2;
 617
 618 __at(0x0FDE) __sfr POSTINC2;
 619
 620 __at(0x0FDF) __sfr INDF2;
 621
 622 __at(0x0FE0) __sfr BSR;
 623
 624 __at(0x0FE1) __sfr FSR1L;
 625
 626 __at(0x0FE2) __sfr FSR1H;
 627
 628 __at(0x0FE3) __sfr PLUSW1;
 629
 630 __at(0x0FE4) __sfr PREINC1;
 631
 632 __at(0x0FE5) __sfr POSTDEC1;
 633
 634 __at(0x0FE6) __sfr POSTINC1;
 635
 636 __at(0x0FE7) __sfr INDF1;
 637
 638 __at(0x0FE8) __sfr WREG;
 639
 640 __at(0x0FE9) __sfr FSR0L;
 641
 642 __at(0x0FEA) __sfr FSR0H;
 643
 644 __at(0x0FEB) __sfr PLUSW0;
 645
 646 __at(0x0FEC) __sfr PREINC0;
 647
 648 __at(0x0FED) __sfr POSTDEC0;
 649
 650 __at(0x0FEE) __sfr POSTINC0;
 651
 652 __at(0x0FEF) __sfr INDF0;
 653
 654 __at(0x0FF0) __sfr INTCON3;
 655 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 656
 657 __at(0x0FF1) __sfr INTCON2;
 658 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 659
 660 __at(0x0FF2) __sfr INTCON;
 661 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 662
 663 __at(0x0FF3) __sfr PROD;
 664
 665 __at(0x0FF3) __sfr PRODL;
 666
 667 __at(0x0FF4) __sfr PRODH;
 668
 669 __at(0x0FF5) __sfr TABLAT;
 670
 671 __at(0x0FF6) __sfr TBLPTR;
 672
 673 __at(0x0FF6) __sfr TBLPTRL;
 674
 675 __at(0x0FF7) __sfr TBLPTRH;
 676
 677 __at(0x0FF8) __sfr TBLPTRU;
 678
 679 __at(0x0FF9) __sfr PC;
 680
 681 __at(0x0FF9) __sfr PCL;
 682
 683 __at(0x0FFA) __sfr PCLATH;
 684
 685 __at(0x0FFB) __sfr PCLATU;
 686
 687 __at(0x0FFC) __sfr STKPTR;
 688 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 689
 690 __at(0x0FFD) __sfr TOS;
 691
 692 __at(0x0FFD) __sfr TOSL;
 693
 694 __at(0x0FFE) __sfr TOSH;
 695
 696 __at(0x0FFF) __sfr TOSU;