sdcc/device/non-free/lib/pic16/libdev/pic18f86k22.c

   1 /*
   2  * This definitions of the PIC18F86K22 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:39 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18f86k22.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F16) __sfr PMD3;
  30 __at(0x0F16) volatile __PMD3bits_t PMD3bits;
  31
  32 __at(0x0F17) __sfr PMD2;
  33 __at(0x0F17) volatile __PMD2bits_t PMD2bits;
  34
  35 __at(0x0F18) __sfr PMD1;
  36 __at(0x0F18) volatile __PMD1bits_t PMD1bits;
  37
  38 __at(0x0F19) __sfr PMD0;
  39 __at(0x0F19) volatile __PMD0bits_t PMD0bits;
  40
  41 __at(0x0F1A) __sfr PSTR3CON;
  42 __at(0x0F1A) volatile __PSTR3CONbits_t PSTR3CONbits;
  43
  44 __at(0x0F1B) __sfr PSTR2CON;
  45 __at(0x0F1B) volatile __PSTR2CONbits_t PSTR2CONbits;
  46
  47 __at(0x0F1C) __sfr TXREG2;
  48
  49 __at(0x0F1D) __sfr RCREG2;
  50
  51 __at(0x0F1E) __sfr SPBRG2;
  52
  53 __at(0x0F1F) __sfr SPBRGH2;
  54
  55 __at(0x0F20) __sfr BAUDCON2;
  56 __at(0x0F20) volatile __BAUDCON2bits_t BAUDCON2bits;
  57
  58 __at(0x0F21) __sfr TXSTA2;
  59 __at(0x0F21) volatile __TXSTA2bits_t TXSTA2bits;
  60
  61 __at(0x0F22) __sfr RCSTA2;
  62 __at(0x0F22) volatile __RCSTA2bits_t RCSTA2bits;
  63
  64 __at(0x0F23) __sfr ANCON2;
  65 __at(0x0F23) volatile __ANCON2bits_t ANCON2bits;
  66
  67 __at(0x0F24) __sfr ANCON1;
  68 __at(0x0F24) volatile __ANCON1bits_t ANCON1bits;
  69
  70 __at(0x0F25) __sfr ANCON0;
  71 __at(0x0F25) volatile __ANCON0bits_t ANCON0bits;
  72
  73 __at(0x0F26) __sfr MEMCON;
  74 __at(0x0F26) volatile __MEMCONbits_t MEMCONbits;
  75
  76 __at(0x0F27) __sfr ODCON3;
  77 __at(0x0F27) volatile __ODCON3bits_t ODCON3bits;
  78
  79 __at(0x0F28) __sfr ODCON2;
  80 __at(0x0F28) volatile __ODCON2bits_t ODCON2bits;
  81
  82 __at(0x0F29) __sfr ODCON1;
  83 __at(0x0F29) volatile __ODCON1bits_t ODCON1bits;
  84
  85 __at(0x0F2A) __sfr REFOCON;
  86 __at(0x0F2A) volatile __REFOCONbits_t REFOCONbits;
  87
  88 __at(0x0F2B) __sfr CCPTMRS2;
  89 __at(0x0F2B) volatile __CCPTMRS2bits_t CCPTMRS2bits;
  90
  91 __at(0x0F2C) __sfr CCPTMRS1;
  92 __at(0x0F2C) volatile __CCPTMRS1bits_t CCPTMRS1bits;
  93
  94 __at(0x0F2D) __sfr CCPTMRS0;
  95 __at(0x0F2D) volatile __CCPTMRS0bits_t CCPTMRS0bits;
  96
  97 __at(0x0F2E) __sfr CM3CON;
  98 __at(0x0F2E) volatile __CM3CONbits_t CM3CONbits;
  99
 100 __at(0x0F2E) __sfr CM3CON1;
 101 __at(0x0F2E) volatile __CM3CON1bits_t CM3CON1bits;
 102
 103 __at(0x0F2F) __sfr CM2CON;
 104 __at(0x0F2F) volatile __CM2CONbits_t CM2CONbits;
 105
 106 __at(0x0F2F) __sfr CM2CON1;
 107 __at(0x0F2F) volatile __CM2CON1bits_t CM2CON1bits;
 108
 109 __at(0x0F30) __sfr T12CON;
 110 __at(0x0F30) volatile __T12CONbits_t T12CONbits;
 111
 112 __at(0x0F31) __sfr PR12;
 113
 114 __at(0x0F32) __sfr TMR12;
 115
 116 __at(0x0F33) __sfr T10CON;
 117 __at(0x0F33) volatile __T10CONbits_t T10CONbits;
 118
 119 __at(0x0F34) __sfr PR10;
 120
 121 __at(0x0F35) __sfr TMR10;
 122
 123 __at(0x0F36) __sfr T8CON;
 124 __at(0x0F36) volatile __T8CONbits_t T8CONbits;
 125
 126 __at(0x0F37) __sfr PR8;
 127
 128 __at(0x0F38) __sfr TMR8;
 129
 130 __at(0x0F39) __sfr T6CON;
 131 __at(0x0F39) volatile __T6CONbits_t T6CONbits;
 132
 133 __at(0x0F3A) __sfr PR6;
 134
 135 __at(0x0F3B) __sfr TMR6;
 136
 137 __at(0x0F3C) __sfr T7GCON;
 138 __at(0x0F3C) volatile __T7GCONbits_t T7GCONbits;
 139
 140 __at(0x0F3D) __sfr T7CON;
 141 __at(0x0F3D) volatile __T7CONbits_t T7CONbits;
 142
 143 __at(0x0F3E) __sfr TMR7;
 144
 145 __at(0x0F3E) __sfr TMR7L;
 146
 147 __at(0x0F3F) __sfr TMR7H;
 148
 149 __at(0x0F40) __sfr CCP10CON;
 150 __at(0x0F40) volatile __CCP10CONbits_t CCP10CONbits;
 151
 152 __at(0x0F41) __sfr CCPR10;
 153
 154 __at(0x0F41) __sfr CCPR10L;
 155
 156 __at(0x0F42) __sfr CCPR10H;
 157
 158 __at(0x0F43) __sfr CCP9CON;
 159 __at(0x0F43) volatile __CCP9CONbits_t CCP9CONbits;
 160
 161 __at(0x0F44) __sfr CCPR9;
 162
 163 __at(0x0F44) __sfr CCPR9L;
 164
 165 __at(0x0F45) __sfr CCPR9H;
 166
 167 __at(0x0F46) __sfr CCP8CON;
 168 __at(0x0F46) volatile __CCP8CONbits_t CCP8CONbits;
 169
 170 __at(0x0F47) __sfr CCPR8;
 171
 172 __at(0x0F47) __sfr CCPR8L;
 173
 174 __at(0x0F48) __sfr CCPR8H;
 175
 176 __at(0x0F49) __sfr CCP3CON;
 177 __at(0x0F49) volatile __CCP3CONbits_t CCP3CONbits;
 178
 179 __at(0x0F4A) __sfr CCPR3;
 180
 181 __at(0x0F4A) __sfr CCPR3L;
 182
 183 __at(0x0F4B) __sfr CCPR3H;
 184
 185 __at(0x0F4C) __sfr ECCP3DEL;
 186 __at(0x0F4C) volatile __ECCP3DELbits_t ECCP3DELbits;
 187
 188 __at(0x0F4D) __sfr ECCP3AS;
 189 __at(0x0F4D) volatile __ECCP3ASbits_t ECCP3ASbits;
 190
 191 __at(0x0F4E) __sfr CCP2CON;
 192 __at(0x0F4E) volatile __CCP2CONbits_t CCP2CONbits;
 193
 194 __at(0x0F4E) __sfr ECCP2CON;
 195 __at(0x0F4E) volatile __ECCP2CONbits_t ECCP2CONbits;
 196
 197 __at(0x0F4F) __sfr CCPR2;
 198
 199 __at(0x0F4F) __sfr CCPR2L;
 200
 201 __at(0x0F50) __sfr CCPR2H;
 202
 203 __at(0x0F51) __sfr ECCP2DEL;
 204 __at(0x0F51) volatile __ECCP2DELbits_t ECCP2DELbits;
 205
 206 __at(0x0F51) __sfr PWM2CON;
 207 __at(0x0F51) volatile __PWM2CONbits_t PWM2CONbits;
 208
 209 __at(0x0F52) __sfr ECCP2AS;
 210 __at(0x0F52) volatile __ECCP2ASbits_t ECCP2ASbits;
 211
 212 __at(0x0F53) __sfr PADCFG1;
 213 __at(0x0F53) volatile __PADCFG1bits_t PADCFG1bits;
 214
 215 __at(0x0F54) __sfr CM1CON;
 216 __at(0x0F54) volatile __CM1CONbits_t CM1CONbits;
 217
 218 __at(0x0F54) __sfr CM1CON1;
 219 __at(0x0F54) volatile __CM1CON1bits_t CM1CON1bits;
 220
 221 __at(0x0F55) __sfr CTMUICON;
 222 __at(0x0F55) volatile __CTMUICONbits_t CTMUICONbits;
 223
 224 __at(0x0F56) __sfr CTMUCONL;
 225 __at(0x0F56) volatile __CTMUCONLbits_t CTMUCONLbits;
 226
 227 __at(0x0F57) __sfr CTMUCONH;
 228 __at(0x0F57) volatile __CTMUCONHbits_t CTMUCONHbits;
 229
 230 __at(0x0F58) __sfr ALRMVAL;
 231
 232 __at(0x0F58) __sfr ALRMVALL;
 233
 234 __at(0x0F59) __sfr ALRMVALH;
 235
 236 __at(0x0F5A) __sfr ALRMRPT;
 237 __at(0x0F5A) volatile __ALRMRPTbits_t ALRMRPTbits;
 238
 239 __at(0x0F5B) __sfr ALRMCFG;
 240 __at(0x0F5B) volatile __ALRMCFGbits_t ALRMCFGbits;
 241
 242 __at(0x0F5C) __sfr RTCVAL;
 243
 244 __at(0x0F5C) __sfr RTCVALL;
 245
 246 __at(0x0F5D) __sfr RTCVALH;
 247
 248 __at(0x0F5E) __sfr RTCCAL;
 249 __at(0x0F5E) volatile __RTCCALbits_t RTCCALbits;
 250
 251 __at(0x0F5F) __sfr RTCCFG;
 252 __at(0x0F5F) volatile __RTCCFGbits_t RTCCFGbits;
 253
 254 __at(0x0F60) __sfr PIE6;
 255 __at(0x0F60) volatile __PIE6bits_t PIE6bits;
 256
 257 __at(0x0F61) __sfr EEDATA;
 258
 259 __at(0x0F62) __sfr EEADR;
 260
 261 __at(0x0F63) __sfr EEADRH;
 262
 263 __at(0x0F64) __sfr OSCCON2;
 264 __at(0x0F64) volatile __OSCCON2bits_t OSCCON2bits;
 265
 266 __at(0x0F65) __sfr BAUDCON;
 267 __at(0x0F65) volatile __BAUDCONbits_t BAUDCONbits;
 268
 269 __at(0x0F65) __sfr BAUDCON1;
 270 __at(0x0F65) volatile __BAUDCON1bits_t BAUDCON1bits;
 271
 272 __at(0x0F65) __sfr BAUDCTL;
 273 __at(0x0F65) volatile __BAUDCTLbits_t BAUDCTLbits;
 274
 275 __at(0x0F66) __sfr SSP2CON2;
 276 __at(0x0F66) volatile __SSP2CON2bits_t SSP2CON2bits;
 277
 278 __at(0x0F67) __sfr SSP2CON1;
 279 __at(0x0F67) volatile __SSP2CON1bits_t SSP2CON1bits;
 280
 281 __at(0x0F68) __sfr SSP2STAT;
 282 __at(0x0F68) volatile __SSP2STATbits_t SSP2STATbits;
 283
 284 __at(0x0F69) __sfr SSP2ADD;
 285
 286 __at(0x0F69) __sfr SSP2MSK;
 287 __at(0x0F69) volatile __SSP2MSKbits_t SSP2MSKbits;
 288
 289 __at(0x0F6A) __sfr SSP2BUF;
 290
 291 __at(0x0F6B) __sfr T4CON;
 292 __at(0x0F6B) volatile __T4CONbits_t T4CONbits;
 293
 294 __at(0x0F6C) __sfr PR4;
 295
 296 __at(0x0F6D) __sfr TMR4;
 297
 298 __at(0x0F6E) __sfr CCP7CON;
 299 __at(0x0F6E) volatile __CCP7CONbits_t CCP7CONbits;
 300
 301 __at(0x0F6F) __sfr CCPR7;
 302
 303 __at(0x0F6F) __sfr CCPR7L;
 304
 305 __at(0x0F70) __sfr CCPR7H;
 306
 307 __at(0x0F71) __sfr CCP6CON;
 308 __at(0x0F71) volatile __CCP6CONbits_t CCP6CONbits;
 309
 310 __at(0x0F72) __sfr CCPR6;
 311
 312 __at(0x0F72) __sfr CCPR6L;
 313
 314 __at(0x0F73) __sfr CCPR6H;
 315
 316 __at(0x0F74) __sfr CCP5CON;
 317 __at(0x0F74) volatile __CCP5CONbits_t CCP5CONbits;
 318
 319 __at(0x0F75) __sfr CCPR5;
 320
 321 __at(0x0F75) __sfr CCPR5L;
 322
 323 __at(0x0F76) __sfr CCPR5H;
 324
 325 __at(0x0F77) __sfr CCP4CON;
 326 __at(0x0F77) volatile __CCP4CONbits_t CCP4CONbits;
 327
 328 __at(0x0F78) __sfr CCPR4;
 329
 330 __at(0x0F78) __sfr CCPR4L;
 331
 332 __at(0x0F79) __sfr CCPR4H;
 333
 334 __at(0x0F7A) __sfr T5GCON;
 335 __at(0x0F7A) volatile __T5GCONbits_t T5GCONbits;
 336
 337 __at(0x0F7B) __sfr T5CON;
 338 __at(0x0F7B) volatile __T5CONbits_t T5CONbits;
 339
 340 __at(0x0F7C) __sfr TMR5;
 341
 342 __at(0x0F7C) __sfr TMR5L;
 343
 344 __at(0x0F7D) __sfr TMR5H;
 345
 346 __at(0x0F7E) __sfr EECON2;
 347
 348 __at(0x0F7F) __sfr EECON1;
 349 __at(0x0F7F) volatile __EECON1bits_t EECON1bits;
 350
 351 __at(0x0F80) __sfr PORTA;
 352 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
 353
 354 __at(0x0F81) __sfr PORTB;
 355 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
 356
 357 __at(0x0F82) __sfr PORTC;
 358 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
 359
 360 __at(0x0F83) __sfr PORTD;
 361 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
 362
 363 __at(0x0F84) __sfr PORTE;
 364 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
 365
 366 __at(0x0F85) __sfr PORTF;
 367 __at(0x0F85) volatile __PORTFbits_t PORTFbits;
 368
 369 __at(0x0F86) __sfr PORTG;
 370 __at(0x0F86) volatile __PORTGbits_t PORTGbits;
 371
 372 __at(0x0F87) __sfr PORTH;
 373 __at(0x0F87) volatile __PORTHbits_t PORTHbits;
 374
 375 __at(0x0F88) __sfr PORTJ;
 376 __at(0x0F88) volatile __PORTJbits_t PORTJbits;
 377
 378 __at(0x0F89) __sfr LATA;
 379 __at(0x0F89) volatile __LATAbits_t LATAbits;
 380
 381 __at(0x0F8A) __sfr LATB;
 382 __at(0x0F8A) volatile __LATBbits_t LATBbits;
 383
 384 __at(0x0F8B) __sfr LATC;
 385 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 386
 387 __at(0x0F8C) __sfr LATD;
 388 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 389
 390 __at(0x0F8D) __sfr LATE;
 391 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 392
 393 __at(0x0F8E) __sfr LATF;
 394 __at(0x0F8E) volatile __LATFbits_t LATFbits;
 395
 396 __at(0x0F8F) __sfr LATG;
 397 __at(0x0F8F) volatile __LATGbits_t LATGbits;
 398
 399 __at(0x0F90) __sfr LATH;
 400 __at(0x0F90) volatile __LATHbits_t LATHbits;
 401
 402 __at(0x0F91) __sfr LATJ;
 403 __at(0x0F91) volatile __LATJbits_t LATJbits;
 404
 405 __at(0x0F92) __sfr TRISA;
 406 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 407
 408 __at(0x0F93) __sfr TRISB;
 409 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 410
 411 __at(0x0F94) __sfr TRISC;
 412 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 413
 414 __at(0x0F95) __sfr TRISD;
 415 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 416
 417 __at(0x0F96) __sfr TRISE;
 418 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 419
 420 __at(0x0F97) __sfr TRISF;
 421 __at(0x0F97) volatile __TRISFbits_t TRISFbits;
 422
 423 __at(0x0F98) __sfr TRISG;
 424 __at(0x0F98) volatile __TRISGbits_t TRISGbits;
 425
 426 __at(0x0F99) __sfr TRISH;
 427 __at(0x0F99) volatile __TRISHbits_t TRISHbits;
 428
 429 __at(0x0F9A) __sfr TRISJ;
 430 __at(0x0F9A) volatile __TRISJbits_t TRISJbits;
 431
 432 __at(0x0F9B) __sfr OSCTUNE;
 433 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 434
 435 __at(0x0F9C) __sfr PSTR1CON;
 436 __at(0x0F9C) volatile __PSTR1CONbits_t PSTR1CONbits;
 437
 438 __at(0x0F9D) __sfr PIE1;
 439 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 440
 441 __at(0x0F9E) __sfr PIR1;
 442 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 443
 444 __at(0x0F9F) __sfr IPR1;
 445 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 446
 447 __at(0x0FA0) __sfr PIE2;
 448 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 449
 450 __at(0x0FA1) __sfr PIR2;
 451 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 452
 453 __at(0x0FA2) __sfr IPR2;
 454 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 455
 456 __at(0x0FA3) __sfr PIE3;
 457 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 458
 459 __at(0x0FA4) __sfr PIR3;
 460 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 461
 462 __at(0x0FA5) __sfr IPR3;
 463 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 464
 465 __at(0x0FA6) __sfr PIR6;
 466 __at(0x0FA6) volatile __PIR6bits_t PIR6bits;
 467
 468 __at(0x0FA7) __sfr PSPCON;
 469 __at(0x0FA7) volatile __PSPCONbits_t PSPCONbits;
 470
 471 __at(0x0FA8) __sfr HLVDCON;
 472 __at(0x0FA8) volatile __HLVDCONbits_t HLVDCONbits;
 473
 474 __at(0x0FA9) __sfr IPR6;
 475 __at(0x0FA9) volatile __IPR6bits_t IPR6bits;
 476
 477 __at(0x0FAA) __sfr T1GCON;
 478 __at(0x0FAA) volatile __T1GCONbits_t T1GCONbits;
 479
 480 __at(0x0FAB) __sfr RCSTA;
 481 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 482
 483 __at(0x0FAB) __sfr RCSTA1;
 484 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits;
 485
 486 __at(0x0FAC) __sfr TXSTA;
 487 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 488
 489 __at(0x0FAC) __sfr TXSTA1;
 490 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits;
 491
 492 __at(0x0FAD) __sfr TXREG;
 493
 494 __at(0x0FAD) __sfr TXREG1;
 495
 496 __at(0x0FAE) __sfr RCREG;
 497
 498 __at(0x0FAE) __sfr RCREG1;
 499
 500 __at(0x0FAF) __sfr SPBRG;
 501
 502 __at(0x0FAF) __sfr SPBRG1;
 503
 504 __at(0x0FB0) __sfr T3GCON;
 505 __at(0x0FB0) volatile __T3GCONbits_t T3GCONbits;
 506
 507 __at(0x0FB1) __sfr T3CON;
 508 __at(0x0FB1) volatile __T3CONbits_t T3CONbits;
 509
 510 __at(0x0FB2) __sfr TMR3;
 511
 512 __at(0x0FB2) __sfr TMR3L;
 513
 514 __at(0x0FB3) __sfr TMR3H;
 515
 516 __at(0x0FB4) __sfr CMSTAT;
 517 __at(0x0FB4) volatile __CMSTATbits_t CMSTATbits;
 518
 519 __at(0x0FB4) __sfr CMSTATUS;
 520 __at(0x0FB4) volatile __CMSTATUSbits_t CMSTATUSbits;
 521
 522 __at(0x0FB5) __sfr CVRCON;
 523 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits;
 524
 525 __at(0x0FB6) __sfr PIE4;
 526 __at(0x0FB6) volatile __PIE4bits_t PIE4bits;
 527
 528 __at(0x0FB7) __sfr PIR4;
 529 __at(0x0FB7) volatile __PIR4bits_t PIR4bits;
 530
 531 __at(0x0FB8) __sfr IPR4;
 532 __at(0x0FB8) volatile __IPR4bits_t IPR4bits;
 533
 534 __at(0x0FB9) __sfr PIE5;
 535 __at(0x0FB9) volatile __PIE5bits_t PIE5bits;
 536
 537 __at(0x0FBA) __sfr PIR5;
 538 __at(0x0FBA) volatile __PIR5bits_t PIR5bits;
 539
 540 __at(0x0FBB) __sfr CCP1CON;
 541 __at(0x0FBB) volatile __CCP1CONbits_t CCP1CONbits;
 542
 543 __at(0x0FBB) __sfr ECCP1CON;
 544 __at(0x0FBB) volatile __ECCP1CONbits_t ECCP1CONbits;
 545
 546 __at(0x0FBC) __sfr CCPR1;
 547
 548 __at(0x0FBC) __sfr CCPR1L;
 549
 550 __at(0x0FBD) __sfr CCPR1H;
 551
 552 __at(0x0FBE) __sfr ECCP1DEL;
 553 __at(0x0FBE) volatile __ECCP1DELbits_t ECCP1DELbits;
 554
 555 __at(0x0FBE) __sfr PWM1CON;
 556 __at(0x0FBE) volatile __PWM1CONbits_t PWM1CONbits;
 557
 558 __at(0x0FBF) __sfr ECCP1AS;
 559 __at(0x0FBF) volatile __ECCP1ASbits_t ECCP1ASbits;
 560
 561 __at(0x0FC0) __sfr ADCON2;
 562 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 563
 564 __at(0x0FC1) __sfr ADCON1;
 565 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 566
 567 __at(0x0FC2) __sfr ADCON0;
 568 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 569
 570 __at(0x0FC3) __sfr ADRES;
 571
 572 __at(0x0FC3) __sfr ADRESL;
 573
 574 __at(0x0FC4) __sfr ADRESH;
 575
 576 __at(0x0FC5) __sfr SSP1CON2;
 577 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits;
 578
 579 __at(0x0FC5) __sfr SSPCON2;
 580 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 581
 582 __at(0x0FC6) __sfr SSP1CON1;
 583 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits;
 584
 585 __at(0x0FC6) __sfr SSPCON1;
 586 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 587
 588 __at(0x0FC7) __sfr SSP1STAT;
 589 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits;
 590
 591 __at(0x0FC7) __sfr SSPSTAT;
 592 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 593
 594 __at(0x0FC8) __sfr SSP1ADD;
 595
 596 __at(0x0FC8) __sfr SSP1MSK;
 597 __at(0x0FC8) volatile __SSP1MSKbits_t SSP1MSKbits;
 598
 599 __at(0x0FC8) __sfr SSPADD;
 600
 601 __at(0x0FC9) __sfr SSP1BUF;
 602
 603 __at(0x0FC9) __sfr SSPBUF;
 604
 605 __at(0x0FCA) __sfr T2CON;
 606 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 607
 608 __at(0x0FCB) __sfr PR2;
 609
 610 __at(0x0FCC) __sfr TMR2;
 611
 612 __at(0x0FCD) __sfr T1CON;
 613 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 614
 615 __at(0x0FCE) __sfr TMR1;
 616
 617 __at(0x0FCE) __sfr TMR1L;
 618
 619 __at(0x0FCF) __sfr TMR1H;
 620
 621 __at(0x0FD0) __sfr RCON;
 622 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 623
 624 __at(0x0FD1) __sfr WDTCON;
 625 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 626
 627 __at(0x0FD2) __sfr IPR5;
 628 __at(0x0FD2) volatile __IPR5bits_t IPR5bits;
 629
 630 __at(0x0FD3) __sfr OSCCON;
 631 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 632
 633 __at(0x0FD4) __sfr SPBRGH1;
 634
 635 __at(0x0FD5) __sfr T0CON;
 636 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 637
 638 __at(0x0FD6) __sfr TMR0;
 639
 640 __at(0x0FD6) __sfr TMR0L;
 641
 642 __at(0x0FD7) __sfr TMR0H;
 643
 644 __at(0x0FD8) __sfr STATUS;
 645 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 646
 647 __at(0x0FD9) __sfr FSR2L;
 648
 649 __at(0x0FDA) __sfr FSR2H;
 650
 651 __at(0x0FDB) __sfr PLUSW2;
 652
 653 __at(0x0FDC) __sfr PREINC2;
 654
 655 __at(0x0FDD) __sfr POSTDEC2;
 656
 657 __at(0x0FDE) __sfr POSTINC2;
 658
 659 __at(0x0FDF) __sfr INDF2;
 660
 661 __at(0x0FE0) __sfr BSR;
 662
 663 __at(0x0FE1) __sfr FSR1L;
 664
 665 __at(0x0FE2) __sfr FSR1H;
 666
 667 __at(0x0FE3) __sfr PLUSW1;
 668
 669 __at(0x0FE4) __sfr PREINC1;
 670
 671 __at(0x0FE5) __sfr POSTDEC1;
 672
 673 __at(0x0FE6) __sfr POSTINC1;
 674
 675 __at(0x0FE7) __sfr INDF1;
 676
 677 __at(0x0FE8) __sfr WREG;
 678
 679 __at(0x0FE9) __sfr FSR0L;
 680
 681 __at(0x0FEA) __sfr FSR0H;
 682
 683 __at(0x0FEB) __sfr PLUSW0;
 684
 685 __at(0x0FEC) __sfr PREINC0;
 686
 687 __at(0x0FED) __sfr POSTDEC0;
 688
 689 __at(0x0FEE) __sfr POSTINC0;
 690
 691 __at(0x0FEF) __sfr INDF0;
 692
 693 __at(0x0FF0) __sfr INTCON3;
 694 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 695
 696 __at(0x0FF1) __sfr INTCON2;
 697 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 698
 699 __at(0x0FF2) __sfr INTCON;
 700 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 701
 702 __at(0x0FF3) __sfr PROD;
 703
 704 __at(0x0FF3) __sfr PRODL;
 705
 706 __at(0x0FF4) __sfr PRODH;
 707
 708 __at(0x0FF5) __sfr TABLAT;
 709
 710 __at(0x0FF6) __sfr TBLPTR;
 711
 712 __at(0x0FF6) __sfr TBLPTRL;
 713
 714 __at(0x0FF7) __sfr TBLPTRH;
 715
 716 __at(0x0FF8) __sfr TBLPTRU;
 717
 718 __at(0x0FF9) __sfr PC;
 719
 720 __at(0x0FF9) __sfr PCL;
 721
 722 __at(0x0FFA) __sfr PCLATH;
 723
 724 __at(0x0FFB) __sfr PCLATU;
 725
 726 __at(0x0FFC) __sfr STKPTR;
 727 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 728
 729 __at(0x0FFD) __sfr TOS;
 730
 731 __at(0x0FFD) __sfr TOSL;
 732
 733 __at(0x0FFE) __sfr TOSH;
 734
 735 __at(0x0FFF) __sfr TOSU;