sdcc/device/non-free/lib/pic16/libdev/pic18f87j11.c

   1 /*
   2  * This definitions of the PIC18F87J11 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:39 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18f87j11.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F5A) __sfr PMSTAT;
  30
  31 __at(0x0F5A) __sfr PMSTATL;
  32 __at(0x0F5A) volatile __PMSTATLbits_t PMSTATLbits;
  33
  34 __at(0x0F5B) __sfr PMSTATH;
  35 __at(0x0F5B) volatile __PMSTATHbits_t PMSTATHbits;
  36
  37 __at(0x0F5C) __sfr PMEL;
  38 __at(0x0F5C) volatile __PMELbits_t PMELbits;
  39
  40 __at(0x0F5C) __sfr PMEN;
  41
  42 __at(0x0F5D) __sfr PMEH;
  43 __at(0x0F5D) volatile __PMEHbits_t PMEHbits;
  44
  45 __at(0x0F5E) __sfr PMDIN2;
  46
  47 __at(0x0F5E) __sfr PMDIN2L;
  48
  49 __at(0x0F5F) __sfr PMDIN2H;
  50
  51 __at(0x0F60) __sfr PMDOUT2;
  52
  53 __at(0x0F60) __sfr PMDOUT2L;
  54
  55 __at(0x0F61) __sfr PMDOUT2H;
  56
  57 __at(0x0F62) __sfr PMMODE;
  58
  59 __at(0x0F62) __sfr PMMODEL;
  60 __at(0x0F62) volatile __PMMODELbits_t PMMODELbits;
  61
  62 __at(0x0F63) __sfr PMMODEH;
  63 __at(0x0F63) volatile __PMMODEHbits_t PMMODEHbits;
  64
  65 __at(0x0F64) __sfr PMCON;
  66
  67 __at(0x0F64) __sfr PMCONL;
  68 __at(0x0F64) volatile __PMCONLbits_t PMCONLbits;
  69
  70 __at(0x0F65) __sfr PMCONH;
  71 __at(0x0F65) volatile __PMCONHbits_t PMCONHbits;
  72
  73 __at(0x0F66) __sfr PMDIN1;
  74
  75 __at(0x0F66) __sfr PMDIN1L;
  76
  77 __at(0x0F67) __sfr PMDIN1H;
  78
  79 __at(0x0F68) __sfr PMADDR;
  80
  81 __at(0x0F68) __sfr PMADDRL;
  82
  83 __at(0x0F68) __sfr PMDOUT1;
  84
  85 __at(0x0F68) __sfr PMDOUT1L;
  86
  87 __at(0x0F69) __sfr PMADDRH;
  88 __at(0x0F69) volatile __PMADDRHbits_t PMADDRHbits;
  89
  90 __at(0x0F69) __sfr PMDOUT1H;
  91
  92 __at(0x0F6A) __sfr CMSTAT;
  93 __at(0x0F6A) volatile __CMSTATbits_t CMSTATbits;
  94
  95 __at(0x0F6A) __sfr CMSTATUS;
  96 __at(0x0F6A) volatile __CMSTATUSbits_t CMSTATUSbits;
  97
  98 __at(0x0F6B) __sfr SSP2CON2;
  99 __at(0x0F6B) volatile __SSP2CON2bits_t SSP2CON2bits;
 100
 101 __at(0x0F6C) __sfr SSP2CON1;
 102 __at(0x0F6C) volatile __SSP2CON1bits_t SSP2CON1bits;
 103
 104 __at(0x0F6D) __sfr SSP2STAT;
 105 __at(0x0F6D) volatile __SSP2STATbits_t SSP2STATbits;
 106
 107 __at(0x0F6E) __sfr SSP2ADD;
 108
 109 __at(0x0F6E) __sfr SSP2MSK;
 110 __at(0x0F6E) volatile __SSP2MSKbits_t SSP2MSKbits;
 111
 112 __at(0x0F6F) __sfr SSP2BUF;
 113
 114 __at(0x0F70) __sfr CCP5CON;
 115 __at(0x0F70) volatile __CCP5CONbits_t CCP5CONbits;
 116
 117 __at(0x0F71) __sfr CCPR5;
 118
 119 __at(0x0F71) __sfr CCPR5L;
 120
 121 __at(0x0F72) __sfr CCPR5H;
 122
 123 __at(0x0F73) __sfr CCP4CON;
 124 __at(0x0F73) volatile __CCP4CONbits_t CCP4CONbits;
 125
 126 __at(0x0F74) __sfr CCPR4;
 127
 128 __at(0x0F74) __sfr CCPR4L;
 129
 130 __at(0x0F75) __sfr CCPR4H;
 131
 132 __at(0x0F76) __sfr T4CON;
 133 __at(0x0F76) volatile __T4CONbits_t T4CONbits;
 134
 135 __at(0x0F77) __sfr CVRCON;
 136 __at(0x0F77) volatile __CVRCONbits_t CVRCONbits;
 137
 138 __at(0x0F77) __sfr PR4;
 139
 140 __at(0x0F78) __sfr TMR4;
 141
 142 __at(0x0F79) __sfr T3CON;
 143 __at(0x0F79) volatile __T3CONbits_t T3CONbits;
 144
 145 __at(0x0F7A) __sfr TMR3;
 146
 147 __at(0x0F7A) __sfr TMR3L;
 148
 149 __at(0x0F7B) __sfr TMR3H;
 150
 151 __at(0x0F7C) __sfr BAUDCON2;
 152 __at(0x0F7C) volatile __BAUDCON2bits_t BAUDCON2bits;
 153
 154 __at(0x0F7D) __sfr SPBRGH2;
 155
 156 __at(0x0F7E) __sfr BAUDCON;
 157 __at(0x0F7E) volatile __BAUDCONbits_t BAUDCONbits;
 158
 159 __at(0x0F7E) __sfr BAUDCON1;
 160 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits;
 161
 162 __at(0x0F7F) __sfr SPBRGH1;
 163
 164 __at(0x0F80) __sfr PORTA;
 165 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
 166
 167 __at(0x0F81) __sfr PORTB;
 168 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
 169
 170 __at(0x0F82) __sfr PORTC;
 171 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
 172
 173 __at(0x0F83) __sfr PORTD;
 174 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
 175
 176 __at(0x0F84) __sfr PORTE;
 177 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
 178
 179 __at(0x0F85) __sfr PORTF;
 180 __at(0x0F85) volatile __PORTFbits_t PORTFbits;
 181
 182 __at(0x0F86) __sfr PORTG;
 183 __at(0x0F86) volatile __PORTGbits_t PORTGbits;
 184
 185 __at(0x0F87) __sfr PORTH;
 186 __at(0x0F87) volatile __PORTHbits_t PORTHbits;
 187
 188 __at(0x0F88) __sfr PORTJ;
 189 __at(0x0F88) volatile __PORTJbits_t PORTJbits;
 190
 191 __at(0x0F89) __sfr LATA;
 192 __at(0x0F89) volatile __LATAbits_t LATAbits;
 193
 194 __at(0x0F8A) __sfr LATB;
 195 __at(0x0F8A) volatile __LATBbits_t LATBbits;
 196
 197 __at(0x0F8B) __sfr LATC;
 198 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 199
 200 __at(0x0F8C) __sfr LATD;
 201 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 202
 203 __at(0x0F8D) __sfr LATE;
 204 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 205
 206 __at(0x0F8E) __sfr LATF;
 207 __at(0x0F8E) volatile __LATFbits_t LATFbits;
 208
 209 __at(0x0F8F) __sfr LATG;
 210 __at(0x0F8F) volatile __LATGbits_t LATGbits;
 211
 212 __at(0x0F90) __sfr LATH;
 213 __at(0x0F90) volatile __LATHbits_t LATHbits;
 214
 215 __at(0x0F91) __sfr LATJ;
 216 __at(0x0F91) volatile __LATJbits_t LATJbits;
 217
 218 __at(0x0F92) __sfr DDRA;
 219 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
 220
 221 __at(0x0F92) __sfr TRISA;
 222 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 223
 224 __at(0x0F93) __sfr DDRB;
 225 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
 226
 227 __at(0x0F93) __sfr TRISB;
 228 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 229
 230 __at(0x0F94) __sfr DDRC;
 231 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
 232
 233 __at(0x0F94) __sfr TRISC;
 234 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 235
 236 __at(0x0F95) __sfr DDRD;
 237 __at(0x0F95) volatile __DDRDbits_t DDRDbits;
 238
 239 __at(0x0F95) __sfr TRISD;
 240 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 241
 242 __at(0x0F96) __sfr DDRE;
 243 __at(0x0F96) volatile __DDREbits_t DDREbits;
 244
 245 __at(0x0F96) __sfr TRISE;
 246 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 247
 248 __at(0x0F97) __sfr DDRF;
 249 __at(0x0F97) volatile __DDRFbits_t DDRFbits;
 250
 251 __at(0x0F97) __sfr TRISF;
 252 __at(0x0F97) volatile __TRISFbits_t TRISFbits;
 253
 254 __at(0x0F98) __sfr DDRG;
 255 __at(0x0F98) volatile __DDRGbits_t DDRGbits;
 256
 257 __at(0x0F98) __sfr TRISG;
 258 __at(0x0F98) volatile __TRISGbits_t TRISGbits;
 259
 260 __at(0x0F99) __sfr DDRH;
 261 __at(0x0F99) volatile __DDRHbits_t DDRHbits;
 262
 263 __at(0x0F99) __sfr TRISH;
 264 __at(0x0F99) volatile __TRISHbits_t TRISHbits;
 265
 266 __at(0x0F9A) __sfr DDRJ;
 267 __at(0x0F9A) volatile __DDRJbits_t DDRJbits;
 268
 269 __at(0x0F9A) __sfr TRISJ;
 270 __at(0x0F9A) volatile __TRISJbits_t TRISJbits;
 271
 272 __at(0x0F9B) __sfr OSCTUNE;
 273 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 274
 275 __at(0x0F9C) __sfr RCSTA2;
 276 __at(0x0F9C) volatile __RCSTA2bits_t RCSTA2bits;
 277
 278 __at(0x0F9D) __sfr PIE1;
 279 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 280
 281 __at(0x0F9E) __sfr PIR1;
 282 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 283
 284 __at(0x0F9F) __sfr IPR1;
 285 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 286
 287 __at(0x0FA0) __sfr PIE2;
 288 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 289
 290 __at(0x0FA1) __sfr PIR2;
 291 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 292
 293 __at(0x0FA2) __sfr IPR2;
 294 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 295
 296 __at(0x0FA3) __sfr PIE3;
 297 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 298
 299 __at(0x0FA4) __sfr PIR3;
 300 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 301
 302 __at(0x0FA5) __sfr IPR3;
 303 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 304
 305 __at(0x0FA6) __sfr EECON1;
 306 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 307
 308 __at(0x0FA7) __sfr EECON2;
 309
 310 __at(0x0FA8) __sfr TXSTA2;
 311 __at(0x0FA8) volatile __TXSTA2bits_t TXSTA2bits;
 312
 313 __at(0x0FA9) __sfr TXREG2;
 314
 315 __at(0x0FAA) __sfr RCREG2;
 316
 317 __at(0x0FAB) __sfr SPBRG2;
 318
 319 __at(0x0FAC) __sfr RCSTA;
 320 __at(0x0FAC) volatile __RCSTAbits_t RCSTAbits;
 321
 322 __at(0x0FAC) __sfr RCSTA1;
 323 __at(0x0FAC) volatile __RCSTA1bits_t RCSTA1bits;
 324
 325 __at(0x0FAD) __sfr TXSTA;
 326 __at(0x0FAD) volatile __TXSTAbits_t TXSTAbits;
 327
 328 __at(0x0FAD) __sfr TXSTA1;
 329 __at(0x0FAD) volatile __TXSTA1bits_t TXSTA1bits;
 330
 331 __at(0x0FAE) __sfr TXREG;
 332
 333 __at(0x0FAE) __sfr TXREG1;
 334
 335 __at(0x0FAF) __sfr RCREG;
 336
 337 __at(0x0FAF) __sfr RCREG1;
 338
 339 __at(0x0FB0) __sfr SPBRG;
 340
 341 __at(0x0FB0) __sfr SPBRG1;
 342
 343 __at(0x0FB1) __sfr CCP3CON;
 344 __at(0x0FB1) volatile __CCP3CONbits_t CCP3CONbits;
 345
 346 __at(0x0FB1) __sfr ECCP3CON;
 347 __at(0x0FB1) volatile __ECCP3CONbits_t ECCP3CONbits;
 348
 349 __at(0x0FB2) __sfr CCPR3;
 350
 351 __at(0x0FB2) __sfr CCPR3L;
 352
 353 __at(0x0FB3) __sfr CCPR3H;
 354
 355 __at(0x0FB4) __sfr ECCP3DEL;
 356 __at(0x0FB4) volatile __ECCP3DELbits_t ECCP3DELbits;
 357
 358 __at(0x0FB5) __sfr ECCP3AS;
 359 __at(0x0FB5) volatile __ECCP3ASbits_t ECCP3ASbits;
 360
 361 __at(0x0FB6) __sfr CCP2CON;
 362 __at(0x0FB6) volatile __CCP2CONbits_t CCP2CONbits;
 363
 364 __at(0x0FB6) __sfr ECCP2CON;
 365 __at(0x0FB6) volatile __ECCP2CONbits_t ECCP2CONbits;
 366
 367 __at(0x0FB7) __sfr CCPR2;
 368
 369 __at(0x0FB7) __sfr CCPR2L;
 370
 371 __at(0x0FB8) __sfr CCPR2H;
 372
 373 __at(0x0FB9) __sfr ECCP2DEL;
 374 __at(0x0FB9) volatile __ECCP2DELbits_t ECCP2DELbits;
 375
 376 __at(0x0FBA) __sfr ECCP2AS;
 377 __at(0x0FBA) volatile __ECCP2ASbits_t ECCP2ASbits;
 378
 379 __at(0x0FBB) __sfr CCP1CON;
 380 __at(0x0FBB) volatile __CCP1CONbits_t CCP1CONbits;
 381
 382 __at(0x0FBB) __sfr ECCP1CON;
 383 __at(0x0FBB) volatile __ECCP1CONbits_t ECCP1CONbits;
 384
 385 __at(0x0FBC) __sfr CCPR1;
 386
 387 __at(0x0FBC) __sfr CCPR1L;
 388
 389 __at(0x0FBD) __sfr CCPR1H;
 390
 391 __at(0x0FBE) __sfr ECCP1DEL;
 392 __at(0x0FBE) volatile __ECCP1DELbits_t ECCP1DELbits;
 393
 394 __at(0x0FBF) __sfr ECCP1AS;
 395 __at(0x0FBF) volatile __ECCP1ASbits_t ECCP1ASbits;
 396
 397 __at(0x0FC0) __sfr WDTCON;
 398 __at(0x0FC0) volatile __WDTCONbits_t WDTCONbits;
 399
 400 __at(0x0FC1) __sfr ADCON1;
 401 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 402
 403 __at(0x0FC1) __sfr ANCON0;
 404 __at(0x0FC1) volatile __ANCON0bits_t ANCON0bits;
 405
 406 __at(0x0FC2) __sfr ADCON0;
 407 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 408
 409 __at(0x0FC2) __sfr ANCON1;
 410 __at(0x0FC2) volatile __ANCON1bits_t ANCON1bits;
 411
 412 __at(0x0FC3) __sfr ADRES;
 413
 414 __at(0x0FC3) __sfr ADRESL;
 415
 416 __at(0x0FC4) __sfr ADRESH;
 417
 418 __at(0x0FC5) __sfr SSP1CON2;
 419 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits;
 420
 421 __at(0x0FC5) __sfr SSPCON2;
 422 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 423
 424 __at(0x0FC6) __sfr SSP1CON1;
 425 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits;
 426
 427 __at(0x0FC6) __sfr SSPCON1;
 428 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 429
 430 __at(0x0FC7) __sfr SSP1STAT;
 431 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits;
 432
 433 __at(0x0FC7) __sfr SSPSTAT;
 434 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 435
 436 __at(0x0FC8) __sfr SSP1ADD;
 437
 438 __at(0x0FC8) __sfr SSP1MSK;
 439 __at(0x0FC8) volatile __SSP1MSKbits_t SSP1MSKbits;
 440
 441 __at(0x0FC8) __sfr SSPADD;
 442
 443 __at(0x0FC9) __sfr SSP1BUF;
 444
 445 __at(0x0FC9) __sfr SSPBUF;
 446
 447 __at(0x0FCA) __sfr T2CON;
 448 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 449
 450 __at(0x0FCB) __sfr MEMCON;
 451 __at(0x0FCB) volatile __MEMCONbits_t MEMCONbits;
 452
 453 __at(0x0FCB) __sfr PR2;
 454
 455 __at(0x0FCC) __sfr PADCFG1;
 456 __at(0x0FCC) volatile __PADCFG1bits_t PADCFG1bits;
 457
 458 __at(0x0FCC) __sfr TMR2;
 459
 460 __at(0x0FCD) __sfr ODCON3;
 461 __at(0x0FCD) volatile __ODCON3bits_t ODCON3bits;
 462
 463 __at(0x0FCD) __sfr T1CON;
 464 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 465
 466 __at(0x0FCE) __sfr ODCON2;
 467 __at(0x0FCE) volatile __ODCON2bits_t ODCON2bits;
 468
 469 __at(0x0FCE) __sfr TMR1;
 470
 471 __at(0x0FCE) __sfr TMR1L;
 472
 473 __at(0x0FCF) __sfr ODCON1;
 474 __at(0x0FCF) volatile __ODCON1bits_t ODCON1bits;
 475
 476 __at(0x0FCF) __sfr TMR1H;
 477
 478 __at(0x0FD0) __sfr RCON;
 479 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 480
 481 __at(0x0FD1) __sfr CM2CON;
 482 __at(0x0FD1) volatile __CM2CONbits_t CM2CONbits;
 483
 484 __at(0x0FD1) __sfr CM2CON1;
 485 __at(0x0FD1) volatile __CM2CON1bits_t CM2CON1bits;
 486
 487 __at(0x0FD2) __sfr CM1CON;
 488 __at(0x0FD2) volatile __CM1CONbits_t CM1CONbits;
 489
 490 __at(0x0FD2) __sfr CM1CON1;
 491 __at(0x0FD2) volatile __CM1CON1bits_t CM1CON1bits;
 492
 493 __at(0x0FD3) __sfr OSCCON;
 494 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 495
 496 __at(0x0FD3) __sfr REFOCON;
 497 __at(0x0FD3) volatile __REFOCONbits_t REFOCONbits;
 498
 499 __at(0x0FD5) __sfr T0CON;
 500 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 501
 502 __at(0x0FD6) __sfr TMR0;
 503
 504 __at(0x0FD6) __sfr TMR0L;
 505
 506 __at(0x0FD7) __sfr TMR0H;
 507
 508 __at(0x0FD8) __sfr STATUS;
 509 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 510
 511 __at(0x0FD9) __sfr FSR2L;
 512
 513 __at(0x0FDA) __sfr FSR2H;
 514
 515 __at(0x0FDB) __sfr PLUSW2;
 516
 517 __at(0x0FDC) __sfr PREINC2;
 518
 519 __at(0x0FDD) __sfr POSTDEC2;
 520
 521 __at(0x0FDE) __sfr POSTINC2;
 522
 523 __at(0x0FDF) __sfr INDF2;
 524
 525 __at(0x0FE0) __sfr BSR;
 526
 527 __at(0x0FE1) __sfr FSR1L;
 528
 529 __at(0x0FE2) __sfr FSR1H;
 530
 531 __at(0x0FE3) __sfr PLUSW1;
 532
 533 __at(0x0FE4) __sfr PREINC1;
 534
 535 __at(0x0FE5) __sfr POSTDEC1;
 536
 537 __at(0x0FE6) __sfr POSTINC1;
 538
 539 __at(0x0FE7) __sfr INDF1;
 540
 541 __at(0x0FE8) __sfr WREG;
 542
 543 __at(0x0FE9) __sfr FSR0L;
 544
 545 __at(0x0FEA) __sfr FSR0H;
 546
 547 __at(0x0FEB) __sfr PLUSW0;
 548
 549 __at(0x0FEC) __sfr PREINC0;
 550
 551 __at(0x0FED) __sfr POSTDEC0;
 552
 553 __at(0x0FEE) __sfr POSTINC0;
 554
 555 __at(0x0FEF) __sfr INDF0;
 556
 557 __at(0x0FF0) __sfr INTCON3;
 558 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 559
 560 __at(0x0FF1) __sfr INTCON2;
 561 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 562
 563 __at(0x0FF2) __sfr INTCON;
 564 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 565
 566 __at(0x0FF3) __sfr PROD;
 567
 568 __at(0x0FF3) __sfr PRODL;
 569
 570 __at(0x0FF4) __sfr PRODH;
 571
 572 __at(0x0FF5) __sfr TABLAT;
 573
 574 __at(0x0FF6) __sfr TBLPTR;
 575
 576 __at(0x0FF6) __sfr TBLPTRL;
 577
 578 __at(0x0FF7) __sfr TBLPTRH;
 579
 580 __at(0x0FF8) __sfr TBLPTRU;
 581
 582 __at(0x0FF9) __sfr PC;
 583
 584 __at(0x0FF9) __sfr PCL;
 585
 586 __at(0x0FFA) __sfr PCLATH;
 587
 588 __at(0x0FFB) __sfr PCLATU;
 589
 590 __at(0x0FFC) __sfr STKPTR;
 591 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 592
 593 __at(0x0FFD) __sfr TOS;
 594
 595 __at(0x0FFD) __sfr TOSL;
 596
 597 __at(0x0FFE) __sfr TOSH;
 598
 599 __at(0x0FFF) __sfr TOSU;