sdcc/device/non-free/lib/pic16/libdev/pic18lf1320.c

   1 /*
   2  * This definitions of the PIC18LF1320 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:59 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18lf1320.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F80) __sfr PORTA;
  30 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
  31
  32 __at(0x0F81) __sfr PORTB;
  33 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
  34
  35 __at(0x0F89) __sfr LATA;
  36 __at(0x0F89) volatile __LATAbits_t LATAbits;
  37
  38 __at(0x0F8A) __sfr LATB;
  39 __at(0x0F8A) volatile __LATBbits_t LATBbits;
  40
  41 __at(0x0F92) __sfr DDRA;
  42 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
  43
  44 __at(0x0F92) __sfr TRISA;
  45 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
  46
  47 __at(0x0F93) __sfr DDRB;
  48 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
  49
  50 __at(0x0F93) __sfr TRISB;
  51 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
  52
  53 __at(0x0F9B) __sfr OSCTUNE;
  54 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
  55
  56 __at(0x0F9D) __sfr PIE1;
  57 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
  58
  59 __at(0x0F9E) __sfr PIR1;
  60 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
  61
  62 __at(0x0F9F) __sfr IPR1;
  63 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
  64
  65 __at(0x0FA0) __sfr PIE2;
  66 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
  67
  68 __at(0x0FA1) __sfr PIR2;
  69 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
  70
  71 __at(0x0FA2) __sfr IPR2;
  72 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
  73
  74 __at(0x0FA6) __sfr EECON1;
  75 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
  76
  77 __at(0x0FA7) __sfr EECON2;
  78
  79 __at(0x0FA8) __sfr EEDATA;
  80
  81 __at(0x0FA9) __sfr EEADR;
  82
  83 __at(0x0FAA) __sfr BAUDCTL;
  84 __at(0x0FAA) volatile __BAUDCTLbits_t BAUDCTLbits;
  85
  86 __at(0x0FAB) __sfr RCSTA;
  87 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
  88
  89 __at(0x0FAC) __sfr TXSTA;
  90 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
  91
  92 __at(0x0FAD) __sfr TXREG;
  93
  94 __at(0x0FAE) __sfr RCREG;
  95
  96 __at(0x0FAF) __sfr SPBRG;
  97
  98 __at(0x0FB0) __sfr SPBRGH;
  99
 100 __at(0x0FB1) __sfr T3CON;
 101 __at(0x0FB1) volatile __T3CONbits_t T3CONbits;
 102
 103 __at(0x0FB2) __sfr TMR3;
 104
 105 __at(0x0FB2) __sfr TMR3L;
 106
 107 __at(0x0FB3) __sfr TMR3H;
 108
 109 __at(0x0FB6) __sfr ECCPAS;
 110 __at(0x0FB6) volatile __ECCPASbits_t ECCPASbits;
 111
 112 __at(0x0FB7) __sfr PWM1CON;
 113 __at(0x0FB7) volatile __PWM1CONbits_t PWM1CONbits;
 114
 115 __at(0x0FBD) __sfr CCP1CON;
 116 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits;
 117
 118 __at(0x0FBE) __sfr CCPR1;
 119
 120 __at(0x0FBE) __sfr CCPR1L;
 121
 122 __at(0x0FBF) __sfr CCPR1H;
 123
 124 __at(0x0FC0) __sfr ADCON2;
 125 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 126
 127 __at(0x0FC1) __sfr ADCON1;
 128 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 129
 130 __at(0x0FC2) __sfr ADCON0;
 131 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 132
 133 __at(0x0FC3) __sfr ADRES;
 134
 135 __at(0x0FC3) __sfr ADRESL;
 136
 137 __at(0x0FC4) __sfr ADRESH;
 138
 139 __at(0x0FCA) __sfr T2CON;
 140 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 141
 142 __at(0x0FCB) __sfr PR2;
 143
 144 __at(0x0FCC) __sfr TMR2;
 145
 146 __at(0x0FCD) __sfr T1CON;
 147 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 148
 149 __at(0x0FCE) __sfr TMR1;
 150
 151 __at(0x0FCE) __sfr TMR1L;
 152
 153 __at(0x0FCF) __sfr TMR1H;
 154
 155 __at(0x0FD0) __sfr RCON;
 156 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 157
 158 __at(0x0FD1) __sfr WDTCON;
 159 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 160
 161 __at(0x0FD2) __sfr LVDCON;
 162 __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits;
 163
 164 __at(0x0FD3) __sfr OSCCON;
 165 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 166
 167 __at(0x0FD5) __sfr T0CON;
 168 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 169
 170 __at(0x0FD6) __sfr TMR0;
 171
 172 __at(0x0FD6) __sfr TMR0L;
 173
 174 __at(0x0FD7) __sfr TMR0H;
 175
 176 __at(0x0FD8) __sfr STATUS;
 177 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 178
 179 __at(0x0FD9) __sfr FSR2L;
 180
 181 __at(0x0FDA) __sfr FSR2H;
 182
 183 __at(0x0FDB) __sfr PLUSW2;
 184
 185 __at(0x0FDC) __sfr PREINC2;
 186
 187 __at(0x0FDD) __sfr POSTDEC2;
 188
 189 __at(0x0FDE) __sfr POSTINC2;
 190
 191 __at(0x0FDF) __sfr INDF2;
 192
 193 __at(0x0FE0) __sfr BSR;
 194
 195 __at(0x0FE1) __sfr FSR1L;
 196
 197 __at(0x0FE2) __sfr FSR1H;
 198
 199 __at(0x0FE3) __sfr PLUSW1;
 200
 201 __at(0x0FE4) __sfr PREINC1;
 202
 203 __at(0x0FE5) __sfr POSTDEC1;
 204
 205 __at(0x0FE6) __sfr POSTINC1;
 206
 207 __at(0x0FE7) __sfr INDF1;
 208
 209 __at(0x0FE8) __sfr WREG;
 210
 211 __at(0x0FE9) __sfr FSR0L;
 212
 213 __at(0x0FEA) __sfr FSR0H;
 214
 215 __at(0x0FEB) __sfr PLUSW0;
 216
 217 __at(0x0FEC) __sfr PREINC0;
 218
 219 __at(0x0FED) __sfr POSTDEC0;
 220
 221 __at(0x0FEE) __sfr POSTINC0;
 222
 223 __at(0x0FEF) __sfr INDF0;
 224
 225 __at(0x0FF0) __sfr INTCON3;
 226 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 227
 228 __at(0x0FF1) __sfr INTCON2;
 229 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 230
 231 __at(0x0FF2) __sfr INTCON;
 232 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 233
 234 __at(0x0FF3) __sfr PROD;
 235
 236 __at(0x0FF3) __sfr PRODL;
 237
 238 __at(0x0FF4) __sfr PRODH;
 239
 240 __at(0x0FF5) __sfr TABLAT;
 241
 242 __at(0x0FF6) __sfr TBLPTR;
 243
 244 __at(0x0FF6) __sfr TBLPTRL;
 245
 246 __at(0x0FF7) __sfr TBLPTRH;
 247
 248 __at(0x0FF8) __sfr TBLPTRU;
 249
 250 __at(0x0FF9) __sfr PC;
 251
 252 __at(0x0FF9) __sfr PCL;
 253
 254 __at(0x0FFA) __sfr PCLATH;
 255
 256 __at(0x0FFB) __sfr PCLATU;
 257
 258 __at(0x0FFC) __sfr STKPTR;
 259 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 260
 261 __at(0x0FFD) __sfr TOS;
 262
 263 __at(0x0FFD) __sfr TOSL;
 264
 265 __at(0x0FFE) __sfr TOSH;
 266
 267 __at(0x0FFF) __sfr TOSU;